CY7C1041CV33 Automotive
4-Mbit (256 K × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-67307 Rev. ** Revised March 11, 2011
4-Mbit (256 K × 16) Static RAM
Features
■Temperature ranges
❐Automotive-A: –40 °C to 85 °C
❐Automotive-E: –40 °C to 125 °C
■Pin and function compatible with CY7C1041BNV33
■High speed
❐tAA = 10 ns (Automotive-A)
❐tAA = 12 ns (Automotive-E)
■Low active power
❐432 mW (max)
■2.0 V data retention
■Automatic power down when deselected
■TTL-compatible inputs and outputs
■Easy memory expansion with CE and OE features
■Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin
TSOP II and 48-ball FBGA packages
Functional Description
The CY7C1041CV33 Automotive is a high performance CMOS
static RAM organized as 262,144 words by 16 bits.
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. For more information, see the Truth
Table on page 10 for a complete description of Read and Write
modes.
The input and output pins (I/O0 through I/O15) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
256K x 16
RAM Array I/O0–I/O7
ROW DECODER
A0
A1
A2
A3
A6
COLUMN DECODER
A10
A11
A12
A13
A14
SENSE AMPS
INPUT BUFFER
OE
A4
A5
I/O8–I/O15
WE
BLE
BHE
A15
A8
A7
A16
A17
CE
A9
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CY7C1041CV33 Automotive
Document Number: 001-67307 Rev. ** Page 2 of 17
Contents
Selection Guide ................................................................3
Pin Configuration .............................................................3
Pin Definitions ..................................................................4
Maximum Ratings .............................................................5
Operating Range ............................................................... 5
Electrical Characteristics .................................................5
Capacitance ......................................................................6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms .......................................6
Switching Characteristics ................................................7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ....................................................................... 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC Solutions ......................................................... 17
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Document Number: 001-67307 Rev. ** Page 3 of 17
Selection Guide
Description -10 -12 -20 Unit
Maximum Access Time 10 12 20 ns
Maximum Operating Current Automotive-A 100 – 85 mA
Automotive-E – 120 90 mA
Maximum CMOS Standby Current Automotive-A 10 – 10 mA
Automotive-E – 15 15 mA
Pin Configuration
Figure 1. 44-pin SOJ/TSOP II (Top View) [1] Figure 2. 48-ball FBGA Pinout (Top View) [1]
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
17
18
17
20
19
27
28
25
26
22
21
23
24
A
16
A
15
A
0
A
1
A
2
A
3
A
4
A
7
A
6
A
14
A
13
A
12
A
11
A
9
A
8
A
10
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
5
WE
A11
A10
A6
A0
A3CE
IO2
IO0
IO1
A4
A5
IO3
IO5
IO4
IO6
IO7
VSS
A9
A8
OE
A7
IO8
BHE
NC
A17
A2
A1
BLE
IO9
IO10
IO11
IO12
IO13 IO14
IO15
A15
A14
A13
A12
NC
NC NC
326541
D
E
B
A
C
F
G
H
A16
NC
VCC
VCC VSS
Note
1. NC pins are not connected on the die.
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CY7C1041CV33 Automotive
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Pin Definitions
Pin Name SOJ, TSOP
Pin Number
BGA
Pin Number I/O Type Description
A0–A17 1–5, 18–27,
42–44
A3, A4, A5, B3,
B4, C3, C4, D4,
H2, H3, H4, H5,
G3, G4, F3, F4,
E4, D3
Input Address Inputs. Used to select one of the address locations.
I/O0–I/O15 7–10,13–16,
29–32, 35–38
B1, C1, C2, D2,
E2, F2, F1, G1,
B6, C6, C5, D5,
E5, F5, F6, G6
Input or Output Bidirectional Data I/O lines. Used as input or output lines
depending on operation.
NC 28 A6, E3, G2, H1,
H6
No Connect No Connects. Not connected to the die.
WE 17 G5 Input or
Control
Write Enable Input, Active LOW. When selected LOW, a write is
conducted. When deselected HIGH, a read is conducted.
CE 6 B5 Input or
Control
Chip Enable Input, Active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
BHE, BLE 40, 39 B2, A1 Input or
Control
Byte Write Select Inputs, Active LOW. BHE controls I/O15 – I/O8,
BLE controls I/O7 – I/O0.
OE 41 A2 Input or
Control
Output Enable, Active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, the I/O pins are tri-stated and act as input data
pins.
VSS 12, 34 D1, E6 Ground Ground for the Device. Connected to ground of the system.
VCC 11, 33 D6, E1 Power Supply Power Supply Inputs to the Device.
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Document Number: 001-67307 Rev. ** Page 5 of 17
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied .......................................... –55 C to +125 C
Supply Voltage on VCC Relative to GND[2] ...–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State[2] .................................. –0.5 V to VCC + 0.5 V
DC Input Voltage[2] .............................. –0.5 V to VCC + 0.5 V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001 V
(MIL-STD-883, Method 3015)
Latch Up Current .................................................... > 200 mA
Operating Range
Range Ambient
Temperature (TA)VCC
Automotive-A –40 C to +85 C 3.3 V 10%
Automotive-E –40 C to +125 C
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions -10 -12 -20 Unit
Min Max Min Max Min Max
VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA 2.4 – 2.4 – 2.4 – V
VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA –0.4–0.4–0.4V
VIH Input HIGH Voltage 2.0 VCC +
0.3
2.0 VCC +
0.3
2.0 VCC +
0.3
V
VIL [2] Input LOW Voltage –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Leakage
Current
GND < VI < VCC Auto-A –1 +1 – – –1 +1 A
Auto-E – – –20 +20 –20 +20
IOZ Output Leakage
Current
GND < VOUT < VCC,
Output disabled
Auto-A –1 +1 – – –1 +1 A
Auto-E – – –20 +20 –20 +20
ICC VCC Operating
Supply Current
VCC = Max,
f = fMAX = 1/tRC
Auto-A – 100 – – – 85 mA
Auto-E – – – 120 – 90
ISB1 Automatic CE Power
Down Current —TTL
Inputs
Max VCC, CE > VIH,
VIN > VIH, or VIN < VIL,
f = fMAX
Auto-A –40– – –40mA
Auto-E – – –45–45
ISB2 Automatic CE Power
Down Current —
CMOS Inputs
Max VCC,
CE > VCC – 0.3 V,
VIN > VCC – 0.3 V,
or VIN < 0.3 V, f = 0
Auto-A –10– – –10mA
Auto-E – – –15–15
Note
2. VIL (min) = –2.0 V and VIH(max) = VCC + 0.5 V for pulse durations of less than 20 ns.
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CY7C1041CV33 Automotive
Document Number: 001-67307 Rev. ** Page 6 of 17
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25 C, f = 1 MHz, VCC = 3.3 V 8 pF
COUT Output Capacitance 8pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions SOJ TSOP II FBGA Unit
JA Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
25.99 42.96 38.15 C/W
JC Thermal Resistance
(Junction to Case)
18.8 10.75 9.15 C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [3]
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
3.3 V
OUTPUT
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
(b)
R 317
R2
351
Rise Time: 1 V/ns Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50
50
1.5 V
(c)
(a)
3.3 V
OUTPUT
5 pF
(d)
R 317
R2
351
10-ns devices: 12-, 15-, 20-ns devices:
High Z characteristics:
Note
3. AC characteristics (except High Z) for 10 ns parts are tested using the load conditions shown in Figure 3 (a). All other speeds are tested using the Thevenin load shown
in Figure 3 (b). High Z characteristics are tested for all speeds using the test load shown in Figure 3 (d).
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Document Number: 001-67307 Rev. ** Page 7 of 17
Switching Characteristics
Over the Operating Range [4]
Parameter Description -10 -12 -20 Unit
Min Max Min Max Min Max
Read Cycle
tpower[5] VCC(Typical) to the First Access 100 – 100 – 100 – s
tRC Read Cycle Time 10 – 12 – 20 – ns
tAA Address to Data Valid – 10 – 12 – 20 ns
tOHA Data Hold from Address Change 3 – 3 – 3 – ns
tACE CE LOW to Data Valid – 10 – 12 – 20 ns
tDOE OE LOW to Data Valid Auto-A –5–6–8 ns
Auto-E –––7–8
tLZOE OE LOW to Low Z[6] 0–0–0– ns
tHZOE OE HIGH to High Z[6, 7] –5–6–8 ns
tLZCE CE LOW to Low Z[6] 3–3–3– ns
tHZCE CE HIGH to High Z[6, 7] –5–6–8 ns
tPU CE LOW to Power Up 0–0–0– ns
tPD CE HIGH to Power Down – 10 – 12 – 20 ns
tDBE Byte Enable to Data Valid Auto-A – 5 – 6 – 8 ns
Auto-E –––7–8
tLZBE Byte Enable to Low Z 0 – 0 – 0 – ns
tHZBE Byte Disable to High Z – 6 – 6 – 8 ns
Write Cycle[8, 9]
tWC Write Cycle Time 10 – 12 – 20 – ns
tSCE CE LOW to Write End 7 – 8 – 10 – ns
tAW Address Setup to Write End 7 – 8 – 10 – ns
tHA Address Hold from Write End 0 – 0 – 0 – ns
tSA Address Setup to Write Start 0 – 0 – 0 – ns
tPWE WE Pulse Width 7 – 8 –10– ns
tSD Data Setup to Write End 5–6–8– ns
tHD Data Hold from Write End 0 – 0 – 0 – ns
tLZWE WE HIGH to Low Z[6] 3–3–3– ns
tHZWE WE LOW to High Z[6, 7] –5–6–8 ns
tBW Byte Enable to End of Write 7 – 8 – 10 – ns
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V.
5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
7. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 3 on page 6. Transition is measured 500 mV from steady state
voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled)[10, 11]
Figure 5. Read Cycle No. 2 (OE Controlled)[11, 12]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
tDBE
tLZBE
tHZCE
HIGH
IMPEDANCE
ICC
ISB
OE
CE
ADDRESS
DATA OUT
VCC
SUPPLY
BHE,BLE
CURRENT
Notes
10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
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Figure 6. Write Cycle No. 1 (CE Controlled)[13, 14]
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
Switching Waveforms (continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
t
DATA IO
ADDRESS
CE
WE
BHE,BLE
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATA IO
ADDRESS
BHE,BLE
CE
WE
Notes
13. Data IO is high impedance if OE, BHE, and/or BLE = VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
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Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)
Truth Table
CE OE WE BLE BHE I/O0 – I/O7I/O8 – I/O15 Mode Power
HXXXXHigh ZHigh Z Power Down Standby (I
SB)
L L H L L Data Out Data Out Read – All Bits Active (ICC)
L H Data Out High Z Read – Lower Bits Only Active (ICC)
H L High Z Data Out Read – Upper Bits Only Active (ICC)
L X L L L Data In Data In Write – All Bits Active (ICC)
L H Data In High Z Write – Lower Bits Only Active (ICC)
H L High Z Data In Write – Upper Bits Only Active (ICC)
L H H X X High Z High Z Selected, Outputs Disabled Active (ICC)
L X X H H High Z High Z Selected, Outputs Disabled Active (ICC)
Switching Waveforms (continued)
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
tSA
tLZWE
tHZWE
DATA IO
ADDRESS
CE
WE
BHE,BLE
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Document Number: 001-67307 Rev. ** Page 11 of 17
Ordering Code Definitions
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available.For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
10 CY7C1041CV33-10BAXA 51-85106 48-ball FBGA (Pb-free) Automotive-A
CY7C1041CV33-10ZSXA 51-85087 44-pin TSOP II (Pb-free)
12 CY7C1041CV33-12BAXE 51-85106 48-ball FBGA (Pb-free) Automotive-E
CY7C1041CV33-12ZSXE 51-85087 44-pin TSOP II (Pb-free)
20 CY7C1041CV33-20ZSXA 51-85087 44-pin TSOP II (Pb-free) Automotive-A
CY7C1041CV33-20VXE 44-pin (400-mil) Molded SOJ (Pb-free) Automotive-E
CY7C1041CV33-20ZSXE 44-pin TSOP II (Pb-free)
Please contact your local Cypress sales representative for availability of these parts
Temperature Range: X = A or E
A = Automotive; E = Automotive Extended
X = Pb-free; X Absent = Leaded
Package Type: XX = BA or ZS or V
BA = 48-ball FBGA
ZS = 44-pin TSOP II
V = 44-pin (400-mil) Molded SOJ
Speed Grade: XX = 10 ns or 12 ns or 20 ns
V33 = 3.0 V to 3.6 V
Process Technology:C 150 nm
Data width: × 16-bits
4-Mbit density
Fast Asynchronous SRAM
Marketing Code: 7C = SRAMs
Company ID: CY = Cypress
CY 1 C - XX XX XV33 X7C 04 1
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Document Number: 001-67307 Rev. ** Page 15 of 17
Acronyms Document Conventions
Units of Measure
Acronym Description
CE Chip Enable
CMOS complementary metal oxide semiconductor
FBGA fine-pitch ball grid array
I/O input/output
OE Output Enable
PLL phase locked loop
SOJ Small Outline J-lead
SRAM static random access memory
TSOP thin small outline package
TTL transistor-transistor logic
WE Write Enable
Symbol Unit of Measure
ohms
ns nano seconds
VVolts
µs micro seconds
µA micro Amperes
mA milli Amperes
mm milli meter
ms milli seconds
MHz Mega Hertz
pF pico Farad
% percent
mW milli Watts
WWatts
°C degree Celcius
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Document History Page
Document Title: CY7C1041CV33 Automotive, 4-Mbit (256 K × 16) Static RAM
Document Number: 001-67307
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 3187164 03/03/2011 PRAS Separation of the automotive datasheet from CY7C1041CV33 spec no. 38-05134
Rev. *K. Further rev of 38-05134 would include only industrial / commercial parts.
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Document Number: 001-67307 Rev. ** Revised March 11, 2011 Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1041CV33 Automotive
© Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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