AVAILABLE
Functional Diagrams
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
General Description
The MAX4820/MAX4821 8-channel relay drivers offer
built-in kickback protection and drive +3.3V/+5V non-
latching or dual-coil-latching relays. These devices are
especially useful when driving +3V relays. Each inde-
pendent open-drain output features a 2Ωon-resistance
and is guaranteed to sink 70mA (min) of load current.
Both devices consume less than 50µA (max) quiescent
current and have 1µA output off-leakage current.
The MAX4820 features an SPI™-/QSPI™-/MICROWIRE™-
compatible serial interface. Input data is shifted into an 8-
bit shift register and latched to the outputs when CS
transitions from low to high. Each data bit in the shift reg-
ister corresponds to a specific output, allowing indepen-
dent control of all outputs.
The MAX4821 features a 4-bit (A0, A1, A2, LVL) paral-
lel-input interface. The first three bits (A0, A1, A2) deter-
mine the output address, and the fourth bit (LVL)
determines whether the selected output is switched on
or off. Data is latched to the outputs when CS transi-
tions from low to high.
Both devices feature separate set and reset functions
that allow the user to turn on or turn off all outputs simul-
taneously with a single control line. Built-in hysteresis
(Schmidt trigger) on all digital inputs allows this device
to be used with slow rising and falling signals, such as
those from optocouplers or RC power-up initialization
circuits. The MAX4820/MAX4821 are available in 20-pin
TSSOP and space-saving 20-pin Thin QFN packages.
Applications
Central Office
ATE
DSL, ADSL Line Cards
Industrial Equipment
E1/T1 Redundancy
Features
♦8 Independent Output Channels
♦Built-In Inductive Kickback Protection
♦Drive +3V and +5V Relays
♦Guaranteed 70mA (min) Coil Drive Current
♦SET Function to Turn On All Outputs
Simultaneously
♦RESET Function to Turn Off All Outputs
Simultaneously
♦SPI-/QSPI-/MICROWIRE-Compatible Serial
Interface (MAX4820)
♦Serial Digital Output for Daisy Chaining
(MAX4820)
♦Parallel Interface (MAX4821)
♦Low 50µA (max) Quiescent Supply Current
♦Space-Saving 20-Pin Thin QFN Package
TOP VIEW
*CONNECT EP TO GND.
*EP
20
19
18
17
SET
VCC
OUT1
OUT2
16 PGND
13
12
11
14
15
OUT5
COM
OUT4
OUT3
OUT6
4
3
2
+
SCLK
DIN
CS
1
5DOUT
6
7
8
9
N.C.
GND
OUT8
OUT7
10PGND
MAX4820
THIN QFN
RESET
Pin Configurations
Ordering Information
19-2751; Rev 2; 1/10
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
Pin Configurations continued at end of data sheet.
Typical Application Circuits and Functional Diagrams
appear at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PART TEMP RANGE PIN-PACKAGE
MAX4820ETP+ -40°C to +85°C 20 Thin QFN-EP*
MAX4820EUP+ -40°C to +85°C 20 TSSOP-EP*
MAX4821ETP+ -40°C to +85°C 20 Thin QFN-EP*
MAX4821EUP+ -40°C to +85°C 20 TSSOP-EP*
MAX4820/MAX4821
Ordering Information
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +3V to +5.5V, VCOM = VCC, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
VCC, COM..............................................................-0.3V to +6.0V
OUT_........................................................-0.3V to (VCOM + 0.3V)
CS, SCLK, DIN, SET, RESET, A0, A1, A2, LVL......-0.3V to +6.0V
DOUT..........................................................-0.3V to (VCC + 0.3V)
Continuous OUT_ Current (all outputs turned on) ............150mA
Continuous OUT_ Current (single output turned on) ........300mA
Continuous Power Dissipation (TA= +70°C)
20-Lead Thin QFN (derate 16.9mW/°C above +70°C)..1350mW
θJA (Note 1) ...............................................................59.3°C/W
20-Pin TSSOP (derate 21.7mW/°C above +70°C) .....1739mW
θJA (Note 1) ..................................................................46°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature (10s) ...........................................+300°C
Reflow Temperature.........................................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Voltage VCC 2.3 5.5 V
VCC = 3.6V 15 50
Quiescent Current IQIOUT_ = 0µA,
logic inputs = 0V or VCC VCC = 5.5V 20 70 µA
Thermal Shutdown 160 °C
Power-On Reset 0.8 1.5 2.2 V
Power-On Reset Hysteresis 140 mV
DIGITAL INPUTS (SCLK, DIN, CS, LVL, A0, A1, A2, RESET, SET)
VCC = 3.3V 2.0
Input Logic-High Voltage VIH VCC = 5V 2.4 V
VCC = 3.3V 0.6
Input Logic-Low Voltage VIL VCC = 5V 0.8 V
Input Logic Hysteresis VHYST 150 mV
Input Leakage Currents ILEAK Input voltages = 0V or 5.5V -1.0 0.01 +1.0 µA
CIN Input Capacitance CIN 5pF
DIGITAL OUTPUT (DOUT)
DOUT Low Voltage VOL ISINK = 6mA 0.4 V
DOUT High Voltage VOH ISOURCE = 0.5mA VCC - 0.5 V
RELAY OUTPUT DRIVERS (OUT1–OUT8)
VCC = 2.7V 70
OUT_ Drive Current VCC = 4.5V 70 mA
OUT_ On-Resistance RON VCC = 2.7V 2 6 Ω
OUT_ Voltage VOUT_V
CC = 3.0V, IOUT_ = 70mA 0.4 V
IOUT Off-Leakage Current ILEAK VOUT_ = VCC, all outputs off -1 +1 µA
Kickback Diode Forward Voltage VFORW IOUT_ = 150mA (Note 3) 1.5 V
Note 1: Package thermal resistances were obtained using the method described in JEDEC specifications. For detailed information on
package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
MAX4820/MAX4821
2
Maxim Integrated
3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SPI TIMING (MAX4820)
Turn-On Time (OUT_) tON From rising edge of CS, RL = 50Ω,
CL = 50pF 1.0 µs
Turn-Off Time (OUT_) tOFF From rising edge of CS, RL = 50Ω,
CL = 50pF 1.0 µs
SCLK Frequency fSCLK 0 2.1 MHz
Cycle Time tCH + tCL 480 ns
CS Fall to SCLK Rise Setup tCSS 240 ns
CS Rise to SCLK Hold tCSH 240 ns
SCLK High Time tCH 190 ns
SCLK Low Time tCL 190 ns
Data Setup Time tDS 100 ns
Data Hold Time tDH 0ns
SCLK Fall to DOUT Valid tDO 50% of SCLK to 10% of DOUT,
CL = 50pF 85 120 ns
Rise Time (DIN, SCLK, CS, SET,
RESET)tSCR 20% of VCC to 70% of VCC, CL = 50pF 2 µs
Fall Time (DIN, SCLK, CS,
RESET, SET)tSCF 20% of VCC to 70% of VCC, CL = 50pF 2 µs
RESET Min Pulse Width tRW 70 ns
SET Min Pulse Width tSW 70 ns
PARALLEL TIMING (MAX4821)
Turn-On Time tON From rising edge of CS, RL = 50Ω,
CL = 50pF 1µs
Turn-Off Time tOFF From rising edge of CS, RL = 50Ω,
CL = 50pF 1µs
LVL Setup Time tLS 100 ns
LVL Hold Time tLH 0ns
Address to CS Setup Time tAH 100 ns
Address to CS Hold Time tAS 0ns
Rise Time (A2, A1, A0, LVL) tSCR 20% of VCC to 70% of VCC, CL = 50pF 2 µs
Fall Time (A2, A1, A0, LVL) tSCF 20% of VCC to 70% of VCC, CL = 50pF 2 µs
RESET Pulse Width tRW 70 ns
SET Pulse Width tSW 70 ns
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3V to +5.5V, VCOM = VCC, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Note 2: Specifications at -40°C are guaranteed by design and not production tested.
Note 3: After relay turn-off, inductive kickback may momentarily cause the voltage at OUT_ to exceed VCOM. This is considered part
of normal operation and will not damage the device.
MAX4820/MAX4821
Maxim Integrated
3
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
Typical Operating Characteristics
(VCOM = VCC, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX4820 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (μA)
5.14.74.33.93.53.12.7
5
10
15
20
25
0
2.3 5.5
ALL LOGIC INPUTS = 0
SUPPLY CURRENT
vs. TEMPERATURE
MAX4820 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
603510-15
5
10
15
20
25
0
-40 85
VCC = 5V VCC = 5.5V
VCC = 2.3V
VCC = 3.3V
SUPPLY CURRENT
vs. INPUT LOGIC VOLTAGE
MAX4820 toc03
INPUT LOGIC VOLTAGE (V)
SUPPLY CURRENT (μA)
4321
100
200
300
400
500
600
700
800
900
1000
0
05
VCC = 3.3V
VCC = 5V
ALL LOGIC INPUTS
CONNECTED
ON-RESISTANCE
vs. SUPPLY VOLTAGE
MAX4820 toc04
SUPPLY VOLTAGE (V)
RON (Ω)
5.14.74.33.93.53.12.7
0.5
1.0
1.5
2.0
2.5
3.0
0
2.3 5.5
IOUT_SINK = 70mA
ON-RESISTANCE
vs. TEMPERATURE
MAX4820 toc05
TEMPERATURE (°C)
RON (Ω)
603510-15
0.5
1.0
1.5
2.0
2.5
3.0
0
-40 85
VCC = 3.3V
VCC = 2.3V
VCC = 5.5V
VCC = 5V
IOUT_SINK = 70mA
POWER-ON RESET VOLTAGE
vs. TEMPERATURE
MAX4820 toc06
TEMPERATURE (°C)
POWER-ON RESET VOLTAGE (V)
6035-15 10
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0
-40 85
OUTPUT OFF-LEAKAGE CURRENT
vs. SUPPLY VOLTAGE
MAX4820 toc07
SUPPLY VOLTAGE (V)
OUTPUT OFF-LEAKAGE (nA)
5.14.73.9 4.33.1 3.52.7
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2.3 5.5
OUTPUT OFF-LEAKAGE CURRENT
vs. TEMPERATURE
MAX4820 toc08
TEMPERATURE (°C)
OUTPUT OFF-LEAKAGE (nA)
6035-15 10
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0
-40 85
VCC = 5.5V
VCC = 5V
VCC = 2.3V
VCC = 3.3V
OUT_ TURN-ON/TURN-OFF DELAY TIMES
vs. SUPPLY VOLTAGE
MAX4820 toc09
SUPPLY VOLTAGE (V)
tON/tOFF DELAY TIME (ns)
5.14.74.33.93.53.12.7
30
40
50
60
70
80
20
2.3 5.5
RL = 50Ω
CL = 50pF
tON
tOFF
MAX4820/MAX4821
4
Maxim Integrated
3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
INPUT LOGIC THRESHOLD
vs. SUPPLY VOLTAGE
MAX4820 toc10
SUPPLY VOLTAGE (V)
INPUT LOGIC THRESHOLD (V)
5.14.72.7 3.1 3.5 3.9 4.3
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
0.50
2.3 5.5
PIN
MAX4820 MAX4821
THIN
QFN TSSOP THIN
QFN TSSOP
NAME FUNCTION
1313RESET
Reset Input. Drive RESET low to clear all latches and registers (all outputs
are turned off). RESET overrides all other inputs. If RESET and SET are pulled
low at the same time, then RESET takes precedence.
2424CS
Chip-Select Input.
MAX4820: Drive CS low to select the device. When CS is low, data at DIN is
clocked into the 8-bit shift register on SCLK’s rising edge. Drive CS from low
to high to latch the data to the registers and activate the appropriate relays.
MAX4821: Drive CS low to select the device and set level on LVL. Drive CS
from low to high to latch the address and level data to the output.
3 5 — — DIN Serial-Data Input
4 6 — — SCLK Serial-Clock Input
5 7 — — DOUT
Serial-Data Output. DOUT is the output of the 8-bit shift register. This output
can be used to daisy chain multiple MAX4820s. The data at DOUT appears
synchronous to SCLK’s falling edge.
6 8 — — N.C. No Connection
7 9 7 9 GND Ground
8 10 8 10 OUT8 Open-Drain Output 8. Connect OUT8 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.
9 11 9 11 OUT7 Open-Drain Output 7. Connect OUT7 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.
10, 16 12, 18 10, 16 12, 18 PGND Power Ground. PGND is a return for the output sinks. Connect PGND pins
together and to GND.
11 13 11 13 OUT6 Open-Drain Output 6. Connect OUT6 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.
Typical Operating Characteristics (continued)
(VCOM = VCC, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
BACK EMF CLAMPING
WITH STANDARD 3V RELAY
MAX4820 toc11
200μs/div
VCS
5V/div
0
0
OUT_
1V/div
OUT_ TURNS OFF
VCC = 3.3V
Pin Description
MAX4820/MAX4821
Maxim Integrated
5
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
Detailed Description
The MAX4820/MAX4821 8-channel relay drivers offer
built-in kickback protection and drive +3.3V/+5V non-
latching or dual-coil-latching relays. These devices are
especially useful when driving +3V relays. Each inde-
pendent open-drain output features a 2Ωon-resistance
and is guaranteed to sink 70mA (min) load current. Both
devices consume less than 50µA (max) quiescent cur-
rent and feature 1µA (min) output off-leakage current.
The MAX4820 features an SPI/QSPI/MICROWIRE-com-
patible serial interface. Input data is shifted into an 8-bit
shift register and latched to the outputs when CS transi-
tions from low to high. Each data bit in the shift register
corresponds to a specific output, allowing independent
control of all outputs.
The MAX4821 features a 4-bit (A0, A1, A2, LVL) parallel
input interface. The three bits (A0, A1, A2) determine
the output address, and LVL determines whether the
selected output is switched on or off. Data is latched to
the outputs when CS transitions from low to high.
Both devices feature separate set and reset functions
that allow the user to turn on or turn off all outputs
simultaneously with a single control line. Built-in hys-
teresis (Schmidt trigger) on all digital inputs allows this
device to be used with slow rising and falling signals,
such as those from optocouplers or RC power-up ini-
tialization circuits. The MAX4820/MAX4821 are avail-
able in 20-pin TSSOP and space-saving 20-pin Thin
QFN packages.
PIN
MAX4820 MAX4821
THIN
QFN
TSSOP
THIN
QFN
TSSOP
NAME
FUNCTION
12 14 12 14
OUT5
Open-Drain Output 5. Connect OUT5 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.
13 15 13 15
COM
Common Free-Wheeling Diodes. Connect COM to VCC. COM can also be
connected to a separate supply that is higher than VCC. In that case, bypass
VCC to GND with a 0.1µF capacitor.
14 16 14 16
OUT4
Open-Drain Output 4. Connect OUT4 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.
15 17 15 17
OUT3
Open-Drain Output 3. Connect OUT3 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.
17 19 17 19
OUT2
Open-Drain Output 2. Connect OUT2 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.
18 20 18 20
OUT1
Open-Drain Output 1. Connect OUT1 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.
19 1 19 1 VCC Input Supply Voltage. Bypass VCC to GND with a 0.1µF capacitor.
20 2 20 2 SET
Set Input. Drive SET low to set all latches and registers high (all outputs are
turned on). SET overrides all parallel and serial control inputs. RESET
overrides SET under all conditions.
— — 3 5 LVL
Level Input. LVL determines whether the selected address is switched on or
off. A logic high on LVL switches on the addressed output. A logic low on
LVL switches off the addressed output.
— — 4 6 A0 Digital Address “0” Input. (See Table 2 for address mapping.)
— — 5 7 A1 Digital Address “1” Input. (See Table 2 for address mapping.)
— — 6 8 A2 Digital Address “2” Input. (See Table 2 for address mapping.)
— — — — EP Exposed Pad. Connect exposed pad to GND.
Pin Description (continued)
MAX4820/MAX4821
6
Maxim Integrated
Digital Interface
Serial Interface (MAX4820)
The serial interface consists of an 8-bit shift register
and parallel latch controlled by SCLK and CS. The
input to the shift register is an 8-bit word. Each data bit
controls one of the eight outputs, with the most signifi-
cant bit (D7) corresponding to OUT8 and the least sig-
nificant bit (D0) corresponding to OUT1 (see Table 1).
When CS is low (device is selected), data at DIN is
clocked into the shift register synchronously with
SCLK’s rising edge. Driving CS from low to high latches
the data in the shift register to the parallel latch.
DOUT is the output of the shift register. Data appears
on DOUT synchronously with SCLK’s falling edge and
is identical to the data at DIN delayed by eight clock
cycles. When shifting the input data, D7 is the first bit in
and out of the shift register.
While CS is low, the switches always remain in their pre-
vious state. Drive CS high after 8 bits of data have been
shifted in to update the output state and inhibit further
data from entering the shift register. When CS is high,
transitions at DIN and SCLK have no effect on the out-
put, and the first input bit (D7) is present at DOUT.
If the number of data bits entered while CS is low is
greater or less than 8, the shift register contains only
the last 8 data bits, regardless of when they were
entered.
The 3-wire serial interface is compatible with SPI, QSPI,
and MICROWIRE standards. The latch that drives the
analog switch is updated on the rising edge of CS,
regardless of SCLK’s state.
Parallel Interface (MAX4821)
The parallel interface consists of three address bits
(A0, A1, A2) and one level selector bit (LVL). The
address bits determine which output is updated, and
the level bit determines whether the addressed output
is switched on (LVL = high) or off (LVL = low). When CS
is high, the address and level bits have no effect on the
state of the outputs. Driving CS from low to high latches
the address and level data to the parallel register and
updates the state of the outputs. Address data entered
after CS is pulled low is not reflected in the state of the
outputs following the next low-to-high transition on CS
(Figure 2).
3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
Table 1. Serial Input Address Map (MAX4820 Only)
DIN D0 D1 D2 D3 D4 D5 D6 D7
OUT_ OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
SCLK
DIN
DOUT
tCSS tCL tCH
tCSW
tCSH
tDO
tON,
tOFF
tCSO
tDS
tDH
D7 D6 D1 D0
CS
OUT_
Figure 1. 3-Wire Serial-Interface Timing Diagram (MAX4820 only)
MAX4820/MAX4821
Maxim Integrated
7
SET
/
RESET
Functions
The MAX4820/MAX4821 feature set and reset inputs that
allow the user to simultaneously turn all outputs on or off
using a single control line. Drive SET low to set all latch-
es and registers to 1 and turn all outputs on. SET over-
rides all serial/parallel control inputs. Drive RESET low to
clear all latches and registers and turn all outputs off.
RESET overrides all other inputs, including SET.
Applications Information
Daisy Chaining
The MAX4820 features a digital output, DOUT, that pro-
vides a simple way to daisy chain multiple devices. This
feature allows the user to drive large banks of relays
using only a single serial interface. To daisy chain multi-
ple devices, connect all CS pins together, and connect
the DOUT of one device to the DIN of another device
(see Figure 3). During operation, a stream of serial data
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
CS
A_
LVL
VOUT
tAS tAH
tLS
tLH
tON,
tOFF
Figure 2. Parallel Interface Timing Diagram (MAX4821 only)
MAX4820
DINDIN
SCLKSCLK
CS
SCLK
DOUT
OUT8
PGNDCS
VCC
VCC 0.1μF
GND
OUT1 MAX4820
DIN
SCLK
DOUT
OUT8
PGND
CS
VCC
VCC 0.1μF
GND
OUT1 MAX4820
DIN
SCLK
DOUT
OUT8
PGNDCS
VCC
VCC 0.1μF
GND
OUT1
SCLK
Figure 3. Daisy-Chain Configuration
Table 2. Parallel Interface Address Map
(MAX4821 Only)
A2 A1 A0 OUTPUT
Low Low Low OUT1
Low Low High OUT2
Low High Low OUT3
Low High High OUT4
High Low Low OUT5
High Low High OUT6
High High Low OUT7
High High High OUT8
MAX4820/MAX4821
8
Maxim Integrated
is shifted through all the MAX4820s in series. When CS
goes high, all outputs update simultaneously.
The MAX4820 can also be used in a slave configuration
that allows the user to address individual devices.
Connect all the DIN pins together, and use the CS input
to address one device at a time. Drive CS low to select
a slave and input the data into the shift register. Drive
CS high to latch the data and turn on the appropriate
outputs. Typically, in this configuration only one slave is
addressed at a time.
Inductive Kickback Protection
The MAX4820/MAX4821 feature built-in inductive kick-
back protection to reduce the voltage spike on OUT_
generated by a relay’s coil inductance when the output
is suddenly switched off. Internal diodes connected
from each output to COM allow the inductor current to
flow back to the supply. Connect the common cathode
(COM) of the internal protection diodes to VCC.
COM also can be connected to a higher voltage than
VCC (+6V max) for faster kickback recovery. In this con-
figuration, bypass COM to PGND with a 0.1µF capacitor.
3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
COMPANY PHONE WEBSITE
Aromat Corp. 310-524-9862 www.aromat.com
CP Clare Corp. 978-524-6700 www.crouzet.com
Coto Techonology 401-943-2686 www.cotorelay.com
Deustch Relays,
Inc. 516-499-6000 www.deutschrelays.com
Fujitsu
Takamisawa 408-745-4900 www.fujitsufta.com
Hella KG Hueck 734-414-0970 www.hella.com
COMPANY PHONE WEBSITE
NEC Electronics,
Inc. 800-366-9782 www.nec-global.com
Omron
Electronics, Inc. 847-843-7900 www.oeiweb.omron.com
Rockwell/Allen-
Bradley 414-382-2000 www.ab.com
Siemens
Electromechanical
Component, Inc.
770-371-3000 www.sec.siemens.com
Teledyne Relays 213-777-0077 www.teledynerelays.com
Relay Manufacturers
Typical Application Circuits
MAX4820
RESET
SET
CLK
CS
DIN
DOUT
OUT1
RELAY
COIL 1
RELAY
COIL 8
OUT8
COM
PGND
VCC
VCC
VCC
0.1μF
GND
MAX4821
RESET
SET
A0
A1
CS
LVL
OUT1
RELAY
COIL 1
RELAY
COIL 8
OUT8
COM
PGND
VCC
VCC
VCC
0.1μF
GND
A2
MAX4820/MAX4821
Maxim Integrated
9
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
MAX4820
OUT1
OUT2
VCC
RESET
PARALLEL
REGISTER
8-BIT
SHIFT
REGISTER
SET
DIN
DOUT
SCLK
CS
COM
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
PGND
GND
MAX4821
OUT1
OUT2
VCC
RESET
PARALLEL
LATCH
4-TO-8
DECODER
SET
LVL
A0
CS
COM
A2
A1
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
PGND
GND
Functional Diagrams
MAX4820/MAX4821
10
Maxim Integrated
3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
Chip Information
PROCESS: BiCMOS
Pin Configurations (continued)
TOP VIEW
20
19
18
17
SET
VCC
OUT1
OUT2
16 PGND
13
12
11
14
15
OUT5
COM
OUT4
OUT3
OUT6
4
3
2
1
A0
LVL
CS
RESET
5A1
6
7
8
9
A2
GND
OUT8
OUT7
10PGND
MAX4821
THIN QFN
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
OUT1
OUT2
PGND
OUT3CS
RESET
SET
VCC
OUT4
COM
OUT5
OUT6A2
A1
A0
LVL
12
11
9
10
PGND
OUT7OUT8
GND
TSSOP
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
OUT1
OUT2
PGND
OUT3CS
RESET
SET
VCC
OUT4
COM
OUT5
OUT6N.C.
DOUT
SCLK
DIN
12
11
9
10
PGND
OUT7OUT8
GND
MAX4820
TSSOP
*CONNECT EP TO GND.
*EP
*EP
+
++
*EP
MAX4821
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
20 TQFN-EP T2044+3 21-0139
20 TSSOP-EP U20E+1 21-0108
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
MAX4820/MAX4821
Maxim Integrated
11
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 1/03 Initial release. —
1 4/09 Corrected error in the Electrical Characteristics table. 1, 2, 3, 5, 11,
12, 13
Added exposed pad to TSSOP package in the Ordering Information,Pin Description,
and Pin Configurations.1, 6, 11
2 1/10
Added Reflow Temperature to the Absolute Maximum Ratings section. 2
MAX4820/MAX4821
12 Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
© 2010 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
