Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent ri ghts nor the rights of oth ers. Motorola products are not desig ned, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
appl ication, Buyer shall indemnify and hold Motorol a and its offi cers, emplo yees, subsidiaries, affiliates, and distributo rs harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or ind irectly , any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the des ign or ma nufacture of the part.
9S12A128DGV1/D
4/2002
1
MC9S12A128
Device Guide
V01.01
Original Release Date: 8 March, 2002
Revised: 17 April, 2002
Motorola, Inc
MC9S1 2A128 Device Guide — V01.01
2
Revision History
For additional information, refer to the MC 9S12A128 8-Bit Mic rocontroller Unit Mask Set Errata
(Motorola document order number, 9S12A128MSE1). The errata can be f ound on the World Wide Web at:
http://www.motorola.com/semiconductors/
Version
Number Revision
Date Effective
Date Au t hor Descri pt i on of C hange s
V01.00 8 MAR
2002 8 MA R
2002 Init ia l re le a s e
V01.01 17 APRIL
2002 12 APRIL
2002
Replaced documen t ord er number with ver sion except for cover
sheet
Corrected Table 1-1 Device Memory Map entries for EEPROM
array a nd RAM array
Table A-4 Oper ati ng Conditions — Increased VDD to 2.35V
Table A-6 5V I/O Characteristics — Corrected rati ng column for
VOH and VOL and typical value for Cin
Table A-8 ATD Operat ing Characteristics — Updated rating
definitions for items 6, 7, and 8 for cl ari ty
MC9S12A128 Device Guide — V01. 01
3
Table of Contents
Section 1 Introduction
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.6 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Section 2 Signal Description
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 8
2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3.3 TEST — Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3.4 VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3.5 XFC — PLL Loop Filter P in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .29
2.3.7 PAD15 / AN15 / ETRIG1 — Port AD Input Pin of A TD1 . . . . . . . . . . . . . . . . . . . . . .29
2.3.8 PAD[14:08] / AN[14:08] — Port AD Input Pins of ATD1 . . . . . . . . . . . . . . . . . . . . . .29
2.3.9 PAD7 / AN07 / ETRIG0 — Port A D Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . . .29
2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . .29
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .29
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.16 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.18 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.19 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.20 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.21 PH7 / KWH7 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
MC9S1 2A128 Device Guide — V01.01
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2.3.22 PH6 / KWH6 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.23 PH5 / KWH5 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.24 PH4 / KWH4 — Port H I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.25 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.26 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.27 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.28 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.29 PJ7 / KWJ7 / SCL — PORT J I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.30 PJ6 / KWJ6 / SDA — PORT J I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.31 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.32 PK7 / ECS / ROMON — Port K I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.33 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.34 PM7 — Port M I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.35 PM6 — Port M I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2. 3.36 PM5 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2. 3.37 PM4 / MOSI0 — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2. 3.38 PM3 / SS0 — Port M I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2. 3.39 PM2 / MISO0 — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.40 PM1 — Port M I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.41 PM0 — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.42 PP7 / KWP7 / PWM7 — Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.43 PP6 / KWP6 / PWM6 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.44 PP5 / KWP5 / PWM5 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.45 PP4 / KWP4 / PWM4 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.46 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.47 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.48 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.49 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.50 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.51 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 4
2.3.52 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.53 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.54 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.55 PS2 / RXD1 — Port S I/O Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3.56 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3.57 PS0 / RXD0 — Port S I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
MC9S12A128 Device Guide — V01.01
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2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.4 Power S upply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.4.1 VDDX, VSSX — P o wer & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . . . . .3 5
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O
Drivers & for Internal Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.4.3 VDD1, VDD2, VSS1, VSS2 — Core Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.4.4 VDDA, VSSA — Po wer Supply Pins for ATD and VREG. . . . . . . . . . . . . . . . . . . . . . .36
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.4.7 VREGEN — On Chip V oltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 6
Section 3 S ystem Clock Description
3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Section 4 Modes of Operation
4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.2.1 Normal Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.2.2 Special Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.2.3 Test Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 6
4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Sect io n 5 Re se ts an d Int er rup ts
5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.3.1 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Section 6 HCS12 Core Block Description
Section 7 Clock and Reset Generator (CRG) Block Description
MC9S1 2A128 Device Guide — V01.01
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7.1 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
7.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 8 Enhanced Capture Timer (ECT) Block Description
Section 9 Analog to Digital Converter (ATD) Block Description
Section 10 Inter-IC Bus (IIC) Block Description
Section 11 Serial Communications Interface (SCI) Block Description
Section 12 Serial Peripheral Interface (SPI) Block Description
Section 13 Pulse Width Modulator (PWM) Block Description
Section 14 Flash EEPROM 128K Block Description
Section 15 EEPROM 2K Block Description
Sect io n 16 RA M Bl oc k Desc r ipt io n
Section 1 7 Port Integration Module (PIM) Bl ock Descripti on
Sect io n 18 Volt ag e Re g ula tor (VREG) Blo ck Descriptio n
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 7
A.1.2 Power S upply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
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A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
A.2.2 Factors Influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
A.3 NVM, Flash, and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
A.3.1 NVM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
A.3.2 NVM Reliabil ity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
A.6 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
A.6.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
A.6.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
A.7 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
A.7.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Appe ndix B Packag e In fo rma tio n
B.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
B.2 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
B.3 80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
MC9S1 2A128 Device Guide — V01.01
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MC9S12A128 Device Guide — V01.01
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List of Figures
Figure 1-1 MC9S12A128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 1-2 MC9S12A128 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 2-1 Pin Assignments in 112-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 4
Figure 2-2 Pin Assignments in 80-Pin QFP for MC9S12A128 . . . . . . . . . . . . . . . . . . . . . . .25
Figure 2-3 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 18-1 Recommended PCB Layout 112 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 18-2 Recommended PCB Layout for 80 QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure A-2 Basic PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure A-3 Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure A-4 Maximum Bus Clock Jitter Approximation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure A-5 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure A-6 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure A-7 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure A-8 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure A-9 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure B-1 112-Pin LQFP Mechanical Dimensions (Case no. 987) . . . . . . . . . . . . . . . . . . 88
Figure B-2 80-pin QFP Mechanical Dimensions (Case no. 841B) . . . . . . . . . . . . . . . . . . . 89
MC9S1 2A128 Device Guide — V01.01
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MC9S12A128 Device Guide — V01.01
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List of Tables
Table 0-1 Document References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 1-2 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 1-3 Memory Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 2-2 MC9S12A128 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . . .37
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table A-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table A-3 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table A-7 Suppl y Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 5
Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table A-9 ATD Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table A-10 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table A-12 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table A-13 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . . . .73
Table A-14 Startup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table A-15 Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Table A-16 PLL C haracteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table A-17 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table A-18 SPI Sl ave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table A-19 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
MC9S1 2A128 Device Guide — V01.01
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MC9S12A128 Device Guide — V01.01
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Preface
The Device User Guide provides information about the MC9S12A128 device made up of standard HCS12
blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes the
CPU12 Reference Manual (Motorola order number, CPU12RM/AD) and all the individual Block Guides
of the implemented modules. In a effort to reduce redundancy all module specific information is located
only in the respective Block Guide. If applicable, special implementation details of the module are given
in the block description sections of this document.
See Table 0-1 for names and versions of the referenced documents throughout the Device Guide.
Table 0-1 Document References
User Guide Version Document Order Number
HCS12 Core User Guide V01 HCS12COREUG/D
CRG Block Guide V03 S12CRGV3/D
ECT_16B8C Block Guide V01 S12ECT16B8CV1/D
ATD_10B8C Block Guide V02 S12ATD10B8CV2/D
IIC Block Guide V02 S12IICV2/D
SCI Block Guide V02 S12SCIV2/D
SPI Block Guide V02 S12SPIV2/D
PWM_8B8C Block Guide V01 S12PWM8B8CV1/D
FTS128K Block Guide V02 S12FTS128KV1/D
EETS2K Block Guide V02 S12EETS2KV1/D
VREG Block Guide V01 S12VREGV1/D
PIM_9A128 Block Guide V01 S12A128PIMV1/D
MC9S1 2A128 Device Guide — V01.01
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MC9S12A128 Device Guide — V01.01
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Section 1 Introduction
1.1 Overview
The MC9S12A128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16- bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 8K
bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communication s interfaces (SCI), two
serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit
analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), 29 discrete digital I/O
channels (Port A, Port B, Port K and Port E), 20 discrete digital I/O lines with interrupt an d wakeup
capability and an Inter-I C Bus. System resource mapping, clock generation, interrupt control and bus
interfacing are managed by the System Integration Module (SIM). The MC9S12A128 has full 16-bit data
paths throughout. Howeve r, the external bus can operate in an 8-bit narrow mode so single 8-bit wide
memory can be interfaced for lowe r cost sys tem s. The inclus ion of a PL L circuit allows power
consumption and performance to be adjusted to suit operational requirements.
1.2 Features
• HCS12 Core
– 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii.Instruction queue
iv.Enhanced indexed addressing
– MEBI (Multiplexed External Bus Interface)
– MMC (Module Mapping Control)
– INT (Interrupt control)
– BKP (Breakpoints)
– BDM (Background Debug Mode)
• CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor)
• 8-bit and 4-bit ports with interrupt functiona lity
– Digital filtering
– Programmable rising or falling edge trigger
• Memory
– 128K Flash EEPROM
– 2K byte EEPROM
– 8K byte RAM
MC9S1 2A128 Device Guide — V01.01
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• Two 8-channel Analog-to-Digital Converters
–10-bit resolution
–External conversion trigger capability
•Enhanced Capture Timer
–16-bit main counter with 7-bit prescaler
–8 programmable input capture or output compare channels
–Two 8-bit or one 16-bit pulse accumulators
•8 PWM channels
–Programmable pe riod and duty cycle
–8-bit 8-channel or 16-bit 4-channel
–Separate control for each pulse width and duty cycle
–Center-aligned or left-aligned outputs
–Programmable clock select logic with a wide range of frequencies
–Fast emergency shutdown input
–Usable as interrupt inputs
•Serial in terfaces
–Two asynchronous Serial Communicat ions Interfaces (SCI)
–Two Synchronous Serial Peripheral Interface (SPI)
•In te r-IC Bus (II C)
–Compatible with I2C Bus standard
–Multi-master operation
–Software programmable for one of 256 different serial clock frequencies
•112-Pin LQFP and 80-pin QFP packages
–I/O lines with 5V input and drive capability
–5V A/D converter inputs
–Operation at 50MHz equivalent to 25MHz Bus Speed
–Development support
–Single-wire background debug™ mode (BDM)
–On-chip hardware breakpoints
MC9S12A128 Device Guide — V01.01
17
1.3 Mo des of Operation
User modes
•Normal and Emulation Operating Modes
–Normal Single-Chip Mode
–Normal Expanded Wide Mode
–Normal Expanded Narrow Mode
–Emulation Expanded Wide Mode
–Emulation Expanded Narrow Mode
•Special Operating Modes
–Special Single-Chip Mode with active Background Debug Mode
–Special Test Mode (Motorola use only)
–Special Peripheral Mode (Motorola use only)
Low power modes
•Stop Mode
•Pseudo Stop Mode
•Wait Mode
MC9S12A128 Device Guide — V01.01
19
Figure 1-1 MC9S12A128 Block Diagram
128K Byte Flash EEPROM
8K Byte RAM
Enhanced Capture
RESET
EXTAL
XTAL
VDD1,2
VSS1,2
SCI0
2K Byte EEPROM
BKGD
R/W
MODB
XIRQ
NOACC/XCLKS
System
Integration
Module
(SIM)
VDDR
CPU12
Periodi c In te rru p t
COP W at c hdog
Clock Mo nitor
Si ngle-wire Bac kg round
Breakpoints
PLL
VSSPLL
XFC
VDDPLL
Multiple xed Ad dress /Da ta B us
VDDA
VSSA
VRH
VRL
ATD0
Multiplexed
Wide Bus
Multiplexed
VDDX
VSSX
I nt e rnal Logic 2. 5 V
Narrow Bus
PPAGE
VDDPL L
VSSPLL
PLL 2.5V
IRQ
LSTRB
ECLK
MODA
PA4
PA3
PA2
PA1
PA0
PA7
PA6
PA5
TEST
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR15
ADDR14
ADDR13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA15
DATA14
DATA13
PB4
PB3
PB2
PB1
PB0
PB7
PB6
PB5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
ADDR7
ADDR6
ADDR5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
PE3
PE4
PE5
PE6
PE7
PE0
PE1
PE2
AN2
AN6
AN0
AN7
AN1
AN3
AN4
AN5
PAD03
PAD04
PAD05
PAD06
PAD07
PAD00
PAD01
PAD02
IOC2
IOC6
IOC0
IOC7
IOC1
IOC3
IOC4
IOC5
PT3
PT4
PT5
PT6
PT7
PT0
PT1
PT2
VRH
VRL
VDDA
VSSA
VRH
VRL
ATD1
AN2
AN6
AN0
AN7
AN1
AN3
AN4
AN5
PAD11
PAD12
PAD13
PAD14
PAD15
PAD08
PAD09
PAD10
VDDA
VSSA
RXD
TXD
MISO
MOSI
PS3
PS4
PS5
PS0
PS1
PS2
SCI1 RXD
TXD
PP3
PP4
PP5
PP6
PP7
PP0
PP1
PP2
PIX2
PIX0
PIX1
PIX3
ECS
PK3
PK7
PK0
PK1
XADDR17
ECS
XADDR14
XADDR15
XADDR16
SCK
SS PS6
PS7
SPI0
IIC SDA
SCL PJ6
PJ7
PM1
PM0
PM2
PM3
PM4
PM5
PM6
PM7
KWH2
KWH6
KWH0
KWH7
KWH1
KWH3
KWH4
KWH5
PH3
PH4
PH5
PH6
PH7
PH0
PH1
PH2
KWJ0
KWJ1 PJ0
PJ1
I/O Driver 5V
VDDA
VSSA
A/D Con verter 5V &
DDRA DDRB
PTA PTB
DDRE
PTE
AD1
AD0
PTK
DDRK
PTT
DDRT
PTP
DDRP
PTS
DDRS
PTM
DDRM
PTH
DDRH
PTJ
DDRJ
PK2
Clock and
Reset
Generation
Module
Voltag e Reg ul at or
VSSR
Deb ug M odule
VDD1,2
VSS1,2
VREGEN
VDDR
VSSR
Voltage Regulator 5V & I/O MISO
MOSI
SCK
SS
SPI1
PIX4
PIX5 PK4
PK5 XADDR18
XADDR19
Voltag e Regulator Re fere nce
KWP2
KWP6
KWP0
KWP7
KWP1
KWP3
KWP4
KWP5
KWJ6
KWJ7
Timer
Signa l s shown in Bold are not avail able on the 80 Pin Packa ge
Module to Port Routing
PWM2
PWM6
PWM0
PWM7
PWM1
PWM3
PWM4
PWM5
PWM
MC9S1 2A128 Device Guide — V01.01
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1.5 D evice Memory Map
Table 1-1 and Figure 1-2 show the device memory map of the MC9S12A128 after reset. Note that after
reset the bottom 1K of the EEPROM ($0000 - $03FF) are hidden by the register space.
Table 1-1 Device Memory Map
Address Module Size
(Bytes)
$0000 – $0017 CORE (Ports A, B, E, Modes, Ini ts, Test) 24
$0018 – $0019 Reserved 2
$001A – $001B Device ID regi ster (PARTI D) 2
$001C – $001F CORE (MEMSIZ, IRQ, HPRIO) 4
$0020 – $0027 Reserved 8
$0028 – $002F CORE (Background Debug Mode) 8
$0030 – $0033 CORE (PPAGE, Port K) 4
$0034 – $003F Clock and Res et Generator (PL L, RTI, COP) 12
$0040 – $007F Enhanced Capture Timer 16-bit 8 channels 64
$0080 – $009F Analog to Digi tal Converter 10 -bi t 8 channels (ATD0) 32
$00A0 – $00C7 Pulse Width Modulator 8-bit 8 channels (PWM) 40
$00C8 – $00CF Serial Communicat ions Interface 0 (SCI0) 8
$00D0 – $00D7 Serial Communi cations Interface 0 (SCI1) 8
$00D8 – $00DF Serial Peripheral In terface (SPI0) 8
$00E0 – $00E7 Inte r IC Bus 8
$00E8 – $00EF Reserved 8
$00F0 – $00F7 Serial Per ipheral Inter face (SPI1) 8
$00F8 – $00FF Reserved 8
$0100- $010F Flash Control Register 16
$0110 – $011B EEPROM Control Register 12
$011C – $011F Reserved 4
$0120 – $013F Analog to Digi tal Converter 10 -bi t 8 channels (ATD1) 32
$0140 – $023F Reserved 256
$0240 – $027F Port I ntegration Mo dule (P IM) 64
$0280 – $03FF Reserved 384
$0000 – $07FF EEPROM array 2048
$0000 – $1FFF RAM arr ay 8192
$4000 – $7FFF Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at start 16384
$8000 – $BFFF Flash EEPROM Pa ge Window 16384
$C000 – $FFFF Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at end
and 256 bytes of Vector Space at $FF80 – $FFFF 16384
MC9S12A128 Device Guide — V01.01
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Figure 1-2 MC9S12A128 Memory Map
$0000
$FFFF
$C000
$8000
$4000
$0400
$0800
$1000
$2000
$FF00
EXT
NORMAL
SINGLE CHIP EXPANDED SPECIAL
SINGLE CHI P
VECTORSVECTORS VECTORS
$FF00
$FFFF
BDM
(I f Ac ti ve )
$C000
$FFFF
16K Fixed Flash EEPROM
2K , 4K , 8K or 16K P r otect e d B oot Secto r
$8000
$BFFF
16K Page Windo w
eigh t * 16K Flash EEPROM Pages
$4000
$7FFF 16K Fixed Flash EEPROM
0.5K, 1K, 2K or 4K Protected Sector
$2000
$3FFF
8K Bytes RAM
Mappa ble to any 8K B oundary
$0800
$0FFF
2K Bytes EEPROM
Mappa ble to any 2K B oundary
$0000
$03FF
1K Register Space
Mappa ble to any 2K B oundary
The address does not show the map aft er r es et, but a usef ul m ap. After r eset the ma p is :
$0000 – $03FF: Register Space
$0000 – $1FFF: 8K RAM
$0000 – $07FF: 2K EEPROM (not visible)
$2000 – $3FFF: 8K Flash
MC9S1 2A128 Device Guide — V01.01
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1.6 Part ID Assignments
The part ID is located in t wo 8-bit registers PAR TIDH and P ARTIDL (addresses $001A and $001B after
reset). The read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned
part ID number.
The device memory size s are located in two 8-bit registers M EMSIZ0 and MEMSIZ1 (addresses $001C
and $001D af ter reset). Table 1-3 shows the read-only values of t hese registers. Refer to the HCS12 Core
User Guide (Motorola document orde r number HCS12COREUG/D) for further details.
Table 1-2 Assigned Part ID Numbers
Device Mask Set Number Part ID 1
NOTES:
1. The coding is as foll ows:
Bit 15-12: Ma jor family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
MC9S12A128 0L85D $0100
Table 1-3 Memory Size Registers
R egister name Value
MEMSIZ0 $13
MEMSIZ1 $80
MC9S12A128 Device Guide — V01.01
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Section 2 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals . It is built from the signal description sections of the Block
Guides of the individual IP bloc ks on the device.
2.1 D evice Pinout
The MC9S12A128 is available in a 112-pin low profile quad flat pack (LQFP) and is also available in a
80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the 2.3 Detailed
Signal Descriptions. Figure 2-1 and Figure 2-2 show the pin assignments.
MC9S1 2A128 Device Guide — V01.01
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Figure 2-1 Pin Assignments in 112-Pin LQFP
VRH
VDDA
PAD15/AN15/ETRIG1
PAD07/AN07/ETRIG0
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
PP4/KWP4/PWM4
PP5/KPW5/PWM5
PP6/KWP6/PWM6
PP7/KWP7/PWM7
PK7/ECS
VDDX
VSSX
PM0
PM1
PM2/MISO0
PM3/SS0
PM4/MOSI
PM5/SCK0
PJ6/KWJ6/SDA
PJ7/KWJ7/SCL
VREGEN
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
PM6
PM7
VSSA
VRL
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
XADDR17/PK3
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
XADDR19/PK5
XADDR18/PK4
KWJ1/PJ1
KWJ0/PJ0
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
KWH7/PH7
KWH6/PH6
KWH5/PH5
KWH4/PH4
XCLKS/NOACC/PE7
MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
SS1/KWH3/PH3
SCK1/KWH2/PH2
MOSI1/KWH1/PH1
MISO1/KWH0/PH0
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0
Signals show n in Bold are not availab le on the 80 Pin Package
MC9S12A128
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
MC9S12A128 Device Guide — V01.01
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Figure 2-2 Pin Assignments in 80-Pin QFP for MC9S12A128
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
MC9S12A128
VRH
VDDA
PAD07/AN07/ETRIG0
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
PP4/KWP4/PWM4
PP5/KWP5/PWM5
PP7/KWP7/PWM7
VDDX
VSSX
PM0
PM1
PM2/MISO0
PM3/SS0
PM4/MOSI0
PM5/SCK0
PJ6/KWJ6/SDA
PJ7/KWJ7/SCL
VREGEN
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
VSSA
VRL
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
XCLKS/NOACC/PE7
MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
MC9S1 2A128 Device Guide — V01.01
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2.2 Sign al Properties Summary
Table 2-1 summarizes the pin functionality. Signals shown in bold are not avail able in the 80 pin
package.
Ta ble 2-1 Sig nal Prop er ties
Pin Name
Function 1 Pin Na me
Function 2 Pin Na me
Function 3 Pin Na me
Function 4 Powered by De s cri pt ion
EXTAL ———
VDDPLL Oscillator Pins
XTAL ———
RESET ———
VDDR External Reset
TEST ———N.A. Test Input
VREGEN ———
VDDX Voltage Regulator Enable Input
XFC ———
VDDPLL PLL Loop Filter
BKGD TAGHI MODC —VDDR Backgr ound Debug, Tag High, Mode Input
PAD15 AN15 ETRIG1 —
VDDA
Port AD Input, Analog Inp ut AN7 of
ATD1, External Trigger Input of ATD1
PAD[14:8] AN[14:08] —— Port AD Inputs, Analog Inputs AN[6:0]
of ATD1
PAD07 AN07 ETRIG0 —Por t AD Input, Analog Input AN7 of ATD0,
External Trigger Input of ATD0
PAD[06:00] AN[06:00] —— Port AD Inputs , Analog Inputs A N[6: 0] of
ATD0
PA[7:0] ADDR[15:8]/
DATA[15:8] ——
VDDR
Port A I/O, Multiplexed Address/Data
PB[7:0] ADDR[7:0]/
DATA[7:0] —— Port B I/O, Multiplexed Address/Data
PE7 NOACC XCLKS —Port E I/O, Access, Clock Select
PE6 IPIPE1 MODB —Port E I/O, Pipe Status, Mo de Input
PE5 IPIPE0 MODA —Port E I/O, Pipe Status, Mo de Input
PE4 ECLK —— Port E I/O, Bus Clock Output
PE3 LSTRB TAGLO —Por t E I/O, Byt e Str obe, Tag Low
PE2 R/W —— Port E I/O, R/W in expanded modes
PE1 IRQ —— Port E Input, Ma skable Inte rr upt
PE0 XIRQ —— Port E Input, Non Maskable Interrupt
PH7 KWH7 —— Port H I/O, Interrupt
PH6 KWH6 —— Port H I/O, Interrupt
PH5 KWH5 —— Port H I/O, Interrupt
PH4 KWH4 —— Port H I/O, Interrupt
PH3 KWH3 SS1 —Port H I/O, Inter rupt, SS of SPI1
PH2 KWH2 SCK1 —Port H I/O, Inter r u p t, SCK of SPI1
PH1 KWH1 MOSI1 —Port H I/O, Inter rupt , MOSI of SPI1
PH0 KWH0 MISO1 —Port H I/O, Interrupt , MISO of SPI1
MC9S12A128 Device Guide — V01.01
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PJ7 KWJ7 SCL
VDDX
Port J I/O, Interrupt, SCL of IIC
PJ6 KWJ6 SDA Port J I/O, Int err upt, SDA of IIC
PJ[1:0] KWJ[1:0] —— Port J I/O, Interrupts
PK7 ECS ROMON —Port K I/O, Emulation Chip Select, ROM
On Enable
PK[5:0] XADDR[19:14] —Port K I/O, Extended Addresses
PM7 ——— Port M I/O
PM6 ——— Port M I/O
PM5 SCK0 —— Port M I/O, SCK of SPI0
PM4 MOSI0 —— Port M I/O, MOSI of SPI0
PM3 SS0 —— Port M I/O, SS of SPI0
PM2 MISO0 —— Port M I/O, MISO of SPI0
PM1 ——— Port M I/O
PM0 ——— Port M I/O
PP7 KWP7 PWM7 —Port P I/O, I nterrupt, Channel 7 of PWM
PP6 KWP6 PWM6 —Por t P I/O, Interrup t, Cha n n el 6 of PWM
PP5 KWP5 PWM5 —Port P I/O, I nterrupt, Channel 5 of PWM
PP4 KWP4 PWM4 —Por t P I/O, I nterrupt, Channel 4 of PWM
PP3 KWP3 PWM3 SS1 Port P I/O, Interrupt, Channel 3 of PWM,
SS of SPI1
PP2 KWP2 PWM2 SCK1 Port P I/O, Interrupt, Channel 2 of PWM,
SCK of SPI1
PP1 KWP1 PWM1 MOSI1 Port P I/O, Interrupt, Channel 1 of PWM,
MOSI of SPI1
PP0 KWP0 PWM0 MISO1 Port P I/O, Interr upt, Channel 0 of PWM,
MISO of SPI1
PS7 SS0 —— Port S I/O, SS of SPI0
PS6 SCK0 —— Port S I/O, SCK of SPI0
PS5 MOSI0 —— Port S I/O, MOSI of SPI0
PS4 MISO0 —— Port S I/O, MISO of SPI0
PS3 TXD1 —— Port S I/O, TXD of SCI1
PS2 RXD1 —— Port S I/O, RXD of SCI1
PS1 TXD0 —— Port S I/O, TXD of SCI0
PS0 RXD0 —— Port S I/O, RXD of SCI0
PT[7:0] IOC[7:0] —— Por t T I/O, Timer channe ls
Pin Name
Function 1 Pin Na me
Function 2 Pin Na me
Function 3 Pin Na me
Function 4 Powered by De s cri pt ion
MC9S1 2A128 Device Guide — V01.01
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2.3 Detailed Signal Descriptions
2. 3. 1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state,
and an output when an internal MCU function causes a reset.
2.3. 3 TEST — Test Pi n
This input only pin is reserved for test.
NOTE: The TEST pin must be tied to VSS in all applications.
2.3.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
2.3.5 XFC — PLL Loop Filter Pin
PLL loop filter, see A.5.3 Ph ase Locked Loop. If needed, contact your Motorola representative for the
interactive application note to compute PLL loop filter elements. Any current leakage on this pin m ust be
avoided.
F igure 2-3 PLL Loop Fi lter Co nnect ions
MCU
XFC
R0
CS
CP
VDDPLL
VDDPLL
MC9S12A128 Device Guide — V01.01
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2.3.6 BKGD / TAGHI / MODC — Bac kgro und Debu g, Ta g Hig h, and Mod e Pin
The BKGD/T AGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.
2.3.7 PAD15 / AN15 / ETRIG1 — Port AD Input Pi n of ATD1
PAD15 is a general purpose input pin and analog input AN7 of the analog to digital converter AT D1. It
can act as an external trigger input for the ATD1.
2.3.8 PAD[14 :08] / AN [14: 08] — Port AD Input Pins of ATD1
PAD14 - PAD08 are general purpos e input pins and analog inputs AN[6:0] of the analog to digital
converter ATD1.
2.3.9 PAD7 / AN07 / ETRIG0 — Port AD Input Pin of ATD0
PAD7 is a general purpose input pi n and analog input AN7 of the analog to digital converter ATD0. I t can
act as an e xternal trigger input for the ATD0.
2.3. 10 PAD[06:00] / AN[06:00] — Port AD In put Pins of ATD0
PAD06 - PAD00 are general purpos e input pins and analog inputs AN[6:0] of the analog to digital
converter ATD0.
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed externa l address and data bus.
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are genera l purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed externa l address and data bus.
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
MC9S1 2A128 Device Guide — V01.01
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The X C LKS input selects between an external clock or oscillator configuration. The state of this pin is
latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external
clock drive. If input is a logic high an oscillator circuit is configured on EXTAL and XTAL. Since this pin
is an input with a pull-up device, if the pin is left floating, the default configuration is an os cillator cir cuit
on EXTAL and XTAL.
2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shar ed with the
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active
when RESE T is low.
2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active
when RESE T is low.
2.3.16 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be c onfigured to drive the inter nal bus clock ECLK.
ECLK can be used as a timing reference.
2.3.17 PE3 / LSTRB / TAGL O — Port E I/O Pin 3
PE3 is a general pur pose input or out put pin. In MC U expanded modes of operation, LS TRB can be used
for the low-byte strobe fu nction to indicate the type of bus access and when instruction tagging is on,
TAGLO is used to tag the low ha lf of the instruction word being read into the instruction queue.
2.3.18 PE2 / R/W — Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expa nded modes of ope rations, this pin drives the
read/write output si gnal for the external bus. It indicates the direction of data on the external bus.
2.3.19 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.20 PE0 / XIRQ — Port E Input Pi n 0
PE0 is a general purpose input pin and t he non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
MC9S12A128 Device Guide — V01.01
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2.3.21 PH7 / KWH7 — Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode.
2.3.22 PH6 / KWH6 — Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode.
2.3.23 PH5 / KWH5 — Port H I/O Pin 5
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode.
2.3.24 PH4 / KWH4 — Port H I/O Pin 4
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode.
2.3.25 PH3 / KWH3 / SS1 — Por t H I/O Pi n 3
PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Se rial P eriphe ral Interf ace
1 (SPI1).
2.3.26 PH2 / KWH2 / SCK1 — Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface
1 (SPI1).
2.3.27 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during m aster mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.28 PH0 / KWH0 / MISO1 — Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during m aster mode) or slave output
(during sl ave mode) pin M ISO of the Serial Peripheral Interface 1 (SPI1).
MC9S1 2A128 Device Guide — V01.01
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2.3.29 PJ7 / KWJ7 / SCL — PORT J I/O Pin 7
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the serial clock pin SCL of the IIC module.
2.3.30 PJ6 / KWJ6 / SDA — PORT J I/O Pin 6
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the serial data pin SDA of the IIC module.
2.3.31 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0]
PJ1 a nd PJ0 are ge neral purpose input or output pins. They can be configured to generate an interrupt
causing the MCU to exit STOP or WAIT mode.
2.3.32 PK7 / ECS / ROMON — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used
as the emulation chip select output (EC S). During MCU normal expanded modes of operation, this pin is
used to enable the Flash E EPROM memory in the memory map (ROMON). At the risi ng edge of RESET,
the state of this pin is latched to the ROMON bit.
2.3.33 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address XADDR[19:14] for the external bus.
2.3.34 PM7 — Port M I/O Pin 7
PM7 is a general purpose input or output pin.
2.3.35 PM6 — Port M I/O Pin 6
PM6 is a general purpose input or output pin.
2.3.36 PM5 / SCK0 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).
2.3.37 PM4 / MOSI0 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the maste r output (during master
mode) or slave input pin (during slave mode) MOSI for the Se rial Pe riph era l In te rf a ce 0 (SPI0 ) .
MC9S12A128 Device Guide — V01.01
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2.3.38 PM3 / SS0 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the sla ve select pin SS of t he Se rial
Peripheral Interface 0 (SPI0).
2.3.39 PM2 / MISO0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the master input (during master mode)
or slave output pin (during slave mode) MISO for t he Seria l Pe riph era l In te r fa c e 0 (SPI 0).
2.3.40 PM1 — Port M I/O Pin 1
PM1 is a general purpose input or output pin.
2.3.41 PM0 — Port M I/O Pin 0
PM0 is a general purpose input or output pin.
2.3.42 PP7 / KWP7 / PWM7 — Por t P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output.
2.3.43 PP6 / KWP6 / PWM6 — Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output.
2.3.44 PP5 / KWP5 / PWM5 — Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output.
2.3.45 PP4 / KWP4 / PWM4 — Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output
2.3.46 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It
can be configured as slave select pin SS of the Se rial P eripheral Interf ace 1 (SPI1).
MC9S1 2A128 Device Guide — V01.01
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2.3.47 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It
can be configured as serial clock pin SCK of the Seria l Pe riph e ral In te rface 1 (SPI1) .
2.3.48 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It
can be configured as master output (during m aster mode) or slave input pin (during slave mode) MOSI of
the Se rial Pe riphe ra l In terface 1 (SPI1).
2.3.49 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It
can be configured as master input (during m aster mode) or slave output (during slave mode) pin MISO of
the Se rial Pe riphe ra l In terface 1 (SPI1).
2.3.50 PS7 / SS0 — Port S I/O Pin 7
PS7 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface 0 (SPI0).
2.3.51 PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).
2.3.52 PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.53 PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the Seria l Pe rip he ra l In terface 0 (SPI0 ) .
2.3.54 PS3 / TXD1 — Po rt S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Seri al
Communication Interface 1 (SCI1).
MC9S12A128 Device Guide — V01.01
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2.3.55 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin R XD of Serial
Communication Interface 1 (SCI1).
2.3.56 PS1 / TXD0 — Po rt S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Seri al
Communication Interface 0 (SCI0).
2.3.57 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin R XD of Serial
Communication Interface 0 (SCI0).
2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input ca pture or output
compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).
2.4 Po wer Sup ply Pi ns
MC9S12A128 power and ground pins are described below.
NOTE: All VSS pins must be connected together in the application.
2.4.1 VDDX, V SSX — Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions pla ce high, short-duration
current demands on the power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal
Volt ag e Reg ul ato r
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal
transitions pla ce high, short-dura tion current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as clos e to the MCU as possible. Bypass requirements
depend on how heavily the MC U pins are loade d.
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2.4.3 VDD1, VDD2, VSS1, VSS2 — Core Power Pins
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high,
short-duration current dem ands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the M CU as possible. This 2.5V supply is derive d from the
internal voltage regulator. There is no static load on those pins allowed. The internal volt age regulator is
turned off, if VREGEN is tied to ground.
NOTE: No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital
converter. It also provides the reference for the internal voltage regulator. This allows the supply voltage
to the ATD and t he reference voltage to be bypassed independently.
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and P LL to be bypassed independently. This 2.5V voltage is generated by
the internal voltage regulator.
NOTE: No load allowed except for bypass capacitors.
2.4.7 VREGEN — On Chip Voltage Regulator Enable
Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and V DDPLL must be
supplied externally.
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Table 2-2 MC9S12A128 Power and Ground Connection Summary
Mnemonic Pin Number Nominal
Voltage Description
1 12- pi n QFP
VDD1, 2 13, 65 2.5 V Internal power and ground generated by internal regulator
VSS1, 2 14, 66 0V
VDDR 41 5.0 V External power and ground, supply to pin drivers and internal
voltage regulator.
VSSR 40 0 V
VDDX 107 5.0 V External power and ground, supply to pin drivers.
VSSX 106 0 V
VDDA 83 5.0 V Operating voltage and ground for the analog-to-digital
converters and the reference for t he internal voltage regulator,
allows the supply voltage to the A/D to be bypassed
independently.
VSSA 86 0 V
VRL 85 0 V Reference voltages for the analog-to-digital converter.
VRH 84 5.0 V
VDDPLL 43 2.5 V Provides operating voltage and ground for the Phased -Locke d
Loop. This allows the supply voltage to the PLL to be
bypassed indep endent ly. Internal power and ground
generated by internal regulator.
VSSPLL 45 0 V
VREGEN 97 5V Internal Voltage Regul ato r enable/disable
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Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the HCS12 Clock and Reset Generator (CRG) Bloc k Guide (Motorola document order numbe r,
S12CRGV3/D) for details on clock generation.
Figure 3-1 Clock Connections
CRG bus clock
core clock
EXTAL
XTAL oscillator clock
S12_CORE
IIC
RAM
SCI0, SCI1
PWM
ATD0, 1
EEPROM
Flash
ECT
SPI0, 1
PIM
BDM1/2
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Section 4 Modes of Oper ation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12A128. Each mode has an
associated default memory map and external bus configuration.
Three low power modes exist for the device.
4.2 Mo des of Operation
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal.
There are two basic types of operating modes:
1. Normal modes: Some register s and bits are prote cted against accidental changes.
2. Special modes: Allow greater access to protected control registers and bits for special purposes such
as testing.
A system development and debug feature, background debug mode (BDM), is available in all mode s. In
specia l single-chip mode, BDM is active immediate ly after reset.
Some as pects of Port E are not mode depe ndent. Bit 1 of Port E is a general purpos e input or the IRQ
interrupt i nput. IRQ can be enabled by bits in the CPU’s condition codes regis ter but it is inhi bited at reset
so thi s pin is i nitially configured as a simple input with a pull-up. Bit 0 of Por t E is a general purpose i nput
or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU’s condition codes register but it is
inhibited at re set so this pin is initially configured as a simple input with a pull-up. The ESTR bit i n the
EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched
Table 4-1 Mode S election
MODC MODB MODA Mode Description
000
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
other modes bu t a serial command is required to make BDM active.
0 0 1 Emulati on Expanded Narrow, BDM allowed
0 1 0 Special Test (Expa nded Wide), BDM allowe d
0 1 1 Emulati on Expanded Wide, BDM all owed
1 0 0 Normal Single Chip, BDM all owed
1 0 1 Normal Expanded Narrow, BDM allowed
110
Peripheral; BDM allo we d but bus o perations would cause bus conflicts
(must not be used)
1 1 1 Normal Expanded Wide, BDM allowed
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even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0
pins act as high-impedance mode select inputs during reset.
The following paragra phs discuss the default bus setup and desc ribe which aspects of the bus can be
changed after reset on a per mode basis.
4.2.1 Normal Operating Modes
These m odes provide thre e operating configurations. Background debug is available in all three modes,
but must first be enabled for some operations by means of a BDM background command, then activated.
4. 2.1.1 Normal Single-C hip Mode
There is no external expansion bus in this mode. All pins of Ports A, B and E are configured as ge neral
purpose I/O pins Port E bits 1 and 0 are available as general purpose input onl y pins with inter nal pull-ups
enabled. All other pins of Port E are bidirec tional I/O pins that are initially configur ed as high-impedance
inputs with internal pull-ups enabled. Ports A and B are configured as high-impedance inputs with their
internal pull-ups disabled.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
I PIPE0, LSTRB, and R/W while the MCU is in single chip modes . In single chip modes, the associated
control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single
chip mode does not change the operation of the associated Port E pins.
In normal single chip mode, the MODE register is wri table one time. This allows a user program to change
the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses.
Port E, bit 4 can be configured for a free-running E clock out put by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application syste m.
4. 2.1.2 Normal Expanded Wide Mode
In expanded wide modes , Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E bit 4 i s configured as the E clock output signal. These signals allow external memory and peripheral
devices to be interfaced to the MCU.
Port E pins other than PE4/ECLK are configu red as general purpose I/O pins (initially high-impedance
inputs w ith internal pull-up resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the
PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose
I/O pins.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but
it would be unusual to do so in this mode. Development systems where pipe status signals are monitored
would typically use the special variation of this mode.
The Por t E bit 2 pin can be r econfigured as the R/W bus control signal by writing “1” to the RDWE bit in
PEAR. I f the expanded system includes e xternal devices that can be wr itten, such as RAM, the RD WE bit
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would need to be set before any attempt to write to an external location. If there are no writable re sources
in the external system, PE2 can be left as a general purpos e I/O pin.
The Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writ ing “1” to the L STRE bit
in PEAR. The default condition of this pin is a general purpose input because the LSTRB function is not
needed in all expanded wide applications.
The Port E bit 4 pin is initially configured as ECLK output with s tretch. The E clock output function
depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE regi ster and
the ESTR bit in the EBICTL regis ter. The E clock is ava ilable for use in external s elect decode logic or as
a constant speed clock for use in the external applicati on system .
4.2.1.3 Norm al Expanded Narrow Mode
This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such
systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of
additional external me mory devices.
Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data. Internal visibility
is not available in this mode because the internal cycles would need to be split into two 8-bit cycles.
Since the PEAR register can only be written one time in this mode, use care to set all bits to the desired
states during the single allowed write.
The PE3/LSTRB pin is always a gene ra l purpose I/O pin in normal expanded narrow mode. Although it
is possi ble to write the LSTRE bit in P EAR to “1” in this mode, the state of L STRE is overridden and Port
E bit 3 cannot be reconfigured as the LSTRB output.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but
it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system
activity. Development systems where pipe status signals are monitored would typically use special
expanded wide mode or occasionally special expanded narrow mode.
The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function
depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE regi ster and
the ESTR bit in the EBICT L register. In normal expanded narrow mode, the E clock is available for use
in external select decode logic or as a constant speed clock for use in the external application system.
The PE2/R/W pin is initially configured as a general purpose input wit h a pull-up but this pi n can be
reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in PEAR. If the expanded
narrow system includes external devices that can be written such as RAM, the RDWE bit would need to
be set before any attempt to write to an external location. If there are no writable resources in the external
system, PE2 can be left as a general purpose I/O pin.
4.2.1.4 Internal Visibility
Internal visibility is available when the MC U is operating in expanded wide modes or e mulation narrow
mode. I t is not available in s ingle-chip, perip heral or normal expa nded narrow mode s. Inter nal visibility is
enabled by setting the IVIS bit in the MODE register.
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If an internal access is made while E, R/W, a nd LS TR B are configured as bus control outputs and internal
visibility is off (IVIS=0), E will remain low for the cycle , R/W will re main high, and addr ess, data and the
LSTRB pins will remain at their previous s tate.
When interna l visibi lity is enabled (IVIS=1) , ce rtain interna l cycles will be blocked from going external.
During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and
address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the
BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will rema in at their
previous state.
4.2.1.5 Emulation Expanded Wide Mode
In expanded wide modes , Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E provides bus control and status signals. These signals allow external memory and peripheral devices
to be interfaced to the MCU. These signals can also be used by a l ogic analyzer to monitor the progress of
application programs.
The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,
PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output
functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR
register in emula tion mode are restricted.
4.2.1.6 Emulation Expanded Narrow Mode
Expanded narrow modes are intended to allow connection of single 8-bi t external memory devices for
lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal
resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR,
PUCR, R DRIV) will be accessed with a 16-bit data bus on Ports A and B. Accesses of 16-bit external
words to addresses which are normally mapped external will be broken into two separate 8-bit accesses
using Por t A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only
visible externally as 16-bit information if IVIS=1.
Ports A and B are configured as multiplexed address and data output ports . During external acces ses,
address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8
and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that
have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data
D0 is associated with PB0.
The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,
PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output
functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR
register in emula tion mode are restricted.
The main difference between special modes and normal modes is that some of the bus control and system
control signals cannot be written in emulation modes .
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4.2.2 Special Operating Modes
There are two special operating modes that correspond to normal operating modes. These operating modes
are commonly used in factory testing and system development.
4.2.2.1 Special Single-Chip Mode
When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does
not fetch the reset vector and execute application code as it would in other modes. Inste ad the active
background mode is in control of CPU execution and BDM fir mwar e is waiting for additional seri al
commands through the BKGD pin. When a serial command instructs the MCU to return to normal
execution, the system will be configured as described below unle ss the reset states of internal control
registers have been changed through background commands after the MCU was reset.
There is no e xternal expans ion bus after r eset in this mode. Por ts A and B are initi ally s imple bidire ctional
I/O pins that are configured as high-i mpedance inp uts with internal pull- ups disabled; however, writing to
the mode se lect bits in the MODE register ( which is allowed in spec ial modes) can change this afte r reset.
All of the Port E pins (except PE4/EC LK) are initially configured as general purpose high-impedan ce
inputs w ith pull-ups enable d. PE4/ECLK is configured as the E clock output in this mode.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
I PIPE0, LSTRB, and R/W while the MCU is in single chip modes . In single chip modes, the associated
control bits PIPOE, LSTRE and R DWE are reset to zero. Writing the opposite value into these bits in
single chip mode does not change the operation of the associated Port E pins.
Port E, bit 4 can be configured for a free-running E clock out put by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application syste m.
4.2.2.2 Special Test Mode
In expanded wide modes , Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E provides bus control and status sig nals. In special test mode, the write protection of many control
bits is lifted so that they can be thoroughly tested without needing to go through reset.
4.2.3 Test Operating Mode
There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip
peripherals.
4.2.3.1 Peripheral Mode
This m ode is intended for Motorola factory te s ting of the M CU. In this mode , the CPU is ina ctive and an
external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In
effect, the whole MCU acts as if it was a peripher al under control of an external CPU. This allows fa ster
testing of o n-chip memory and peripherals than pr evious testing methods. Since the mode control register
is not acc essible in pe ripheral mode, the only way to change to another mode is to reset the MCU into a
different mode. Background debugging should not be used while the MCU is in special peripheral mode
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as internal bus conflicts between BDM and the external master can ca use improper operation of both
functions.
4.3 Secu rity
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
•Protection of the contents of FLASH,
•Protection of the contents of EEPROM,
•Operation in single-chip mode,
•Operation from external me mory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the cont ents of the internal program. This code would def eat the purpose
of security. At the same tim e the user may also wish to put a back door i n the user’s program. An example
of this is the user downloads a key through the SCI which allows a cces s to a programming routine that
updates parameters stored in EEPROM.
4.3. 1 Secur ing th e Micr o co ntro lle r
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits loca ted in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the HCS12 128K Flash Block Guide (Motorola document order number, S12FTS128KV1/D) for
more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will be the most common usage of t he secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
4.3.2.2 Executing from External Memory
The user may wish to execute from externa l space with a secure d microc ontroller. This is accomplishe d
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.
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4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontrolle r, the internal FLASH and EEPROM must be era sed. This can be
done through an external program in expanded mode.
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user coul d also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the secur ity bits are reprogrammed to the unsecure state, the part will be
secu red again.
4.4 Low Power Modes
Consult the respective Block Guide for information on the module behavior in Stop, Pseudo Stop, and
Wait Mode.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the HCS12 Core User Guide (Motorola document order
number HCS12CO REUG/D) for infor mation on res ets and interrupts .
5.2 Vecto rs
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
Vector Address I nterr upt Source CCR
Mask Local Enab le HPRIO Value
to Elevate
$FFFE, $FFFF Reset None None –
$FFFC, $FFFD Clock Monit or fa il reset None PLLCTL (CME, SCME) –
$FFFA, $FFFB COP failure reset None COP rat e select –
$FFF8, $FFF9 Unimplemented instruction trap None None –
$FFF6, $FFF7 SWI None None –
$FFF4, $FFF5 XIRQ X-Bit None –
$FFF2, $FFF3 IRQ I-Bit IRQCR (IRQEN) $F2
$FFF0, $FFF1 Real Time Interrupt I-Bit CRGINT (RTIE) $F0
$FFEE, $FFEF Enhanc ed Capture Ti m er c hannel 0 I-Bit TIE (C0I) $EE
$FFEC, $FFED Enhanced Capture Ti m er c hannel 1 I-Bit TIE (C1I) $EC
$FFEA, $FFEB Enhanced Capture Timer channel 2 I-Bit TIE (C2I) $EA
$FFE8, $FFE9 Enhanced Capture Timer channel 3 I-Bit TIE (C3I) $E8
$FFE6, $FFE7 Enhanced Capture Timer channel 4 I-Bit TIE (C4I) $E6
$FFE4, $FFE5 Enhanced Capture Timer channel 5 I-Bit TIE (C5I) $E4
$FFE2, $FFE3 Enhanced Capture Timer channel 6 I-Bit TIE (C6I) $E2
$FFE0, $FFE1 Enhanced Capture Timer channel 7 I-Bit TIE (C7I) $E0
$FFDE, $FFDF Enhanced Capture Timer overflow I-Bit TSRC2 (TOF) $DE
$FFDC, $FFDD Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC
$FFDA, $FFDB Pulse accumulator input edge I-Bit PACTL (PAI) $DA
$FFD8, $FFD9 SPI0 I-Bit SP0CR1 (SPIE, SPTIE) $D8
$FFD6, $FFD7 SCI0 I-Bit SC0CR2
(TI E , T C IE , R IE, ILI E ) $D6
$FFD4, $FFD5 SCI1 I-Bit SC1CR2
(TI E , T C IE , R IE, ILI E ) $D4
$FFD2, $FFD3 ATD0 I-Bit ATD0CTL2 (ASCIE) $D2
$FFD0, $FFD1 ATD1 I-Bit ATD1CTL2 (ASCIE) $D0
$FFCE, $FFCF Port J I-Bit PTJIF (PTJIE) $CE
$FFCC, $FFCD Port H I-Bit PTHIF(PTHIE) $CC
$FFCA, $FFCB Modulus Down Counter underflow I-Bit MCCTL(MCZI ) $CA
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5.3 Effects of Reset
When a reset occurs , MCU registers and c ontrol bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states.
5.3.1 I/O Pins
Re fer to the HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) for mode
dependent pin configura tion of port A, B, E and K out of reset.
Re fer to the MC9S12A128 P ort Integration Module ( PIM) Block Guide (Motorola document order
number, S12A128PIMV1/D) for rese t configurations of all peripheral module ports.
NOTE: For devices assembled in 80-pin QFP packages all non-bonded out pins should be
configured as outputs after rese t in order to avoid current drawn from floating
inputs. Refer to Ta ble 2-1 Sig nal Prop ert ies for affected pins.
5.3. 2 Memor y
Re fe r to Table 1-1 Device Memory Map for locations of the me mories depending on the operating
mode after re set.
The RAM array is not automatically initialize d out of reset .
$FFC8, $FFC9 Pulse Accumulat or B Over fl ow I-Bit PBCTL(PBOVI) $C8
$FFC6, $FFC7 CRG PLL lock I-Bit CRGINT(LOCKIE) $C6
$FFC4, $FFC5 CRG Self Clock Mode I-Bit CRG INT (SCMIE) $C4
$FFC2, $FFC3 Reserved
$FFC0, $FFC1 IIC Bus I-Bit IBCR (IBIE) $C0
$FFBE, $FFBF SPI1 I -Bit SP1CR1 (SPIE, SPTIE) $BE
$FFBC, $FFBD Reserved
$FFBA, $FFBB EEPROM I-Bit EECTL(CCIE, CBEIE) $BA
$FFB8, $FFB9 FLASH I-Bit FCTL(CCIE, CBEIE) $B8
$FF90 to
$FFB7 Reserved
$FF8E, $FF8F Port P Interr upt I-Bit P TPIF (PTPIE) $8E
$FF8C, $FF8D PWM Emergency Shutdown I-Bit PWMSDN (PWM IE) $8C
$FF80 to
$FF8B Reserved
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Section 6 HCS12 Core Block Description
Consult the HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) for
information about the HCS12 core modules, i.e. centr al processing unit (CPU), interrupt module (INT),
module mapping control m odule (MMC), multiplexed external bus interface (MEBI), breakpoint module
(BKP) and background debug mode module (BDM) .
Section 7 Clock and Reset Generator (CRG) Block
Description
Consult the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola document order number,
S12CRGV3/D) for information about the Clock and Reset Generator module.
7.1 Device-Specific Information
7.1. 1 XCLK S
The X C LKS input signal is active low (see 2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7).
Refer to Figure 2- 3. Pierce Oscillator Connections (XCLKS=1) of the HCS12 Clock and Reset Generator
(CRG) Block Guide (Motorola document order number, S12 CRGV3/D).
Section 8 Enhanced Capture Timer (ECT) Block Description
Consult the HCS12 16-Bit, 8-Channel Enhanced Capture Timer (ECT) Block Guide (Motorola document
order number, S12ECT16 B8CV1/D) for information about the Enhanced Capture Timer module.
Section 9 Analog to Digital Converter (ATD) Block
Description
There are two Analog to Digital Conve rters (ATD1 and ATD0) implemented on the MC9S12A128.
Consult the HCS12 10-Bit, 8-Channel Analog-to-Digital Converter (ATD) Block Guide (Motorola
document order number, S12ATD10B8CV2/D) for information about each Analog to Digital Converter
module.
Section 10 Inter-IC Bus (IIC) Block Description
Consult the HCS12 Inter-Integrated Circuit (IIC) Block Guide (Motorola document order number,
S12IICV2/D) for information about the Inter-IC Bus module.
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Section 11 Serial Commu nica tions Inter fa ce (SCI) Block
Description
There are two Serial Communications Interfaces (SCI1 and SCI0) imple mented on the M C9S12A128
device. Consult the HCS12 Serial Communications Inter face (SC I) Block Guide (Motorola document
order number, S12SCI V2/D) for inform ation about each Serial Communications Interface module.
Section 12 Serial Peripheral Interface (SPI) Block
Description
There are two Serial Peripheral Interfaces (SP I1 and SPI0) implemented on MC9S12A128. Consult the
HCS12 Serial Per ipheral Interface (SPI) Block Guide (Motorola docum ent order number, S12SPIV2/D)
for information about each Serial Peripheral Interface module.
Section 13 Pulse Width Modulator (PWM) Block Description
Consult the HCS12 8-Bit, 8-Channel Puls e Width Modulator (PWM) Block Guide (Motorola document
order number, S12PWM8B8CV1/D) for information about the Pulse Width Modulator module.
Section 14 Flash EEPROM 128K Block Description
Consult the HCS12 128K FLASH Block Guide (Motorola document order number, S12FTS128KV1/D) for
information about the flash module.
Section 15 EEPROM 2K Block Description
Consult the HCS12 2K EEPROM Block Guide (Motorola document order number, S12EETS2KV1/D) for
information about the EEPROM module.
Section 16 RAM Block Description
This module support s single-cycle misaligned word accesses.
MC9S12A128 Device Guide — V01.01
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Section 17 Port Integration Module (PIM) Block Description
Consult the MC9S12A 128 Port Integration Module (PIM) Block Guide (Motorola document order
number, S12A128PIMV1/D) for information about the Port Integration Module.
Section 18 Voltage Regulator (VREG) Block Description
Consult the HC S12 V oltage R egulator B lock Guide (Motorola document order number, S12VREGV1/D)
for infor mation about the dual output linear voltage regulator.
Component Purpose Type Value
C1 VDD1 filter cap ceramic X7R 100 .. 220nF
C2 VDD2 filter cap ceramic X7R 100 .. 220nF
C3 VDDA f ilt er cap ceramic X7R 1 00nF
C4 VDDR f ilt e r cap X7R/tantalum >=100nF
C5 VDDPLL fil te r cap ceramic X7R 100nF
C6 VDDX f ilt er cap X7R/tantalum >=100nF
C7 OSC load cap
C8 OSC load cap
C9 PLL loop filter cap
See A.5.3 Phase Locked Lo op
C10 PLL loop filter cap
C11 DC cutoff cap
R1 PLL loop filter res
Q1 Quartz
MC9S1 2A128 Device Guide — V01.01
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The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
•Every supply pair must be decoupled by a ceramic capacitor connected as n ear as possible to the
corresponding pins (C1 - C6).
•Central point of the ground star should be the VSSR pin.
•Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
•VSSPLL must be directly c onnected to VSSR.
•Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8,
C11 and Q1 as small as poss ible.
•Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
•Central power input should be fed in at the VDDA/VSSA pins.
MC9S12A128 Device Guide — V01.01
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Figure 18-1 Recommended PCB Layout 112 LQFP
C5
C4
C1
C6
C3
C2
C8
C7
Q1
C10
C9
R1
VDDX
VSSX
VDDR
VSSR
VDD1
VSS1
VDD2
VSS2
VDDPLL
VSSPLL
VDDA
VSSA
VREGEN
C11
MC9S1 2A128 Device Guide — V01.01
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Figure 18-2 Recommended PCB Layout for 80 QFP
C5
C4
C3
C2
C8
C7
C10
C9
R1
C11
C6
C1
Q1
VDD1
VSS1
VSS2
VDD2
VSSR
VDDR
VSSPLL
VDDPLL
VDDA
VSSA
VSSX
VREGEN
VDDX
MC9S12A128 Device Guide — V01.01
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Appendix A Electrical C haracteri stic s
A.1 General
NOTE: The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values cannot be guaranteed by Motorola and are subject to
change without notice.
This suppleme nt contains the most accurate electrical information for the MC9S12A128 microcontroller
available at the time of publication. The information should be considered PRELIMINARY and is subject
to change.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in thi s supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE: This classification is shown in the column labeled “C” in the parameter tables
where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a s tatistically relevant
sample size across process variations.
T:
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within
this category.
D:
Those parameters are derived mainly from simulations .
A.1. 2 Power Sup pl y
The MC9S12A128 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL
as well as t he digital core.
The V DDA, V SSA pair supplies the A/D converter and the res istor ladder of the internal voltage regulator.
MC9S12A128 Device Guide — V01.01
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The V DDX, V SSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage
regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator
and the PLL.
VSS1 and VSS2 are internally connected by metal.
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.
NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used
for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins.
VDD is used for VDD1, VDD2 and VDDPLL, V SS is used for VSS1, VSS2 and VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 5V I/O pins
Those I/O pins have a nominal level of 5V. This class of pins is comp rised of all port I/O pins, the analog
inputs, BKGD and the R ESET pins.The internal str ucture of all those pins is identical, howe ver some of
the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down
resistors are disabled permanently.
A.1.3.2 Analog Reference
This group is made up by the VRH and VRL pins.
A.1.3.3 Oscillator
The pins XFC, EXTAL, XTAL de dicated to the os cillator have a nominal 2.5V level. They are supplied
by VDDPLL.
A.1.3.4 TEST
This pin is used for production testing only.
A.1.3.5 VREGEN
This pin is used to enable the on chip voltage regulator.
MC9S12A128 Device Guide — V01.01
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A.1.4 Current Injection
Power supply must maintain re gulation within operating VDD5 or VDD r ange during instantaneous and
operating maximum current conditi ons. If pos itive inj ection curre nt (V in > VDD5) is gre ater than I DD5, the
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock ra te is
very low whic h would reduc e overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum r atings are stress ratings only. A functional operati on under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fiel ds;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltage s to this high-impedance circuit. Reliability of ope ration is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1 Absolute Maximum Ratings(1)
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
Num Rating Symbol Min Max Unit
1 I/O, Regulator and Analog Supply Voltage VDD5 –0.3 6.0 V
2Digi tal Logic Supply Voltage (2)
2. The device contains an internal voltage regul ator t o generate the logic and PLL su pply out of t he I/O supply. The absolute
maxim um ratings apply when the device is powered from an external source.
VDD –0.3 3.0 V
3PLL Supply Voltage 2VDDPLL –0.3 3.0 V
4Voltage di fferenc e VDDX to VDDR and VDDA ∆VDDX –0.3 0.3 V
5Voltage di fferenc e VSSX to VSSR and VSSA ∆VSSX –0.3 0.3 V
6 Digital I/O Input Voltage VIN –0.3 6.0 V
7 Analog Reference VRH, VRL –0.3 6.0 V
8 XFC, EXTAL, XTAL inputs VILV –0.3 3.0 V
9 TEST input VTEST –0.3 10.0 V
10 Instantaneous Maximum Current
Single pin limit for all digital I/O pins (3)
3. All digital I/O pins are internal ly clamped to VSSX and VDDX, V SSR and VDDR or VSSA and VDDA.
ID–25 +25 mA
11 Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL(4)
4. Those pins are internally clamped to VSSPLL and VDDPLL.
IDL –25 +25 mA
12 Instantaneous Maximum Current
Single pin limit for TEST (5)
5. This pin i s clamped low to VSSPLL, but not clamp ed high. This pin must be ti ed low in applications.
IDT –0.25 0 mA
13 Storage Temperature Range Tstg –65 155 °C
MC9S12A128 Device Guide — V01.01
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A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conf ormity with CDF-AEC-Q100 Stress test qualifica tion for Automotive Grade
Integrated Circuits. During the device qualification ESD str esses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Human Body
Series Resistance R1 1500 Ohm
Storage Capacitance C 100 pF
Number of Pulse per pin
positive
negative —
—3
3
Machine
Series Resistance R1 0 Ohm
Storage Capacitance C 200 pF
Number of Pulse per pin
positive
negative —
—3
3
Latch-up Minimum input voltage limit —–2.5 V
Max imum input voltage limit —7.5 V
Table A-3 ESD and Latch-Up Protection Characteristics
Num C Rating Symbol Min Max Unit
1 C Human Body Model (HBM) VHBM 2000 —V
2 C Machine Model ( MM) VMM 200 —V
3 C Charge Device Model (CDM) VCDM 500 —V
4C
Latch-up Curren t at TA = 125°C
positive
negative ILAT +100
–100 —
—mA
5C
Latch-up Curren t at TA = 27°C
positive
negative ILAT +200
–200 —
—mA
MC9S12A128 Device Guide — V01.01
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A.1.7 Operating Conditions
This chapter describes the operating conditions of the de vice. Unless otherwise noted those conditions
apply to all the following data.
NOTE: Please refer to the temperature rating of the device (C) with regards to the ambient
temperature TA and the junction temperature TJ. For pow er dissipation
calculations refer to A . 1.8 Power Dissipation and Thermal Characteristics.
Table A-4 Operating Conditions
Rating Symbol Min Typ Max Unit
I/O, Regulator and Analog Supply Voltage VDD5 4.5 5 5.25 V
Digital Logic Supply Voltage(1)
NOTES:
1. The device contains an internal voltage regul ator t o generate the logic and PLL su pply out of t he I/O supply. The absolute
maxim um ratings apply when this regulator is disabled and the devi ce is po wered from an external source.
VDD 2.35 2.5 2.75 V
PLL Supply Volta ge(2) VDDPLL 2.25 2.5 2.75 V
Voltage Difference VDDX to VDDR and VDDA ∆VDDX –0.1 0 0.1 V
Voltage Difference VSSX to VSSR and VSSA ∆VSSX –0.1 0 0.1 V
Oscillator fosc 0.5 —16 MHz
Bus Frequency fbus 0.5 —25 MHz
MC9S12A128C
Operating Junction Temperature Range TJ–40 —100 °C
Operating Ambient Temperature Range (2)
2. Please refer to A.1.8 Power Dissip ati on and Thermal Charac ter istics for more details about the relation b etween
ambient temperat ure TA and device junction temperature TJ.
TA–40 27 85 °C
MC9S12A128 Device Guide — V01.01
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A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be
obtained from:
The total powe r dissipation can be calculated from:
Two cases with internal voltage regulator enabled and disabled must be consider ed:
1. Intern al Voltage Regulator disable d
PIO is the sum of all output currents on I/O ports associated wit h VDDX and VDDR.
For RDSON is valid:
respectively
TJTAPDΘJA
•()+=
TJJunction Temperature, [°C]=
TAAmb i ent Te m perature, [°C]=
PDTotal Chip Power Dissipation, [W]=
ΘJA Package The rmal Re sistance, [°C/W]=
PDPINT PIO
+=
PINT Chip In te rnal Po w er Dissipat ion, [W]=
PINT IDD VDD
⋅IDDPLL VDDPLL
⋅IDDA
+V
DDA
⋅+=
PIO RDSON
i
∑IIOi2
⋅=
RDSON VOL
IOL
------------ for outputs driven low;=
RDSON VDD5 VOH
–
IOH
------------------------------------ for outputs driven high;=
MC9S12A128 Device Guide — V01.01
63
2. I nternal voltage regulator enabled
IDDR is the current shown in Table A-7 and not the overall current flowing into VDDR, wh ich
additionally contains the current flowing into the external loads with output high.
PIO is the sum of all output currents on I/O ports associated wit h VDDX and VDDR.
Table A-5 Thermal Package Characteristics(1)
NOTES:
1. The values for thermal resis tance are achie ved by package simulations
Num C Rating Symbol Min Typ Max Unit
1T
Thermal Resistance LQFP112, single sided PCB(2)
2. PC Board according to EIA/JEDEC Standard 51-2
θJA ——54 oC/W
2T
Thermal Resistance LQFP112, double sided PCB
with 2 inter nal planes(3)
3. PC Board according to EIA/JEDEC Standard 51-7
θJA ——41 oC/W
3 T Ther m al Resistance LQFP 80, single sided PCB θJA ——51 oC/W
4T
Thermal Resistance LQFP 80, double sided PCB
with 2 inter nal planes θJA ——41 oC/W
PINT IDDR VDDR
⋅IDDA VDDA
⋅+=
PIO RDSON
i
∑IIOi2
⋅=
MC9S12A128 Device Guide — V01.01
64
A.1.9 I/O Charact er ist ics
This section describes the characteristics of all 5V I/O pins. All parameters are not al ways applicable, e.g.
not all pins feature pull up/down resistances .
Table A-6 5V I/O Characteristics
Conditions are show n in Table A-4 unl ess otherwise no ted
Num C Rating Symbol Min Typ Max Unit
1 P Input High Voltage VIH 0.65*VDD5 ——V
T Input High Voltage VIH ——
VDD5 + 0.3 V
2 P Input Low Voltage VIL ——
0.35*VDD5 V
T Input Low Voltage VIL VSS5 – 0.3 ——V
3 C Input Hystere sis VHYS —250 —mV
4P
Input Leak age Curren t (pin s in high im pedance i nput
mode)(1)
Vin = V DD5 or VSS5
NOTES:
1. Maximum leakag e curr ent occurs at maxi m um operating te mp erat ure. Curre nt decreases by approximat ely on e-half for
each 8°C to 12°C in the temperature range from 50°C to 125°C.
Iin –2.5 —2.5 µA
5P
Output High Volt age (pi ns in output mode)
Partial Drive IOH = –2.0mA
Full Dri ve IOH = –10.0mA VOH VDD5 – 0.8 ——V
6P
Output Low Voltage (pins in output mode)
Partial Drive IOL = +2.0mA
Full Dri ve IOL = +10.0mA VOL ——0.8 V
7P
Internal Pull Up Device Current,
tested at VIL Max. IPUL ——–130 µA
8P
Internal Pull Up Device Current,
tested at VIH Min. IPUH –10 ——µA
9P
Int ernal Pull Down Device Curre nt,
tested at VIH Min. IPDH ——130 µA
10 P Internal Pull Down Device Current,
tested at VIL Max. IPDL 10 ——µA
11 D Input Capacitance Cin —6—pF
12 T Injection current(2)
Singl e Pin limit
Total Device Limit. Sum of all injected cur rents
2. Refe r to A.1.4 Current Inj ection, for more details
IICS
IICP
–2.5
–25 —2.5
25 mA
13 P Port H, J, P Interru p t Input Pulse filtered(3)
3. Parameter only applies in STOP or Pseudo STOP mode.
tPULSE —— 3µs
14 P Port H, J , P Interr upt Input Pulse passed(3) tPULSE 10 ——µs
MC9S12A128 Device Guide — V01.01
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A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
A.1. 10.1 Measur eme nt Cond itio ns
All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in
Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input.
A.1.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the addr ess, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
given. A ve ry good estima te is to take the single chip curr ents and add the currents due to the externa l
loads.
Table A-7 S upply Current Characteristics
Conditions are show n in Table A-4 unl ess otherwise no ted
Num C Rating Symbol Min Typ Max Unit
1P
Run supply currents
Single Chip, Internal regulator enabl ed IDD5 ——65 mA
2P
P
Wait Supply current All modules enabled, PLL on
only RTI enabled(1) IDDW —
——
—40
5mA
3
C
P
C
C
P
C
Pseudo St op Current (RTI and COP disabl ed) ( 1), (2)
–40°C
27°C
70°C
85°C
“C” Temp Opti on 100°C
105°C
NOTES:
1. PLL off
2. At those low power dissipation levels TJ = TA can be assumed
IDDPS
—
—
—
—
—
—
370
400
450
550
600
650
500
1600
µA
4
C
C
C
C
C
Pseudo Stop Cu rr ent (RTI and COP enabl ed)(1) ,(2)
–40°C
27°C
70°C
85°C
105°C
IDDPS
—
—
—
—
—
—
570
600
650
750
850
—
—
—
—
—
—
µA
5
C
P
C
C
P
C
Stop Current(2)
–40°C
27°C
70°C
85°C
“C” Temp Opti on 100°C
105°C
IDDS
—
—
—
—
—
—
12
25
100
130
160
200
100
1200
µA
MC9S12A128 Device Guide — V01.01
66
A.2 A TD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2. 1 ATD Op erating Char ac te ris ti cs
The Table A-8 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constr aint exi sts since the sample buff er a mplifie r can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
A.2.2 Factors Influencing accuracy
Three factors — source resistance, source capacitance and current injection — have an influence on the
accuracy of the ATD.
A.2.2.1 Source Resistance
Due to the input pin leakage current as specified in Table A-6 in conjuncti on with the source resistance
there will be a voltage drop from t he signal source to the ATD input. The maximum source resistance RS
Table A-8 ATD Operating Characteristics
Conditions are shown in Table A-4 unles s otherwise not ed
Num C Rating Symbol Min Typ Max Unit
1D
Reference Potent ial Low
High VRL
VRH
VSSA
VDDA/2 —
—VDDA/2
VDDA
V
V
2C
Differential Reference Voltage(1)
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
VRH–VRL 4.50 5.00 5.25 V
3 D ATD Clock Frequency fATDCLK 0.5 —2.0 MHz
4D
ATD 10 -B i t Co nve rsion Per i o d Clock Cycles(2)
Conv, Ti me at 2.0 MHz ATD Clock fATDCLK
2. The minim um time a ssumes a f inal sample per i od of 2 ATD clock s cy cles whi le t he max imum t ime assu mes a f inal sampl e
period o f 16 ATD clo cks.
NCONV10
TCONV10
14
7—
—28
14 Cycles
µs
5D
ATD 8-Bit Conversion Period Clock Cycles(2)
Conv, Ti me at 2.0 MHz ATD Clock fATDCLK
NCONV8
TCONV8
12
626
13 Cycles
µs
6D
Stop Re covery T ime (VDDA=5.0 Volts) tSR ——20 µs
7 P Reference Suppl y current (B oth ATD bl ocks on) IREF ——0.750 mA
8 P Reference Supply current (Only one ATD block on) IREF ——0.375 mA
MC9S12A128 Device Guide — V01.01
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speci fies res ults in an error of less than 1/2 LSB (2.5mV) at the maximum leakage curr ent. If device or
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowed.
A.2.2.2 Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor , Cf ≥ 1024 * (CINS- CINN).
A.2.2.3 Current Injection
There are two cases t o consider.
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than
VRL unless the current is higher than specified as disruptive condition.
2. Curr ent is injected into pins i n the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), T his additional current impacts the accuracy
of the conversion depending on the source r esistance.
The additional input voltage error on the converted channel can be calculated as VERR = K * RS *
IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted
channel.
Table A-9 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 C Max input Source Resistance RS—— 1KΩ
2T
Total Inpu t Capacitanc e
Non Sampling
Sampling CINN
CINS
—
——
—10
22 pF
3 C Disruptive Analog Input Current INA –2.5 —2.5 mA
4 C Coupling Ratio positive current injec ti on Kp——
10–4A/A
5 C Coupling Ratio negative cu rrent injection Kn——
10–2A/A
MC9S12A128 Device Guide — V01.01
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A.2.3 ATD Accuracy
Table A-10 specifies the ATD conversion performance excluding any errors due to current injection,
input capacitance and source resistance.
For the following definitions see also Figure A-1.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
The Integral Non-Linearity ( INL) is defined as the sum of all DNLs:
Table A-10 ATD Conversion Performance
Conditions are show n in Table A-4 unl ess otherwise no ted
VREF = VRH – VRL = 5.12V. Res ult ing to one 8 bit count = 20mV and one 10 bit count = 5 mV
fATDCLK = 2.0MHz
Num C Rating Symbol Min Typ Max Unit
1 P 10-Bit Resolution LSB —5—mV
2 P 10-Bit Differential Nonlinearity DNL –1 1 Counts
3 P 10-Bit Integral Nonlinearity INL –2.5 ±1.5 2.5 Counts
4P
10-Bit Absolute Error(1)
NOTES:
1. These val ues include the quantization error which is inherently 1/2 count for any A/D converter.
AE –3±2.0 3 Counts
5 P 8-Bit Resolution LSB —20 —mV
6 P 8-Bit Differential Nonlinearity DNL –0.5 —0.5 Counts
7 P 8-Bit Integral Nonlinearity INL –1.0 ±0.5 1.0 Counts
8P
8-Bit Absolute Error(1) AE –1.5 ±1.0 1.5 Counts
DNL i() ViVi1–
–
1LSB
-------------------------- 1–=
INL n() DNL i()
i1=
n
∑VnV0
–
1LSB
---------------------n–==
MC9S12A128 Device Guide — V01.01
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Figure A-1 ATD Accuracy Defini tio ns
NOTE: Figure A-1 shows only definitions, for specification values refer to Table A -10.
1
5Vin
mV
10 15 20 25 30 35 40 5085 5090 5095 5100 5105 5110 5115 51205065 5070 5075 50805060
0
3
2
5
4
7
6
45
$3F7
$3F9
$3F8
$3FB
$3FA
$3FD
$3FC
$3FE
$3FF
$3F4
$3F6
$3F5
8
9
1
2
$FF
$FE
$FD
$3F3
10-Bit Resolution
8-Bit Re solution
Ideal Transf er Curve
10-Bit Transf er Curve
8-Bit Transf er Cu rve
5055
10-Bit Absolute Error Boundary
8-Bit Absolute Error Boundary
LSB
Vi-1 Vi
DNL
MC9S12A128 Device Guide — V01.01
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A.3 N VM , Flash, and EEPROM
NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for
both Flash and EEPROM.
A.3.1 NVM Timing
The time base for all NVM program or erase operations is derived from the oscilla tor. A minimum
oscillator frequency fNVM OSC is required for performing progr am or erase operations. The NVM modules
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lowe r frequency a full program or erase trans ition is not assured.
The Fla sh and EEP ROM program and erase oper at ions are timed using a cloc k derived fr om the oscillator
using the F CLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within
the limits specified as fNVMOP.
The minimum program and erase times shown in Table A-11 are calcula ted for ma ximum fNVMOP and
maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
A.3.1.1 Single Word Programming
The programming time for single word programming is dependant on the bus freque ncy as a well as on
the frequency fNVMOP and can be calculated according to the following formula.
A.3.1.2 Burst Programming
This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst
programming by keeping the command pipeline filled. The time to progra m a consecutive word can be
calculated as:
The time to program a whole row is:
Burst programming is more than 2 times faster than single word programming.
tswpgm 91
fNVMOP
-------------------------⋅25 1
fbus
------------⋅+=
tbwpgm 41
fNVMOP
-------------------------⋅91
fbus
------------⋅+=
tbrpgm tswpgm 31 tbwpgm
⋅+=
MC9S12A128 Device Guide — V01.01
71
A.3.1.3 Sector Erase
Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:
The setup time can be ignore d for this operation.
A.3.1.4 Mass Erase
Erasing a NVM block takes:
The setup time can be ignore d for this operation.
A.3.1.5 Blank Check
The time it ta kes to perform a blank check on the Flash or EEPROM is dependant on the location of the
first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup
of the command.
Table A-11 NVM Timing Characteristics
Conditions are show n in Table A-4 unl ess otherwise no ted
Num C Rating Symbol Min Typ Max Unit
1 D Exter nal Oscillator Clock fNVMOSC 0.5 —50(1)
NOTES:
1. Restrictions for oscillator in crystal mode apply!
MHz
2 D Bus frequency for Programming or Er ase Operations fNVMBUS 1—MHz
3 D Operating Frequency fNVMOP 150 —200 kHz
4 P Single Wor d Programming Time tswpgm 46(2)
2. Mini m um Programming times are achieved under max imum NVM ope rating frequency fNVMOP and maximum bus
frequency fbus.
—74.5(3)
3. Maximum Erase and Programm ing times ar e achieved under par ti cular combinations of fNVMOP and bus frequency fbus.
Refer to formulae in A.3.1.1 Sin g le Word Programming- A.3.1.4 Mas s Erase f or gui dance.
µs
5D
Flash Burst Programming consecutive word (4)
4. urs t Programming oper ati ons are not applicable to EEPROM
tbwpgm 20.4(2) —31(3) µs
6D
Flash Burst Programming Time for 32 Words 4tbrpgm 678.4(2) —1035.5(3) µs
7 P Sector Erase Time tera 20(5)
5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP.
—26.7(3) ms
8 P Ma ss Erase Time tmass 100(5) —133(3) ms
9 D Blank Check Time Flash per block tcheck 11(6)
6. Mini m um ti me , if first word in th e array is not blank
—32,778(7)
7. Maximum time to comp lete check on an erased block
tcyc
10 D Blank Check Time EEPR OM per block tcheck 11(6) —2058(7) tcyc
tera 4000 1
fNVMOP
-------------------------
⋅≈
tmass 20000 1
fNVMOP
-------------------------
⋅≈
tcheck location tcyc 10 tcyc
⋅+⋅≈
MC9S12A128 Device Guide — V01.01
72
A.3.2 NVM Reliability
The reliability of the N VM blocks is gua ranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
NOTE: All values show n in Table A-12 are target values and subject to further extensive
characterization.
NOTE: Flash cycling performance is 1000 cycles at –40 to +85°C. Data Retention is
spec ifi e d f o r 1 0 ye ars.
NOTE: EEPROM cycling performance is 10,000 cycles at –40 to +85°C. Data retention is
spec ifi e d f o r 1 0 ye ars.
NOTE: These figures are provided for commercial quality levels not automotive.
Table A-12 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C NVM Array Cycles Data Reten tion
Lifetime
1 C Flash/EEPROM (–40 to + 85°C) 1000 10 years
2 C EEPROM (–40 to + 85°C) 10,000 10 years
MC9S12A128 Device Guide — V01.01
73
A.4 Vo ltage Regulator
The on-chip voltage regulator is intended to supply the internal logic and oscillator circ uits. No external
DC load is allowed.
Table A-13 Voltage Regulator Recommended Load Capacitances
Rating Symbol Min Typ Max Unit
Load Capacitance on VDD1, 2 CLVDD —220 —nF
Load Capacitance on VDDPLL CLVDDPLL —220 —nF
MC9S12A128 Device Guide — V01.01
74
A.5 R eset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14 summarizes several startup characteristics explained in this section. Detailed de scription of
the startup behavior can be found in the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola
document order number, S12CRGV3/D) .
A.5.1.1 POR
The release level VPORR and the assert level V PORA are derived from the VDD s upply. They are also valid
if the device is powered extern ally. Aft er releasing the POR reset the oscillator and the clock quality check
are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by nuposc.
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 i s out of spe ci fication limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.5.1.3 External Reset
When external rese t is asser ted for a time greater than PWRSTL the CRG module generates a n internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscilla tion before re set.
Table A-14 Startup Characteristics
Condit ions are shown in Table A-4 unless other wise noted
Num C Rating Symbol Min Typ Max Unit
1 T POR release level VPORR ——2.07 V
2 T PO R assert level VPORA 0.97 ——V
3 D Reset input pulse width, minimum input tim e PWRSTL 2——
tosc
4 D Startup from Reset nRST 192 —196 nosc
5 D Interrupt pulse width, IRQ edge-sensitive mode PWIRQ 20 ——ns
6 D Wait rec o ve ry sta rtup tim e tWRS ——14 tcyc
MC9S12A128 Device Guide — V01.01
75
A.5.1.4 Stop Recovery
Out of STOP the c ontroller can be woken up by an externa l interrupt. A clock quality check as aft er POR
is performed before releasing the clocks to the system.
A.5.1.5 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by interna l or external interr upts. After twrs the CPU starts
fetching the i nterrupt vector.
A.5.2 Oscillator
The device features an internal Colpitts oscill ator. By asserting the XCLKS input during reset this
oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the os cillation is checked for each start from either power-on, ST OP
or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after
POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
oscilla tor star t-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is
asserted if the frequenc y of the incoming clock signal is below the Assert Fre quency fCMFA.
Table A-15 Oscillator Characteristics
Condit ions are shown in Table A-4 unless other wise noted
Num C Rating Symbol Min Typ Max Unit
1 C Crystal oscillator range fOSC 0.5 —16 MHz
2 P Startup Cur rent IOSC 100 ——µA
3 D O s ci lla tor star t-up time fr om POR or STO P nUPOSC 4100 ——
cycOSC
4 C Oscillator start-up time tUPOSC —8(1)
NOTES:
1. fosc = 4MHz, C = 22pF.
100(2)
2. Maximum value is for extreme cases using high Q, l ow frequency cry stals
ms
5 D Clock Quality check time-out tCQOUT 0.45 2.5 s
6 P Clock Monit or Failure Assert Frequency fCMFA 50 100 200 KHz
7P
External square wave input frequency(3)
3. XCLKS =0 during reset
fEXT 0.5 —50 MHz
8 D External square wave pulse width low tEXTL 9.5 ——ns
9 D External square wave pulse width high tEXTH 9.5 ——ns
10 D Ex ter nal s quare wave rise t ime tEXTR —— 1ns
11 D External square wave fall ti m e tEXTF —— 1ns
12 D Input Capaci tance (EXTAL, XTAL pin s) CIN —9—pF
13 C DC Opera ti ng Bias in Colpitts Configuration on
EXTAL Pin VDCBIAS —1.1 —V
MC9S12A128 Device Guide — V01.01
76
A.5.3 Phase Locked Loop
The oscillator provide s the refe rence clock for the PLL. The PLL´s Voltage Controlle d Oscillator (VCO)
is also t he system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Figure A-2 Basic PLL Functional Diagram
The following proc edure can be used to calculate the resistance and capacitance values using typica l
values for K1, f1 and ich from Table A-16.
The VCO Gain at the desired VCO output frequenc y is approxima ted by:
The phase detector relationship is given by:
ich is the current in tracking mode.
fosc 1
refdv+1 fref
Phase
Detector
VCO
KV
1
synr+1
fvco
Loop Divider
KΦ
1
2
∆
fcmp
Cs
R
Cp
VDDPLL
KVK1e
f
1
f
vco
–
()
K11V⋅
----------------------------
⋅=
KΦich
–KV
⋅=
MC9S12A128 Device Guide — V01.01
77
The loop bandwidth fC should be chosen to fulfill the Gardner’s stabili ty c r ite ria by at l eas t a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above inputs the resistance can be calculated as:
The capacita nce Cs can now be calculated as:
The capacita nce Cp should be chosen in the range of:
The stabilization delays shown in Table A-16 are dependant on PLL operational settings and external
component selection (e.g. crystal, XFC filter).
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. W ith each transition of the clock fcmp, th e
deviation from the r ef erence clock fref is meas ured and input voltage to the VC O is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitte r affec ts the real minimum and maximum clock periods as illustrated in Figure A-3.
fC2ζfref
⋅⋅
πζ 1ζ2
++
⋅
-------------------------------------------1
50
------ fCfref
450⋅
-------------- ζ0.9=();<→⋅<
nfVCO
fref
--------------- 2 s y n r 1+()⋅==
R2πnf
C
⋅⋅⋅
KΦ
-----------------------------=
Cs2ζ2
⋅
πfCR⋅⋅
---------------------- 0.516
fCR⋅
---------------ζ0.9=();≈=
Cs20⁄CpCs10⁄≤≤
MC9S12A128 Device Guide — V01.01
78
Figure A-3 Jitter Defini tions
The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
Defini ng the jitter as:
For N < 100, the following equation is a good fit for the maximum jitter:
Figure A-4 Maximum Bus Clock Jitter Approximation
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effec t of the jitter to a large extent.
23 N-1N1
0
tnom
tmax1
tmin1
tmaxN
tminN
JN() max 1 tmax N()
Nt
nom
⋅
-----------------------
–1tmin N()
Nt
nom
⋅
-----------------------
–,
=
JN() j1
N
-------- j2
+=
1 5 10 20 N
J(N)
MC9S12A128 Device Guide — V01.01
79
Table A-16 PLL Characteristics
Condit ions are shown in Table A-4 unless other wise noted
Num C Rating Symbol Min Typ Max Unit
1 P Self Clock Mode frequency fSCM 1—5.5 MHz
2 D VCO locking range fVCO 8—50 MHz
3D
Lock Detector transiti on from Acquisition to Trackin g
mode |∆trk|3—4%(1)
NOTES:
1. % deviation from target frequency
4 D Lock Dete ction |∆Lock|0—1.5 %(1)
5 D Un-Lock Detection |∆unl|0.5 —2.5 %(1)
6D
Lock Detector transiti on from Tracking to Acquisitio n
mode |∆unt|6—8%(1)
7C
PL LO N Total S t a b iliz a tio n del a y (Auto M o de) (2)
2. fREF = 4 M Hz , fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF,
Rs = 10 KΩ.
tstab —0.5 —ms
8D
PLLON Acq uisition mode sta bil ization delay(2) tacq —0.3 —ms
9D
PLLON Tracking mode stabilization delay (2) tal —0.2 —ms
10 D Fitting parameter VCO loop gai n K1—–120 —MHz/V
11 D Fitting param eter VCO loop frequency f1—75 —MHz
12 D Cha rge pump current acquisition mo de | ich | —38.5 —µA
13 D Charge pump current trac king mode | ich | —3.5 —µA
14 C Jitter fi t param eter 1(2) j1——1.1 %
15 C Jitter fi t param eter 2(2) j2——0.13 %
MC9S12A128 Device Guide — V01.01
80
A.6 SPI
A.6. 1 Master Mo de
Figure A-5 and Figure A-6 illustra te the master mode timing. Timing values are shown in Ta ble A-17.
Figure A-5 SPI Master Timing (CPHA = 0)
Figure A-6 SPI Master Timing (CPHA =1)
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS1
(OUTPUT)
1
9
5 6
MSB IN2
BIT 6 . . . 1
LS B I N
MSB OUT 2LSB OUT
BI T 6 . . . 1
10
4
4
2
9
(CPOL = 0)
(CPOL = 1)
311
12
1. If conf ig ured as output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
1
5 6
MS B IN2
BIT 6 . . . 1
LSB IN
MASTER MSB O UT2MASTER LSB OUT
BIT 6 . . . 1
4
4
9
11 12
10
PORT DATA
(CPOL = 0)
(CPOL = 1)
PORT DATA
SS1
(OUTPUT)
212 11 3
1. If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
MC9S12A128 Device Guide — V01.01
81
A.6.2 Slave Mode
Figure A- 7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-18.
Figure A-7 SPI Slave Timing (CPHA = 0)
Table A-17 SPI Master Mode Timing Characteristics1
NOTES:
1. The nu mbers 7, 8 in the column labeled “Num” are missing. This has been done on pur pose to be consi stent bet ween the
Master and the Slave timing shown in Table A-18.
Conditions are show n in Table A-4 unl ess otherwise no ted, CLOAD = 200pF on al l out puts
Num C Rating Symbol Min Typ Max Unit
1 P Operating Frequency fop DC —1/4fbus
1P
SCK Period tsck = 1./fop tsck 4—2048 tbus
2 D Enable Lead Time tlead 1/2——
tsck
3 D Enable Lag Time tlag 1/2——
tsck
4 D Clock ( SCK ) High or Low Time twsck tbus − 30 —1024 tbus ns
5 D Data Setup Time (Inputs) tsu 25 ——ns
6 D Data Hold Time (Inputs) thi 0——ns
9 D Data Valid (af ter Enable Edge) tv——25 ns
10 D Data Hold Time (Outputs) tho 0——ns
11 D Rise Time Inputs and Output s tr——25 ns
12 D Fall Time Inputs and Outputs tf——25 ns
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
SS
(INPUT)
1
9
5 6
MSB IN
BI T 6 . . . 1
LSB IN
MSB O UT SLAVE LSB OUT
BIT 6 . . . 1
10
4
4
2
7
(CPOL = 0)
(CPOL = 1)
3
12
SLAVE
12
11
10
11
8
MC9S12A128 Device Guide — V01.01
82
Figure A-8 SPI Slave Timing (CPHA =1)
Table A-18 SPI Slave Mode Timing Characteristics
Conditions are show n in Table A-4 unless otherw ise noted, CLOAD = 200pF on all outputs
Num C Rating Symbol Min Typ Max Unit
1 P Operating Frequency fop DC —1/4fbus
1P
SCK Period tsck = 1./fop tsck 4—2048 tbus
2 D Enable Lead Time tlead 1——
tcyc
3 D Enable Lag Time tlag 1——
tcyc
4 D Clock ( SCK ) High or Low Time twsck tcyc − 30 ——ns
5 D Data Setup Time (Inputs) tsu 25 ——ns
6 D Data Hold Time (Inputs) thi 25 ——ns
7 D Slave Access Time ta—— 1tcyc
8 D Slave MISO Disable Time tdis —— 1tcyc
9 D Data Valid (after SCK Edge) tv——25 ns
10 D Data Hold Time (Outputs) tho 0——ns
11 D Rise Time Inputs and Output s tr——25 ns
12 D Fall Time Inputs and Outputs tf——25 ns
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
1
5 6
MSB IN
BI T 6 . . . 1
LSB IN
MSB O UT SLAVE LSB OUT
BI T 6 . . . 1
4
4
9
11 12
10
(CPOL = 0)
(CPOL = 1)
SS
(INPUT)
212 11 3
SLAVE
7
8
MC9S12A128 Device Guide — V01.01
83
A.7 Extern al Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Fi gure A-9 with the actual timing
values shown on table Table A -1 9. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A. 7.1 General Muxed Bus Timing
The expanded bus timings are highly depende nt on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
MC9S12A128 Device Guide — V01.01
84
Figure A-9 General External Bus Timing
Addr/Data
(read)
Addr/Data
(write)
addr data
data
510 11
8
166
ECLK
1, 2
3 4
addr data
data
12
159
7
14 13
ECS
2120 22 23
Non-Multiplexed
17
19
LSTRB
29
NOACC
32
IPIPO0
IPIP O 1, PE 6 ,5
35
18
27
28
30
33 36
31
34
R/W
24
26
25
Addresses
PE4
PA, PB
PA, PB
PK5:0
PK7
PE2
PE3
PE7
MC9S12A128 Device Guide — V01.01
85
Table A-19 Expanded Bus Timing Characteristics
Conditions are show n in Table A-4 unl ess otherwise no ted, CLOAD = 50pF
Num C Rating Symbol Min Typ Max Unit
1 P Frequency of operati on (E-clock) fo0—25.0 MHz
2PCycle time tcyc 40 ——ns
3 D Pulse width, E low PWEL 19 ——ns
4D
Pulse wi dth, E high(1) PWEH 19 ——ns
5 D Address delay tim e tAD —— 8ns
6D
Address v ali d ti m e to E rise (PWEL–tAD)t
AV 11 ——ns
7 D Muxed address hold time tMAH 2——ns
8 D Address hold to data valid tAHDS 7——ns
9 D Data hol d to address tDHA 2——ns
10 D Read data set up time tDSR 13 ——ns
11 D Read data hol d ti m e tDHR 0——ns
12 D Wr ite data delay ti m e tDDW —— 7ns
13 D Wr ite data hold ti m e tDHW 2——ns
14 D Wr ite data setup ti m e(1) (PWEH–tDDW)tDSW 12 ——ns
15 D Address access time(1) (tcyc–tAD–tDSR)tACCA 19 ——ns
16 D E high ac ce ss t im e(1) (PWEH–tDSR)tACCE 6——ns
17 D Non-m ultiplexed addres s delay time tNAD —— 6ns
18 D Non-muxed address valid to E rise (PWEL–tNAD)t
NAV 15 ——ns
19 D Non-multiplexed address hold time tNAH 2——ns
20 D Chip select delay time tCSD ——16 ns
21 D Chip select access time(1) (tcyc–tCSD–tDSR)tACCS 11 ——ns
22 D Chip select hold time tCSH 2——ns
23 D Chip select negat ed ti m e tCSN 8——ns
24 D Read /write delay ti m e tRWD —— 7ns
25 D Read/write valid time to E rise (PWEL–tRWD)t
RWV 14 ——ns
26 D Read /write hold ti me tRWH 2——ns
27 D Low strobe delay time tLSD —— 7ns
28 D Low strobe valid time to E rise (PWEL–tLSD)t
LSV 14 ——ns
29 D Lo w stro be ho ld t ime tLSH 2——ns
30 D NOACC strobe del ay time tNOD —— 7ns
31 D NOACC valid time to E rise (PWEL–tNOD)t
NOV 14 ——ns
MC9S12A128 Device Guide — V01.01
86
32 D NO A C C ho ld tim e tNOH 2——ns
3 3 D IPIPO [1:0] delay ti m e tP0D 2—7ns
34 D IPI P O [1 : 0] va lid time to E rise (P WEL–tP0D)t
P0V 11 ——ns
35 D IPIPO[1:0] delay time1 (PWEH-tP1V)tP1D 2—25 ns
36 D IPI P O [1 : 0] va lid time to E fa ll tP1V 11 ——ns
NOTES:
1. Aff ected by clock stretch: add N x tcyc where N=0,1, 2 or 3, depending on the number of clock stret ches.
Table A-19 Expanded Bus Timing Characteristics
Conditions are show n in Table A-4 unl ess otherwise no ted, CLOAD = 50pF
Num C Rating Symbol Min Typ Max Unit
MC9S12A128 Device Guide — V01.01
87
Appendix B Package Information
B.1 General
This section provides the physical dimensions of the MC9S12A128 packages.
MC9S1 2A128 Device Guide — V01.01
88
B.2 112-Pin LQFP Package
Figure B-1 112-Pin LQFP Mechanical Dimensions (Case no. 987)
DIM
AMIN MAX
20.000 BSC
MILLIMETERS
A1 10.000 BSC
B20.000 BSC
B1 10.000 BSC
C--- 1.600
C1 0.050 0.150
C2 1.350 1.450
D0.270 0.370
E0.450 0.750
F0.270 0.330
G0.650 BSC
J0.090 0.170
K0. 50 0 R EF
P0.325 BSC
R1 0.100 0.200
R2 0.100 0.200
S22.000 BSC
S1 11.000 BSC
V22.000 BSC
V1 11.000 BSC
Y0. 25 0 R EF
Z1. 00 0 R EF
AA 0.090 0.160
θ
θ
θ
θ11 °
11 °13 °
7 °
13 °
VIEW Y
L-M0.20 N
T
4X 4X 28 TIPS
PIN 1
IDENT
1
112 85
84
28 57
29 56
BV
V1
B1
A1
S1
A
S
VIEW AB
0.10
3
CC2
θ
2θ
0.050
SEATING
PLANE
GAGE PLANE
1θ
θ
VIEW AB
C1
(Z)
(Y) E
(K)
R2
R1 0.25
J1
VIEW Y
J1
P
G
108X
4X
SECTION J1-J1
BASE
ROTATED 90 COUNTERCLOCKWISE
°
METAL
JAA
F
DL-M
M
0.13 NT
1
2
3
C
L
L-M0.20 NT
L
N
M
T
T
112X
X
X=L, M OR N
R
R
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y1 4.5M, 19 94 .
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOL D PRO T RUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTR USION. AL L OWABLE DA MB AR
PROTRUSION SHAL L NOT CAUSE THE D
DIMENSION TO EXCEED 0 .46.
8 °
3 °
0 °
MC9S12A128 Device Guide — V01.01
89
B.3 8 0-Pi n QFP Package
Figure B-2 80-pin QFP Mechanical Dimensions (Case no. 841B)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
A NS I Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE T HE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING LINE.
4. DA TUMS -A-, -B- AND -D- TO BE
DETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLA NE -C-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PRO TRU SION IS 0. 25 P ER SIDE. D IMENS IONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MAT ERIAL CONDITION. DAM BAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR
THE FOOT.
SECTION B-B
61 60
DETAIL A
L
41
40
80
-A-
L
-D-
A
S
A-B
M
0.20 D S
H
0.05 A-B
S
120
21
-B-
BV
J
F
N
D
VIEW ROTATED 90°
DETAIL A
B
BP
-A-,-B-,-D-
E
H
GM
MDETAIL C
SEATING
PLANE
-C-
CDATUM
PLANE
0.10
-H-
DATUM
PLANE -H-
U
T
R
Q
K
WX
DETAIL C
DIM MIN MAX
MILLIMETERS
A13.90 14.10
B13.90 14.10
C2.15 2.45
D0.22 0.38
E2.00 2.40
F0.22 0.33
G0.65 BSC
H--- 0.25
J0.13 0.23
K0.65 0.95
L12. 3 5 R EF
M5 10
N0.13 0.17
P0.325 BSC
Q0 7
R0.13 0.30
S16.95 17.45
T0.13 ---
U0 ---
V16.95 17.45
W0.35 0.45
X1.6 R EF
°°
°°
°
S
A-B
M
0.20 D S
C
S
A-B
M
0.20 D
S
H
0.05 D
S
A-B
M
0.20 D
S
C
S
A-B
M
0.20 D S
C
MC9S1 2A128 Device Guide — V01.01
90
MC9S12A128 Device Guide — V01.01
91
User G uide End Sheet
MC9S1 2A128 Device Guide — V01.01
92
FINAL PAGE OF
92
PAGES
