AZ100LVE310
ECL/PECL 2:8 Differential Clock Driver
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
• Operating Range of 3.0V to 5.5V
• Low Skew
• Guaranteed Skew Spec
• Differential Design
• VBB Output
• 75kΩ Internal Input Pulldown Resistors
• Direct Replacement for ON Semiconductor
MC100LVE310 & MC100E310
DESCRIPTION
The AZ100LVE310 is a low skew 2:8 fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and system skew. The AZ100LVE310 offers two
selectable clock inputs allowing redundant or test clocks to be incorporated into the system clock trees.
The AZ100LVE310 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the VBB reference should be connected to one side of the CLKa/CLKb
differential input pair. The input signal is then fed to the other CLKa/CLKb input. The VBB pin should be used only
as a bias for the AZ100LVE310 as its current sink/source capability is limited. When used, the VBB pin should be
bypassed to ground via a 0.01µF capacitor.
Both sides of the differential output must be terminated into 50Ω to ensure that the tight skew specification is
met, even if only one side is used. In most applications all eight differential pairs will be used and therefore
terminated. In the case where fewer than eight pairs are used, all output pairs on the same package side (sharing the
same VCCO) as the pairs being used should be terminated to maintain minimum skew. Failure to do this will result in
small degradations of propagation delay (on the order of 10–20ps) of the outputs being used; while not being
catastrophic to most designs this will result in an increase in skew.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
PACKAGE AVAILABILITY
PACKAGE PART NO. MARKING
PLCC 28 AZ100LVE310FN AZM100LVE310
PLCC 28 T&R AZ100LVE310FNR2 AZM100LVE310
VEE
VBB
CLK_SEL
CLKa
CLKa
CLKb
VCC
CLKb
Q1 Q1Q0 Q0 Q2 Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
NC
26
28
27
25 24 23 22 21 20 19
56 7 8 91011
1
2
3
4
18
16
17
15
14
13
12
VCCO
VCCO
VCCO
Pinout: 28-Lead
PLCC (top view)
AZ100LVE310
March 2002 * REV - 3 www.azmicrotek.com
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Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol Characteristic Rating Unit
VCC PECL Power Supply (VEE = 0V) 0 to +8.0 Vdc
VI PECL Input Voltage (VEE = 0V) 0 to +6.0 Vdc
VEE ECL Power Supply (VCC = 0V) -8.0 to 0 Vdc
VI ECL Input Voltage (VCC = 0V) -6.0 to 0 Vdc
IOUT Output Current --- Continuous
--- Surge
50
100 mA
TA Operating Temperature Range -40 to +85 °C
TSTG Storage Temperature Range -65 to +150 °C
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND)
-40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
VOH Output HIGH Voltage1 -1085 -1005 -880 -1025 -955 -880 -1025 -955 -880 -1025 -955 -880 mV
VOL Output LOW Voltage1 -1830 -1695 -1555 -1810 -1705 -1620 -1810 -1705 -1620 -1810 -1705 -1620 mV
VIH Input HIGH Voltage -1165 -880 -1165 -880 -1165 -880 -1165 -880 mV
VIL Input LOW Voltage -1810 -1475 -1810 -1475 -1810 -1475 -1810 -1475 mV
VBB Reference Voltage -1380 -1260 -1380 -1260 -1380 -1260 -1380 -1260 mV
IIH Input HIGH Current 150 150 150 150
µA
IIL Input LOW Current 0.5 0.5 0.5 0.5 µA
IEE Power Supply Current 55 60 55 60 55 60 65 70 mA
1. Each output is terminated through a 50Ω resistor to VCC – 2V.
LOGIC SYMBOL
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
CLKa
CLKb
CLKa
CLKb
CLK_SEL
VBB
PIN DESCRIPTION
PIN FUNCTION
CLKa, CLKa ¯¯¯¯¯
CLKb, CLKb ¯¯¯¯¯
Differential Input Pairs
Differential Input Pairs
CLK_SEL Input Clock Select
Q0, Q0¯¯ – Q7, Q7¯¯ Differential Output Pairs
VBB VBB Output
VCC , VCCO Positive Supply
VEE Negative Supply
NC No Connect
CLK_SEL Input Clock
0
1
CLKa Selected
CLKb Selected
AZ100LVE310
March 2002 * REV - 3 www.azmicrotek.com
3
100K LVPECL DC Characteristics (VEE = GND, VCC = VCCO = +3.3V)
-40°C 0°C 25°C 85°C
Symbol Characteristic Min T
yp
Max Min T
yp
Max Min T
yp
Max Min T
yp
Max Unit
VOH Output HIGH Voltage1,2 2215 2295 2420 2275 2345 2420 2275 2345 2420 2275 2345 2420 mV
VOL Output LOW Voltage1,2 1470 1605 1745 1490 1595 1680 1490 1595 1680 1490 1595 1680 mV
VIH Input HIGH Voltage1 2135 2420 2135 2420 2135 2420 2135 2420 mV
VIL Input LOW Voltage1 1490 1825 1490 1825 1490 1825 1490 1825 mV
VBB Reference Voltage1 1920 2040 1920 2040 1920 2040 1920 2040 mV
IIH Input HIGH Current 150 150 150 150
µA
IIL Input LOW Current 0.5 0.5 0.5 0.5 µA
IEE Power Supply Current 55 60 55 60 55 60 65 70 mA
1. For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.
2. Each output is terminated through a 50Ω resistor to VCC – 2V.
100K PECL DC Characteristics (VEE = GND, VCC = VCCO = +5.0V)
-40°C 0°C 25°C 85°C
Symbol Characteristic Min T
yp
Max Min T
yp
Max Min T
yp
Max Min T
yp
Max Unit
VOH Output HIGH Voltage1,2 3915 3995 4120 3975 4045 4120 3975 4045 4120 3975 4045 4120 mV
VOL Output LOW Voltage1,2 3170 3305 3445 3190 3295 3380 3190 3295 3380 3190 3295 3380 mV
VIH Input HIGH Voltage1 3835 4120 3835 4120 3835 4120 3835 4120 mV
VIL Input LOW Voltage1 3190 3525 3190 3525 3190 3525 3190 3525 mV
VBB Reference Voltage1 3620 3740 3620 3740 3620 3740 3620 3740 mV
IIH Input HIGH Current 150 150 150 150
µA
IIL Input LOW Current 0.5 0.5 0.5 0.5 µA
IEE Power Supply Current 55 60 55 60 55 60 65 70 mA
1. For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
2. Each output is terminated through a 50Ω resistor to VCC – 2V.
AC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND or VEE = GND, VCC = VCCO = +3.0 to +5.5V)
-40°C 0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
tPLH / tPHL
Propagation Delay to
Output IN (Diff)1
IN (SE)2
525
500
725
750
550
550
750
775
550
550
750
800
575
600
775
850
ps
tSKEW Within-Device Skew
Part-to-Part Skew (Diff)3
75
250
75
250
50
200
50
200
ps
VPP (AC) Minimum Input Swing4 250 250 250 250 mV
VCMR Common Mode Range5 VEE +
1.8
V
CC -
0.4
VEE +
1.8
V
CC -
0.4
VEE +
1.8
V
CC -
0.4
VEE +
1.8
V
CC -
0.4 V
tr / tf Rise/Fall Time
20 – 80% 250 450 650 275 375 600 275 375 600 275 375 600 ps
1. The differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the
differential output signals.
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
3. The within-device skew is defined as the worst-case difference between any two similar delay paths within a single device.
4. VPP is the minimum peak-to-peak differential input swing for which AC parameters are guaranteed. The VPP(min) is AC limited for the LVE310,
because differential input as low as 50 mV will still produce full ECL levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP(min).
AZ100LVE310
March 2002 * REV - 3 www.azmicrotek.com
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PACKAGE DIAGRAM
PLCC 28
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 12.32 12.57 0.485 0.495
B 12.32 12.57 0.485 0.495
C 4.20 4.57 0.165 0.180
E 2.29 2.79 0.090 0.110
F 0.33 0.48 0.013 0.019
G 1.27 BSC 0.050 BSC
H 0.66 0.81 0.026 0.032
J 0.51 0.020
K 0.64 0.025
R 11.43 11.58 0.450 0.456
U 11.43 11.58 0.450 0.456
V 1.07 1.21 0.042 0.048
W 1.07 1.21 0.042 0.048
X 1.07 1.42 0.042 0.056
T 0.50 0.020
Z 2O 10O 2
O 10O
G1 10.42 10.92 0.410 0.430
K1 1.02 0.040
N
OTES:
1. DATUMS –L-, -M-, AND –N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALOWABLE MOLD FLASH IS
0.010mm (0.250in.) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKGE BOTTOM BY UP TO 0.012mm
(0.300in.). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, THE BAR
BURRS, GATE BURRS AND INTERLEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN
THE TOP AND BOTTOM OF THE PLASTIC
BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE SMALLER THAN 0.025mm
(0.635in.).
AZ100LVE310
March 2002 * REV - 3 www.azmicrotek.com
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Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges tha
t
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
