L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK041xx Family Precision Clock Conditioner with Dual PLLs and Integrated VCO Evaluation Board Operating Instructions 2012-01-16 LMK04100EVAL LMK04131EVAL LMK04102EVAL LMK04133EVAL Texas Instruments Precision Timing Devices 1 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Table of Contents QUICK START................................................................................................................................... 3 PLL LOOP FILTERS AND LOOP PARAMETERS ................................................................................... 4 PLL 1 Loop Filter .......................................................................................................................................................4 PLL2 Loop Filter ........................................................................................................................................................4 122.88 MHz VCXO (Reference Input) ................................................................................... 4 EVALUATION BOARD INPUTS/OUTPUTS ........................................................................................... 5 APPENDIX A: CODELOADER USAGE ................................................................................................ 8 Port Setup Tab ............................................................................................................................................................ 8 Clock Outputs Tab......................................................................................................................................................9 PLL1 Tab.................................................................................................................................................................. 10 PLL2 Tab.................................................................................................................................................................. 11 Bits/Pins Tab ............................................................................................................................................................ 12 Registers Tab ............................................................................................................................................................ 14 APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS ......................................................... 15 PLL1 ......................................................................................................................................................................... 15 Crystek 122.88 MHz VCXO................................................................................................. 15 PLL2 ......................................................................................................................................................................... 16 Clock Outputs ........................................................................................................................................................... 17 Clock Output Measurement Technique ................................................................................ 17 LMK041x0 Phase Noise........................................................................................................................................... 18 LMK041x1 Phase Noise........................................................................................................................................... 19 LMK041x2 Phase Noise........................................................................................................................................... 20 LMK041x3 Phase Noise........................................................................................................................................... 21 APPENDIX C: SCHEMATICS ............................................................................................................ 22 Power ........................................................................................................................................................................ 22 Main ......................................................................................................................................................................... 23 Clock Outputs ........................................................................................................................................................... 24 APPENDIX D: BOARD LAYERS STACKUP ....................................................................................... 25 APPENDIX E: BILL OF MATERIALS ................................................................................................ 26 Common Bill of Materials for Evaluation Boards .................................................................................................... 26 Bill of Material Custom to LMK04100BEVAL ....................................................................................................... 29 Bill of Material Custom to LMK04100BEVAL-XO ................................................................................................ 29 Bill of Material Custom to LMK04131BEVAL ....................................................................................................... 30 Bill of Material Custom to LMK04131BEVAL-XO ................................................................................................ 30 Bill of Material Custom to LMK04102BEVAL ....................................................................................................... 31 Bill of Material Custom to LMK04133BEVAL ....................................................................................................... 31 APPENDIX F: BALUN INFORMATION ............................................................................................... 32 Typical Balun Frequency Response ......................................................................................................................... 32 APPENDIX G: VCXO/CRYSTAL CHANGES ..................................................................................... 33 Changing from Crystal Resonator to VCXO ............................................................................................................ 33 Changing from VCXO to Crystal Resonator ............................................................................................................ 36 APPENDIX H: LMK04100 .............................................................................................................. 39 APPENDIX I: PROPERLY CONFIGURING LPT PORT ......................................................................... 42 LPT Driver Loading ................................................................................................................................................. 42 Correct LPT Port/Address ........................................................................................................................................ 42 Correct LPT Mode.................................................................................................................................................... 43 APPENDIX J: TROUBLESHOOTING INFORMATION ........................................................................... 44 1) Confirm Communications ............................................................................................................................. 44 2) Confirm PLL1 operation/locking .................................................................................................................. 44 3) Confirm PLL2 operation/locking .................................................................................................................. 45 2 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Quick Start Full evaluation board instructions with data are downloadable from the product folder of the device at National Semiconductors website, www.ti.com. CLKout1 CLKout1* CLKout2 CLKout2* CLKout3 Power 3.3 V Vcc or Vcc LMK041XX GND OSCin* Fout OSCin uWire header Parallel Port Connector CLKin1* Reference clock from signal generator or other external source CLKin1 CLKout0* Parallel Port Ribbon cable CLKin0* CLKout0 1 CLKout3* CLKout4* 1. Connect a voltage of 3.3 volts to either the Vcc SMA connector or the alternate connector. 2. Connect a reference clock from a signal generator or other source. Exact frequency depends on programming. Default modes use a 122.88 MHz reference. 3. Connect the uWire header to a computer parallel port with the CodeLoader cable. A USB communication option is available, search at www.ti.com for: USB2UWIREIFACE. 4. Program the device with CodeLoader. Ctrl-L must be pressed at least once to load all registers once after CodeLoader is started or after restoring a Mode. CodeLoader is available for download at www.ti.com/tool/codeloader . 5. Measurements may be made at any clock output or Fout if enabled by programming. 2 Reference 4 Program with CodeLoader Be sure to press `Ctrl - L' 3 Laptop or PC Figure 1 - Quick Start Diagram 3 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL Loop Filters and Loop Parameters The loop filters on the LMK041xx evaluation board are setup using the approach above. The loop filter for PLL1 has been configured for a narrow loop bandwidth (< 100 Hz), while the loop filter of PLL2 has been configured for a wide loop bandwidth (> 100 kHz). The specific loop bandwidth values depend on the phase noise performance of the oscillator mounted on the board. The following tables contain the parameters for PLL1 and PLL2 for each oscillator option. Nationals Clock Design Tool can be used to optimize PLL phase noise/jitter for given specifications. See: http://www.ti.com/tool/clockdesigntool PLL 1 Loop Filter Table 1. PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO and 12.288 MHz Vectron Crystal Phase Margin Loop Bandwidth 50 12 Hz K (Charge Pump) Phase Detector Freq 100 uA 1.024 MHz VCO Gain 2.5 kHz/Volt Reference Clock Frequency 122.88 MHz Output Frequency 122.88 MHz (To PLL 2) Loop Filter Components C1 = 100 nF C2 = 680 nF R2 = 39 k PLL2 Loop Filter 122.88 MHz VCXO (Reference Input) LMK041x0B C1 C2 C3 C4 R2 R3 R4 Charge Pump Current, K Phase Detector Frequency Frequency Kvco N Phase Margin Loop Bandwidth 1228.8 8 20 85.5 366 LMK041x1B LMK041x2B Open 12 0 0.01 1.8 0.6 0.2 1474.56 9 24 85.5 343 LMK041x3B Units nF nF nF k k k 3.2 mA 61.44 MHz 1720.32 13 28 85.0 424 1966.08 19 32 84.0 542 MHz MHz/V degrees kHz Note: PLL Loop Bandwidth is a function of K , Kvco, N as well as loop components. Changing K and N will change the loop bandwidth. 4 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Evaluation Board Inputs/Outputs The following table contains descriptions of the various inputs and outputs for the evaluation board. Table 2. LMK041xx Evaluation Board I/O Connector Name CLKout0 / CLKout0*, CLKout1 / CLKout1*, CLKout2 / CLKout2*, CLKout3 / CLKout3*, CLKout4 / CLKout4* Input/Output Description Populated connectors. Differential clock output pairs. See Error! Reference source not found. for format of the output depending on part number. If an LVCMOS output, each output can be independently configured (non-inverted, inverted, tri-state, and LOW). Output On the evaluation board, all clock outputs are AC-coupled to allow safe testing with RF test equipment. All LVPECL/2VPECL clock outputs are terminated to GND with a 120 ohm resistor, one on each output pin of the pair. CLKout4 is configured with an on board balun. Part number is Mini-circuits ADT2-1T. According to the ADT2-1T datasheet the 3 dB frequency range is 0.4 to 450 MHz. See Appendix F: Balun Information for more detail. Populated connector. Fout Vcc Output Input When enabled, buffered VCO output. AC-coupled. The default configuration on the board contains a 3-dB attenuator on the Fout signal. Populated connector. DC power supply for the PCB. Removing R1, R2, or R3 allow for splitting the power to various devices on the board. For example, the VCXO is powered from the VccAUXPlane connected via R3. Note: The LMK04100 Family contains internal voltage regulators for the VCO, PLL and related circuitry. The clock outputs do not have an internal regulator. A clean power supply is required for best performance. Unpopulated connector. VccLDO Input Vcc input for LDOs on bottom of PCB. Refer to schematics for more information. 5 SNLU099 L M K 0 4 1 X X - R E V 3 Connector Name E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Input/Output Description Populated connectors. Reference clock inputs for PLL1. The default board configuration is setup for a single-ended reference source at CLKin0* (CLKin0 pin is AC-coupled to ground). The mode of the clock input buffer is programmable in CodeLoader on the Bits/Pins tab, and may be either bipolar junction mode or MOS mode. CLKin0/CLKin0*, CLKin1/CLKin1* Input The input level for the various modes is as in the datasheet: AC Coupled Input Clock Voltage Levels Input Mode Min Max Units Differential Bipolar 0.25 2.0 Vpp Differential MOS 0.25 2.0 Vpp Single Ended Bipolar 0.5 3.1 Vpp Single Ended MOS 0.5 3.1 Vpp If a DC-coupled clock is used to drive either of the inputs, the high voltage level must be at least 2 volts and the low voltage no greater than 0.4 volts. By default CLKin0 is the active input in either of the autoswitching modes (CLKin0 non-revertive, CLKin0 revertive). When loss of CLKin0 is detected, the device automatically switches to CLKin1 if an active reference clock is attached. See datasheet for further explanation. Unpopulated connectors. LOS0, LOS1 OSCin/OSCin* Output Input Loss-of-Signal indicator (when LOS_TYPE = Active CMOS, default) for CLKin0/0* and CLKin1/1*. The LEDs D5 and D3 are light red when no signal is detected according to the datasheet specification for LOS pins. Bits/Pins, LOS_TYPE = Active CMOS for default operation. Populated connectors. By altering the PCB an external VCXO may be attached to the OSCin/OSCin* SMA connectors. Either a differential or single-ended device may be used. If a single-end device is used, OSCin* should be tied to GND through a capacitor that matches the AC-coupling capacitor value used for the OSCin pin. See datasheet for OSCin port signal specifications. 6 SNLU099 L M K 0 4 1 X X - R E V 3 Connector Name Vtune1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Input/Output Description Unpopulated connector. Output Tuning voltage output from the loop filter for PLL1. If an external VCXO is used, this tuning voltage should be connected to the voltage control pin of the external VCXO. Note: Resistor R38 must be populated with a zero ohm resistor to control an off-board VCXO. Populated connector. uWire Input/Output 10-pin header programming interface for the board. Of Most important are the CLKuWire, DATAuWire, and LEuWire programming lines from this header. Each of these signals, GEO, and SYNC* can be monitored through test points on the board. Unpopulated connector. Output The LD pin is attached to a multiplexer inside the device and may be programmed with a variety of internal signals for monitoring internal device functions and troubleshooting. See datasheet for further explanation. LD_TP Output The lock detect signal is accessible through this pin. Test point attached to the LD pin of the device. See LD above for more information. Unpopulated connector. GOE Input LD Access to GOE of device. Unpopulated connector. SYNC* Input Access to SYNC* of device. Unpopulated connector. PTO Output Vcc SMA located close to OSCin SMAs for powering external oscillator boards. 7 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix A: CodeLoader Usage Code Loader is used to program the evaluation board with either an LPT port using the included CodeLoader cable or with a USB port using the optional USB <--> uWire cable available from http://www.ti.com/tool/usb2uwire-iface. The part number is USB2UWIRE-IFACE. Port Setup Tab Figure 2 - Port Setup tab On the Port Setup tab, the user may select the type of communication port (USB or Parallel) that will be used to program the device on the evaluation board. If parallel port is selected, the user should ensure that the correct port address is entered. The Pin Configuration field is hardware dependent and normally SHOULD NOT be changed by the user. Figure 2 shows the default settings. 8 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Clock Outputs Tab Figure 3 - Clock Outputs tab The clock outputs tab allows the user to Enable/Disable individual clock outputs, select the clock mode (Bypass/Divided/Delayed/Divided & Delayed), set the clock output delay value (if delay is enabled), and the clock output divider value (2, 4, 6, ..., 510). This tab also allows the user to select the VCO Divider value (2, 3, ..., 8). Note that the total PLL2 N divider value is composed of both the VCO Divider value and the N value shown in the blue box in the image, and is given by: N_TOTAL = VCO Divider * N. Clicking on the blue box that contains R, PDF and N values takes the user to the PLL2 tab where these values may be changed. Clicking on the components in the box containing the Internal Loop Filter values allows the user to change these component values. 9 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S The Reference Oscillator value field may be changed in either the Clock Outputs tab or the PLL2 tab. Note this value should match the value of the on-board VCXO or Crystal. When using the EN_PLL2_REF2X = 1, then Reference Oscillator field should be twice the VCXO or Crystal frequency. PLL1 Tab Figure 4 - PLL1 tab. The PLL1 tab allows the user to change: External VCXO (or Crystal oscillator) frequency. Note: This value must be entered in both the PLL1 and PLL2 tabs. PLL1 Phase detector frequency PLL1 R-counter value PLL1 N-counter value CLKin (Reference) oscillator frequency PLL1 Phase Detector polarity (for external VCXO tuning slope, click on the polarity value) PLL1 Charge pump gain (left click and right click on the charge pump current value) PLL1 Charge pump state (click on the charge pump state value) Note that the value entered in the VCO frequency field on the PLL1 tab must match the Reference Oscillator frequency entered on the PLL2 tab and the OSCin_FREQ on the Bits/Pins tab. Updating the PLL2 tab Reference Oscillator frequency will automatically update the value of OSCin_FREQ on the Bits/Pins tab. The only time that the Reference Oscillator frequency of PLL2 tab will be different from the VCO frequency of PLL1 is when the EN_PLL2_REF2X mode is enabled. 10 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL2 Tab Figure 5 - PLL2 tab. The PLL2 tab allows the user to change: VCO frequency PLL2 Phase detector frequency PLL2 R-counter value PLL2 N-counter value The frequency of the external VCXO (or XTAL oscillator). Note: This value must be entered in both the PLL1 and PLL2 tabs. PLL2 Charge pump gain PLL2 Charge pump state Any changes made on this tab are reflected in the Clock Outputs tab. Note that the PLL2 Phase Detector polarity is fixed and cannot be changed by the user. Also note that the VCO frequency should conform to the specified frequency range for the device. Note that the value entered in the VCO frequency field on the PLL1 tab must match the Reference Oscillator frequency entered on the PLL2 tab and the OSCin_FREQ on the Bits/Pins tab. Updating the PLL2 tab Reference Oscillator frequency will automatically update the value of OSCin_FREQ on the Bits/Pins tab. The only time that the Reference Oscillator frequency of PLL2 tab will be different from the VCO frequency of PLL1 is when the EN_PLL2_REF2X mode is enabled. 11 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bits/Pins Tab Figure 6 - Bits/Pins tab. The Bits/Pins tab allows the user to program bits directly. Many of which are not available on other tabs. Refer to the datasheet for more detailed information. The bits available are: Common Box o RESET - Set the reset bit. This will reset the device. In a normal application it is not necessary to program this bit clear since it is auto-clearing. However in the CodeLoader software, RESET must be clicked again (cleared) to not cause a reset every time R7 is programmed. o POWERDOWN - Place the device in powerdown mode. o EN_Fout - Enable the Fout port. PLL Box o PLL_MUX - Set the function of the LD pin. o RC_DLD1_Start - Prevent PLL2 from locking until digital lock detect from PLL1 is achieved. 12 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S o EN_PLL2_XTAL - Enables Crystal mode for PLL2. For use with Crystals as opposed to a VCXO. o EN_PLL2_REF2X - Doubles the reference frequency of PLL2. Note with this is enabled, the PLL_R value is invalid. Program the Reference Oscillator on PLL2 Tab to be twice the VCO frequency on PLL1 tab. This adjustment must be done manually. CLKin Options Box o CLKin_SEL - Sets manual or automatic switching modes for selecting a reference oscillator for PLL1. o LOS_TIMEOUT - The timeout value before a loss of signal on a clock input is registered on the LOS pins. o LOS_TYPE - Set the type of output for the LOS pins. o CLKin0_BUFTYPE & CLKin1_BUFTYPE - Select the input buffer used for the respective clock input. PLL2_LF Box o Set the integrated loop filter values for PLL2 including, PLL2_R3_LF - R3 value PLL2_R4_LF - R4 value PLL2_C3_C4_LF - C3 and C4 value at the same time o It is also possible to set these values by clicking on the loop filter values on the Clock Outputs tab. CLKout Options Box o EN_CLKout_Global - A global enable for clocks, if unchecked no outputs will be observed! o EN_CLKout0 through EN_CLKout4 - Individual clock output enables. These can also be set on the Clock Outputs tab. o The number of options vary depending on the option of the LMK device selected. CLKout#_PECL_LVL - Set the level of an LVPECL output to LVPECL or 2VPECL. The 2VPECL a higher output level than LVPECL. CLKout CMOS Options Box o The presence of this box and the number of options on this tab depends upon the option of the LMK device. CLKout##_STATE - Set the state of the individual LVCMOS output. VCO Control - FC Box o OSCin_FREQ - Must be set to the reference frequency of PLL2 in MHz, which should normally be the VCO frequency of PLL1. NOTE: It is important to enter the correct frequency value in this field, as it is used by the internal state machine of the LMK041xx to execute its calibration routine for the internal VCO. An incorrect value may result in an unlocked condition for the synthesizer. Entering a reference oscillator frequency on PLL2 tab will automatically update this register with the frequency to the nearest MHz. Program Pins Box o GOE - Set high or low voltage on GOE pin. Checked is high voltage. If GOE is low, then no clock outputs will be observed! 13 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S o SYNC* - Set high or low voltage on SYNC* pin. Checked is high voltage. If SYNC* is low, then no clock outputs will be observed on divided clock outputs! o TRIGGER - Set high or low voltage on pin 10 of uWire header. Registers Tab The registers tab shows the value of each register. This is convenient for programming the device to the desired settings, then recording the hex values for programming in your own application. By clicking in the "bit field" it is possible to manually change the value of registers by typing 1 and 0. 14 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix B: Typical Phase Noise Performance Plots PLL1 The LMK041xxs two stage jitter cleaning process involves masking the reference noise with a VCXO or Crystal. Therefore the phase noise performance of the VCXO or Crystal of PLL1 is a very important contributor to the final phase noise of the system. Crystek 122.88 MHz VCXO The phase noise of the reference is masked by the phase noise of this VCXO by using a narrow loop bandwidth. This VCXO sets the reference noise to PLL2. Figure 7 shows the open loop typical phase noise performance of the CVHD-950-122.88 Crystek VCXO. Phase Noise (dBc/Hz) VCXO Phase Noise -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 CVHD-950-122.88 10 100 1000 10000 100000 1000000 10000000 1E+08 Offset (Hz) Figure 7 - CVHD-950-122.88 MHz VCXO Phase Noise at 122.88 MHz Table 3 - VCXO Phase Noise at 122.88 MHz (dBc/Hz) Phase Offset Noise 10 Hz -76.6 100 Hz -108.9 1 kHz -137.4 10 kHz -153.3 100 kHz -162.0 1 MHz -165.7 10 MHz -168.1 40 MHz -168.1 Table 4 - VCXO RMS Jitter to high offset of 20 MHz at 122.88 MHz (rms fs) Low Jitter Offset 10 Hz 515.4 100 Hz 60.5 1 kHz 36.2 10 kHz 35.0 100 kHz 34.5 1 MHz 32.9 10 MHz 22.7 15 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL2 The closed loop performance of the system as measured at the VCO output Fout. Fout phase noise performance of the various LMK options is plotted in Figure 8. Table 5 and Table 6 summarize the phase noise and jitter of Fout. LMK041xx Fout Phase Noise LMK041x0 LMK041x1 LMK041x2 LMK041x3 -50 -60 -70 Phase-80 Noise (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 -170 10 100 1000 10000 100000 1000000 10000000 100000000 Offset (Hz) Figure 8 - LMK041xx PLL2 Phase Noise (Fout) Table 5 - LMK041x0 Phase Noise (dBc/Hz) Offset LMK041x0 LMK041x1 LMK041x2 10 Hz -58.7 -58.3 -61.3 100 Hz -88.0 -88.3 -85.7 1 kHz -111.6 -110.2 -108.9 10 kHz -118.2 -116.3 -115.7 100 kHz -121.1 -119.5 -118.4 1 MHz -132.0 -131.1 -128.6 10 MHz -157.1 -155.8 -154.0 40 MHz -165.9 -164.2 -162.3 LMK041x3 -61.1 -90.4 -107.5 -113.5 -117.0 -125.6 -152.7 -160.8 Table 6 - LMK041x0 RMS Jitter; Integrated to from low limit to 20 MHz (rms fs) Low LMK041x0 LMK041x1 LMK041x2 LMK041x3 Offset 10 Hz 580.0 506.6 443.4 356.0 100 Hz 127.2 117.5 124.5 132.8 1 kHz 114.8 111.3 114.9 128.1 10 kHz 111.7 108.0 112.0 125.0 100 kHz 97.3 92.7 99.2 112.2 1 MHz 39.7 36.2 41.6 50.9 10 MHz 6.0 5.9 6.0 5.5 16 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Clock Outputs The LMK04100 Family features LVDS, LVPECL, 2VPECL, and LVCMOS types of outputs. Included below are various phase noise measurements for each output. Device LVDS LVPECL/2VPECL LVCMOS VCO Frequency LMK041x0 X X 1185 to 1296 MHz (LMK04100) LMK041x1 X X X 1430 to 1570 MHz (LMK04131) LMK041x2 X X 1566 to 1724 MHz (LMK04102) LMK041x3 X X X 1840 to 2160 MHz (LMK04133) Note: The device in parenthesis is the device used for the measurement in these evaluation board instructions. Clock Output Measurement Technique The measurement technique for each output type varies. LVDS - measured with an ADT2-1T balun to test equipment. LVPECL/2VPECL - Measured by terminating complementary output with 50 ohm load, then taking output to test equipment. LVCMOS - Measured by enabling only one side of the LVCMOS output and taking the operating output to test equipment. The following table lists the test conditions used for the phase noise measurements for the VCXO option: Table 7 . LMK041xx test conditions Parameter PLL1 Reference clock input PLL1 Reference Clock frequency PLL1 Phase detector frequency PLL1 Charge Pump Gain VCXO frequency PLL2 phase detector frequency PLL2 Charge Pump Gain PLL2 REF2X mode Value CLKin0* single-ended input, CLKin0 AC-coupled to GND 122.88 MHz 1024 kHz 100 uA 122.88 MHz 61.44 MHz 3200 uA Disabled 17 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK041x0 Phase Noise Fout LVPECL 2VPECL LVCMOS LVPECL; div4 2VPECL; div4 LVCMOS; div4 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 100 1000 10000 100000 1000000 1E+07 1E+08 Offset (Hz) Figure 9 - LMK041x0B Phase Noise The Fout frequency is 1228.8 MHz. The clock out frequency is 614.4 MHz, and the clock out div 4 frequency is 153.6 MHz. Table 8 - LMK041x0 Phase Noise (dBc/Hz) Offset Fout 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 40 MHz -58.7 -88.0 -111.6 -118.2 -121.1 -132.0 -157.1 -165.9 LVPECL 2VPECL LVCMOS -67.1 -95.8 -117.6 -123.8 -127.0 -137.9 -153.8 -154.8 -67.1 -96.8 -117.7 -123.8 -127.0 -137.8 -153.8 -154.8 -66.3 -94.8 -117.9 -124.2 -127.3 -138.1 -152.8 -153.6 LVPECL div4 -79.8 -107.5 -129.5 -134.8 -139.4 -149.5 -157.4 -157.3 2VPECL LVCMOS div4 div4 -81.5 -79.7 -109.1 -106.6 -130.2 -129.4 -135.2 -136.0 -139.3 -139.6 -149.6 -150.0 -158.1 -159.2 -158.0 -159.7 Table 9 - LMK041x0 RMS Jitter; Integrated to from low limit to 20 MHz (rms fs) Low LVPECL 2VPECL LVCMOS Fout LVPECL 2VPECL LVCMOS Limit div4 div4 div4 10 Hz 580.0 474.7 449.2 522.4 493.9 466.5 493.5 100 Hz 127.2 128.3 127.9 127.1 148.9 145.6 139.4 1 kHz 114.8 119.9 120.4 117.9 141.8 138.7 129.9 10 kHz 111.7 116.8 117.3 114.9 139.3 136.2 127.3 100 kHz 97.3 102.9 103.3 101.6 128.8 125.3 116.3 1 MHz 39.7 50.5 50.6 52.4 94.3 89.5 79.5 18 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK041x1 Phase Noise LMK040x1 Phase Noise Fout LVDS LVPECL -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 2VPECL LVCMOS LVDS; div4 LVPECL; div4 2VPECL; div4 LVCMOS; div4 10 100 1000 10000 100000 1000000 1000000 1E+08 0 Offset (Hz) Figure 10 - LMK041x1 Phase Noise The Fout frequency is 1474.56 MHz. The clock out frequency is 737.28 MHz, and the clock out div 4 frequency is 184.32 MHz. Note that the LVDS performance at 737.28 MHz is degraded because it is outside of the baluns operational bandwidth. Table 10 - LMK041x1 Phase Noise (dBc/Hz) LVDS LVPECL div4 div4 -74.8 -76.7 -106.7 -107.7 -128.3 -128.3 -132.8 -134.0 -137.7 -137.7 -148.5 -148.7 -156.9 -157.1 -157.5 -157.3 2VPECL div4 -73.8 -105.3 -128.1 -134.3 -137.8 -148.7 -157.5 -158.0 LVCMOS div4 -74.6 -106.7 -128.3 -134.7 -137.9 -148.9 -158.3 -158.8 Table 11 - LMK041x1 RMS Jitter; Integrated to from low limit to 20 MHz (rms fs) Low LVDS LVPECL Fout LVDS LVPECL 2VPECL LVCMOS Limit div4 div4 10 Hz 506.6 538.4 425.5 458.5 501.9 532.2 445.6 100 Hz 117.5 178.3 132.4 131.8 123.1 141.0 138.6 1 kHz 111.3 174.2 127.0 126.4 116.2 135.1 133.3 10 kHz 108.0 169.5 123.4 122.8 113.0 132.4 130.7 100 kHz 92.7 147.7 107.2 106.7 98.7 120.7 119.0 1 MHz 36.2 72.9 50.4 50.1 49.1 85.2 83.4 2VPECL div4 591.0 139.1 131.4 128.7 116.8 80.3 LVCMOS div4 544.1 132.5 125.5 122.8 110.8 73.4 Offset Fout LVDS 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 40 MHz -58.3 -88.3 -110.2 -116.3 -119.5 -131.1 -155.8 -164.2 -62.0 -96.4 -115.3 -118.1 -122.0 -133.5 -148.2 -149.5 LVPECL 2VPECL LVCMOS -65.4 -95.9 -115.7 -121.2 -124.7 -136.2 -152.3 -153.5 -66.4 -96.0 -115.8 -121.3 -124.7 -136.2 -152.3 -153.6 19 -63.4 -94.8 -116.2 -122.0 -125.5 -137.0 -151.7 -152.5 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK041x2 Phase Noise Fout LMK040x2 Phase Noise LVPECL 2VPECL -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 LVCMOS LVPECL; div4 2VPECL; div4 LVCMOS; div4 10 100 1000 10000 100000 Offset (Hz) 1000000 1000000 0 1E+08 The Fout frequency is 1720.32 MHz. The clock out frequency is 860.16 MHz, and the clock out div 4 frequency is 215.04 MHz. Table 12 - LMK041x2 Phase Noise (dBc/Hz) Offset Fout 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 40 MHz -61.3 -85.7 -108.9 -115.7 -118.4 -128.6 -154.0 -162.3 LVPECL 2VPECL LVCMOS -66.6 -91.5 -114.3 -120.7 -123.5 -133.4 -151.5 -153.0 -67.3 -90.4 -114.2 -120.7 -123.5 -133.4 -151.5 -153.2 -67.7 -91.9 -114.6 -120.6 -123.5 -133.4 -151.6 -153.2 LVPECL div4 -80.1 -103.3 -126.7 -133.5 -136.7 -146.2 -156.7 -157.0 2VPECL LVCMOS div4 div4 -78.7 -78.9 -103.2 -103.8 -127.2 -126.5 -133.7 -134.1 -136.7 -136.8 -146.3 -146.5 -157.0 -157.7 -157.3 -158.2 Table 13 - LMK041x2 RMS Jitter; Integrated to from low limit to 20 MHz (rms fs) Low LVPECL 2VPECL LVCMOS Fout LVPECL 2VPECL LVCMOS Limit div4 div4 div4 10 Hz 443.4 498.1 477.3 450.5 439.3 473.4 458.5 100 Hz 124.5 143.1 140.8 140.4 141.0 140.7 136.6 1 kHz 114.9 132.7 132.1 132.0 132.3 131.1 126.6 10 kHz 112.0 129.6 129.0 129.0 130.0 128.7 124.2 100 kHz 99.2 115.7 115.2 115.2 119.7 118.3 113.7 1 MHz 41.6 54.9 54.8 54.7 79.2 77.1 71.8 20 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK041x3 Phase Noise LMK040x3 Phase Noise -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 Fout LVDS LVPECL 2VPECL LVCMOS LVDS; div4 LVPECL; div4 2VPECL; div4 LVCMOS; div4 10 100 1000 10000 100000 1000000 1E+07 1E+08 Offset (Hz) The Fout frequency is 1966.08 MHz. The clock out frequency is 983.04 MHz, and the clock out div 4 frequency is 245.76 MHz. Note that the LVDS performance at 737.28 MHz is degraded because it is outside of the baluns operational bandwidth. Table 14 - LMK041x3 Phase Noise (dBc/Hz) LVDS LVPECL div4 div4 -76.1 -75.2 -103.5 -103.7 -125.5 -125.8 -130.3 -131.4 -135.2 -135.3 -143.5 -143.6 -156.3 -156.1 -156.8 -156.4 2VPECL div4 -75.9 -104.4 -125.5 -131.5 -135.3 -143.6 -156.3 -156.6 LVCMOS div4 -80.1 -106.3 -125.4 -132.0 -135.3 -143.7 -156.8 -157.3 Table 15 - LMK041x3 RMS Jitter; Integrated to from low limit to 20 MHz (rms fs) Low LVDS LVPECL Limit Fout LVDS LVPECL 2VPECL LVCMOS div4 div4 10 Hz 356.0 531.5 367.7 339.0 367.6 471.8 499.6 100 Hz 132.8 210.0 153.3 153.4 137.4 147.1 146.5 1 kHz 128.1 205.5 149.2 149.5 132.6 140.7 140.5 10 kHz 125.0 200.9 145.8 146.1 129.6 138.1 137.9 100 kHz 112.2 181.2 131.6 131.9 117.3 127.2 127.1 1 MHz 50.9 88.9 64.4 64.5 59.5 79.6 80.6 2VPECL div4 464.0 146.2 140.2 137.6 126.7 79.7 LVCMOS div4 338.9 141.5 137.1 134.4 123.5 75.8 Offset Fout LVDS 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 40 MHz -61.1 -90.4 -107.5 -113.5 -117.0 -125.6 -152.7 -160.8 -63.9 -92.1 -112.2 -115.1 -119.1 -127.6 -148.0 -147.2 LVPECL 2VPECL LVCMOS -66.2 -94.6 -112.8 -118.1 -121.8 -130.4 -150.6 -151.9 -67.6 -93.9 -112.8 -118.2 -121.9 -130.4 -150.6 -151.9 21 -67.0 -94.3 -113.6 -119.7 -123.0 -131.5 -150.0 -151.2 SNLU099 GND_TP VccAuxPlane VccAuxPlane 8 7 22 SNLU099 6 PCB of bottom on placed are 200 to equal and than greater Designators 4 2 1 3 5 VccPLLPlane 4 3 VccCLKoutPlane VccCLKoutPlane 6 5 VccPLLPlane Vcc Vcc values Component LP5900 D N G 2 1 3 Open Header GND Header Vcc Open Open 2 C223 Open C221 5 1 Open R215 V_LM5900 VccAuxPlane uF 10 C21 boards Oscillator external for Off Take Power VccAuxPlane nF 3.9 = (C4) C215 uF 10 = (C3) C216 uF 0.01 = (C2) C218 etc. LDOs, VCXOs, and XO for Plane Power uF 4.7 = C214(C1) values: component V 3.3 LP3878-ADJ Open C220 CLK4 Open R213 3 D N C N C N T U O Open Open Open uF 1 P C219 Open C218 VccCLKoutPlane PTO uF 0.1 uF 1 C23 C22 k 51 = R211(R3) k 1 = (R2) R213 k 2.3 = (R1) R212 nF 10 uF 0.1 2 L L C20 C19 C18 D N G P LP5900SD-3.3 A V U202 D G P VIN 6 A VEN 4 R216 C222 R214 D Open Open Open Open Open C217 Open CLK3 C N Open 7 C216 R212 C215 Open P Y B C N R211 1 2 C214 J D A D S Open 6 8 uF 0.1 Open T U O V VIN 5 4 R210 C17 C213 Open PDCP2 V_LM3878-ADJ U200 C212 LP3878-ADJ CLK2 nF 10 uF 0.1 uF 1 C16 C15 C14 Open C211 Open OSCin LDO_Out C210 CLK1 Open Open C209 Open Open R209 VCXO_IC R208 C208 VccAuxPlane Open Open Open uF 0.1 uF 1 uF 10 C207 C206 Open Open C13 C12 C11 R207 C205 CLK0 Open R206 4 2 VccCLKoutPlane uF 0.1 Open Open R205 VccCLKoutPlane Open TAB Vadj Open PDCP1 C10 C204 R204 Open R203 Open Vout Vin Outputs CLKout LMK for Plane Power 3 1 R202 R201 VccPLLPlane V_LM317 U201 LM317 Open Open C203 CLKin R200 Options Power LDO nF 10 uF 0.1 uF 1 nF 10 uF 0.1 uF 1 9 C 8 C 7 C 6 C 5 C 4 C Open Digital C202 ohm 0 2 2 1 1 3 R Open uF 0.1 uF 1 uF 10 VccAuxPlane 1 J 3 C 2 C 1 C C201 LDO] [inc VCO ohm 0 2 R VccPLLPlane VccCLKoutPlane ohm 0 SMA Open Outputs Except LMK for Plane Power Vcc C200 LDO] [inc Fout 1 R VccPLLPlane Vcc Power Direct O P E R A T I N G Open D N G uF 0.47 = C222 POWER_SMALL B O A R D Vcc_TP uF 0.47 = C223 VccLDO E V A L U A T I O N Open k 51 = R216 Open L M K 0 4 1 X X - R E V 3 I N S T R U C T I O N S LMK04100BEVAL schematic. Refer to BOM for differences. Appendix C: Schematics Power Attenuation and Matching 23 ohm 0 C62 R64 Open uF 0.1 C61 R63 Open uF 0.1 R62 ohm 0 XO CLKin1 SMA CLKin1 Open R60 C60 C59 C57 Open C56 Open Open Open R59 Open R58 SNLU099 R57 R56 Open 1 6 Open Vtune s V C55 Open Open R55 R54 R53 R52 VccAuxPlane VccAuxPlane D N G F R C 2 5 N RF* C54 3 4 ohm 100 3 U Open Open Open R51 Open R50 R49 R48 C52 SMA ohm 0 CLKin1* R47 ohm 0 C51 Open uF 0.1 C50 ohm Open 270 R46 C49 Open LD Analog R45 C48 ohm 0 k 3.9 R44 R2_B1 Open VccAuxPlane Open Open D L LED Green Open R43 R42 1 D 2 D uF 10 Open nF 330 uF 1 Indicator LD C2pB1 C2_B1 C1_B1 D L VccAuxPlane C47 zener V 3.3 Filter Loop Crystal Vtune_XTAL 7 D Open E O G Translation Voltage GOE ohm 180 k 2.2 R41 R40 k 39 Open Open R37 R2_A1 Vtune1 R38 Vtune1 Open Open C46 C45 0.1 uF VccAuxPlane ohm 0 Open nF 680 nF 100 R39 C2pA1 C2_A1 C1_A1 VoltageTranslation SYNC* Vtune1 Filter Loop VCXO Vtune_VCXO Open zener V 3.3 C44 ohm 180 8 D Filters Loop PLL1 R36 Open Open uF 0.1 Open R34 Open VCXO OSCin uWire C42 C43 1 8 6 HEADER_2X5(POLARIZED) 4 9 7 2 VccAuxPlane 5 R35 3 k 2.2 1 SYNC* * C N Y S R33 0 Open OSCin pF 2.0 ohm 0 R32 C41 D L Open R31 k 4.7 nF 2.2 C40 uF 1 pF 100 R30 2 C39 C38 R29 R28 ohm 0 Open Open SMV-1249-074 R27 nF 1 Open R26 R25 k 15 k 27 C37 k 10 Open uF 0.1 Open CVHD-950-122.88 C3_AB1 VccAuxPlane 1 Y R24 C36 3 Open Vtune s V R23 1 6 Vtune_XTAL Y200 LEuWire Vtune_VCXO 1 D N G F R C 2 5 R22 k 4.7 N RF* Open 9 D nF 2.2 Open CLKout0_P 3 4 R21 R19 R18 uF 0.1 pF 2.0 4 U R20 C35 CLKout0_N Open C34 k 15 k 27 R17 C33 ohm 100 Open R16 Crystal Tuneable OSCin R15 uF 0.47 LD_TP GOE_TP DATAuWire Open C32 VccPLLPlane VccPLLPlane OSCin* Open VccCLKoutPlane uF 0.1 VccPLLPlane R14 C31 ohm 51 R12 R11 2 2 2 2 2 1 1 1 1 1 1 1 4 3 2 1 0 9 8 7 6 5 4 3 R13 Vcc7 CPout1 Vcc6 CLKin0* CLKin0 Vcc5 Vcc4 G DLD_BYP CLKout0* CLKout0 Vcc3 k 2.7 k 15 k 27 N R2_B2 D Open nF 6.8 Open CLKin1 D L Filter Loop Crystal 1 C2pB2 C2_B2 C1_B2 6 2 5 2 CLKin1* E O 1 G 2 uF 0.1 1 SYNC*_TP CLKuWire C30 SYNC* LDObyp2 uF 10 7 2 0 1 C29 SYNC* OSCin LDObyp1 8 2 9 pF 33 pF 33 PAD DAP Filters Loop PLL2 0 C28 C27 OSCin* Vcc2 k 1.8 Open 9 2 8 R2_A2 C1_A2 VccPLLPlane pF 33 Vcc8 C N 0 3 7 C26 VccPLLPlane nF 12 Open Open R10 Vcc9 LEuWire LMK040xxB Translation Voltage uWire C2_A2 1 3 6 ohm 0 C2pA2 Filter Loop VCXO CPout2 DATAuWire 2 3 5 9 R VccPLLPlane Vcc10 CLKuWire 2 E N U T V 3 3 4 CLKin0_LOS Vcc1 4 3 3 LED Red Open CLKout1 CLKout2 CLKout3 CLKout4 Bias Vcc11 Vcc12 Vcc13 Vcc14 VccAuxPlane 6 3 1 ohm 270 8 R uF 1 Open 3 3 3 4 4 4 4 4 4 4 4 4 7 8 9 0 1 2 3 4 5 6 7 8 LOS0 C25 LMK04000B 1 U Indication LOS VccPLLPlane VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane Open C24 LOS1 CLKout4_N ohm 270 CLKout4_P 4 R CLKout1_P Open CLKout3_N CLKout1_N CLKout3_P VccAuxPlane CLKout2_P LED Red 6 D 5 CLKout1* CLKout2* CLKout3* CLKout4* D N G 5 R D 5 3 2 pF 100 ohm 18 Matching Impedance and Balun Fout 3 CLKin1_LOS t u o F 7 R 6 R t u o F D 4 D VTUNE2_TP1 VccPLLPlane ohm 270 ohm 270 SMA PCB of bottom on placed are 200 to equal and than greater Designators CLKout2_N I N S T R U C T I O N S Open Open Open C53 CLKin0 O P E R A T I N G Open ohm 51 R65 R61 Open Open B O A R D Impedance Crystal CLKin1 ohm 0 Open C58 CLKin0* E V A L U A T I O N CLKin1 Attenuation and Matching Impedance CLKin0 ohm 0 SMA L M K 0 4 1 X X - R E V 3 LMK04100BEVAL schematic. Refer to BOM for differences. Main mask. metal via CMOS or LVPECL made be can CLKout3 and CLKout2 CLKout1, 3. PCB of bottom on placed are 200 to equal and than greater Designators CMOS. never and type same the both are CLKout4 and CLKout0 2. loading. capacitive of effects the test to connectors SMA CLKout all near placed be will stub A 1. Notes: 24 SNLU099 R118 Open Simulation Load Resistors Emitter CLKout3_2_N CLKout3_1_N CLKout2_2_N SMA SMA C72 R114 C71 Open ohm 120 Open Bias Vcc Block DC Block DC CLKout3* CLKout2* Bias Vcc R112 R111 R110 R109 Open ohm 120 Open Open uF 0.1 uF 0.1 R108 R107 R106 R105 ohm 0 ohm 0 CLKout3_P CLKout3_2_P CLKout3_1_P CLKout2_2_P CLKout2_1_P SMA SMA C70 R104 C69 R103 Open Open Open Open CLKout3 CLKout2 R102 R101 R100 R99 VccCLKoutPlane VccCLKoutPlane LVCMOS - 3 option Output LVPECL/2VPECL - 3 option Output LVPECL/2VPECL - 1 option Output LVPECL/2VPECL - 1 option Output LVCMOS - 0 option Output LVPECL/2VPECL - 0 option Output CLKout2 CLKout3 VccCLKoutPlane Open Open uF 0.1 R98 R97 ohm 0 Simulation Load Resistors Emitter CLKout1_2_N CLKout1_1_N R96 SMA C68 Open Open Bias Vcc Block DC CLKout1* R95 R94 Open Open uF 0.1 R93 R92 ohm 0 CLKout1_P CLKout1_2_P CLKout1_1_P R91 SMA C67 Open Open CLKout1 R90 R89 VccCLKoutPlane LVPECL/2VPECL - 3 option Output LVPECL/2VPECL - 1 option Output LVCMOS - 0 option Output CLKout1 VccCLKoutPlane VccCLKoutPlane R88 Open R86 R85 R84 R83 R87 uF 0.1 uF 0.1 Open Open Open ohm 0 Open ohm 0 SMA CLKout4_N CLKout0_N Simulation Load Resistors Emitter Point Test Probe Simulation Load Resistors Emitter CLKout4_3_N CLKout4_2_N CLKout4_1_N CLKout0* CLKout0_2_N CLKout0_1_N R82 SMA ADT2-1T C66 C65 Block DC ohm 120 ohm 120 Open Open Bias Vcc Bias Vcc Bias Vcc Block DC CLKout4* D P S 3 4 R81 R80 R79 R78 C N SCT 2 5 P D S Open ohm 120 Open 1 6 ohm 120 Open uF 0.1 R77 1 B R76 R75 R74 ohm 0 Open ohm 0 SMA CLKout4_P CLKout0_P CLKout4_3_P CLKout4_2_P CLKout4_1_P CLKout0 CLKout0_2_P CLKout0_1_P R73 Open C64 R72 R71 C63 Open Open ohm 0 Open Open CLKout4 R70 R69 R68 R67 R66 VccCLKoutPlane VccCLKoutPlane LVDS - 3 option Output LVPECL/2VPECL - 1 option Output LVPECL/2VPECL - 0 option Output LVDS - 3 option Output CLKout4 CLKout0 LVPECL/2VPECL - 1 option Output LVPECL/2VPECL - 0 option Output O P E R A T I N G R117 ohm 0 CLKout3_N Simulation Load CLKout2_1_N R113 Open CLKout1_N B O A R D Open uF Open 0.1 R116 R115 uF 0.1 Open Resistors Emitter CLKout2_P E V A L U A T I O N VccCLKoutPlane VccCLKoutPlane ohm 0 CLKout2_N L M K 0 4 1 X X - R E V 3 I N S T R U C T I O N S LMK04100BEVAL schematic. Refer to BOM for differences. Clock Outputs L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix D: Board Layers Stackup Layers of the 6 layer evaluation board include: Blue is dielectrics Top Copper. 1oz thick [LMK04100.GTL] Top layer for high priority high frequency signals o 1 oz CU RO4003 Dielectric, 16 mils Ground plane FR4, 2.5 mils thick. Power plane #1 - VccCLK FR4, xx mils middle ground plane FR4, xx mils VccPLL, VccAux FR4, xx mils Bottom layer copper clad for thermal relief RO4003 (Er = 3.38) CONTROLLED THICKNESS of 16 mils thick GND plane [LMK04100.GP1] FR4 Top to bottom layer order: LMK04100.GTL (1) top copper LMK04100.GP1 (2) gnd LMK04100.GP2 (3) vcc LMK04100.GP3 (4) gnd LMK04100.G1 (5) vcc LMK04100.GBL (6) bottom copper Middle Ground Plane FR4 Vcc mixed plane [LMK04100.G1] FR4 Bottom Copper - Thermal relief [LMK04100.GBL] 25 SNLU099 62 mils thick total FR4 (Er = ~4.6) CONTROLLED THICKNESS: 2.5 mils thick VccCLK plane [LMK04100.GP2] L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix E: Bill of Materials Common Bill of Materials for Evaluation Boards (page 1/3) Part Capacitors 2.0 pF 33 pF 100 pF 1 nF 2.2 nF 6.8 nF 10 nF 12 nF Manufacturer Part Number Kemet Kemet Kemet Kemet Kemet Kemet Kemet Panasonic C0603C209C5GAC C0402C330J5GAC C0603C101J5GAC C0603C102J5GAC C0603C222K5RAC C0603C682K1RACTU C0603C103K1RACTU ECH-U01123JX5 2 3 2 1 2 1 4 1 0.1 uF Kemet C0603C104J3RAC 25 100 nF 330 nF 0.47 uF 680 nF 1 uF 10 uF Kemet Kemet Kemet Kemet Kemet Kemet C0603C104J3RAC C0603C334K4RACTU C0603C474K8PACTU C0603C684K8PAC C0603C105K8PAC C0805C106K9PAC 1 1 1 1 10 5 26 SNLU099 Qnt Identifier C33, C41 C26, C27, C28 C24, C38 C37 C35, C40 C2_B2 C6, C9, C16, C20 C2_A2 C3, C5, C8, C10, C13, C15, C17, C19, C23, C30, C34, C36, C45, C48, C59, C60, C63, C65, C66, C67, C68, C69, C70, C71, C72 C1_A1 C1_B1 C32 C2_A1 C2, C4, C7, C12, C14, C18, C22, C25, C39, C47 C1, C2pB1, C11, C21, C29 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Common Bill of Materials for Evaluation Boards (continued, 2/3) Resistors 0 ohm Vishay/Dale CRCW06030000Z0EA 23 18 ohm 51 ohm 100 ohm 120 ohm 180 ohm 270 ohm 1.8 k 2.2 k 2.7 k 3.9 k 4.7 k 10 k 15 k 27 k 39 k Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale Vishay/Dale CRCW060318R0JNEA CRCW060351R0JNEA CRCW0603100RJNEA CRCW0603120RJNEA CRCW0603180RJNEA CRCW0603270RJNEA CRCW06031K80JNEA CRCW06032K20JNEA CRCW06032K70JNEA CRCW06033K90JNEA CRCW06034K70JNEA CRCW060310K0JNEA CRCW060315K0JNEA CRCW060327K0JNEA CRCW060339K0JNEA 1 2 2 2 2 5 1 2 1 1 2 1 3 3 1 Other POWER_SMALL Weidmuller 1594540000 1 SMA Johnson Components 142-0701-851 14 SMA_FRAME Red LED Green LED 0.875" Standoff ADT2-1T HEADER_2X5(POLARIZED) 3.3 V zener SMV-1249-074 Printed Circuits Corp. Lumex Lumex SPC Technology Minicircuits FCI Electronics Comchip Skyworks PCB SML-LX2832IC-TR SML-LX2832GC-TR SPCS-14 ADT2-1T+ 52601-S10-8 CZRU52C3V3 SMV1249-074LF 1 2 1 4 1 1 2 1 27 SNLU099 C51, C58, C62, R1, R2, R3, R26, R32, R44, R47, R60, R65, R68, R71, R73, R82, R85, R91, R96, R103, R104, R113, R114 R5 R13, R62 R16, R51 R107, R111 R36, R41 R4, R6, R7, R8, R45 R2_A2 R35, R40 R2_B2 R2_B1 R20, R30 R23 R12, R19, R29 R11, R18, R28 R2_A1 J1 CLKin0*, CLKin1, CLKin1*, CLKout0*, CLKout0, CLKout1*, CLKout1, CLKout2*, CLKout2, CLKout3*, CLKout3, CLKout4*, Fout, Vcc F1 D3, D5 D1 S1, S2, S3, S4 B1 uWire D7, D8 D9 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Common Bill of Materials for Evaluation Boards (continued, 3/3) Open Open R 78 Open C 44 Open U 4 Open SMA 12 Open Open Y D 1 3 28 SNLU099 R14, R17, R21, R22, R24, R25, R27, R33, R34, R38, R42, R43, R46, R48, R49, R50, R52, R53, R54, R55, R56, R57, R58, R59, R61, R63, R64, R66, R67, R69, R70, R72, R75, R77, R78, R79, R83, R84, R86, R87, R88, R89, R90, R93, R94, R97, R98, R99, R100, R101, R102, R105, R106, R108, R109, R110, R112, R115, R116, R117, R118, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216 C1_A2, C1_B2, C2pB2, C2pA2, C2pA1, C2_B1, C3_AB1, C43, C44, C46, C49, C50, C52, C53, C54, C55, C56, C57, C61, C64, C200, C201, C202, C203, C204, C205, C206, C207, C208, C209, C210, C211, C212, C213, C214, C215, C216, C217, C218, C219, C220, C221, C222, C223 U3, U200, U201, U202 OSCin*, OSCin, LOS0, LOS1, VccLDO, LD, PTO, GOE, SYNC*, CLKout4, Vtune1, CLKin0 Y200 D2, D4, D6 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bill of Material Custom to LMK04100BEVAL Part Capacitors 0.1 uF Manufacturer Part Number Kemet C0603C104J3RAC 2 C31, C42 Resistors 0 ohm 120 ohm Vishay/Dale Vishay/Dale CRCW06030000Z0EA CRCW0603120RJNEA 2 4 R9, R39 R74, R76, R80, R81 Other LMK04100B CVHD-950-122.88 National Semiconductor Crystek LMK04100B CVHD-950-122.88 1 1 U1 U4 6 1 R10, R15, R31, R37, R92, R95 Y1 Open Open Open Qnt Identifier Bill of Material Custom to LMK04100BEVAL-XO Part Capacitors Manufacturer Part Number Resistors 0 ohm 120 ohm Vishay/Dale Vishay/Dale CRCW06030000Z0EA CRCW0603120RJNEA 4 4 R10, R15, R31, R37 R74, R76, R80, R81 Other LMK04100B 12.288 MHz XTAL National Semiconductor Vectron LMK04100B VXB1-1127-12M288 1 1 U1 Y1 2 4 1 C31, C42 R9, R39, R92, R95 U4 Open Open Open Open 29 SNLU099 Qnt Identifier L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bill of Material Custom to LMK04131BEVAL Part Capacitors 0.1 uF Manufacturer Part Number Qnt Identifier Kemet C0603C104J3RAC 2 C31, C43 Resistors 0 ohm 120 ohm Vishay/Dale Vishay/Dale CRCW06030000Z0EA CRCW0603120RJNEA 2 2 R9, R39 R92, R95 Other LMK04131B CVHD-950-122.88 National Semiconductor Crystek LMK04131B CVHD-950-122.88 1 1 U1 U4 Open Open 8 Open 1 R10, R15, R31, R37, R74, R76, R80, R81 Y1 Bill of Material Custom to LMK04131BEVAL-XO Part Capacitors Manufacturer Part Number Resistors 0 ohm 120 ohm Vishay/Dale Vishay/Dale CRCW06030000Z0EA CRCW0603120RJNEA 4 2 R10, R15, R31, R37 R92, R95 Other LMK04131B 12.288 MHz XTAL National Semiconductor Vectron LMK04131B VXB1-1127-12M288 1 1 U1 Y1 2 6 1 C31, C42 R9, R39, R74, R76, R80, R81 U4 Open Open Open Open 30 SNLU099 Qnt Identifier L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Bill of Material Custom to LMK04102BEVAL Part Capacitors 0.1 uF Manufacturer Part Number Kemet C0603C104J3RAC 2 C31, C42 Resistors 0 ohm 120 ohm Vishay/Dale Vishay/Dale CRCW06030000Z0EA CRCW0603120RJNEA 2 4 R9, R39 R74, R76, R80, R81 Other LMK04102B CVHD-950-122.88 National Semiconductor Crystek LMK04102B CVHD-950-122.88 1 1 U1 U4 6 1 R10, R15, R31, R37, R92, R95 Y1 Open Open Open Qnt Identifier Bill of Material Custom to LMK04133BEVAL Part Capacitors 0.1 uF Manufacturer Part Number Qnt Identifier Kemet C0603C104J3RAC 2 C31, C42 Resistors 0 ohm 120 ohm Vishay/Dale Vishay/Dale CRCW06030000Z0EA CRCW0603120RJNEA 2 2 R9, R39 R92, R95 Other LMK04133B CVHD-950-122.88 National Semiconductor Crystek LMK04133B CVHD-950-122.88 1 1 U1 U4 Open Open 8 Open 1 31 SNLU099 R10, R15, R31, R37, R74, R76, R80, R81 Y1 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix F: Balun Information Typical Balun Frequency Response The following figure illustrates the typical frequency response of the Mini-circuits ADT2-1T balun. Typical Balun Insertion Loss 10 9 8 Loss (dB) 7 6 ADT2-1T 5 4 3 2 1 0 10 100 1000 Frequency (MHz) Figure 11 - Typical Balun Frequency Response 32 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix G: VCXO/Crystal changes This appendix contains instructions for changing the active on-board oscillator for PLL1. Changing from Crystal Resonator to VCXO If the board has been setup to use the crystal-based oscillator with PLL1, the crystal may be disabled and the VCXO enabled as described on the following pages: Summary 1. Connect power to VCXO 2. Disconnect Crystal RF path and connect VCXO RF path 3. Connect charge pump output from PLL1 to VCXO Loop Filter (A1) and VCXO. 4. Connect charge pump output from PLL2 to VCXO Loop filter (A2). Procedures 1. Connect power to VCXO a. Install a 0 ohm resistor in R26 (near the VCXO) Figure 12 33 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 2. Disconnect Crystal RF path and connect VCXO RF path a. Remove resistors R15 and R31. b. Install 0.1 uF capacitors in C31 and C43. Figure 13 3. Connect charge pump output from PLL1 to VCXO Loop Filter (A1) and VCXO. a. Remove R37 and install a 0 ohm resistor in R39. This resistor can be "switched" between the two footprints. Figure 14 34 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 4. Connect charge pump output from PLL2 to VCXO Loop filter (A2). a. Remove R10 and install a 0 ohm resistor in R9. This resistor can be "switched" between the two footprints. Figure 15 35 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Changing from VCXO to Crystal Resonator If the board has been setup to use the VCXO for PLL1, the VCXO may be disabled and the crystal enabled as described on the following pages: Summary 1. Remove power from VCXO 2. Disconnect VCXO RF path and connect Crystal RF path 3. Connect charge pump output from PLL1 to Crystal Loop Filter (B1) and Crystal 4. Connect charge pump output from PLL2 to Crystal Loop filter (B2) Procedures 1. Remove power from VCXO a. Remove 0 ohm resistor in R26 (near the VCXO) Figure 16 36 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 2. Disconnect VCXO RF path and connect Crystal RF path a. Install 0 ohm resistors R15 and R31. b. Remove 0.1 uF capacitors in C31 and C43. Figure 17 3. Connect charge pump output from PLL1 to Crystal Loop Filter (B1) and Crystal a. Remove R39 and install a 0 ohm resistor in R37. This resistor can be "switched" between the two footprints. Figure 18 37 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 4. Connect charge pump output from PLL2 to Crystal Loop filter (B2) a. Remove R9 and install a 0 ohm resistor in R10. This resistor can be "switched" between the two footprints. Figure 19 38 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix H: LMK04100 The block diagram in Figure 20 illustrates the functional architecture of the LMK041xx clock conditioner. It features a cascaded, dual PLL arrangement, available internal loop filter components for PLL2, internal VCO with PLL2 for frequency synthesis, and clock distribution section with individual clock output dividers and delay adjustment blocks. The dual reference clock input to PLL1 provides fail-safe redundancy for phase locked loop operation. The cascaded PLL architecture allows PLL1 to be used as a jitter cleaner for an incoming reference clock that contains excessive phase noise. This requires the user to select an external oscillator (VCXO or crystal) that provides the desired phase noise performance at the clock output. This external oscillator becomes the reference clock for PLL2 and along with the phase noise characteristics of PLL2 and the internal VCO, determines the final phase noise performance at FOUT and the output of the clock distribution section. vcxo CLKin0 R1 Dq1 R2 FOUT Dq2 VCO CLKin1 N1 PLL1 N2 PLL2 CHAN DIV DATA CLK VCO DIV CLKout_0 D uWire Interface 5 Output Clock Channels LVPECL, LVDS, LVCMOS LE CHAN DIV D CLKout_4 Figure 20 - Functional Block Diagram of the LMK041xx Dual PLL Precision Clock Conditioner with External VCXO module. 39 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S PLL1 has been designed to work with either an off-the-shelf VCXO package or with a userdesigned discrete implementation that employs a crystal resonator and associated tuning components. The Figure 21 shows an example of a discretely implemented VCXO using a crystal resonator. CLKin0 R1 Dq1 R2 FOUT Dq2 VCO CLKin1 N1 PLL1 N2 PLL2 CHAN DIV DATA CLK VCO DIV CLKout_0 D uWire Interface 5 Output Clock Channels LVPECL, LVDS, LVCMOS LE CHAN DIV D CLKout_4 Figure 21 - LMK041xx with the XTAL Resonator option and Tuning Circuit LMK04100 Family evaluation boards are configured with either a VCXO or Crystal (-XO) on board. It is possible to place a VCXO on a Crystal board or a Crystal on a VCXO board by removing and replacing certain components on the board. Instructions for modifying the board are presented in Appendix G: VCXO/Crystal changes. Figure 22 below shows the crystal oscillator circuit diagram. 40 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S OSCin* Copt CC1 = 2.2 nF R1 = 4.7k SMV1249-074LF R3 = 10k LMK040xx XTAL 1 nF R2 = 4.7k CC2 = 2.2 nF OSCin CPout1 Copt PLL1 Loop Filter Figure 22 - Crystal Oscillator Circuit diagram 41 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix I: Properly Configuring LPT Port When trying to solve any communications issue, it is convenient to program the POWERDOWN bit to confirm high/low current draw of the evaluation board or the PLL_MUX between "Logic Low" and "Logic High" LD output to confirm successful communications. LPT Driver Loading The parallel port must be configured for proper operation. To confirm that the LPT port driver is successfully loading click "LPT/USB" "Check LPT Port." If the driver properly loads then the following message is displayed: Figure 23 - Successfully Opened LPT Driver Successful loading of LPT driver does not mean LPT communications in CodeLoader are setup properly. The proper LPT port must be selected and the LPT port must not be in an improper mode. The PC must be rebooted after install for LPT support to work properly. Correct LPT Port/Address To determine the correct LPT port in Windows, open the device manager (On Windows XP, Start Settings Control Panel System Hardware Tab Device Manager) and check the LPT port under the Ports (COM & LPT) node of the tree. It can be helpful to confirm that the LPT port is mapped to the expected port address, for instance to confirm that LPT1 is really mapped to address 0x378. This can be checked by viewing the properties of the LPT1 port and viewing resources tab to verify that the I/O Range starts at 0x378. CodeLoader expects the a traditional port mapping: Port Address LPT1 0x378 LPT2 0x278 LPT3 0x3BC If a non-standard address is used, use the "Other" port address in CodeLoader and type in the port address in hexadecimal. It is possible to change the port address in the computers BIOS settings. The port address is set in CodeLoader at the Port Setup tab as shown in Figure 24. 42 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Figure 24 - Selecting the LPT Port Correct LPT Mode If communications are not working, then it is possible the LPT port mode is set improperly. It is recommended to use the simple, Output-only mode of the LPT port. This can be set in the BIOS of the computer. Common terms for this desired parallel port mode are "Normal," "Output," or "AT." It is possible to enter BIOS setup during the initial boot up sequence of the computer. 43 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S Appendix J: Troubleshooting Information If the evaluation board is not behaving as expected, the most likely issues are... 1) Board communication issue 2) Incorrect Programming of the device 3) Setup Error Refer to this checklist for a practical guide on identifying/exposing possible issues. 1) Confirm Communications Refer to Appendix I: Properly Configuring LPT Port to trouble shoot this item. Remember to load device with Ctrl-L! 2) Confirm PLL1 operation/locking 1) Program PLL_MUX = "PLL 1 R Divider /2" 2) Confirm that LD pin output is half the expected phase detector frequency of PLL1. i. If not, examine CLKin_SEL programming. ii. If not, examine CLKin0_BUFTYPE / CLKin1_BUFTYPE. iii. If not, examine PLL1 register R programming. iv. If not, examine physical CLKin input. 3) Program PLL_MUX = "PLL 1 N Divider /2" 4) Confirm that LD pin output is half the expected phase detector frequency of PLL1. i. If not, examine PLL1 register N programming. ii. If not, examine physical OSCin input. Naturally, the output frequency of the above two items, PLL 1 R Divider/2 and PLL 1 N Divider /2, on LD pin should be the same frequency. 5) Program PLL_MUX = "PLL1 DLD Active High" 6) Confirm the LD pin output is high. i. If high, then PLL1 is locked, continue to PLL2 operation/locking. (continued on next page) 44 SNLU099 L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S 7) If LD pin output is low, but the frequencies are the same, it is possible that excessive leakage on Vtune pin is causing the digital lock detect to not activate. By default PLL2 waits for the digital lock detect to go high before allowing PLL2 and the integrated VCO to lock. Different VCXO models have different input leakage specifications. High leakage, low PLL1 phase detector frequencies, and low PLL1 charge pump current settings can cause the PLL1 charge pump to operate longer than the digital lock detect timeout which allows the device to lock, but prevents the digital lock detect from activating. i. Redesign PLL1 loop filter with higher phase detector frequency ii. Redesign PLL1 loop filter with higher charge pump current iii. Isolate VCXO tuning input from PLL1 charge pump with an op amp. iv. Program RC_DLD1_Start = 0, this will allow PLL2 to starting lock even if the digital lock detect on PLL1 is not high. 3) Confirm PLL2 operation/locking 1) Program PLL_MUX = "PLL 2 R Divider /2" 2) Confirm that LD pin output is half the expected phase detector frequency of PLL2. i. If not, examine PLL2 register R programming. ii. If not, examine physical OSCin input. 3) Program PLL_MUX = "PLL 2 N Divider /2" 4) Confirm that LD pin output is half the expected phase detector frequency of PLL2. i. If not, confirm OSCin_FREQ is programmed to OSCin frequency. ii. If not, examine PLL2 register N programming. Naturally, the output frequency of the above two items should be the same frequency. 5) Program PLL_MUX = "PLL2 DLD Active High" 6) Confirm the LD pin output is high. 7) Program PLL_MUX = "PLL1/2 DLD Active High" 8) Confirm the LD pin output is high. 45 SNLU099 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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