CY62148ESL MoBL(R) 4-Mbit (512K x 8) Static RAM Features Functional Description Very high speed: 55 ns Wide voltage range: 2.2V to 3.6V and 4.5V to 5.5V Ultra low standby power Typical standby current: 1 A Maximum standby current: 7 A Ultra low active power Typical active current: 2 mA at f = 1 MHz Easy memory expansion with CE and OE features Automatic power down when deselected The CY62148ESL is a high performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). CMOS for optimum speed and power Available in Pb-free 32-pin STSOP package To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram IO0 INPUT BUFFER IO1 512K x 8 ARRAY IO3 IO4 IO5 IO6 CE * IO7 POWER DOWN A18 A17 A15 A13 A14 OE A16 COLUMN DECODER WE Cypress Semiconductor Corporation Document #: 001-50045 Rev. ** IO2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised January 21, 2009 [+] Feedback CY62148ESL MoBL(R) Pin Configuration Figure 1. 32-Pin STSOP (Top View) A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 STSOP Top View (not to scale) OE A10 CE1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3 Product Portfolio Power Dissipation Product Range VCC Range (V) [1] Speed (ns) Operating ICC, (mA) f = 1 MHz Typ CY62148ESL Industrial 2.2V to 3.6V and 4.5V to 5.5V 55 2 [2] f = fmax Standby, ISB2 (A) Max Typ [2] Max Typ [2] Max 2.5 15 20 1 7 Notes 1. Data sheet specifications are not guaranteed for VCC in the range of 3.6V to 4.5V. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. Document #: 001-50045 Rev. ** Page 2 of 10 [+] Feedback CY62148ESL MoBL(R) Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied .............................................. 55C to +125C Supply Voltage to Ground Potential ...........................................................-0.5V to 6.0V Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch Up Current .................................................... > 200 mA Operating Range Device Range CY62148ESL Industrial DC Voltage Applied to Outputs in High-Z State [3, 4] ..........................................-0.5V to 6.0V Ambient Temperature VCC[5] -40C to +85C 2.2V to 3.6V, and 4.5V to 5.5V DC Input Voltage [3, 4] .......................................-0.5V to 6.0V Electrical Characteristics Over the Operating Range 55 ns Parameter VOH VOL VIH VIL Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage [6] Input LOW Voltage Test Conditions Min Typ [2] Max 2.2 < VCC < 2.7 IOH = -0.1 mA 2.0 2.7 < VCC < 3.6 IOH = -1.0 mA 2.4 4.5 < VCC < 5.5 IOH = -1.0 mA 2.4 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 2.7 < VCC < 3.6 IOL = 2.1 mA 0.4 4.5 < VCC < 5.5 IOL = 2.1 mA 0.4 Unit V V 2.2 < VCC < 2.7 1.8 VCC + 0.3 2.7 < VCC < 3.6 2.2 VCC + 0.3 4.5 < VCC < 5.5 2.2 VCC + 0.5 2.2 < VCC < 2.7 -0.3 0.4 2.7 < VCC < 3.6 -0.3 0.6 4.5 < VCC < 5.5 -0.5 0.6 GND < VI < VCC -1 +1 A -1 +1 A mA IIX Input Leakage Current IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current f = fmax = 1/tRC V V VCC = VCCmax IOUT = 0 mA, CMOS levels 15 20 2 2.5 ISB1 Automatic CE Power CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Down Current -- CMOS f = fmax (Address and Data Only), f = 0 (OE and WE), Inputs VCC = VCC(max) 1 7 A ISB2 Automatic CE Power CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Down Current -- CMOS f = 0, VCC = VCC(max) Inputs 1 7 A f = 1 MHz Notes 3. VIL(min) = -2.0V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 5. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 6. Under DC conditions the device meets a VIL of 0.8V (for VCC range of 2.7V to 3.6V and 4.5V to 5.5V) and 0.6V (for VCC range of 2.2V to 2.7V). However, in dynamic conditions Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. Refer to AN13470 for details. Document #: 001-50045 Rev. ** Page 3 of 10 [+] Feedback CY62148ESL MoBL(R) Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max TA = 25C, f = 1 MHz, VCC = VCC(typ) Unit 10 pF 10 pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two layer printed circuit board STSOP Unit 49.02 C/W 14.07 C/W Figure 2. AC Test Loads and Waveforms R1 ALL INPUT PULSES VCC OUTPUT VCC 30 pF INCLUDING JIG AND SCOPE R2 90% 10% 90% 10% GND Rise Time = 1 V/ns Equivalent to: Fall Time = 1 V/ns THEVENIN EQUIVALENT RTH OUTPUT V Parameters 2.50V 3.0V 5.0V Unit R1 16667 1103 1800 R2 15385 1554 990 RTH 8000 645 639 VTH 1.20 1.75 1.77 V Document #: 001-50045 Rev. ** Page 4 of 10 [+] Feedback CY62148ESL MoBL(R) Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR [7] Chip Deselect to Data Retention Time tR [8] Operation Recovery Time Conditions Min Typ [2] Max 1.5 CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V VCC = 1.5V Unit V 1 7 A 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC VCC(min) VDR > 1.5V tCDR VCC(min) tR CE Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. Document #: 001-50045 Rev. ** Page 5 of 10 [+] Feedback CY62148ESL MoBL(R) Switching Characteristics Over the Operating Range [9] Parameter Description 55 ns Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 55 ns tDOE OE LOW to Data Valid 25 ns tLZOE 55 OE LOW to Low Z tHZOE [10] OE HIGH to High Z tLZCE CE LOW to Low Z CE HIGH to High Z tPU CE LOW to Power Up Write Cycle 10 ns 20 10 ns ns 20 0 CE HIGH to Power Up ns ns 5 [10, 11] tHZCE tPD 55 [10, 11] [10] ns ns ns 55 ns [12] tWC Write Cycle Time 55 ns tSCE CE LOW to Write End 40 ns tAW Address Setup to Write End 40 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 40 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE tLZWE WE LOW to High Z [10, 11] WE HIGH to Low Z [10] 20 10 ns ns Notes 9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 4. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 001-50045 Rev. ** Page 6 of 10 [+] Feedback CY62148ESL MoBL(R) Switching Waveforms Figure 3. Read Cycle No. 1 (Address Transition Controlled) [13, 14] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA VALID DATA OUT tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE ICC 50% 50% ISB Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [16, 17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA IO NOTE 18 tHD DATA VALID tHZOE Notes 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycles. 15. Address valid before or similar to CE transition LOW. 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 18. During this period, the IOs are in output state. Do not apply input signals. Document #: 001-50045 Rev. ** Page 7 of 10 [+] Feedback CY62148ESL MoBL(R) Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (CE Controlled) [16, 17] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA IO tHD DATA VALID Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tHD tSD NOTE 18 DATA IO DATA VALID tLZWE tHZWE Truth Table CE WE OE Inputs/Outputs H X X High Z Deselect/Power Down Standby (ISB) L H L Data Out Read Active (ICC) L H H High Z Output Disabled Active (ICC) L L X Data in Write Active (ICC) Document #: 001-50045 Rev. ** Mode Power Page 8 of 10 [+] Feedback CY62148ESL MoBL(R) Ordering Information Speed (ns) 55 Ordering Code CY62148ESL-55ZAXI Package Diagram Package Type 51-85094 32-Pin STSOP (Pb-Free) Operating Range Industrial Package Diagram Figure 8. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094 51-85094-*D Document #: 001-50045 Rev. ** Page 9 of 10 [+] Feedback CY62148ESL MoBL(R) Document History Page Document Title: CY62148ESL MoBL(R) 4-Mbit (512K x 8) Static RAM Document Number: 001-50045 Rev. ECN No. Orig. of Change Submission Date ** 2612938 VKN/PYRS 01/21/09 Description of Change New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors image.cypress.com psoc.cypress.com/precision-analog (c) Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Document #: 001-50045 Rev. ** Revised January 21, 2009 Page 10 of 10 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback