CY62158EV30 MoBL
8-Mbit (1024K x 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05578 Rev. *F Revised December 14, 2010
8-Mbit (1024K x 8) Static RAM
Features
■Very high speed: 45 ns
❐Wide voltage range: 2.20V–3.60V
■Pin compatible with CY62158DV30
■Ultra low standby power
❐Typical standby current: 2 A
❐Maximum standby current: 8 A
■Ultra low active power
❐Typical active current: 1.8 mA at f = 1 MHz
■Easy memory expansion with CE1, CE2, and OE features
■Automatic power down when deselected
■CMOS for optimum speed/power
■Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and 48-pin
TSOP I packages[1]
Functional Description [2]
The CY62158EV30 is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption significantly when deselected (CE1 HIGH or
CE2 LOW). The eight input and output pins (I/O0 through I/O7)
are placed in a high impedance state when the device is
deselected (CE1 HIGH or CE2 LOW), the outputs are disabled
(OE HIGH), or a write operation is in progress (CE1 LOW and
CE2 HIGH and WE LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and OE LOW while forcing the WE HIGH. Under these
conditions, the contents of the memory location specified by the
address pins appear on the I/O pins. See the “Truth Table” on
page 9 for a complete description of read and write modes.
A0IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
WE
OE
A13
A14
A15
A16
ROW DECODER
COLUMN DECODER
1024K x 8
ARRAY
DATA IN DRIVERS
A10
A11
A17
CE1
CE2
A12
A18
A19
Logic Block Diagram
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Notes
1. For 48 pin TSOP I pin configuration and ordering information, please refer to CY62157EV30 Data sheet.
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
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Document #: 38-05578 Rev. *F Page 2 of 14
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ....................................................................... 4
Thermal Resistance...........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ........................................ 5
Data Retention Waveform ................................................5
Switching Characteristics.................................................6
Switching Waveforms ......................................................7
Truth Table ........................................................................ 9
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products ....................................................................14
PSoC Solutions ......................................................... 14
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Document #: 38-05578 Rev. *F Page 3 of 14
Pin Configurations [3]
Product Portfolio
Product
VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA)
Standby, ISB2 (µA)
f = 1 MHz f = fmax
Min Typ[4] Max Typ[4] Max Typ[4] Max Typ[4] Max
CY62158EV30LL 2.2 3.0 3.6 45 1.8 3 18 25 2 8
Top View
WE
V
CC
A11
A10
A6
A0
A3CE1
I/O
0
A4
A5
I/O1
I/O
2
I/O
3
A9
A8
OE
V
SS A7
CE2
A17
A2
A1
V
CC
I/O
4
I/O
5
I/O
6
I/O
7
A15
A14
A13
A
12
NC
A18 A19
3
26
5
4
1
D
E
B
A
C
F
G
H
A16 V
SS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
48-Ball VFBGA
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
VCC
A19
A18
A17
A16
A4
A3
OE
VSS
A5
NC
A2
CE1
I/O0
NC
NC
CE2
A1
A0
18
17
20
19
I/O1
27
28
25
26
22
21
23
24
VSS
NC
I/O2
I/O3
NC
A6
A7
A8
VCC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
A10
A11
A12
A13
A15 A14
A9
Top View
44-Pin TSOPII
Notes
3. NC pins are not connected on the die.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
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Document #: 38-05578 Rev. *F Page 4 of 14
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential –0.3V to VCC(max) + 0.3V
DC Voltage Applied to Outputs
in High-Z State[5, 6] .........................–0.3V to VCC(max) + 0.3V
DC Input Voltage[5, 6] ......................–0.3V to VCC(max) + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(MIL-STD-883, Method 3015)
Latch up Current...................................................... >200 mA
Operating Range
Product Range
Ambient
Temperature
(TA)
VCC[7]
CY62158EV30LL Industrial –40°C to +85°C 2.2V – 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions 45 ns Unit
Min Typ[8] Max
VOH Output HIGH Voltage IOH = –0.1 mA 2.0 V
IOH = –1.0 mA, VCC > 2.70V 2.4 V
VOL Output LOW Voltage IOL = 0.1 mA 0.4 V
IOL = 2.1 mA, VCC > 2.70V 0.4 V
VIH Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC + 0.3V V
VCC = 2.7V to 3.6V 2.2 VCC + 0.3V V
VIIL Input LOW Voltage VCC = 2.2V to 2.7V –0.3 0.6 V
VCC = 2.7V to 3.6V –0.3 0.8 V
IIX Input Leakage Current GND < VI < VCC –1 +1 A
IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 A
ICC VCC Operating Supply Current f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
18 25 mA
f = 1 MHz 1.8 3 mA
ISB1 Automatic CE
Power down Current —
CMOS Inputs
CE1 > VCC – 0.2V, CE2 < 0.2V
VIN > VCC – 0.2V, VIN < 0.2V)
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60V
28A
ISB2[9] Automatic CE
Power down Current —
CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
28A
Capacitance[10]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output Capacitance 10 pF
Notes
5. VIL(min) = –2.0V for pulse durations less than 20 ns.
6. VIH(max)= VCC + 0.75V for pulse duration less than 20 ns.
7. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
9. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
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Document #: 38-05578 Rev. *F Page 5 of 14
Thermal Resistance[12]
Parameter Description Test Conditions BGA TSOP II Unit
JA Thermal Resistance
(Junction to Ambient) Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board 72 76.88 C/W
JC Thermal Resistance
(Junction to Case) 8.86 13.52 C/W
AC Test Loads and Waveforms
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT VTH
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Fall time: 1 V/ns
Rise Time: 1 V/ns
Parameters 2.5V 3.0V Unit
R1 16667 1103
R2 15385 1554
RTH 8000 645
VTH 1.20 1.75 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ[4] Max Unit
VDR VCC for Data Retention 1.5 V
ICCDR[11] Data Retention Current VCC = 1.5V, CE1 > VCC 0.2V
or CE2 < 0.2V, VIN > VCC 0.2V
or VIN < 0.2V
25A
tCDR[12] Chip Deselect to Data
Retention Time
0ns
tR[13] Operation Recovery
Time
tRC ns
Data Retention Waveform
VCC, min
VCC, min
tCDR
VDR >1.5V
tR
CE1
VCC
CE2
DATA RETENTI/ON MODE
or
Note
11. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
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Document #: 38-05578 Rev. *F Page 6 of 14
Switching Characteristics (Over the Operating Range) [14]
Parameter Description 45 ns Unit
Min Max
Read Cycle
tRC Read Cycle Time 45 ns
tAA Address to Data Valid 45 ns
tOHA Data Hold from Address Change 10 ns
tACE CE1 LOW and CE2 HIGH to Data Valid 45 ns
tDOE OE LOW to Data Valid 22 ns
tLZOE OE LOW to Low Z[15] 5ns
tHZOE OE HIGH to High Z[15, 16] 18 ns
tLZCE CE1 LOW and CE2 HIGH to Low Z[15] 10 ns
tHZCE CE1 HIGH or CE2 LOW to High Z[15, 16] 18 ns
tPU CE1 LOW and CE2 HIGH to Power Up 0 ns
tPD CE1 HIGH or CE2 LOW to Power Down 45 ns
Write Cycle[17]
tWC Write Cycle Time 45 ns
tSCE CE1 LOW and CE2 HIGH to Write End 35 ns
tAW Address Setup to Write End 35 ns
tHA Address Hold from Write End 0 ns
tSA Address Setup to Write Start 0 ns
tPWE WE Pulse Width 35 ns
tSD Data Setup to Write End 25 ns
tHD Data Hold from Write End 0 ns
tHZWE WE LOW to High Z[15, 16] 18 ns
tLZWE WE HIGH to Low Z[15] 10 ns
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 5.
15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
16. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
17. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
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Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[18, 19]
Read Cycle No. 2 (OE Controlled)[19, 20]
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
ICC
ISB
IMPEDANCE
OE
CE1
ADDRESS
CE2
DATA OUT
SUPPLY
CURRENT
VCC
Notes
18. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
19. WE is HIGH for read cycle.
20. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
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Write Cycle No. 1 (WE Controlled)[21, 22, 23]
Write Cycle No. 2 (CE1 or CE2 Controlled)[21, 22, 23]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
t
HZOE
VALID DATA
NOTE 24
CE1
ADDRESS
CE2
WE
DATA I/O
OE
tWC
VALID DATA
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
CE1
ADDRESS
CE2
WE
DATA I/O
OE
Notes
21. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
22. Data I/O is high impedance if OE = VIH.
23. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
24. During this period, the I/Os are in output state. Do not apply input signals.
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Write Cycle No. 3 (WE Controlled, OE LOW)[25]
Truth Table
CE1CE2WE OE Inputs/Outputs Mode Power
HX
[27] X X High-Z Deselect/Power down Standby (ISB)
X[27] L X X High-Z Deselect/Power down Standby (ISB)
L H H L Data Out Read Active (ICC)
L H L X Data In Write Active (ICC)
L H H H High-Z Selected, Outputs Disabled Active (ICC)
Switching Waveforms (continued)
VALID DATA
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
NOTE 26
CE1
ADDRESS
CE2
WE
DATA I/O
Notes
25. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
26. During this period, the I/Os are in output state. Do not apply input signals.
27. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
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Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62158EV30LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Industrial
CY62158EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
Temperature Grade: I = Industrial
Package Type: BVX / ZSX = VFBGA (Pb-free)
xx = Speed Grade = 45 ns / 55 ns
LL = Low Power
Voltage Range = 3 V typical
E = Process Technology 90 nm
Buswidth = × 8
Density = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
CY -xx xxx
621 58EV30 LL I/A
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Document #: 38-05578 Rev. *F Page 12 of 14
Figure 2. 44-Pin TSOP II, 51-85087
Package Diagrams (continued)
MAX
MIN.
DIMENSION IN MM (INCH)
(OPTIONAL)
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
EJECTOR MARK
Z
A
Z
Z
Z
Z
X
A
10.058 (0.396)
10.262 (0.404)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
TOP VIEW BOTTOM VIEW
PLANE
SEATING
18.517 (0.729)
0.800 BSC
0°-5°
0.400(0.016)
0.300 (0.012)
1.194 (0.047)
0.991 (0.039)
0.150 (0.0059)
0.050 (0.0020)
(0.0315)
18.313 (0.721)
BASE PLANE
0.10 (.004)
11.938 (0.470)
PIN 1 I.D.
44
1
11.735 (0.462)
10.058 (0.396)
10.262 (0.404)
22
23
51-85087-*C
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Document #: 38-05578 Rev. *F Page 13 of 14
Document History Page
Document Title: CY62158EV30 MoBL, 8-Mbit (1024K x 8) Static RAM
Document Number: 38-05578
Rev. ECN No. Issue Date Orig. of
Change Description of Change
** 270329 See ECN PCI New Data Sheet
*A 291271 See ECN SYT Converted from Advance Information to Preliminary
Changed ICCDR from 4 to 4.5 A
*B 444306 See ECN NXR Converted from Preliminary to Final.
Removed 35 ns speed bin
Removed “L” bin.
Removed 44 pin TSOP II package
Included 48 pin TSOP I package
Changed the ICC Typ value from 16 mA to 18 mA and ICC max value from 28
mA to 25 mA for test condition f = fax = 1/tRC.
Changed the ICC max value from 2.3 mA to 3 mA for test condition f = 1MHz.
Changed the ISB1 and ISB2 max value from 4.5 A to 8 A and Typ value from
0.9 A to 2 A respectively.
Updated Thermal Resistance table
Changed Test Load Capacitance from 50 pF to 30 pF.
Added Typ value for ICCDR .
Changed the ICCDR max value from 4.5 A to 5 A
Corrected tR in Data Retention Characteristics from 100 s to tRC ns
Changed tLZOE from 3 to 5
Changed tLZCE from 6 to 10
Changed tHZCE from 22 to 18
Changed tPWE from 30 to 35
Changed tSD from 22 to 25
Changed tLZWE from 6 to 10
Updated the ordering Information and replaced the Package Name column with
Package Diagram.
*C 467052 See ECN NXR Included 44 pin TSOP II package in Product Offering.
Removed TSOP I package; Added reference to CY62157EV30 TSOP I
Updated the ordering Information table
*D 1015643 See ECN VKN Added footnote #8 related to ISB2 and ICCDR
*E 2934396 06/03/10 VKN Added footnote #21 related to chip enable
Updated package diagrams
Updated template
*F 3110202 12/14/2010 PRAS Updated Logic Block Diagram and Package Diagram.
Added Ordering Code Definitions.
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All products and company names mentioned in this document may be the trademarks of their respective holders.
CY62158EV30 MoBL
© Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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