General Purpose Transistors
PNP Silicon
MAXIMUM RATINGS
Rating Symbol Value Unit
Collector–Emitter Voltage VCEO –45 V
Collector–Base Voltage VCBO –50 V
Emitter–Base V oltage VEBO –5.0 V
Collector Current — Continuous IC–500 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR–5 Board, (1)
TA = 25°C
Derate above 25°C
PD225
1.8 mW
mW/°C
Thermal Resistance, Junction to Ambient RJA 556 °C/W
Total Device Dissipation
Alumina Substrate, (2) TA = 25°C
Derate above 25°C
PD300
2.4 mW
mW/°C
Thermal Resistance, Junction to Ambient RJA 417 °C/W
Junction and Storage Temperature TJ, Tstg –55 to +150 °C
DEVICE MARKING
BC807–16LT1 = 5A; BC807–25LT1 = 5B; BC807–40LT1 = 5C
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage
(IC = –10 mA) V(BR)CEO –45 V
Collector–Emitter Breakdown Voltage
(VEB = 0, IC = –10 µA) V(BR)CES –50 V
Emitter–Base Breakdown Voltage
(IE = –1.0 A) V(BR)EBO –5.0 V
Collector Cutoff Current
(VCB = –20 V)
(VCB = –20 V, TJ = 150°C)
ICBO
–100
–5.0 nA
µA
1. FR–5 = 1.0 x 0.75 x 0.062 in.
2. Alumina = 0.4 x 0.3 x 0.024 in. 99.5% alumina.
ON Semiconductor
Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 3 1Publication Order Number:
BC807–16LT1/D
BC807-16LT1
BC807-25LT1
BC807-40LT1
12
3
CASE 318–08, STYLE 6
SOT–23 (TO–236AB)
COLLECTOR
3
1
BASE
2
EMITTER
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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Characteristic Symbol Min Typ Max Unit
ON CHARACTERISTICS
DC Current Gain
(IC = –100 mA, VCE = –1.0 V) BC807–16
BC807–25
BC807–40
(IC = –500 mA, VCE = –1.0 V)
hFE 100
160
250
40
250
400
600
Collector–Emitter Saturation Voltage
(IC = –500 mA, IB = –50 mA) VCE(sat) –0.7 V
Base–Emitter On Voltage
(IC = –500 mA, IB = –1.0 V) VBE(on) –1.2 V
SMALL–SIGNAL CHARACTERISTICS
Current–Gain — Bandwidth Product
(IC = –10 mA, VCE = –5.0 Vdc, f = 100 MHz) fT100 MHz
Output Capacitance
(VCB = –10 V, f = 1.0 MHz) Cobo 10 pF
IC, COLLECTOR CURRENT (mA)
Figure 1. DC Current Gain
hFE, DC CURRENT GAIN
1000
10
-1000-0.1 -10 -100
100
-1.0
VCE = -1.0 V
TA = 25°C
BC807–16LT1 BC807–25LT1 BC807–40LT1
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IB, BASE CURRENT (mA)
Figure 2. Saturation Region
IC, COLLECTOR CURRENT (mA)
Figure 3. “On” Voltages
100
10
1.0
VR, REVERSE VOLTAGE (VOLTS)
Figure 4. Temperature Coefficients
+1.0
IC, COLLECTOR CURRENT
Figure 5. Capacitances
-0.1 -1.0-1.0 -10 -100 -1000
-2.0
-1.0
0
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS
)
V, VOLTAGE (VOLTS)
V, TEMPERATURE COEFFICIENTS (mV/ C)°θ
C, CAPACITANCE (pF)
-1.0
-0.8
-0.6
-0.4
-0.2
0
-0.01 -0.1 -10 -100-1.0
-1.0
-0.8
-0.6
-0.4
-0.2
0
-1.0 -10 -1000-100
-10 -100
TJ = 25°C
IC = -10 mA
IC = -100 mA
IC = -300 mA
IC =
-500 mA
TA = 25°C
VBE(sat) @ IC/IB = 10
VBE(on) @ VCE = -1.0 V
VCE(sat) @ IC/IB = 10
θVC for VCE(sat)
θVB for VBE
Cob
Cib
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4
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT–23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT–23 POWER DISSIPATION
PD = TJ(max) – TA
RθJA
PD = 150°C – 25°C
556°C/W = 225 milliwatts
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipa-
tion. Power dissipation for a surface mount device is deter-
mined b y T J(max), the maximum rated junction temperature
of the die, RθJA, the thermal resistance from the device
junction to ambient, and the operating temperature, TA.
Using the values provided on the data sheet for the SOT–23
package, PD can be calculated as follows:
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 225 milli-
watts. There are other alternatives to achieving higher
power dissipation from the SOT–23 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the
rated temperature of the device. When the entire device is
heated to a high temperature, failure to complete soldering
within a short time could result in device failure. There-
fore, the following items should always be observed in
order to minimize the thermal stress to which the devices
are subjected.
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause exces-
sive thermal shock and stress which can result in damage
to the device.
BC807–16LT1 BC807–25LT1 BC807–40LT1
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5
PACKAGE DIMENSIONS
CASE 318–08
ISSUE AF
SOT–23 (TO–236)
DJ
K
L
A
C
BS
H
GV
3
12
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0140 0.0285 0.35 0.69
L0.0350 0.0401 0.89 1.02
S0.0830 0.1039 2.10 2.64
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
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Notes
BC807–16LT1 BC807–25LT1 BC807–40LT1
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7
Notes
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Phone: 81–3–5740–2700
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