(R) Signal Processing IP Megafunctions Signal Processing Solutions for System-on-a Programmable-Chip Designs May 2001 Signal Processing IP: Proven Performance in One Portfolio performance, high-throughput signal coding schemes, W processing algorithms. ireless and digital signal processing (DSP) modulation functions, and traditional signal engineers face a difficult challenge: to You can choose blocks of IP from the comprehensive design communications infrastructure signal processing portfolio of standard functions to create systems with increasing performance requirements, and an entire SOPC. Alternatively, you can use individual rapid technology changes. Altera(R) signal processing signal processing IP functions in systems that need intellectual property (IP) megafunctions are a complete focused performance enhancements. All signal processing portfolio of proven, high-performance standard functions IP is reusable; you can instantiate each function multiple created to help engineers meet these design challenges times in different designs. and implement a solution using a single Altera programmable logic device (PLD). Each function in the Hardware Acceleration for Existing Designs portfolio--including MegaCore(R) and Altera Megafunction Signal processing IP can be integrated easily into the Partners Program (AMPP ) functions--has been rigorously datapath as a pre- and post-processor to implement tested and meets the exacting requirements of IEEE and computationally rigorous routines, leaving the DSP world wide communications standards. Today, millions of processor at the center of the original design. Adding a business users and consumers are powered by Altera's high-performance PLD to attack bottlenecks at both ends signal processing IP. of existing processes allows DSP software engineers to SM leverage existing software code while enjoying the PLD You can download signal processing IP functions benefits of hardware acceleration (see Figure 2). from the IP MegaStoreTM web site at http://www.altera.com/IPmegastore. The functions have Figure 2. Hardware Acceleration for DSP Processor Systems a user-friendly, wizard-driven graphical user interface (GUI) that provides an intuitive, flexible environment to Signal Processing IP Solution Signal Processing IP Solution customize the IP to meet any system's requirements (see Figure 1). Convolutional Encoder Figure 1. Intuitive GUI for IP Customization ReedSolomon Encoder Hardware Acceleration Processor & Memory Existing Software FIR Filter Hardware Acceleration Signal Coding Altera provides a variety of signal coding functions for encryption, forward error correction (FEC), and cyclic redundancy code (CRC) checking (see Figure 3). Encryption Altera's data encryption standard (DES) cores are certified by the National Institute of Standards and Technology A Complete High-Performance Solution for the DSP Market (NIST) and can be used in applications requiring Altera provides an extensive portfolio of drop-in DSP DES in any operating mode or to add proprietary pre- and wireless IP functions. The signal processing processing to the encryption stream. In addition to the portfolio includes everything you need to build system- DES core, Altera has Rijndael, SHA-1, and MD5 cores. electronic code book (ECB) or triple-DES encryption. Using a PLD for encryption makes it easy to implement on-a-programmable-chip (SOPC) solutions using high- 2 Altera Corporation Figure 3. Typical Transmitter Using Signal Processing IP Forward Error Correction Encryption Basic Math Functions Cyclic Redundancy Code Check Transforms Signal Coding Filters Mappers Comparator & Shift Registers Numerically Controlled Oscillator QPSK & QAM Hardware DSP Blocks Modulation Antenna FEC implemented in an Altera PLD for less than $20 per When starting a new design, communications systems device. As with all signal processing functions, engineers must weigh the trade-off between data performance is not compromised; the maximum data reliability and throughput. Using modern FEC techniques, throughput is increased from a typical DSP processor rate receivers can correct the data that was corrupted during of 1 Mbps to over 100 Mbps. signal transmission, thereby increasing the effective data Turbo: Specified by the third-generation partnership bandwidth, as shown in Figure 4. project (3GPP) for third-generation wireless infrastructure, turbo convolutional codes are complex and Figure 4. Signal Coding Block Diagram difficult to easily implement on any DSP processors. However, Altera's signal processing solution allows designers to easily implement Data In Outer Encoding Encryption/ CRC/FEC Inner Encoding FEC Noisy Channel Inner Decoding FEC Outer Decoding Decryption/ CRC/FEC Data Out turbo convolutional codes. Supporting data rates in excess of 2 Mbps, the turbo decoder features a max-logMAP algorithm for maximum error correction and includes a 3GPP-compliant interleaver. Altera is the first PLD vendor to offer Reed-Solomon: Reed-Solomon is an advanced error 3GPP-compliant turbo encoders and decoders as off-the- correction technique that is widely used in data shelf mainstream products. communication, storage, and mobile computing. The efficient Reed-Solomon algorithm uses polynomials to add redundancy to the transmitted data. Implementing ReedSolomon functionality using DSP processors is expensive and unsuitable for high-performance applications. The signal processing IP portfolio provides a wide range of Reed-Solomon encoders and decoders, including discrete, streaming, continuous, and erasures-support. Implemented CRC & Other Coding Techniques Altera provides general-purpose functions such as cyclic redundancy code (CRC) checkers and specialized application-specific coding techniques such as color space converters. Hardware DSP Blocks in an Altera PLD, the parameterized Reed-Solomon Signal processing hardware DSP blocks include filter solution can provide 10-Mbps throughput at a cost of less transform functions and basic building blocks, as shown than $2, or high-performance Reed-Solomon decoding at in Figure 5. up to 900 Mbps for less than $80 (using an EP20K100E device operating at 92 MHz). Filters Digital filters such as finite impulse response (FIR) and Viterbi: High-performance, area-optimized 100-Mbps Viterbi decoding (or convolutional decoding) with flexible constraint lengths, soft bits, and traceback length can be Altera Corporation infinite impulse response (IIR) filters offer more than 10 times the performance of DSP processors when implemented in PLDs. Altera's FIR compiler and IIR 3 Figure 5. QAM Reference Design Using Altera FIR & NCO IP same PLD provide faster design cycles and higher performance, as well as power and board space savings. xin I-Input yout Altera FIR Raised Cosine Filter X Integrated Design Environment Cosine_mult Altera provides an integrated design environment to cosine ++ phi_inc Carrier Phase Increment sine QAM Signal NCO xin Q-Input streamline your design flow. Set Parameters with MegaWizard Plug-Ins Altera MegaWizard Plug-Ins provide a GUI yout X SIne_mult Altera FIR Raised Cosine Filter1 compiler signal processing functions reduce the design time from weeks to hours. Fast Fourier Transform Functions Traditionally performed by DSP processors, complex functions can be performed in PLDs using parallel instantiations to take advantage of hardware acceleration. for customizing IP and integrating it into your design flow using any EDA tool. The plug-ins graphically demonstrate the functionality of the IP and allow easy customization of new designs or easy modification of existing designs, as shown in figure 6. With MegaWizard Plug-Ins, you can efficiently customize functions in your own design environment, saving time and money. Figure 6. IIR Compiler MegaWizard Plug-Ins The Altera signal processing portfolio contains several parameterizable functions to integrate your design on one PLD. Basic Building Blocks Basic building blocks such as adders, multipliers, counters, comparators, and dividers are available through the standard library of parameterized modules (LPM). Parameterizable LPM functions can be instantiated easily using the MegaWizard(R) Plug-In manager. Modulation & Demodulation Designing modulators and demodulators such as quadrature amplitude modulation (QAM), m-ary phase Both Altera and AMPP partners offer parameterized shift keying (MPSK), and differential phase shift keying functions with MegaWizard Plug-Ins. For a demonstration (DPSK) are easy using Altera's FIR compiler, constellation of various MegaWizard Plug-Ins, visit the signal mapper/demapper, and numerically-controlled oscillator processing page on the IP MegaStore web site. (NCO) functions. Altera provides reference designs for direct digital synthesis (DDS) and QAM, that can be easily Third-Party System-Level DSP Tools modify to meet customized specifications. Using Signal processing IP integrates easily into any EDA or programmable logic to implement your modulation third-party system-level DSP design tool flow. The scheme lets you test your design in hardware the day Mega Wizard Plug-Ins output graphical symbols or Altera you build the design. Hardware Description Language (AHDL), VHDL, or Verilog Using the power of digital logic, signals can be cleanly modulated to an intermediate frequency (IF), digitally filtered, and readied for transmission. Single-chip integration of the modulator and the ability to integrate HDL files for easy integration into custom designs. They also generate high-level simulation output files for the MATLAB and Simulink software as well as and VHDL or Verilog HDL simulation models. signal coding techniques and customized logic onto the 4 Altera Corporation Figure 7. MATLAB/Simulink Interface You can download all IP functions from the IP MegaStore site for evaluation. Simply search for the desired IP and follow the download instructions. Development Boards Board-level verification is essential to successful IP design. To support the development and verification of SOPC designs, Altera and its partners provide a variety of development and prototyping boards that speed system design by allowing application software development to begin concurrently with hardware development. Additionally, hardware designers can verify IP functionality quickly and effectively. A complete listing of development boards can be found on the IP MegaStore web site. Signal Processing IP Applications Signal processing IP functions are ideal for highEasy Verification As with all advanced designs, the verification process is essential. To verify the functionality of any IP, the Altera Quartus(R) II and MAX+PLUS(R) II software tools generate post place-and-route VHDL or Verilog HDL netlist files that can be imported into any simulation tool. performance, high-throughput applications. These applications, which would normally require several DSP processors, can be placed into a single highly flexible, high-performance PLD. Wired Signal processing IP are ideal for communications Altera also provides functional simulation models, applications requiring high throughput such as DSL allowing you to test the IP prior to synthesis. You can access multiplexers (DSLAMs), or those requiring flexible download the functional simulation models from the modulation schemes such as cable broadcasting. Media IP MegaStore site. storage applications, such as mass storage (magnetic or To facilitate the verification process, system simulation optical), digital video disc, and digital tape applications models for MATLAB and Simulink are provided with require robust FEC algorithms. many of the cores. These models, which reflect the parameters you set, can be run in these popular DSP design tools with a few simple keystrokes (see Figure 7). Wireless & Broadband The signal processing communications solution is ideal for the rigorous high-throughput requirements of wireless and Test-Drive Functions Risk-Free Altera offers a no-risk MegaCore function evaluation through the OpenCore(R) OpenCore TM feature. The OpenCore feature lets you compile and simulate IP using the Quartus II or MAX+PLUS II software. You can verify the functionality of the IP quickly and easily, as well as broadband applications. The performance advantages of parallel processing coupled with the traditional flexibility of programmable logic make signal processing IP ideal for emerging areas such as third-generation wireless, digital audio and video broadcasting, multi-channel multipoint distribution services (MMDS), and orthogonal frequency division multiplexing (OFDM) systems. evaluate the size and speed of the IP before making a Using IP, designers can quickly adapt to changing purchase decision. After licensing the IP, you can output standards such as the Wireless 802.11a, Wireless Broadband EDIF, VHDL, and Verilog HDL netlist files, and create Working Group 802.16, and HiperLAN/2. The building programming or configuration files for Altera PLDs. blocks for these applications require FEC, modulation, Altera Corporation 5 filtering, and encryption--all areas addressed by Altera's all the major blocks required to implement an OFDM signal processing portfolio. system, as shown in Figure 8. 10-Gbps Solution for ITU-T G.709 Proven Solutions ITU-T G.709 defines the network node interface for the Examples of complete systems using IP from the signal optical transport network operating at 2.5, 10, and processing portfolio include: 40 Gbps, and specifies the use of a Reed-Solomon Third-generation wireless CDMA basestations FEC section. Digital video basestations Altera has a 10-Gbps single-chip solution available today. Wireless broadband modems The Altera continuous Reed-Solomon decoder runs at over Global system for mobile communication (GSM)-Edge 96 MHz, yielding 760-Mbps throughput. Altera's signal basestations processing Reed-Solomon decoder is able to achieve DSP prototyping platforms 2.5 Gbps by using Reed-Solomon decoder cores in MMDS basestations parallel--each decoder is positioned to process every Professional DVD recorders fourth code word. Multimedia satellite ground stations The Reed-Solomon continuous decoder requires 2,460 logic elements (LEs) and 2 embedded system blocks (ESBs). With the addition of buffer memory and minimal control logic, VDSL modems Video processing systems Local multipoint distribution service (LMDS) Altera's Reed-Solomon core enables 2.7-Gbps throughput basestations for 10,500 LEs and 36 ESBs. This solution easily fits into Performance Advantages over DSP Processors an APEXTM EP20K300E device. Further leveraging the advantages of dedicated hardware, Programmable logic offers compelling performance advantages over DSP processors. Programmable logic can Altera's signal processing Reed-Solomon decoder can be thought of as an array of elements, each of which can implement 10-Gbps throughput in only 80% of a single be configured as a complex processor routine. These APEX EP20K1500E. processor routines can then be linked together in serial (the same way a DSP processor would execute them), or OFDM they can be connected in parallel. In parallel, they offer OFDM has recently surged in popularity for wireless systems. Broadcast applications such as terrestrial digital video broadcast, digital audio broadcast (DAB), and many times the performance of a DSP processor by executing hundreds of instructions at once. Algorithms that benefit from this type of performance increase "last-mile" connectivity applications such as MMDS include FEC, modulation/demodulation, and encryption and wireless local area networks have all adopted and (see Figure 9). standardized behind OFDM as the modulation method of choice. Time-to-Market Advantages over ASICs & ASSPs With a high-performance, parameterizable fast Fourier A company with a new product typically makes 50% of transform (FFT), as well as Reed-Solomon and Viterbi its profit in the first six months of production, before functions, Altera's signal processing IP portfolio contains competition enters and drives down prices. ASIC Figure 8. Complete System Solution For a Typical OFDM Transmitter Data In Forward Error Correction Coder Interleaver Constellation Mapper Buffer Inverse Fast Fourier Transform Parallel to Serial Cyclic Prefix Insertion Shaper FIR Filter DAC OFDM Modulator = Altera IP Solution 6 = Altera PLD Solution = Non-PLD Solution Altera Corporation Flexibility Figure 9. Signal Processing IP Advantage Traditional DSP Processor Programmable Logic Device Serial Operation Parallel Operation fx DSP Engine fx System specification changes, bug fixes, or additional customer fx fx fx fx fx fx fx fx fx fx fx fx fx fx fx fx fx fx fx fx requirements can obsolete an expensive ASIC. With programmable logic, systems can be upgraded in the field, eliminating costly recalls and lost sales. fx IP MegaStore Memory Altera's IP MegaStore web site fx fx fx fx fx fx (http://www.altera.com/IPmegastore) features information on IP Sequential (Serial) Operation Parallel Operation technology and system overviews and provides a searchable list of IP N Clocks 1 Clock available from Altera and its AMPP partners. Literature, board-level implementations provide the same performance as demonstrations, simulation models, and IP evaluation functions implemented in programmable logic, but tools are available on the site (see Table 1). development lead times can stretch out up to one year from design start. This programmable logic solution shortens development time, improving time-to-market. Table 1. Signal Processing IP Functions FUNCTION Color Space Converter (PLSM-CSC) SOURCE Altera Corporation PRODUCT FAMILY APEX, APEX II, FLEX(R), ACEXTM, MercuryTM FIR Filter Compiler (PLSM-FIR) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury Numerically Controlled Oscillator Compiler (PLSM-NCO) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury Cyclic Redundancy Code Checker (PLSM-CRC) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury Symbol Interleaver/Deinterleaver (PLSM-INLV) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury Reed-Solomon Compiler, Encoder (PLSM-RSENC) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury Reed-Solomon Compiler, Decoder (PLSM-RSDEC2) Altera Corporation APEX, APEX II, FLEX 10K, ACEX, Mercury Turbo Encoder Function (PLSM-TURBO/ENC) Altera Corporation APEX, APEX II, Mercury Turbo Decoder Function (PLSM-TURBO/DEC) Altera Corporation APEX, APEX II, APEX II, Mercury Viterbi Compiler, High-Speed Parallel Decoder (PLSM-HC-VITERBI/HS) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury Viterbi Compiler, Low-Speed/Hybrid Serial Decoder (PLSM-HC-VITERBI/SS) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury IIR Compiler (PLSM-IIR) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury Constellation Mapper/Demapper (PLSM-SYMMAP) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury 8b10b Encoder & Decoder (PLSM-ED8BIOB) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury FFT/IFFT Processor (PLSM-HC-FFT) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury ARCTAN HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury Hadamard Transform Processor (PLSM-HADAMARD) HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury Reed-Solomon Decoder Minicore (PLSM-RSDEC/MINI) HammerCores by Altera APEX, APEX II, FLEX 10K, ACEX, Mercury High-Speed Rijndael Encryption/Decryption (PLSM-RIJNDAEL/HS) HammerCores by Altera APEX, APEX II, FLEX 10K, ACEX, Mercury Low-Speed Rijndael Encryption/Decryption (PLSM-RIJNDAEL/LS) HammerCores by Altera APEX, APEX II, FLEX 10K, ACEX, Mercury Secure Hash Algorithm (PLSM-SHA1) HammerCores by Altera APEX, APEX II, FLEX 10K, ACEX, Mercury Message Digest Algorithm (PLSM-MD5) HammerCores by Altera APEX, APEX II, FLEX 10K, ACEX, Mercury Adaptive Equalizer (PLSM-HC-EQUALIZER) HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury Altera Corporation 7 Table 1. Signal Processing IP Functions (continued from page 7) FUNCTION SOURCE PRODUCT FAMILY CORDIC HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury U-Law and A-Law Companders HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury Logarithm Function HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury Square Root Function HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury DES Encryption Processor (PLSM-HC-DES) HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury VCO BIST Jitter Measurement Function Fluence Technology APEX, APEX II, FLEX, ACEX, Mercury DES (X_DES) Digital Encryption Function CAST Inc. APEX, APEX II, FLEX, ACEX, Mercury DES Encryption Core Sciworx APEX, APEX II, FLEX, ACEX, Mercury FFT 256-Point Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Convolutional Interleaver Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Adaptive Equalizer Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Sync Detector Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Trellis-Coded Modulator Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Discrete Cosine Transform Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury FFT/IFFT High Performance 64-Point Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury FFT/IFFT Low Latency 64-Point Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Floating-Point Operator Library Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Image Processing Library Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Laplacian Edge Detector Amphion Semiconductor Ltd. APEX, APEX II, FLEX 10KA, Mercury Rank Order Filter Library Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury JPEG Encoder & Decoder Functions Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Adaptive Filters Amphion Semiconductor Ltd. APEX, APEX II, FLEX 10K, Mercury FIR Filter, Cascadable, Adaptive Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Convolutional Encoder Amphion Semiconductor Ltd. APEX, APEX II, FLEX 6000, Mercury DVB FEC Codec Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury FIR Filter Library Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury IIR Filter Library Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Multi-Standard ADPCM Encoder/Decoder Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury QPSK Equalizer Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Reed-Solomon Decoder Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Reed-Solomon Encoder Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Viterbi Decoder Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury Convolutional Interleaver Ktech Telecommunications, Inc. APEX, APEX II, FLEX, MAX(R), Mercury Complex Multiplier/Mixer Nova Engineering, Inc. APEX, APEX II, FLEX, Mercury Linear Feedback Shift Register Nova Engineering, Inc. APEX, APEX II, FLEX, MAX, Mercury Binary Pattern Correlator Nova Engineering, Inc. APEX, APEX II, FLEX, Mercury Digital Modulator Nova Engineering, Inc. APEX, APEX II, FLEX, ACEX, Mercury Digital IF Receiver Nova Engineering, Inc. APEX, APEX II, FLEX, ACEX, Mercury Early-Late-Gate Symbol Synchronizer Nova Engineering, Inc. APEX, APEX II, FLEX, ACEX, Mercury Numerically Controlled Oscillator Nova Engineering, Inc. APEX, APEX II, FLEX, ACEX, Mercury Viterbi Decoder (Dual Constraint Length) Nova Engineering, Inc. APEX, APEX II, FLEX, ACEX, Mercury TC1000 Turbo Decoder TurboConcept APEX, APEX II, FLEX, ACEX, Mercury Turbo Product Code TurboConcept APEX, APEX II, FLEX, ACEX, Mercury Altera Offices Altera Corporation 101 Innovation Drive San Jose, CA 95134 USA Telephone: (408) 544-7000 http://www.altera.com Altera European Headquarters Holmers Farm Way High Wycombe Buckinghamshire HP12 4XF United Kingdom Telephone: (44) 1 494 602 000 Altera Japan Ltd. Shinjuku i-Land Tower 32F 5-1, Nishi-Shinjuku, 6-Chome Shinjuku-ku, Tokyo 163-1332 Japan Telephone: (81) 3 3340 9480 http://www.altera.com/japan Altera International Ltd. 2102 Tower 6 The Gateway, Harbour City 9 Canton Road, Tsimshatsui Kowloon Hong Kong Telephone: (852) 2945 7000 Copyright (c) 2001 Altera Corporation. ACEX, Altera, AMPP, APEX, APEX II, FLEX, FLEX 10K, FLEX 6000, IP MegaStore, MAX, MAX+PLUS, MAX+PLUS II, Mercury, MegaCore, MegaWizard, OpenCore, Quartus, Quartus II, and specific device designations are trademarks and/or service marks of Altera Corporation in the United States and other countries. Other brands or products are trademarks of their respective holders. The specifications contained herein are subject to change without notice. All rights reserved. M-GB-SIGNAL-01