+
RS
ZLOAD
V1
V2
RR
RR
V+
V+
V-
V-
+
-
-
I = (V2 ± V1)
RS
A1
A2
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LMP770x Precision, CMOS Input, RRIO, Wide Supply Range Amplifiers
1 Features 3 Description
The LMP770x are single, dual, and quad low-offset
1• Unless Otherwise Noted, voltage, rail-to-rail input and output precision
Typical Values at VS=5V amplifiers, each with a CMOS input stage and a wide
• Input Offset Voltage (LMP7701): ±200-µV supply voltage range. The LMP770x are part of the
(Maximum) LMP™ precision amplifier family and are ideal for
sensor interface and other instrumentation
• Input Offset Voltage (LMP7702/LMP7704): ±220- applications.
µV (Maximum)
• Input Bias Current: ±200 fA The specified low-offset voltage of less than ±200 µV,
along with the specified low input bias current of less
• Input Bias Current: ±200 fA than ±1 pA, make the LMP7701 ideal for precision
• Input Voltage Noise: 9 nV/√Hz applications. The LMP770x are built using VIP50
• CMRR: 130 dB technology, which allows the combination of a CMOS
input stage and a 12-V common-mode and supply
• Open-Loop Gain: 130 dB voltage range. This makes the LMP770x ideal for
• Temperature Range: −40°C to 125°C applications where conventional CMOS parts cannot
• Unity-Gain Bandwidth: 2.5 MHz operate under the desired voltage conditions.
• Supply Current (LMP7701): 715 µA Device Information(1)
• Supply Current (LMP7702): 1.5 mA PART NUMBER PACKAGE BODY SIZE (NOM)
• Supply Current (LMP7704): 2.9 mA SOT-23 (5) 1.60 mm × 2.90 mm
• Supply Voltage Range: 2.7 V to 12 V LMP7701 SOIC (8) 3.91 mm × 4.90 mm
• Rail-to-Rail Input and Output VSSOP (8) 3.00 mm × 3.00 mm
LMP7702 SOIC (8) 3.91 mm × 4.90 mm
2 Applications TSSOP (14) 4.40 mm × 5.00 mm
• High Impedance Sensor Interface LMP7704 SOIC (14) 3.91 mm × 8.65 mm
• Battery-Powered Instrumentation (1) For all available packages, see the orderable addendum at
• High Gain Amplifiers the end of the data sheet.
• DAC Buffer
• Instrumentation Amplifier
• Active Filters
Typical Application Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMP7701
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,
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SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
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Table of Contents
8.2 Functional Block Diagram....................................... 21
1 Features.................................................................. 18.3 Feature Description................................................. 21
2 Applications ........................................................... 18.4 Device Functional Modes........................................ 25
3 Description............................................................. 19 Application and Implementation ........................ 25
4 Revision History..................................................... 29.1 Application Information............................................ 25
5 Description (continued)......................................... 39.2 Typical Application.................................................. 27
6 Pin Configuration and Functions......................... 310 Power Supply Recommendations ..................... 30
7 Specifications......................................................... 511 Layout................................................................... 31
7.1 Absolute Maximum Ratings ..................................... 511.1 Layout Guidelines ................................................. 31
7.2 ESD Ratings.............................................................. 511.2 Layout Example .................................................... 31
7.3 Recommended Operating Conditions ...................... 612 Device and Documentation Support................. 32
7.4 Thermal Information.................................................. 612.1 Related Links ........................................................ 32
7.5 Electrical Characteristics 3-V.................................... 612.2 Community Resources.......................................... 32
7.6 Electrical Characteristics 5-V.................................... 912.3 Trademarks........................................................... 32
7.7 Electrical Characteristics ±5-V................................ 11 12.4 Electrostatic Discharge Caution............................ 32
7.8 Typical Characteristics............................................ 14 12.5 Glossary................................................................ 32
8 Detailed Description............................................ 21 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................. 21 Information........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (March 2013) to Revision I Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision G (March 2013) to Revision H Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 27
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V+
1
2
3
45
6
7
8
N/C
-IN
+IN
V-
OUTPUT
N/C
N/C
+
-
OUT
V-
IN+
V+
IN-
+-
1
2
3
5
4
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SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
5 Description (continued)
The LMP770x each have a rail-to-rail input stage that significantly reduces the CMRR glitch commonly
associated with rail-to-rail input amplifiers. This is achieved by trimming both sides of the complimentary input
stage, thereby reducing the difference between the NMOS and PMOS offsets. The output of the LMP770x
swings within 40 mV of either rail to maximize the signal dynamic range in applications requiring low supply
voltage.
The LMP7701 is offered in the space-saving 5-Pin SOT-23 and 8-Pin SOIC package. The LMP7702 is offered in
the 8-Pin SOIC and 8-Pin VSSOP package. The quad LMP7704 is offered in the 14-Pin SOIC and 14-Pin
TSSOP package. These small packages are ideal solutions for area constrained PC boards and portable
electronics.
6 Pin Configuration and Functions
LMP7701 DBV Package LMP7701 D Package
5-Pin SOT-23 8-Pin SOIC
Top View Top View
Pin Functions - LMP7701
PIN I/O DESCRIPTION
NAME SOT-23 SOIC
IN+ 3 3 I Noninverting Input
IN– 4 2 I Inverting Input
IN A +— — I Noninverting Input for Amplifier A
IN A–— — I Inverting Input for Amplifier A
IN B+— — I Noninverting Input for Amplifier B
IN B–— — I Inverting Input for Amplifier B
IN C+— — I Noninverting Input for Amplifier C
IN C–— — I Inverting Input for Amplifier C
IN D+— — I Noninverting Input for Amplifier D
IN D–— — I Inverting Input for Amplifier D
NC — 1, 5, 8 — No connection
OUT 1 6 O Output
OUT A — — O Output for Amplifier A
OUT B — — O Output for Amplifier B
OUT C — — O Output for Amplifier C
OUT D — — O Output for Amplifier D
V+5 7 P Positive Supply
V–2 4 P Negative Supply
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LMP7702 D or DGK Package
8-Pin SOIC or VSSOP
Top View
Pin Functions - LMP7702
PIN I/O DESCRIPTION
NAME SOIC, VSSOP
IN+ — I Noninverting Input
IN– — I Inverting Input
IN A +3 I Noninverting Input for Amplifier A
IN A–2 I Inverting Input for Amplifier A
IN B+5 I Noninverting Input for Amplifier B
IN B–6 I Inverting Input for Amplifier B
IN C+— I Noninverting Input for Amplifier C
IN C–— I Inverting Input for Amplifier C
IN D+— I Noninverting Input for Amplifier D
IN D–— I Inverting Input for Amplifier D
NC — — No connection
OUT — O Output
OUT A 1 O Output for Amplifier A
OUT B 7 O Output for Amplifier B
OUT C — O Output for Amplifier C
OUT D — O Output for Amplifier D
V+8 P Positive Supply
V–4 P Negative Supply
LMP7704 D or PW Package
14-Pin SOIC or TSSOP
Top View
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Pin Functions - LMP7704
PIN I/O DESCRIPTION
NAME SOIC, TSSOP
IN+ — I Noninverting Input
IN– — I Inverting Input
IN A +3 I Noninverting Input for Amplifier A
IN A–2 I Inverting Input for Amplifier A
IN B+5 I Noninverting Input for Amplifier B
IN B–6 I Inverting Input for Amplifier B
IN C+10 I Noninverting Input for Amplifier C
IN C–9 I Inverting Input for Amplifier C
IN D+12 I Noninverting Input for Amplifier D
IN D–13 I Inverting Input for Amplifier D
NC — — No connection
OUT — O Output
OUT A 1 O Output for Amplifier A
OUT B 7 O Output for Amplifier B
OUT C 8 O Output for Amplifier C
OUT D 14 O Output for Amplifier D
V+4 P Positive Supply
V–11 P Negative Supply
7 Specifications
7.1 Absolute Maximum Ratings
See (1)(2)
MIN MAX UNIT
VIN differential ±300 mV
Supply voltage (VS= V+– V−) 13.2 V
Voltage at input/output pins V++ 0.3, V−−0.3 V
Input current 10 mA
Junction temperature (3) +150 °C
Infrared or convection (20 sec) 235 °C
Soldering information Wave soldering lead temp. (10 sec) 260 °C
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/ Distributors for availability and specifications.
(3) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
7.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2000
Electrostatic
V(ESD) Charged-device model (CDM), per JEDEC specification JESD22-C101(3) ±1000 V
discharge Machine Model (MM) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions MIN NOM MAX UNIT
Temperature range (1) −40 125 °C
Supply voltage (VS= V+– V−) 2.7 12 V
(1) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
7.4 Thermal Information LMP7701,
LMP7701 LMP7702 LMP7704
LMP7702
DBV D DGK D PW
THERMAL METRIC(1) UNIT
(SOT-23) (SOIC) (VSSOP) (SOIC) (TSSOP)
5 PINS 8 PINS 8 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance (2) 122.9 114.3 167.5 79.9 107.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 69.3 59.5 58.7 36.9 33.0 °C/W
RθJB Junction-to-board thermal resistance 63.3 54.8 87.5 34.7 50.4 °C/W
ψJT Junction-to-top characterization parameter 19.4 12.1 6.6 5.5 1.8 °C/W
Junction-to-board characterization
ψJB 62.8 54.2 86.1 34.4 49.7 °C/W
parameter
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
(2) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
7.5 Electrical Characteristics 3-V
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3 V, V−= 0 V, VCM = V+/2, and RL> 10 kΩto V+/2.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
±37 ±200
LMP7701 at the temperature ±500
extremes
VOS Input Offset Voltage μV
±56 ±220
LMP7702/LMP7704 at the temperature ±520
extremes ±1
Input Offset Voltage Temperature
TCVOS See (4) μV/°C
at the temperature
Drift ±5
extremes ±0.2 ±1
See (4) (5) at the temperature
−40°C ≤TA≤85°C ±50
extremes
IBInput Bias Current pA
±0.2 ±1
See (4) (5) at the temperature
−40°C ≤TA≤125°C ±400
extremes
IOS Input Offset Current 40 fA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ> TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
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Electrical Characteristics 3-V (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3 V, V−= 0 V, VCM = V+/2, and RL> 10 kΩto V+/2.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
86 130
0 V ≤VCM ≤3 V at the temperature
LMP7701 80
extremes
CMRR Common-Mode Rejection Ratio dB
84 130
0 V ≤VCM ≤3 V at the temperature
LMP7702/LMP7704 78
extremes 86 98
PSRR Power Supply Rejection Ratio 2.7 V ≤V+≤12 V, Vo = V+/2 dB
at the temperature 82
extremes
CMRR ≥80 dB –0.2 3.2
CMVR Common-Mode Voltage Range V
at the temperature
CMRR ≥77 dB –0.2 3.2
extremes 100 114
RL= 2 kΩ(LMP7701) at the temperature
VO= 0.3 V to 2.7 V 96
extremes 100 114
RL= 2 kΩ
AVOL Open-Loop Voltage Gain (LMP7702/LMP7704) dB
at the temperature 94
VO= 0.3 V to 2.7 V extremes 100 124
RL= 10 kΩat the temperature
VO= 0.2 V to 2.8 V 96
extremes
VOUT 40 80
RL= 2 kΩto V+/2 at the temperature
LMP7701 120
extremes 40 80
RL= 2 kΩto V+/2 at the temperature
LMP7702/LMP7704 150
extremes mV
Output Voltage Swing High from V+
30 40
RL= 10 kΩto V+/2 at the temperature
LMP7701 60
extremes 35 50
RL= 10 kΩto V+/2 at the temperature
LMP7702/LMP7704 100
extremes 40 60
RL= 2 kΩto V+/2 at the temperature
LMP7701 80
extremes 45 100
RL= 2 kΩto V+/2 at the temperature
LMP7702/LMP7704 170
extremes
Output Voltage Swing Low mV
20 40
RL= 10 kΩto V+/2 at the temperature
LMP7701 50
extremes 20 50
RL= 10 kΩto V+/2 at the temperature
LMP7702/LMP7704 90
extremes
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Electrical Characteristics 3-V (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3 V, V−= 0 V, VCM = V+/2, and RL> 10 kΩto V+/2.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
25 42
Sourcing VO= V+/2 at the temperature
VIN = 100 mV 15
extremes 25 42
Sinking VO= V+/2
IOUT Output Current (6) (7) mA
at the temperature
VIN =−100 mV (LMP7701) 20
extremes 25 42
Sinking VO= V+/2
VIN =−100 mV at the temperature 15
(LMP7702/LMP7704) extremes 0.670 1
LMP7701 at the temperature 1.2
extremes 1.4 1.8
ISSupply Current LMP7702 mA
at the temperature 2.1
extremes 2.9 3.5
LMP7704 at the temperature 4.5
extremes
AV= +1, VO= 2 VPP
SR Slew Rate (8) 0.9 V/μs
10% to 90%
GBW Gain Bandwidth 2.5 MHz
THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV= 1, R.L= 10 kΩ0.02%
Input Referred Voltage Noise
enf = 1 kHz 9 nV/√Hz
Density
Input Referred Current Noise
inf = 100 kHz 1 fA/√Hz
Density
(6) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
(7) The short circuit test is a momentary test.
(8) The number specified is the slower of positive and negative slew rates.
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7.6 Electrical Characteristics 5-V
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−= 0 V, VCM = V+/2, and RL> 10 kΩto V+/2.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
±37 ±200
LMP7701 at the temperature ±500
extremes
VOS Input Offset Voltage μV
±32 ±220
LMP7702/LMP7704 at the temperature ±520
extremes ±1 ±5
Input Offset Voltage
TCVOS See (4) μV/°C
at the temperature
Temperature Drift extremes ±0.2 ±1
See (4) (5) at the temperature
−40°C ≤TA≤85°C ±50
extremes
IBInput Bias Current pA
±0.2 ±1
See (4) (5) at the temperature
−40°C ≤TA≤125°C ±400
extremes
IOS Input Offset Current 40 fA
88 130
0 V ≤VCM ≤5 V at the temperature
LMP7701 83
extremes
CMRR Common-Mode Rejection Ratio dB
86 130
0 V ≤VCM ≤5 V at the temperature
LMP7702/LMP7704 81
extremes 86 100
PSRR Power Supply Rejection Ratio 2.7 V ≤V+≤12 V, VO= V+/2 dB
at the temperature 82
extremes
CMRR ≥80 dB –0.2 5.2
CMVR Common-Mode Voltage Range V
at the temperature
CMRR ≥78 dB –0.2 5.2
extremes 100 119
RL= 2 kΩ(LMP7701) at the temperature
VO= 0.3 V to 4.7 V 96
extremes 100 119
RL= 2 kΩ
AVOL Open-Loop Voltage Gain (LMP7702/LMP7704) dB
at the temperature 94
VO= 0.3 V to 4.7 V extremes 100 130
RL= 10 kΩat the temperature
VO= 0.2 V to 4.8 V 96
extremes
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ> TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
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Electrical Characteristics 5-V (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−= 0 V, VCM = V+/2, and RL> 10 kΩto V+/2.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
60 110
RL= 2 kΩto V+/2 at the temperature
LMP7701 130
extremes 60 120
RL= 2 kΩto V+/2 at the temperature
LMP7702/LMP7704 200
extremes mV
Output Voltage Swing High from V+
40 50
RL= 10 kΩto V+/2 at the temperature
LMP7701 70
extremes 40 60
RL= 10 kΩto V+/2 at the temperature
LMP7702/LMP7704 120
extremes
VOUT 50 80
RL= 2 kΩto V+/2 at the temperature
LMP7701 90
extremes 50 120
RL= 2 kΩto V+/2 at the temperature
LMP7702/LMP7704 190
extremes
Output Voltage Swing Low mV
30 40
RL= 10 kΩto V+/2 at the temperature
LMP7701 50
extremes 30 50
RL= 10 kΩto V+/2 at the temperature
LMP7702/LMP7704 100
extremes 40 66
Sourcing VO= V+/2 at the temperature
VIN = 100 mV (LMP7701) 28
extremes 38 66
Sourcing VO= V+/2
VIN = 100 mV at the temperature 25
(LMP7702/LMP7704) extremes
IOUT Output Current (6) (7) mA
40 76
Sinking VO= V+/2 at the temperature
VIN =−100 mV (LMP7701) 28
extremes 40 76
Sinking VO= V+/2
VIN =−100 mV at the temperature 23
(LMP7702/LMP7704) extremes 0.715 1
LMP7701 at the temperature 1.2
extremes 1.5 1.9
ISSupply Current LMP7702 mA
at the temperature 2.2
extremes 2.9 3.7
LMP7704 at the temperature 4.6
extremes
AV= +1, VO= 4 VPP
SR Slew Rate (8) 1 V/μs
10% to 90%
GBW Gain Bandwidth 2.5 MHz
(6) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
(7) The short circuit test is a momentary test.
(8) The number specified is the slower of positive and negative slew rates.
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Electrical Characteristics 5-V (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−= 0 V, VCM = V+/2, and RL> 10 kΩto V+/2.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
Total Harmonic Distortion +
THD+N f = 1 kHz, AV= 1, RL= 10 kΩ0.02%
Noise
Input Referred Voltage Noise
enf = 1 kHz 9 nV/√Hz
Density
Input Referred Current Noise
inf = 100 kHz 1 fA/√Hz
Density
7.7 Electrical Characteristics ±5-V
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−=−5 V, VCM = 0 V, and RL> 10 kΩto 0 V.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
±37 ±200
LMP7701 at the temperature ±500
extremes
VOS Input Offset Voltage μV
±37 ±220
LMP7702/LMP7704 at the temperature ±520
extremes ±1
Input Offset Voltage
TCVOS See (4) μV/°C
at the temperature
Temperature Drift ±5
extremes ±0.2 1
See (4) (5) at the temperature
−40°C ≤TA≤85°C ±50
extremes
IBInput Bias Current pA
±0.2 1
See (4) (5) at the temperature
−40°C ≤TA≤125°C ±400
extremes
IOS Input Offset Current 40 fA
92 138
−5 V ≤VCM ≤5 V at the temperature
LMP7701 88
extremes
CMRR Common-Mode Rejection Ratio dB
90 138
−5 V ≤VCM ≤5 V at the temperature
LMP7702/LMP7704 86
extremes 86 98
PSRR Power Supply Rejection Ratio 2.7 V ≤V+≤12 V, VO= 0 V dB
at the temperature 82
extremes
CMRR ≥80 dB −5.2 5.2
CMVR Common-Mode Voltage Range V
at the temperature
CMRR ≥78 dB −5.2 5.2
extremes
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ> TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
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,
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,
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Electrical Characteristics ±5-V (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−=−5 V, VCM = 0 V, and RL> 10 kΩto 0 V.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
100 121
RL= 2 kΩ(LMP7701) at the temperature
VO=−4.7 V to 4.7 V 98
extremes 100 121
RL= 2 kΩ
(LMP7702/LMP7704) at the temperature 94
VO=−4.7 V to 4.7 V extremes
AVOL Open Loop Voltage Gain dB
100 134
RL= 10 kΩ(LMP7701) at the temperature
VO=−4.8 V to 4.8 V 98
extremes 100 134
RL= 10 kΩ
(LMP7702/LMP7704) at the temperature 97
VO=−4.8 V to 4.8 V extremes 90 150
RL= 2 kΩto 0 V at the temperature
LMP7701 170
extremes 90 180
RL= 2 kΩto 0 V at the temperature
LMP7702/LMP7704 290
extremes mV
Output Voltage Swing High from V+
40 80
RL= 10 kΩto 0 V at the temperature
LMP7701 100
extremes 40 80
RL= 10 kΩto 0 V at the temperature
LMP7702/LMP7704 150
extremes
VOUT 90 130
RL= 2 kΩto 0 V at the temperature
LMP7701 150
extremes 90 180
RL= 2 kΩto 0 V at the temperature
LMP7702/LMP7704 260
extremes mV
Output Voltage Swing Low from V–
40 50
RL= 10 kΩto 0 V at the temperature
LMP7701 60
extremes 40 60
RL= 10 kΩto 0 V at the temperature
LMP7702/LMP7704 110
extremes 50 86
Sourcing VO= 0 V at the temperature
VIN = 100 mV (LMP7701) 35
extremes 48 86
Sourcing VO= 0 V
IOUT Output Current (6) (7) VIN = 100 mV mA
at the temperature 33
(LMP7702/LMP7704) extremes 50 84
Sinking VO= 0 V at the temperature
VIN =−100 mV 35
extremes
(6) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
(7) The short circuit test is a momentary test.
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,
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SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
Electrical Characteristics ±5-V (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−=−5 V, VCM = 0 V, and RL> 10 kΩto 0 V.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
0.790 1.1
LMP7701 at the temperature 1.3
extremes 1.7 2.1
ISSupply Current LMP7702 mA
at the temperature 2.5
extremes 3.2 4.2
LMP7704 at the temperature 5
extremes
AV= +1, VO= 9 VPP
SR Slew Rate (8) 1.1 V/μs
10% to 90%
GBW Gain Bandwidth 2.5 MHz
Total Harmonic Distortion +
THD+N f = 1 kHz, AV= 1, RL= 10 kΩ0.02%
Noise
Input Referred Voltage Noise
enf = 1 kHz 9 nV/√Hz
Density
Input Referred Current Noise
inf = 100 kHz 1 fA/√Hz
Density
(8) The number specified is the slower of positive and negative slew rates.
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TCVOS (PV/°C)
-3 -2 -1 0 1 2 3
0
4
8
12
16
20
PERCENTAGE (%)
VS = 10V
-40°C dTAd125°C
TCVOS (PV/°C)
-3 -2 -1 0 1 2 3
0
4
8
12
16
20
PERCENTAGE (%)
VS = 5V
-40°C dTAd125°C
TCVOS (PV/°C)
-3 -2 -1 0 1 2 3
0
4
8
12
16
20
PERCENTAGE (%)
VS = 3V
-40°C dTAd125°C
LMP7701
,
LMP7702
,
LMP7704
SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
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7.8 Typical Characteristics
TA= 25°C, VCM = VS/2, RL> 10 kΩ(unless otherwise noted)
Figure 1. Figure 1. Offset Voltage Distribution Figure 2. TCVOS Distribution
Figure 3. Offset Voltage Distribution Figure 4. TCVOS Distribution
Figure 5. Offset Voltage Distribution Figure 6. TCVOS Distribution
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-1 0 1 2 3 4 5 6
-200
-150
-100
-50
0
50
100
150
200
OFFSET VOLTAGE (PV)
VCM (V)
VS = 5V
-40°C
25°C
125°C
-1 0 1 2 7 8 9 10 11
VCM (V)
-200
-150
-100
-50
0
50
100
150
200
OFFSET VOLTAGE (PV)
3 4 56
-40°C
125°C
25°C
VS = 10V
2 4 6 8 10 12
-200
-150
-100
-50
0
50
100
150
200
OFFSET VOLTAGE (PV)
SUPPLY VOLTAGE (V)
-40°C
25°C
125°C
-0.5 0 0.5 11.5 2 2.5 3 3.5
VCM (V)
-200
-150
-100
-50
0
50
100
150
200
OFFSET VOLTAGE (PV)
VS = 3V
25°C
125°C
-40°C
10 1k 1M
FREQUENCY (Hz)
-140
-100
-60
0
CMRR (dB)
100k
10k
100
-20
-80
-120
-40 VS = 5V
VS = 3V
VS = 10V
-40 -20 0 20 40 60 80 100 120125
-200
-150
-100
-50
0
50
200
OFFSET VOLTAGE (PV)
TEMPERATURE (°C)
100
150
VS = 3V
VS = 5V
VS = 10V
LMP7701
,
LMP7702
,
LMP7704
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SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
Typical Characteristics (continued)
TA= 25°C, VCM = VS/2, RL> 10 kΩ(unless otherwise noted)
Figure 7. Offset Voltage vs Temperature Figure 8. CMRR vs Frequency
Figure 10. Offset Voltage vs VCM
Figure 9. Offset Voltage vs Supply Voltage
Figure 11. Offset Voltage vs VCM Figure 12. Offset Voltage vs VCM
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0 2 4 6 8 10
-500
-250
0
250
500
IBIAS (fA)
VCM (V)
VS = 10V
-40°C
25°C
0 2 4 6 8 10
-300
-200
-100
0
100
200
300
IBIAS (pA)
VCM (V)
VS = 10V
85°C
125°C
0 1 2 3 4 5
-300
-200
-100
0
100
200
300
IBIAS (fA)
VCM (V)
VS = 5V
-40°C
25°C
01 2 3
VCM (V)
-300
-200
0
200
300
IBIAS (pA)
100
-100
85°C
125°C
45
VS = 5V
00.5 1 1.5 2 2.5 3
VCM (V)
-200
-100
0
100
200
IBIAS (fA)
VS = 3V
-40°C
25°C
01 2 3
VCM (V)
-300
-200
0
200
300
IBIAS (pA)
VS = 3V
0.5 1.5 2.5
100
-100
85°C
125°C
LMP7701
,
LMP7702
,
LMP7704
SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
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Typical Characteristics (continued)
TA= 25°C, VCM = VS/2, RL> 10 kΩ(unless otherwise noted)
Figure 14. Input Bias Current vs VCM
Figure 13. Input Bias Current vs VCM
Figure 16. Input Bias Current vs VCM
Figure 15. Input Bias Current vs VCM
Figure 17. Input Bias Current vs VCM Figure 18. Input Bias Current vs VCM
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0 20 40 60 80 100
0
1
2
(V+) -2
(V+) -1
V+
VOUT FROM RAIL (V)
OUTPUT CURRENT (mA)
||
VS = 3V, 5V, 10V
TA = -40°C, 25°C, 125C
3V
2 4 6 8 10 12
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
SLEW RATE (V/Ps)
SUPPLY VOLTAGE (V)
FALLING EDGE
RISING EDGE
AV = +1
VIN = 2 VPP
RL = 10 k:
CL = 10 pF
2 4 6 8 10 12
0
20
40
60
80
100
120
ISINK (mA)
SUPPLY VOLTAGE (V)
125°C
-40°C
25°C
2 4 6 8 10 12
0
20
40
60
80
100
120
ISOURCE (mA)
SUPPLY VOLTAGE (V)
125°C
-40°C
25°C
2 4 6 8 10 12
0
0.2
0.4
0.6
0.8
1
1.2
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE (V)
125°C
-40°C
25°C
10 1k 1M
FREQUENCY (Hz)
0
40
120
PSRR (dB)
100k
10k
100
100
60
20
80
-PSRR
+PSRR
VS = 10V
VS = 5V
VS = 3V
VS = 10V
VS = 5V
VS = 3V
LMP7701
,
LMP7702
,
LMP7704
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SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
Typical Characteristics (continued)
TA= 25°C, VCM = VS/2, RL> 10 kΩ(unless otherwise noted)
Figure 19. PSRR vs Frequency Figure 20. Supply Current vs Supply Voltage (Per Channel)
Figure 21. Sinking Current vs Supply Voltage Figure 22. Sourcing Current vs Supply Voltage
Figure 23. Output Voltage vs Output Current Figure 24. Slew Rate vs Supply Voltage
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1V/DIV
10 Ps/DIV
VS = 5V
f = 10 kHz
AV = +10
VIN = 400 mVPP
RL = 10 k:
CL = 10 pF
200 mV/DIV
10 Ps/DIV
VS = 5V
f = 10 kHz
AV = +10
VIN = 100 mVPP
RL = 10 k:
CL = 10 pF
500 mV/DIV
10 Ps/DIV
VS = 5V
f = 10 kHz
AV = +1
VIN = 2 VPP
RL = 10 k:
CL = 10 pF
20 mV/DIV
10 Ps/DIV
VS = 5V
f = 10 kHz
AV = +1
VIN = 100 mVPP
RL = 10 k:
CL = 10 pF
100
100 10k 1M 100M
FREQUENCY (Hz)
-60
-20
40
GAIN (dB)
10M100k
1k
80
60
20
0
-40
GAIN
PHASE
VS = 5V
CL = 20 pF
RL = 10 k:
225
-135
-45
90
180
135
45
0
-90
PHASE (°)
125°C
-40°C
25°C
125°C
-40°C
25°C
100
100 10k 1M 100M
FREQUENCY (Hz)
-60
-20
40
GAIN (dB)
10M100k
1k
80
60
20
0
-40
GAIN
PHASE
VS = 10V
CL = 20 pF
VS = 3V
CL = 100 pF
VS = 3V, 5V, 10V
CL = 20 pF, 50 pF, 100 pF
RL = 10 k:
225
-135
-45
90
180
135
45
0
-90
PHASE (°)
LMP7701
,
LMP7702
,
LMP7704
SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
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Typical Characteristics (continued)
TA= 25°C, VCM = VS/2, RL> 10 kΩ(unless otherwise noted)
Figure 25. Open-Loop Frequency Response Figure 26. Open-Loop Frequency Response
Figure 27. Large Signal Step Response Figure 28. Small Signal Step Response
Figure 29. Large Signal Step Response Figure 30. Small Signal Step Response
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2 4 6 8 10 12
0
20
40
60
80
100
VOUT FROM RAIL (mV)
SUPPLY VOLTAGE (V)
125°C
25°C
-40°C
RL = 2 k:
2 4 6 8 10 12
0
20
40
60
80
100
VOUT FROM RAIL (mV)
SUPPLY VOLTAGE (V)
125°C
25°C
-40°C
RL = 2 k:
2 4 6 8 10 12
0
10
20
30
40
50
VOUT FROM RAIL (mV)
SUPPLY VOLTAGE (V)
125°C 25°C
-40°C
RL = 10 k:
2 4 6 8 10 12
0
10
20
30
40
50
VOUT FROM RAIL (mV)
SUPPLY VOLTAGE (V)
125°C 25°C
-40°C
RL = 10 k:
500 400 300 200 100 0
60
70
80
90
100
110
120
130
140
150
OPEN LOOP GAIN (dB)
OUTPUT SWING FROM RAIL (mV)
RL = 2 k:
RL = 10 k:
VS = 3V
VS = 10V VS = 5V
1100 100k
FREQUENCY (Hz)
0
40
120
10k
1k
10
100
60
20
80
VS = 3V
VS = 5V
VS = 10V
INPUT REFERRED VOLTAGE NOISE
(nV/
Hz)
LMP7701
,
LMP7702
,
LMP7704
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SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
Typical Characteristics (continued)
TA= 25°C, VCM = VS/2, RL> 10 kΩ(unless otherwise noted)
Figure 31. Input Voltage Noise vs Frequency Figure 32. Open Loop Gain vs Output Voltage Swing
Figure 33. Output Swing High vs Supply Voltage Figure 34. Output Swing Low vs Supply Voltage
Figure 35. Output Swing High vs Supply Voltage Figure 36. Output Swing Low vs Supply Voltage
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100 1k 10k 100k 1M
FREQUENCY (Hz)
40
60
80
100
120
140
CROSSTALK REJECTION (dB)
VS = 3V VS = 5V
VS = 12V
0.001 0.01 0.1 1 10
VOUT (V)
0.001
0.01
0.1
1
THD+N (%)
AV = +1
AV = +10
VS = 5V
f = 1 kHz
RL = 100 k:
10 100 1k 10k 100k
FREQUENCY (Hz)
0.001
0.01
0.1
1
THD+N (%)
AV = +1
AV = +10
VS = 5V
VO = 4.5 VPP
RL = 100 k:
LMP7701
,
LMP7702
,
LMP7704
SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
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Typical Characteristics (continued)
TA= 25°C, VCM = VS/2, RL> 10 kΩ(unless otherwise noted)
Figure 37. THD+N vs Frequency Figure 38. THD+N vs Output Voltage
Figure 39. Crosstalk Rejection Ratio vs Frequency (LMP7702/LMP7704)
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OUT
V-
IN+
V+
IN-
+-
1
2
3
5
4
LMP7701
,
LMP7702
,
LMP7704
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SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
8 Detailed Description
8.1 Overview
The LMP770x are single, dual, and quad low offset voltage, rail-to-rail input and output precision amplifiers each
with a CMOS input stage and wide supply voltage range of 2.7V to 12V. The LMP770x have a very low input
bias current of only ±200 fA at room temperature.
The wide supply voltage range of 2.7V to 12V over the extensive temperature range of −40°C to 125°C makes
the LMP770x excellent choices for low voltage precision applications with extensive temperature requirements.
The LMP770x have only ±37 μV of typical input referred offset voltage and this offset is specified to be less than
±500 μV for the single and ±520 μV for the dual and quad, over temperature. This minimal offset voltage allows
more accurate signal detection and amplification in precision applications.
The low input bias current of only ±200 fA along with the low input referred voltage noise of 9 nV/√Hz gives the
LMP770x superiority for use in sensor applications. Lower levels of noise from the LMP770x mean of better
signal fidelity and a higher signal-to-noise ratio.
Texas Instruments is heavily committed to precision amplifiers and the market segment they serve. Technical
support and extensive characterization data is available for sensitive applications or applications with a
constrained error budget.
The LMP7701 is offered in the space saving 5-Pin SOT-23 and 8-Pin SOIC package. The LMP7702 comes in
the 8-Pin SOIC and 8-Pin VSSOP package. The LMP7704 is offered in the 14-Pin SOIC and 14-Pin TSSOP
package. These small packages are ideal solutions for area constrained PC boards and portable electronics.
8.2 Functional Block Diagram
Figure 40. Functional Block Diagram (LMP7701)
8.3 Feature Description
8.3.1 Capacitive Load
The LMP770x can each be connected as a non-inverting unity gain follower. This configuration is the most
sensitive to capacitive loading.
The combination of a capacitive load placed on the output of an amplifier along with the amplifier's output
impedance creates a phase lag which in turn reduces the phase margin of the amplifier. If the phase margin is
significantly reduced, the response will be either underdamped or it will oscillate.
To drive heavier capacitive loads, an isolation resistor, RISO,inFigure 41 should be used. By using this isolation
resistor, the capacitive load is isolated from the amplifier's output, and hence, the pole caused by CLis no longer
in the feedback loop. The larger the value of RISO, the more stable the output voltage will be. If values of RISO are
sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values of RISO
result in reduced output swing and reduced output current drive.
Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
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+¨
©
§
¨
©
§
-1
2CIN
P1,2 = 1
R1
1
R2r1
R1
1
R2
+
2
-4 A0CIN
R2
-R2/R1
1 + s
¨
©
§
¨
©
§
+s2
A0
CIN R2
¨
©
§
¨
©
§
VOUT
VIN (s) =
A0 R1
R1 + R2
CIN
R1
R2
VOUT
+
-
+
-
VIN
+
-
VOUT
VIN
R2
R1
AV = - = -
CF
LMP7701
,
LMP7702
,
LMP7704
SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
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Feature Description (continued)
Figure 41. Isolating Capacitive Load
8.3.2 Input Capacitance
CMOS input stages inherently have low input bias current and higher input referred voltage noise. The LMP770x
enhance this performance by having the low input bias current of only ±200 fA, as well as, a very low input
referred voltage noise of 9 nV/√Hz. To achieve this a larger input stage has been used. This larger input stage
increases the input capacitance of the LMP770x. The typical value of this input capacitance, CIN, for the
LMP770x is 25 pF. The input capacitance will interact with other impedances such as gain and feedback
resistors, which are seen on the inputs of the amplifier, to form a pole. This pole will have little or no effect on the
output of the amplifier at low frequencies and DC conditions, but will play a bigger role as the frequency
increases. At higher frequencies, the presence of this pole will decrease phase margin and will also cause gain
peaking. To compensate for the input capacitance, care must be taken in choosing the feedback resistors. In
addition to being selective in picking values for the feedback resistor, a capacitor can be added to the feedback
path to increase stability.
The DC gain of the circuit shown in Figure 42 is simply –R2/R1.
Figure 42. Compensating for Input Capacitance
For the time being, ignore CF. The AC gain of the circuit in Figure 42 can be calculated as follows:
(1)
This equation is rearranged to find the location of the two poles:
(2)
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1k 10k 100k 1M 10M
FREQUENCY (Hz)
-10
-8
-6
-4
-2
0
2
NORMALIZED GAIN (dB)
VS = 5V
R1 = R2 = 100 k:
AV = -1
CF = 5 pF
CF = 3 pF
CF = 1 pF
CF = 0 pF
(1 - AV)2
2A0AVCIN
<
R1
1k 10k 100k 1M 10M
FREQUENCY (Hz)
-10
-8
-6
-4
-2
0
2
NORMALIZED GAIN (dB)
VS = 5V
CF = 0 pF
AV = -1
R1 = R2 = 100 k:
R1 = R2 = 30 k:
R1 = R2 = 10 k:
R1 = R2 = 1 k:
LMP7701
,
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,
LMP7704
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SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
Feature Description (continued)
As shown in Equation 2, as values of R1and R2are increased, the magnitude of the poles is reduced, which in
turn decreases the bandwidth of the amplifier. Whenever possible, it is best to choose smaller feedback resistors.
Figure 43 shows the effect of the feedback resistor on the bandwidth of the LMP770x.
Figure 43. Closed-Loop Gain vs Frequency
Equation 2 has two poles. In most cases, it is the presence of pairs of poles that causes gain peaking. To
eliminate this effect, the poles should be placed in Butterworth position, because poles in Butterworth position do
not cause gain peaking. To achieve a Butterworth pair, the quantity under the square root in Equation 2 should
be set to equal −1. Using this fact and the relation between R1and R2, R2=−AVR1, the optimum value for R1
can be found. This is shown in Equation 3. If R1is chosen to be larger than this optimum value, gain peaking will
occur.
(3)
In Figure 42, CFis added to compensate for input capacitance and to increase stability. Additionally, CFreduces
or eliminates the gain peaking that can be caused by having a larger feedback resistor. Figure 44 shows how CF
reduces gain peaking.
Figure 44. Closed-Loop Gain vs Frequency With Compensation
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ESD R1
IN+
ESD
D1
D2
R2ESD
IN-
ESD
V+
V-V-
V+
LMP7701
,
LMP7702
,
LMP7704
SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
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Feature Description (continued)
8.3.3 Diodes Between the Inputs
The LMP770x have a set of anti-parallel diodes between the input pins, as shown in Figure 45. These diodes are
present to protect the input stage of the amplifier. At the same time, they limit the amount of differential input
voltage that is allowed on the input pins. A differential signal larger than one diode voltage drop might damage
the diodes. The differential signal between the inputs needs to be limited to ±300 mV or the input current needs
to be limited to ±10 mA.
Figure 45. Input of LMP7701
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I = V2 ± V1
RS
V2R
R + R
(V0 ± IRS)R V1R V0R
+= +
R + R R + R R + R
+
RS
ZLOAD
V1
V2
RR
RR
V+
V+
V-
V-
+
-
-
I = (V2 ± V1)
RS
A1
A2
LMP7701
,
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,
LMP7704
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SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
8.4 Device Functional Modes
8.4.1 Precision Current Source
The LMP770x can each be used as a precision current source in many different applications. Figure 46 shows a
typical precision current source. This circuit implements a precision voltage controlled current source. Amplifier
A1 is a differential amplifier that uses the voltage drop across RSas the feedback signal. Amplifier A2 is a buffer
that eliminates the error current from the load side of the RSresistor that would flow in the feedback resistor if it
were connected to the load side of the RSresistor. In general, the circuit is stable as long as the closed loop
bandwidth of amplifier A2 is greater then the closed loop bandwidth of amplifier A1. If A1 and A2 are the same
type of amplifiers, then the feedback around A1 will reduce its bandwidth compared to A2.
Figure 46. Precision Current Source
The equation for output current can be derived as shown in Equation 4.
(4)
Solving for the current I results in the Equation 5.
(5)
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Low Input Voltage Noise
The LMP770x have the very low input voltage noise of 9 nV/√Hz. This input voltage noise can be further reduced
by placing N amplifiers in parallel as shown in Figure 47. The total voltage noise on the output of this circuit is
divided by the square root of the number of amplifiers used in this parallel combination. This is because each
individual amplifier acts as an independent noise source, and the average noise of independent sources is the
quadrature sum of the independent sources divided by the number of sources. For N identical amplifiers, this
means:
Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LMP7701 LMP7702 LMP7704
eni = en +
2ei +
2et
2
V-
V+
VOUT
RO
RG
VIN
RF
V-
V+
RO
RG
RF
V-
V+
RO
RG
RF
V-
V+
RO
RG
RF
+
-
+
-
+
-
+
-
REDUCED INPUT VOLTAGE NOISE = en1+en2+
2 2 +enN
2
=
1
N
1
NNen
2=N
Nen
=1en
N
LMP7701
,
LMP7702
,
LMP7704
SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
www.ti.com
Application Information (continued)
(6)
Figure 47 shows a schematic of this input voltage noise reduction circuit. Typical resistor values are:
RG= 10Ω, RF=1kΩ, and RO=1kΩ.
Figure 47. Noise Reduction Circuit
9.1.2 Total Noise Contribution
The LMP770x have very low input bias current, very low input current noise, and very low input voltage noise. As
a result, these amplifiers are ideal choices for circuits with high impedance sensor applications.
Figure 48 shows the typical input noise of the LMP770x as a function of source resistance where:
endenotes the input referred voltage noise
eiis the voltage drop across source resistance due to input referred current noise or ei= RS* in
etshows the thermal noise of the source resistance
eni shows the total noise on the input.
Where:
26 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: LMP7701 LMP7702 LMP7704
A1
V+
1
LM35
V+
pH ELECTRODE
pH ELECTRODE TEMPERATURE
R3
10 k:
R4
10 k:
+
-A2
V+
R1
10 k:
R2
10 k:
V-
V-
+
-
ADC12034
0.01 PF
0.1 PF
10 PF
VD+
CH0
CH1
VREF-
VREF+
DGND
0.01 PF
10 PF
AGND
VOUT
VA+
V+
V+
LM4140A 6
2
1,4,7,8
3R5
10 k:
R6
3.3 k:
VOFFSET = 0.5012V
0.1 PF
RT
-V+
1 PF
75:
10 1k 100k 10M
RS (:)
0.1
1
10
1000
1M10k
100
100
VOLTAGE NOISE DENSITY (nV/
Hz)
eni en
ei
et
LMP7701
,
LMP7702
,
LMP7704
www.ti.com
SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
Application Information (continued)
The input current noise of the LMP770x is so low that it will not become the dominant factor in the total noise
unless source resistance exceeds 300 MΩ, which is an unrealistically high value.
As is evident in Figure 48, at lower RSvalues, total noise is dominated by the amplifier's input voltage noise.
Once RSis larger than a few kilo-Ohms, then the dominant noise factor becomes the thermal noise of RS. As
mentioned before, the current noise will not be the dominant noise factor for any practical application.
Figure 48. Total Input Noise
9.2 Typical Application
Figure 49. pH Measurement Circuit
Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LMP7701 LMP7702 LMP7704
ACID BASE
024710 12 14
+414 mV -414 mV
-177 mV
0 mV
+177 mV
pH
SENSOR V+
V-
RS+
-
IBVIN+
VS+
-
LMP7701
,
LMP7702
,
LMP7704
SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
www.ti.com
Typical Application (continued)
9.2.1 Design Requirements
pH electrodes are very high impedance sensors. As their name indicates, they are used to measure the pH of a
solution. They usually do this by generating an output voltage which is proportional to the pH of the solution. pH
electrodes are calibrated so that they have zero output for a neutral solution, pH = 7, and positive and negative
voltages for acidic or alkaline solutions. This means that the output of a pH electrode is bipolar and must be level
shifted to be used in a single supply system. The rate of change of this voltage is usually shown in mV/pH and is
different for different pH sensors. Temperature is also an important factor in a pH electrode reading. The output
voltage of the senor will change with temperature.
9.2.2 Detailed Design Procedure
Many sensors have high source impedances that may range up to 10 MΩ. The output signal of sensors often
needs to be amplified or otherwise conditioned by means of an amplifier. The input bias current of this amplifier
can load the sensor's output and cause a voltage drop across the source resistance as shown in Figure 50,
where VIN+= VS– IBIAS*RS
The last term, IBIAS*RS, shows the voltage drop across RS. To prevent errors introduced to the system due to this
voltage, an op amp with very low input bias current must be used with high impedance sensors. This is to keep
the error contribution by IBIAS*RSless than the input voltage noise of the amplifier, so that it will not become the
dominant noise factor.
Figure 50. Noise Due to IBIAS
Figure 51 shows a typical output voltage spectrum of a pH electrode. The exact values of output voltage will be
different for different sensors. In this example, the pH electrode has an output voltage of 59.15 mV/pH at 25°C.
Figure 51. Output Voltage of a pH Electrode
The temperature dependence of a typical pH electrode is shown in Figure 52. As is evident, the output voltage
changes with changes in temperature.
The schematic shown in Figure 49 is a typical circuit which can be used for pH measurement. The LM35 is a
precision integrated circuit temperature sensor. This sensor is differentiated from similar products because it has
an output voltage linearly proportional to Celcius measurement, without converting the temperature to Kelvin. The
LM35 is used to measure the temperature of the solution and feeds this reading to the Analog to Digital
Converter, ADC. This information is used by the ADC to calculate the temperature effects on the pH readings.
The LM35 needs to have a resistor, RTin Figure 49, to –V+to be able to read temperatures less than 0°C. RTis
not needed if temperatures are not expected to be less than zero.
28 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: LMP7701 LMP7702 LMP7704
1
2
3
4
5 7
8
9
10
11
12
13
14
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
pH
mV
10°C (74.04 mV/pH)
25°C (59.15 mV/pH)
0°C (54.20 mV/pH)
LMP7701
,
LMP7702
,
LMP7704
www.ti.com
SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
Typical Application (continued)
The output of pH electrodes is usually large enough that it does not require much amplification; however, due to
the very high impedance, the output of a pH electrode needs to be buffered before it can go to an ADC. Because
most ADCs are operated on single supply, the output of the pH electrode also needs to be level shifted. Amplifier
A1 buffers the output of the pH electrode with a moderate gain of +2, while A2 provides the level shifting. VOUT at
the output of A2 is given by: VOUT =−2VpH + 1.024V.
The LM4140A is a precision, low noise, voltage reference used to provide the level shift needed. The ADC used
in this application is the ADC12032 which is a 12-bit, 2 channel converter with multiplexers on the inputs and a
serial output. The 12-bit ADC enables users to measure pH with an accuracy of 0.003 of a pH unit. Adequate
power supply bypassing and grounding is extremely important for ADCs. Recommended bypass capacitors are
shown in Figure 49. It is common to share power supplies between different components in a circuit. To minimize
the effects of power supply ripples caused by other components, the op amps must have bypass capacitors on
the supply pins. Using the same value capacitors as those used with the ADC are ideal. The combination of
these three values of capacitors ensures that AC noise present on the power supply line is grounded and does
not interfere with the amplifiers' signal.
9.2.3 Application Curves
Figure 52. Temperature Dependence of a pH Electrode
Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: LMP7701 LMP7702 LMP7704
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,
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,
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SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
www.ti.com
10 Power Supply Recommendations
For proper operation, the power supplies must be decoupled. For supply decoupling, TI recommends placing
10-nF to 1-µF capacitors as close as possible to the operational-amplifier power supply pins. For single supply
configurations, place a capacitor between the V+and V–supply pins. For dual supply configurations, place one
capacitor between V+and ground, and place a second capacitor between V–and ground. Bypass capacitors
must have a low ESR of less than 0.1 Ω.
30 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: LMP7701 LMP7702 LMP7704
+3.3V
+3.3V
+3.3V
GND
+3.3V
1
+3.3V
2
+3.3V
1
V+
2
V+
V+
3
V+
2
GND 1
VOUT
2
GND
5
+3.3V
+3.3V
+3.3V
VOUT
4
V–
1
GND GND
1
GND
2
VOUT
2
VOUT
1
V–
1
V–
2
V–
GND
GND
V+
LMP7701
,
LMP7702
,
LMP7704
www.ti.com
SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
11 Layout
11.1 Layout Guidelines
Take care to minimize the loop area formed by the bypass capacitor connection between supply pins and
ground. A ground plane underneath the device is recommended; any bypass components to ground should have
a nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding
supply pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins will lower the
power supply inductance and provide a more stable power supply.
The feedback components should be placed as close to the device as possible to minimize stray parasitics.
11.2 Layout Example
Figure 53. LMP7701 Example Layout
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Product Folder Links: LMP7701 LMP7702 LMP7704
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,
LMP7702
,
LMP7704
SNOSAI9I –SEPTEMBER 2005–REVISED NOVEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL TOOLS AND SUPPORT AND
PARTS PRODUCT FOLDER SAMPLE AND BUY DOCUMENTS SOFTWARE COMMUNITY
LMP7701 Click here Click here Click here Click here Click here
LMP7702 Click here Click here Click here Click here Click here
LMP7704 Click here Click here Click here Click here Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
LMP, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: LMP7701 LMP7702 LMP7704
PACKAGE OPTION ADDENDUM
www.ti.com 5-Oct-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMP7701MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM LMP77
01MA
LMP7701MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM LMP77
01MA
LMP7701MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 AC2A
LMP7701MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AC2A
LMP7701MFX NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 AC2A
LMP7701MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AC2A
LMP7702MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM LMP77
02MA
LMP7702MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM LMP77
02MA
LMP7702MM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 AA3A
LMP7702MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AA3A
LMP7702MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AA3A
LMP7704MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM LMP7704
MA
LMP7704MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM LMP7704
MA
LMP7704MT NRND TSSOP PW 14 94 TBD Call TI Call TI -40 to 125 LMP77
04MT
LMP7704MT/NOPB ACTIVE TSSOP PW 14 94 Pb-Free
(RoHS) CU SN Level-1-260C-UNLIM -40 to 125 LMP77
04MT
LMP7704MTX/NOPB ACTIVE TSSOP PW 14 2500 Pb-Free
(RoHS) CU SN Level-1-260C-UNLIM -40 to 125 LMP77
04MT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Oct-2015
Addendum-Page 2
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMP7701MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMP7701MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMP7701MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMP7701MFX SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMP7701MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMP7702MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMP7702MM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMP7702MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMP7702MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMP7704MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMP7704MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMP7701MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMP7701MF SOT-23 DBV 5 1000 210.0 185.0 35.0
LMP7701MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMP7701MFX SOT-23 DBV 5 3000 210.0 185.0 35.0
LMP7701MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMP7702MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMP7702MM VSSOP DGK 8 1000 210.0 185.0 35.0
LMP7702MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMP7702MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LMP7704MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LMP7704MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
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