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Microcontrollers
M68HC05
MC68HC05B4
MC68HC705B5
MC68HC05B5
MC68HC05B6
MC68HC05B8
MC68HC05B16
MC68HC705B16
MC68HC705B16N
MC68HC05B32
MC68HC705B32
Technical Data
MC68HC05B6/D
Rev. 4.1
08/2005
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
INPUT/OUTPUT PORTS
PROGRAMMABLE TIMER
SERIAL COMMUNICATIONS INTERFACE
PULSE LENGTH D/A CONVERTERS
ANALOG TO DIGITAL CONVERTER
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
ORDERING INFORMATION
APPENDICES
HIGH SPEED OPERATION
TPG
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
INPUT/OUTPUT PORTS
PROGRAMMABLE TIMER
SERIAL COMMUNICATIONS INTERFACE
PULSE LENGTH D/A CONVERTERS
ANALOG TO DIGITAL CONVERTER
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
ORDERING INFORMATION
APPENDICES
HIGH SPEED OPERATION
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SECTION 1 INTRODUCTION
SECTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS
SECTION 3 MEMORY AND REGISTERS
SECTION 4 INPUT/OUTPUT PORTS
SECTION 5 PROGRAMMA BLE TIMER
SECTION 6 SERIAL COMMUNICATIONS INTERFACE
SECTION 7 PULSE LENGTH D/A CONVERTERS
SECTION 8 ANALOG TO DIGITAL CONVER TER
SECTION 9 RESETS AND INTERRUPTS
SECTION 10 CPU CORE AND INSTRUCTION SET
SECTION 11 ELECTRICAL SPECIFICATIONS
SECTION 12 MECHANICAL DATA
SECTION 13 ORDERING INFORMATION
SECTION 14 APPENDICES
SECTION 15 HIGH SPEED OPERATION
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Freescale LTD., 2005
All Trade Marks recognized. This document contains information on new products. Specifications and information herein are
subject to change without notice .
MC68HC05B6
High-density Complementary
Metal Oxide Semiconductor
(HCMOS) Microcomputer Unit
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Conventions
Where abbreviations are used in the text, an explanation can be found in the
glossary, at the back of this manual. Register and bit mnemonics are def ined in the
paragraphs describing the m .
An overbar is used to designate an active-low signal, eg: RESET.
Unless otherwise stated, shaded cells in a register diagram indicate that the bit is
either unused or reserved; ‘u’ is used to indicate an undefined state ( on reset).
Unless otherwise stated, pins labelled “NU” should be tied to VSS in an electrically
noisy en vironment. Pins labelled “NC” can be le ft floating, since the y are not bonded
to any part of the device.
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MC68HC05B6
Rev. 4.1 Freescale
i
TABLE OF CONTENTS
Paragraph
Number Page
NumberTITLE
TA BLE OF CONTENTS
1
INTRODUCTION
1.1 Features.............................................................................................................1–2
1.2 Mask options for the MC68HC05B6..................................................................1–3
2
MODES OF OPERATION AND PIN DESCRIPTIONS
2.1 Modes of operation............................................................................................2–1
2.1.1 Single chip mode .........................................................................................2–1
2.2 Serial RAM loader .............. .................... .................................... .................... ...2–2
2.3 ‘Ju mp to any address’............................. .................................... .................... ...2–4
2.4 Low power modes..............................................................................................2–6
2.4.1 STOP ...........................................................................................................2–6
2.4.2 WAIT............................................................................................................2–8
2.4.2.1 Power consumption during WAIT mode.................................................2–8
2.4.3 SLOW mode.................................................................................................2–9
2.4.3.1 Miscellaneous register...........................................................................2–9
2.5 Pin descriptions ..............................................................................................2–10
2.5.1 VDD and VSS............................................................................................2–10
2.5.2 IRQ ............................................................................................................2–10
2.5.3 RESET.......................................................................................................2–10
2.5.4 TCAP1 .......................................................................................................2–10
2.5.5 TCAP2 .......................................................................................................2–11
2.5.6 TCMP1.......................................................................................................2–11
2.5.7 TCMP2.......................................................................................................2–11
2.5.8 OSC1, OSC2 .............................................................................................2–11
2.5.8.1 Crystal..................................................................................................2–11
2.5.8.2 Ceramic resonator................................................................................2–11
2.5.8.3 Extern al clock.......................................................................................2–12
2.5.9 RDI (Receive data in).................................................................................2–13
2.5.10 TDO (Transmit data out) ............................................................................2–13
2.5.11 SCLK..........................................................................................................2–13
2.5.12 PLMA.........................................................................................................2–13
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2.5.13 PLMB.........................................................................................................2–13
2.5.14 VPP1..........................................................................................................2–13
2.5.15 VRH...........................................................................................................2–13
2.5.16 VRL............................................................................................................2–13
2.5.17 PA0 – PA7/PB0 – PB7/PC0 – PC7 ............................................................2–13
2.5.18 PD0/AN0–PD7/AN7...................................................................................2–13
3
MEMORY AND REGISTERS
3.1 Registers...........................................................................................................3–1
3.2 RAM ..................................................................................................................3–1
3.3 ROM..................................................................................................................3–1
3.4 Self-check ROM ................................................................................................3–2
3.5 EEPROM...........................................................................................................3–3
3.5.1 EEPROM control register ............................................................................3–3
3.5.2 EEPROM read operation.............................................................................3–5
3.5.3 EEPROM erase operation ...........................................................................3–5
3.5.4 EEPROM programming operation...............................................................3–6
3.5.5 Options register (OPTR)............ .................... .. .................... .................... ....3–6
3.6 EEPROM during STOP mode...........................................................................3–7
3.7 EEPROM during WAIT mode............................................................................3–7
3.8 Miscellaneous register......................................................................................3–9
4
INPUT/OUTPUT PORTS
4.1 Input/output programming .................................................................................4–1
4.2 Ports A and B ....................................................................................................4–2
4.3 Port C................................................................................................................4–3
4.4 Port D................................................................................................................4–3
4.5 Port registers.....................................................................................................4–4
4.5.1 Port data registers A and B (PORTA and POR T B).................... .. ................4–4
4.5.2 Port data register C (PORTC).......... .. .................... .................................... ..4–4
4.5.3 Port data register D (PORTD).......... .. .................... .................................... ..4–5
4.5.3.1 A/D status/control register......................................................................4–5
4.5.4 Data direction registe r s (DDRA, DDRB and DDRC)....................................4–5
4.6 Other port considerations..... ... .. ... ... ... ...............................................................4–6
MC68HC05B6
Rev. 4.1 Freescale
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TABLE OF CONTENTS
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5
PROGRAMMABLE TIMER
5.1 Counter..............................................................................................................5–1
5.1.1 Counter register and alternate counter register............ ... ... ................... ... ...5–3
5.2 Timer control and status....................................................................................5–4
5.2.1 Timer control register (TCR)................... ................... .................... ..............5–4
5.2.2 Timer status register (TSR).......................................................................... 5–6
5.3 Input capture.... ... .. ...................................................................... .......................5–7
5.3.1 Input capture register 1 (ICR1) .................................................................... 5–7
5.3.2 Input capture register 2 (ICR2) .................................................................... 5–8
5.4 Output compare.................................................................................................5–9
5.4.1 Output compare register 1 (OCR1)..............................................................5–9
5.4.2 Output compare register 2 (OCR2)............................................................5–10
5.4.3 Software force compare.............................................................................5–11
5.5 Pulse Length Modulation (PLM) ......................................................................5–11
5.5.1 Pulse length modulation registe r s A and B (PLMA/PLMB)........................5–11
5.6 Timer during STOP mode................................................................................5–12
5.7 Timer during WAIT mode.................................................................................5–12
5.8 Timer state diagrams.......................................................................................5–12
6
SERIAL COMMUNICATIONS INTERFACE
6.1 SCI two-wire system features............................................................................6–1
6.2 SCI receiver features.........................................................................................6–3
6.3 SCI transmitter features.....................................................................................6–3
6.4 Functional description........................................................................................6–3
6.5 Data format........................................................................................................6–5
6.6 Receive r wake-up oper ation...................... ................... ... .................... ... ...........6–5
6.6.1 Idle line wake-up..........................................................................................6–6
6.6.2 Address mark wake-up ................................................................................6–6
6.7 Receive data in (RDI) ........................................................................................6–6
6.8 Start bit detection...............................................................................................6–6
6.9 Transmit data out (TDO).............. ................... .................... .................... ...........6–8
6.10 SCI synchronous transmission..........................................................................6–9
6.11 SCI registers....................................................................................................6–10
6.11.1 Serial communications data register (SCDR)............................................6–10
6.11.2 Serial communications control register 1 (SCCR1) ...................................6–10
6.11.3 Serial communications control register 2 (SCCR2) ...................................6–14
6.11.4 Serial communications statu s register (SCSR)..........................................6–16
6.11.5 Baud rate register (BAUD) .........................................................................6–18
6.12 Baud rate selection..........................................................................................6–19
6.13 SCI during STOP mode...................................................................................6–21
6.14 SCI during WAIT mode....................................................................................6–21
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7
PULSE LENGTH D/A CONVERTERS
7.1 Miscellaneous register.......................................................................................7–3
7.2 PLM clock selection...........................................................................................7–4
7.3 PLM during STOP mode ...................................................................................7–4
7.4 PLM during WAIT mode....................................................................................7–4
8
ANALOG TO DIGITAL CONVERTER
8.1 A/D converter oper a tion......................... ................... .................... ................... ..8–1
8.2 A/D registers........... ... .. ................................................... ... .. ..............................8–3
8.2.1 Port D data register (PORTD).......... .. ... .................... ................... ................8–3
8.2.2 A/D result data register (ADDATA)...............................................................8–3
8.2.3 A/D status/control register (ADSTAT)...........................................................8–4
8.3 A/D converter during STOP mode.....................................................................8–6
8.4 A/D converter during WAIT mode......................................................................8–6
8.5 Port D analog input............................................................................................8–6
9
RESETS AND INTERRUPTS
9.1 Resets...............................................................................................................9–1
9.1.1 Power-on reset.............................................................................................9–2
9.1.2 Miscellaneous register................................................................................9–2
9.1.3 RESET pin................ ... ................. ... ................................. ... ........................9–3
9.1.4 Computer operating properly (COP) watchdog reset ..................................9–3
9.1.4.1 COP watchdog during STOP mode.......................................................9–4
9.1.4.2 COP watchdog during WAIT mode........................................................9–4
9.1.5 Functions aff ected by reset..........................................................................9–5
9.2 Interrupts...........................................................................................................9–6
9.2.1 Interrupt priorities.........................................................................................9–6
9.2.2 Nonmaskable software interrupt (SWI)........................................................9–6
9.2.3 Maskable hardware interrupts .....................................................................9–7
9.2.3.1 External interrupt (IRQ)..........................................................................9–7
9.2.3.2 Miscellaneous register ................ ... .................... ... ................... ... ..........9–9
9.2.3.3 Timer interrupts....................................................................................9–10
9.2.3.4 Serial communications interface (SCI) interrupts.................................9–10
9.2.4 Hardware controlled interrupt sequence....................................................9–11
MC68HC05B6
Rev. 4.1 Freescale
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TABLE OF CONTENTS
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10
CPU CORE AND INSTRUCTION SET
10.1 Registers .........................................................................................................10–1
10.1.1 Accumulator (A).........................................................................................10–2
10.1.2 Index register (X)........................................................................................10–2
10.1.3 Program counter (PC)................................................................................10–2
10.1.4 Stack pointer (SP)......................................................................................10–2
10.1.5 Condition code register (CCR)...................................................................10–2
10.2 Instr uction set..................................................................................................10–3
10.2.1 Register/memory Instructions....................................................................10–4
10.2.2 Branch instructions ....................................................................................10–4
10.2.3 Bit manipulation instructions......................................................................10–4
10.2.4 Read/modify/write instructions...................................................................10–4
10.2.5 Control instructions....................................................................................10–4
10.2.6 Tables.........................................................................................................10–4
10.3 Addressing modes.........................................................................................10–11
10.3.1 Inherent....................................................................................................10–11
10.3.2 Immediate................................................................................................10–11
10.3.3 Direct........................................................................................................10–11
10.3.4 Extended..................................................................................................10–12
10.3.5 Indexed, no offset.....................................................................................10–12
10.3.6 Indexed, 8-bit offset..................................................................................10–12
10.3.7 Indexed, 16-bit offset................................................................................10–12
10.3.8 Relative....................................................................................................10–13
10.3.9 Bit set/clear..............................................................................................10–13
10.3.10 Bit test and branch...................................................................................10–13
11
ELECTRICAL SPECIFICATIONS
11.1 Absolute maximum ratings ..............................................................................11–1
11.2 DC electrical characteri stics............................................................................11–2
11.2.1 IDD trends for 5V operation ........................................................................11–3
11.2.2 IDD trends for 3.3V operation .....................................................................11–6
11.3 A/D converter characteristics...........................................................................11–8
11.4 Control timing ................................................................................................11–10
12
MECHANICAL DATA
12.1 MC68HC05B family pin configurations............................................................12–1
12.1.1 52-pin plastic leaded chip carrier (PLCC)..................................................12–1
12.1.2 64-pin quad flat pa ck (QFP).......................................................................12–2
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12.1.3 56-pin shrink dual in line package (SDIP)............................................. ... ..12–3
12.2 MC68HC05B6 mechanical dimensions.......................... ... .. .................... ... ... ..12–4
12.2.1 52-pin plastic leaded chip carrier (PLCC)..................................................12–4
12.2.2 64-pin quad flat pack (QFP).......................................................................12–5
12.2.3 56-pin shrink dual in line package (SDIP)............................................. ... ..12–6
13
ORDERING INFORMATION
13.1 EPROMS.........................................................................................................13–2
13.2 Verification media............................................................................................13–2
13.3 ROM verification units (RVU)................... ... .................... ................... ... ...........13–2
A
MC68HC05B4
A.1 Features ........................................................................................................... A–1
A.2 Self-check mode............................................................................................... A–5
B
MC68HC05B8
B.1 Features ........................................................................................................... B–1
C
MC68HC705B5
C.1 Features ........................................................................................................... C–1
C.2 EPROM ............................................................................................................ C–5
C.2.1 EPROM pr ogramming operat ion........... ... ... ................... .................... .........C–5
C.3 EPROM registers.............................................................................................. C–6
C.3.1 EPROM cont rol register......................................... .................... .................C–6
C.4 Options register (OPTR)................................................................................... C –7
C.5 Boots trap mode........... ... ................. ... ... ...........................................................C–8
C.5.1 Erased EPROM verification......................................................................C–11
C.5.2 EPROM parallel bootstrap load ......... .................... .................... .. .............C–11
C.5.3 EPROM (RAM) serial bootstrap load and execute ...................................C–13
C.5.4 RAM parallel bootstrap load and execute.................................................C–14
C.5.5 Bootstrap loader timing diagrams............................................................. C–17
C.6 DC electrical characteristics........................................................................... C–19
C.7 Control timing.................................................................................................C–19
MC68HC05B6
Rev. 4.1 Freescale
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TABLE OF CONTENTS
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D
MC68HC05B16
D.1 Features............................................................................................................D–1
D.2 Self-check routines...........................................................................................D–2
D.3 External clock...................................................................................... .............D–4
E
MC68HC705B16
E.1 Features............................................................................................................ E–2
E.2 External clock......................................... .......................................................... E–5
E.3 EPROM............................................................................................................. E–5
E.3.1 EPROM read operation...............................................................................E–5
E.3.2 EPROM program operation .........................................................................E–5
E.3.3 EPROM/EEPROM/ECLK control register................................................... E–6
E.3.4 Mask option register.... .. ... .................... ................... .................... ................E–8
E.3.5 EEPROM options register (OPTR) ............................................................. E–9
E.4 Bootstrap mode..............................................................................................E–10
E.4.1 Erased EPROM verification ......................................................................E–13
E.4.2 EPROM/EEPROM parallel bootstrap........................................................E–13
E.4.3 EEPROM/EPR OM/RAM serial bootstrap..................................................E–16
E.4.4 RAM parallel bootstrap .................. ... .................... ................... .................E–19
E.4.4.1 Jump to start of RAM ($0050)............................................................. E–20
E.5 Absolute maximum ratings .............................................................................E–21
E.6 DC electrical characteristics...........................................................................E–22
E.7 A/D converter characteristics..........................................................................E–24
E.8 Control timing ................................................................................................. E–26
E.9 EPROM electrical characteristics...................................................................E–28
F
MC68HC705B16N
F.1 Features............................................................................................................ F–2
F.2 External clock............. .................... .................................................................. F–5
F.3 RESET pin........................................................................................................ F–5
F.4 EPROM............................................................................................................. F–5
F.4.1 EPROM read operation............................................................................... F–5
F.4.2 EPROM program operation......................................................................... F–6
F.4.3 EPROM/EEPROM/ECLK control register................................................... F–6
F.4.4 Mask option register.... .. ..................................... ................... ...................... F–8
F.4.5 EEPROM options register (OPTR) ............................................................. F–9
F.5 Bootstrap mode.............................................................................................. F–10
F.5.1 Erased EPROM verification ...................................................................... F–13
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F.5.2 EPROM/EEPROM parallel bootstrap.........................................................F–13
F.5.3 Serial RAM loader...................................................................................... F–16
F.5.3.1 Jump to start of RAM ($0051)..............................................................F–16
F.6 Absolute maximum ratings..............................................................................F–19
F.7 DC electrical characteristics............................................................................F–20
F.8 A/D converter characteristics ..................... ... ... ................... ... ... .................... ..F–22
F.9 Control timing..................................................................................................F–24
F.10 EPROM electrical characteristics....................................................................F–26
G
MC68HC05B32
G.1 Features ...........................................................................................................G–1
G.2 External clock...................................................................................................G–2
H
MC68HC705B32
H.1 Features ........................................................................................................... H–3
H.2 External clock...................................................................................................H–7
H.3 RESET pin......................... ... ... ................ ... ... ................. ... .. ................. ... ... ...... H–7
H.4 EPROM ............................................................................................................ H–7
H.4.1 EPROM read oper a tion.................... ................... ..................................... ... H–8
H.4.2 EPROM pr ogram opera tion ..................... .................... ................... ............H–8
H.4.3 EPROM/EEPR OM cont rol register............................................................. H–8
H.4.4 Mask option register .................................................................................H–11
H.4.5 Options register (OPTR)......... .................... ... ................... .................... .... H–12
H.5 Bootstrap mode.............. ... .............................................................................H–13
H.5.1 Erased EPROM verification......................................................................H–16
H.5.2 EPROM/EEPR OM parallel bootstrap........................................................ H–16
H.5.3 Serial RAM loader.....................................................................................H–19
H.5.3.1 Jump to start of RAM ($0051)............................................................. H–19
H.6 Absolute maximum ratings.............................................................................H–22
H.7 DC electrical characteristics...........................................................................H–23
H.8 A/D converter characteristics ..................... ... .................... .. .................... ... ... .H–25
H.9 Control timing.................................................................................................H–27
H.10 EPROM electrical characteristics...................................................................H–29
I
HIGH SPEED OPERATION
I.1 DC electrical characteristics...............................................................................I–2
I.2 A/D converter char act eristics ..................... ... .................... .. .................... ... ........I–3
I.3 Control timing for 5V operation...........................................................................I–4
MC68HC05B6
Rev. 4.1 Freescale
ix
LIST OF FIGURES
Figure
Number Page
NumberTITLE
LIST OF FIGURES
1-1 MC68HC05B6 block diagram.............................................................................1–3
2-1 MC68HC05B6 ‘load program in RAM and execute’ schematic diagram............2–3
2-2 MC68HC05B6 ‘jump to any address’ schematic diagram..................................2–5
2-3 STOP and WAIT flowcharts................................................................................2–7
2-4 Slow mode divider block diagram.......................................................................2–9
2-5 Oscillator connections ......................................................................................2–12
3-1 Memory map of the MC68HC05B6....................................................................3–2
4-1 Standard I/O port structure.................................................................................4–2
4-2 ECLK timing diagram..........................................................................................4–3
4-3 Port logic levels...................................................................................................4–6
5-1 16-bit programmable timer block diagram ..........................................................5–2
5-2 Tim er state timing diagram for reset......... ................... .................... .................5–13
5-3 Timer state tim ing diagram f o r input capture........................ ... ................... ... ...5–13
5-4 Timer state tim ing diagram f o r output c om pare....................... .. ... ....................5–14
5-5 Timer state tim ing diagram f o r timer overflow....................... ................... ... ... ...5–14
6-1 Serial communications interface block diagram .................................................6–2
6-2 SCI rate generator division.................... .............................................................6–4
6-3 Data format.........................................................................................................6–5
6-4 SCI examples of start bit sampling technique ....................................................6–7
6-5 SCI sampling technique used on all bits.............................................................6–7
6-6 Artificial start following a framing error...............................................................6–8
6-7 SCI start bit following a break.............................................................................6–8
6-8 SCI e xample of synchronous and asynchronous tr ansmission.................. ... ... ..6–9
6-9 SCI data clock timing diagram (M=0) ........................................ .................... ...6–12
6-10 SCI dat a clock timing diagr am (M=1) ..................... ... .. ... .................... ..............6–13
7-1 PLM system block diagram.................................................................................7–1
7-2 PLM output waveform examples ........................................................................7–2
7-3 PLM clock selection................................................... .........................................7–4
8-1 A/D converter bloc k diagram .............. ... .................... .................................... .....8–2
8-2 Electrical model of an A/D input pin ...................................................................8–6
9-1 Reset timing diagram..........................................................................................9–1
9-2 Watchdog system block diagram........................................................................9–3
9-3 Interrupt flow char t..............................................................................................9–8
Freescale
xMC68HC05B6
Rev. 4.1
LIST OF FIGURES
Figure
Number Page
NumberTITLE
10-1 Programming model.........................................................................................10–1
10-2 Stacking order..................................................................................................10–1
11-1 Run IDD vs internal operating frequency (4.5V, 5.5V)......................................11–3
11-2 Run IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V).......................11–3
11-3 Wait IDD vs internal operating frequency (4.5V, 5.5V) ......................................11–3
11-4 Wait IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V).......................11–4
11-5 Increase in IDD vs frequency for A/D, SCI systems active, VDD = 5.5V...........11–4
11-6 IDD vs mode vs internal operating freque ncy, VDD = 5.5V ...............................11–4
11-7 Run IDD vs internal operating frequency (3V, 3.6V).........................................11–6
11-8 Run IDD (SM = 1) vs internal operating frequency (3V,3.6V)...........................11–6
11-9 Wait IDD vs internal operating frequency (3V, 3.6V).........................................11–6
11-10 Wait IDD (SM = 1) vs internal operating frequency (3V, 3.6V)..........................11–7
11-11 Increase in IDD vs frequency for A/D, SCI systems active, VDD = 3.6V............11–7
11-12 IDD vs mode vs internal operating frequency, VDD = 3.6V ...............................11–7
11-13 Timer relationship...........................................................................................11–12
12-1 52-pin PLCC pinout for the MC68HC05B6.......................................................12–1
12-2 64-pin QFP pinout for the MC68HC05B6.........................................................12–2
12-3 56-pin SDIP pinout for the MC68HC05B6........................................................12–3
12-4 52-pin PLCC mechanical dimensions ..............................................................12–4
12-5 64-pin QFP mechanical dimensions.................................................................12–5
12-6 56-pin SDIP mechanical dimensions................................................................12–6
A-1 MC68HC05B4 block diagram.............................................................................A–2
A-2 Memory map of the MC68HC05B4................. ... ................... ... .................... ......A–3
A-3 MC68HC05B4 self-chec k schematic diagram....................................................A–7
B-1 MC68HC05B8 block diagram.............................................................................B–2
B-2 Memory map of the MC68HC05B8................. ... ................... ... .................... ......B–3
C-1 MC68HC705B5 block diagram...........................................................................C–2
C-2 Memory map of the MC68HC705B 5.......................... ... ................... ..................C–3
C-3 Modes of operation flow chart (1 of 2)................................................................C–9
C-4 Modes of operation flow chart (2 of 2)..............................................................C–10
C-5 Timing diagram with handshake.......................................................................C–11
C-6 EPROM(RAM) parallel bootstrap schematic diagram.............. ... ... ..................C–12
C-7 EPROM (RAM) serial bootstrap schematic diagram........................................C–15
C-8 RAM parallel bootstrap schematic diagram......................................................C–16
C-9 EPROM parallel bootstrap loader timing diagram............................................C–17
C-10 RAM parallel loader timing diagram ................................................................C–18
D-1 MC68HC05B16 block diagram...........................................................................D–3
D-2 Oscillator connections........................................................................................D–4
D-3 Memory map of the MC68HC05B16......... ... ... ... ................... ... .................... .. ....D–5
E-1 MC68HC705B16 bloc k diagram........ ... .. ... .................... ... .. .................... ... ... ......E–2
E-2 Memory map of the MC68HC705B16.......... ... ... ................... .................... ... ......E–3
E-3 Modes of operation flow chart (1 of 2)..............................................................E–11
MC68HC05B6
Rev. 4.1 Freescale
xi
LIST OF FIGURES
Figure
Number Page
NumberTITLE
E-4 Modes of operation flow chart (2 of 2)..............................................................E–12
E-5 Timing diagram with handshake.......................................................................E–14
E-6 Parallel EPROM loader timing diagram............................................................E–14
E-7 EPROM Parallel bootstrap schematic diagram.................................................E–15
E-8 RAM/EPROM/EEPROM serial bootstrap schematic diagr am..........................E–17
E-9 Parallel RAM loader timing diagram.................................................................E–19
E-10 RAM parallel bootstrap schematic diagram... .................... ... ... .. .................... ...E–20
E-11 Timer relationship...... .................... ................... .................... ................... .........E–28
F-1 MC68HC705B16N block diagram.......................................................................F–2
F-2 Memory map of the MC68HC705B16N..............................................................F–3
F-3 Modes of operation flow chart (1 of 2)..............................................................F–11
F-4 Modes of operation flow chart (2 of 2)..............................................................F–12
F-5 Timing diagram with handshake.......................................................................F–14
F-6 Parallel EPROM loader timing diagram............................................................F–14
F-7 EPROM parallel bootstrap schematic diagram.................................................F–15
F-8 RAM load and execute schematic diagram ......................................................F–17
F-9 Parallel RAM loader timing diagram.................................................................F–18
F-10 Timer relationship.............. ... ... .................................... .................... .................F–26
G-1 MC68HC05B32 block diagram.............. ... ... ................... ... ... ................... ... ... ....G–2
G-2 Memory map of the MC68HC05B32 .................................................................G–3
H-1 MC68HC705B32 block diagram........................................................................ H–4
H-2 Memory map of the MC68HC705B32 ............................................................... H–5
H-3 Modes of operation flow chart (1 of 2)............................................................. H–14
H-4 Modes of operation flow chart (2 of 2)............................................................. H–15
H-5 Timing diagram with handshake...................................................................... H–17
H-6 Parallel EPROM loader timing diagr am........................................................... H–17
H-7 EPROM parallel bootstrap schematic diagram................................................ H–18
H-8 RAM load and execute schematic diagram ..................................................... H–20
H-9 Parallel RAM loader timing diagram................................................................ H–21
H-10 Timer relationship......... .................................... .................... ........................... H–29
I-1 Timer relationship.......................... ......................................................................I–5
Freescale
xii MC68HC05B6
Rev. 4.1
LIST OF FIGURES
THIS PAGE LEFT BLANK INTENTIONALLY
MC68HC05B6
Rev. 4.1 Freescale
xiii
LIST OF TABLES
Table
Number Page
NumberTITLE
LIST OF TABLES
1-1 Data sheet appendices.......................................................................................1–1
2-1 Mode of operation selection ...............................................................................2–1
3-1 EEPROM control bits description.......................................................................3–4
3-2 Register out line....... ................. ... ... .....................................................................3–8
3-3 IRQ sensitivity.....................................................................................................3–9
4-1 I/O pin stat es............. ... ................. .. ... ................. ... ... ................................. ... ... ..4–2
6-1 Method of receiver wake-up .............................................................................6–11
6-2 SCI clock on SCLK pin....................... ................................................... .. ... ......6–13
6-3 First prescaler stage.........................................................................................6–18
6-4 Second prescaler stage (transmitter) ...............................................................6–18
6-5 Second prescaler stage (receiver) ....................................................................6–19
6-6 SCI baud rat e selection.............. ... ................... ... .................... ................... ......6–20
8-1 A/D clock selection................................... ..........................................................8–4
8-2 A/D channel assignment....... .................... ................... ..................................... ..8–5
9-1 Effect of RESET, POR, ST O P and WAIT..... .. .................... .................................9–5
9-2 Interrupt priorities ...............................................................................................9–7
9-3 IRQ sensitivity.....................................................................................................9–9
10-1 MUL instruction ................................................................................................10–5
10-2 Register/ memory instructions................ ... ... ................... ... .................... .. .........10–5
10-3 Branch instructions...........................................................................................10–6
10-4 Bit manipulation instructions....... ................... ... .................... ................... ... ......10–6
10-5 Read/modify/ write instructions ......................... .................... ... .. .................... ...10–7
10-6 Control inst ructions.... ... ... .................................... .................... .........................10–7
10-7 Instruction set (1 of 2) .......................................................................................10–8
10-8 Instruction set (2 of 2) .......................................................................................10–9
10-9 M68HC05 opcode map...................................................................................10–10
11-1 Absolute maximum ratings...............................................................................11–1
11-2 DC electrical characteristics for 5V operation...................................................11–2
11-3 DC electrical characteristics for 3.3V operation................................................11–5
11-4 A/D characteristics for 5V operation.................................................................11–8
11-5 A/D characteristics for 3.3V operation..............................................................11–9
11-6 Co ntrol timing for 5V oper ation.......................................................................11–10
11-7 Co ntrol timing for 3.3V operation....................................................................11–11
Freescale
xiv MC68HC05B6
Rev. 4.1
LIST OF TABLES
Table
Number Page
NumberTITLE
13-1 MC order numbers ...........................................................................................13–1
13-2 EPROMs for pattern generation.......................................................................13–2
A-1 Mode of operation selection...............................................................................A–1
A-2 Register outline ..................................................................................................A–4
A-3 MC68HC05B4 self-check results .......................................................................A–6
B-1 Register outline ..................................................................................................B–4
C-1 Register outline ..................................................................................................C–4
C-2 Mode of operation selection...............................................................................C–8
C-3 Bootstrap vector targets in RAM ......................................................................C–14
C-4 Additional DC electrical characteristics for MC68HC705B5......................... ....C–19
C-5 Additional control timing for MC68HC705B5....................................................C–19
D-1 Mode of operation selection...............................................................................D–2
D-2 Register outline ..................................................................................................D–6
E-1 Register outline ..................................................................................................E–4
E-2 EPROM control bits description ................... ... ................... ... ... .................... .. ....E–6
E-3 EEPROM control bits description.......................................................................E–7
E-4 Mode of operation selection.............................................................................E–10
E-5 Bootstrap vector targets in RAM ......................................................................E–18
E-6 Absolute maximum ratings...............................................................................E–21
E-7 DC electrical characteristics for 5V operation ..................................................E–22
E-8 DC electrical characteristics for 3.3V operation ...............................................E–23
E-9 A/D characteristics for 5V oper ation..................... ... ... ... ................... ... .............E–24
E-10 A/D characteristics for 3.3V operation.................. ... ... ... ................... ... ... ..........E–25
E-11 Control timing for 5V operation.........................................................................E–26
E-12 Control timing for 3.3V operation......................................................................E–27
E-13 DC electrical characteri stics for 5V operation ..................................................E–28
E-14 Control timing for 5V operation.........................................................................E–28
E-15 Control timing for 3.3V operation......................................................................E–28
F-1 Register outline ..................................................................................................F–4
F-2 EPR OM cont rol bits description ................ .................... ... .. .................... ... ... ......F–7
F-3 EEPROM control bits description.......................................................................F–8
F-4 Mode of operation selection.............................................................................F–10
F-5 Bootstrap vector targets in RAM ......................................................................F–16
F-6 Absolute maximum ratings...............................................................................F–19
F-7 DC electrical character istics for 5V operation ..................................................F–20
F-8 DC electrical characteristics for 3.3V operation ............... .. ... ....................... ....F–21
F-9 A/D characteristics for 5V operation............. .................... .. .................... ... .......F–22
F-10 A/D characteristics for 3. 3V operation................ .. ... .................... ... .. ................F–23
F-11 Control timing for 5V operation .........................................................................F–24
F-12 Control timing for 3.3V operation ......................................................................F–25
F-13 DC electrical characteri stics for 5V operation ..................................................F–26
F-14 Control timing for 5V operation .........................................................................F–26
MC68HC05B6
Rev. 4.1 Freescale
xv
LIST OF TABLES
Table
Number Page
NumberTITLE
F-15 Control timing for 3.3V operation......................................................................F–26
G-1 Register outline................................................................................ ..................G–4
H-1 Register outline........................... .................................... .................... ............... H–6
H-2 EPROM control bits description......................................................................... H–9
H-3 EEPROM control bits description.................................................................... H–10
H-4 Mode of operation selection ............................................................................ H–13
H-5 Bootstrap vector targets in RAM...................................................................... H–19
H-6 Absolute Maxim u m ratings.............. ... .................... ................... ...................... H–22
H-7 DC electrical characteristics for 5V operation.................................................. H–23
H-8 DC electrical characteristics for 3.3V operation............................................... H–24
H-9 A/D characteristics for 5V operation................................................................ H–25
H-10 A/D characteristics for 3.3V operation............................................................. H–26
H-11 Control ti ming for 5V op e ration........................................................................ H–27
H-12 Control timing for operation at 3.3V................................................................. H–28
H-13 DC electrical characteristics for 5V operation.................................................. H–29
H-14 Control ti ming for 5V op e ration........................................................................ H–29
H-15 Control ti ming for 3.3V operation..................................................................... H–29
I-1 Ordering info rmation............. ... .................... ................... .....................................I–1
I-2 DC electrical characteristics for 5V operation......................................................I–2
I-3 A/D characteristics for 5V operation....................................................................I–3
Freescale
xvi MC68HC05B6
Rev. 4.1
LIST OF TABLES
THIS PAGE LEFT BLANK INTENTIONALLY
MC68HC05B6
Rev. 4.1 Freescale
1-1
INTRODUCTION
1
1
INTRODUCTION
The MC68HC05B6 microcomputer (MCU) is a member of Freescale’s MC68HC05 family of
low-cost single chip microcomputers. This 8-bit MCU contains an o n-chip oscillator, CPU, RAM,
ROM, EEPROM, A/D converter, pulse length modulated outputs, I/O, serial communications
interface, programmable timer system and watchdog. The fully static design allows operation at
frequencies down to dc to further reduce the already low power consumption to a fe w micro-amps.
This data sheet is structured such that de vices similar to the MC68HC05B6 are described in a set
of appendices (see Table 1-1).
Table 1-1 Data sheet appendices
Device Appendix Differences from MC68HC05B6
MC68HC05B4 A 4K bytes ROM; no EEPROM
MC68HC05B8 B 7.25K bytes ROM
MC68HC705B5 C 6K bytes EPROM; self-check replaced by bootstrap
firmware; no EEPROM
MC68HC05B16 D 16K bytes ROM; increased RAM and self-check ROM
MC68HC705B16 E 16K bytes EPROM; increased RAM; self-check replaced
by bootstrap firmware; modified power-on reset routine
MC68HC705B16N F 16K bytes EPROM; increased RAM; self-check replaced
by bootstrap firmware; modified power-on reset routine
MC68HC05B32 G 32K bytes ROM; no page zero ROM; increased RAM
MC68HC705B32 H 32K bytes EPROM; no page zero ROM; increased RAM;
self-check mode replaced by bootstrap firmware
Freescale
1-2 MC68HC05B6
Rev. 4.1
INTRODUCTION
11.1 Features
Hardware features
• Fully sta tic design featuring the industry standard M68HC05 family CPU core
• On chip crystal oscillator with divide by 2 or a software selectable divide b y 32 option (SLO W
mode)
• 2.1 MHz internal operating frequency at 5V; 1.0 MHz at 3V
• High speed version available
• 176 bytes of RAM
• 5936 bytes of user ROM plus 14 bytes of user vectors
• 256 bytes of byte erasable EEPROM with internal charge pump and security bit
• Write/erase protect bit for 224 of the 256 bytes EEPROM
• Self te st/bootstrap mode
• Power saving STOP, WAIT and SLOW modes
• Thr ee 8-bit parallel I/O por ts and one 8-bit inp ut-only port
• Software option available to output the internal E-clock to port pin PC2
• 16-bit timer with 2 input captures and 2 output compares
• Computer operating properly (COP) watchdog timer
• Serial communications interf ace system (SCI) with independent tr ansmitter/receiv er baud rate
selection; receiver wake-up func tion for use in multi-receiver systems
• 8 channel A/D converter
• 2 pulse length modulation systems which can be used as D/A converters
• One interrupt request input plus 4 on-board hardware interrupt sources
• Av ailable in 52-pin plastic leaded chip carrier (PLCC), 64-pin quad flat pac k (QFP) and 56-pin
shrink dual in line (SDIP) packages
• Complete de velopment system support available using the MMDS05 development station with
the M68HC05B32EM emulation module
• Extended operating temperature range of -40 to +125 °C
MC68HC05B6
Rev. 4.1 Freescale
1-3
INTRODUCTION
1
1.2 Mask options for the MC68HC05B6
The MC68HC05B6 has three mask options th at are programmed dur ing manufacture and must
be specified on the order form.
• Power-on-reset delay (tPORL) = 16 or 4064 cycles
• Automatic watchdog enable/disable following a power-on or external reset
• Watchdog enable/disable during WAIT mode
Warning: It is recommended that an e xternal clock is alwa ys used if tPORL is s et to 16 cycles. This
will prevent any problems arising with oscillator stability when the device is put into
STOP mode.
Figure 1-1 MC68HC05B6 block diagram
Port A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Port B
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Port C
PC0
PC1
PC2/ECLK
PC3
PC4
PC5
PC6
PC7
16-bit
programmable
timer
Port D
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
Oscillator
176 bytes
RAM
COP watchdog
RESET
IRQ
VDD
VSS
OSC1
OSC2
M68HC05
CPU
SCI
A/D converter
PLM
TCAP1
TCAP2
TCMP1
TCMP2
VRH
VRL
RDI
SCLK
TDO
VPP1
256 bytes
EEPROM
Charge pump
÷ 2 / ÷ 32
PLMA D/A
PLMB D/A
8-bit
432 bytes
User ROM
5950 bytes
self check ROM
(including 14 bytes
User vectors)
Freescale
1-4 MC68HC05B6
Rev. 4.1
INTRODUCTION
1
THIS PAGE LEFT BLANK INTENTIONALLY
MC68HC05B6
Rev. 4.1 Freescale
2-1
MODES OF OPERATION AND PIN DESCRIPTIONS
2
2
MODES OF OPERATION AND PIN
DESCRIPTIONS
2.1 Modes of operation
The MC68HC05B6 MCU has two modes of operation, namely single chip and self check modes.
Table 2-1 shows the conditions required to enter each mode on the rising edge of RESET.
2.1.1 Single chip mode
This is the nor mal operating mode of the MC68HC05B6. In this mode the device functions as a
self-contained microcomputer (MCU) with all on-board peripherals, including the three 8-bit I/O
ports and the 8-bit input-only port, av ailable to the user . All address and data activity occurs within
the MCU.
Table 2-1 Mode of operation selection
IRQ pin TCAP1 pin PD3 PD4 Mode
VSS to VDD VSS to VDD X X Single chip
2VDD VDD 1 0 Serial RAM loader
2VDD VDD 1 1 Jump to any address
Freescale
2-2 MC68HC05B6
Rev. 4.1
MODES OF OPERATION AND PIN DESCRIPTIONS
22.2 Serial RAM loader
The ‘load program in RAM and execute’ mode is entered if the following conditions are sati sfied
when the reset pin is released to VDD. The format used is identical to the format used for the
MC68HC805C4. The SEC bit in the options register must be inactive, i.e. set to ‘1’.
–IRQ
at 2xVDD
– TCAP1 at VDD
–PD3 at V
DD for at least 30 machine cycles after reset
–PD4 at V
SS for at least 30 machine cycles after reset
In the ‘load program in RAM and execute’ routine, user programs are loaded into MCU RAM via
the SCI port and then executed. Data is loaded sequentially, starting at RAM location $0050, until
the last byte is loaded. Program control is then transf erred to the RAM program starting at location
$0051. The first byte loaded is the count of the total number of bytes in the program plus the count
byte. The program star ts at th e second byte in RAM. Dur ing the fir mware initialization stage, the
SCI is configured for the NRZ data f ormat (idle line, start bit, eight data bits and stop bit). The baud
rate is 9600 with a 4 MHz crystal. A program to con v ert ASCII S-records to the f ormat required by
the RAM loader is available from Freescale.
If immediate execution is not desired after loading the RAM program, it is possible to hold off
e xecution. This is accomplished by setting the byte count to a v alue that is greater than the ov erall
length of the loaded data. When the last byte is loaded, the firmware will halt operation expecting
additional data to arrive. At this point, the reset switch is placed in the reset position which will reset
the MCU, but keep the RAM program intact. All routines can now be entered from this state,
including the one which will execute the program in RAM (see Section 2.3).
To load a program in the EEPROM, the ‘load prog ram in RAM and e xecute’ function is also used.
In this instance the p r ocess involves two distinct steps. Firstly, the RAM is loaded with a program
which will control the loading of the EEPROM, and when the RAM contents are ex ecuted, the MCU
is instructed to load the EEPROM.
The erased state of the EEPROM is $FF.
Figure 2-1 shows the schematic diagram of the circuit required for the ser ial RAM loader.
MC68HC05B6
Rev. 4.1 Freescale
2-3
MODES OF OPERATION AND PIN DESCRIPTIONS
2
Figure 2-1 MC68HC05B6 ‘load program in RAM and execute’ schematic diagram
32
OSC1
OSC2
IRQ
TCAP2
TCMP2
TCAP1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET
VDD
18
24
25
26
27
28
29
30
31
16
17
19
41
10 kΩ
0.01 µF
10 nF 47 µF
10 MΩ
4 MHz
22 pF 22 pF
P1 GND
+5V
2xVDD
RESET 10
VRH
VRL
VPP1
PLMA
PLMB
TCMP1
RDI
TDO
NC
NC
RS232 level translator
suggested:
MC145406 or MAX232
9600 Bd
RS232
SCLK
10 kΩ
11
9
22
8
7
40
20
21
51
1
23
2
3
4
5
12
13
14
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
6
15
50
52
Connect as required
for the application
Connect as required
for the application
MC68HC05B6 (52-pin package)
Freescale
2-4 MC68HC05B6
Rev. 4.1
MODES OF OPERATION AND PIN DESCRIPTIONS
22.3 ‘Ju mp to any address’
The ‘jump to any address’ mode is entered when the reset pin is released to VDD, if th e following
conditions are satisfied:
–IRQ
at 2xVDD
– TCAP1 at VDD
–PD3 at V
DD for at least 30 machine cycles after reset
–PD4 at V
DD for at least 30 machine cycles after reset
This function allows execution of programs previously loaded in RAM or EEPROM using the
methods outlined in Section 2.2.
To execute the ‘jump to any address’ function, data input at port A has to be $CC and data input at
port B and port C should represent the MSB and LSB respectively, of the address to jump to for
e x ecution of the user prog ram. A sch ematic d iagr am of the circuit required i s shown in Figure 2-2.
MC68HC05B6
Rev. 4.1 Freescale
2-5
MODES OF OPERATION AND PIN DESCRIPTIONS
2
Figure 2-2 MC68HC05B6 ‘jump to any address’ schematic diagram
32
OSC1
OSC2
IRQ
TCAP2
TCMP2
TCAP1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET
VDD
18
24
25
26
27
28
29
30
31
16
17
19
41
10 kΩ
0.01 µF
10 nF 47 µF
10 MΩ
4 MHz
22 pF 22 pF
P1 GND
+5V
2xVDD
RESET 10
VRH
VRL
VPP1
PLMA
PLMB
TCMP1
RDI
TDO
NC
NC
SCLK
10 kΩ
11
9
22
8
7
40
20
21
51
1
23
2
3
4
5
12
13
14
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
6
15
50
52 Connect as required
for the application
8 x 10 kΩopti onal (see note)
8 x 10 kΩ
8 x 10 kΩ
MSBLSB
Select required address
Note: These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7
are kept in input mode during application.
MC68HC05B6 (52-pin package)
