July 2008 Rev 1 1/17
17
L6386AD
High-voltage high and low side driver
Features
■High voltage rail up to 600 V
■dV/dt immunity ±50 V/nsec in full temperature
range
■Driver current capability:
– 400 mA source,
– 650 mA sink
■Switching times 50/30 nsec rise/fall with 1nF
load
■CMOS/TTL Schmitt trigger inputs with
hysteresis and pull down
■Under voltage lock out on lower and upper
driving section
■Integrated bootstrap diode
■Outputs in phase with inputs
Description
The L6386AD is an high-voltage device,
manufactured with the BCD "OFF-LINE"
technology. It has a driver structure that enables
to drive independent referenced Channel Power
MOS or IGBT. The high-side (floating) section is
enabled to work with voltage rail up to 600 V. The
Logic Inputs are CMOS/TTL compatible for ease
of interfacing with controlling devices.
SO-14
www.st.com
Figure 1. Block diagram
LOGIC
UV
DETECTION
LEVEL
SHIFTER
UV
DETECTION R
R
S
V
CC
LVG
DRIVER
V
CC
HIN
SD
HVG
DRIVER HVG
H.V.
TO LOAD
OUT
LVG
PGND
D97IN520D
LIN DIAG
VREF
+
-
BOOTSTRAP DRIVER Vboot
CIN
C
BOOT
SGND
5
7 6
8
9
12
13
14
1
2
3
4
Contents L6386AD
2/17
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
L6386AD Electrical data
3/17
1 Electrical data
1.1 Absolute maximum ratings
Note: ESD immunity for pins 12, 13 and 14 is guaranteed up to 900V (Human Body Model)
1.2 Thermal data
1.3 Recommended operating conditions
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
V
out
Output voltage -3 to Vboot - 18 V
V
cc
Supply voltage - 0.3 to +18 V
V
boot
Floating supply voltage -1 to 618 V
V
hvg
High-side gate output voltage - 1 to Vboot V
V
lvg
Low-side gate output voltage -0.3 to Vcc +0.3 V
V
i
Logic input voltage -0.3 to Vcc +0.3 V
V
diag
Open drain forced voltage -0.3 to Vcc +0.3 V
V
cin
Comparator input voltage -0.3 to 10 V V
dV
out
/dt Allowed output slew rate 50 V/ns
P
tot
Total power dissipation (TJ = 85 °C) 750 mW
T
j
Junction temperature 150 °C
T
stg
Storage temperature -50 to 150 °C
Table 2. Thermal data
Symbol Parameter SO-14 Unit
R
th(JA)
Thermal Resistance Junction to ambient 165 °C/W
Table 3. Recommended operating conditions
Symbol Pin Parameter Test condition Min Typ Max Unit
V
out
12 Output voltage (1)
1. If the condition Vboot - Vout < 18 V is guaranteed, Vout can range from -3 to 580 V
580 V
V
BS
(2)
2. VBS = Vboot - Vout
14 Floating supply voltage (1) 17 V
f
sw
Switching frequency HVG,LVG load C
L
= 1 nF 400 kHz
V
cc
4 Supply voltage 17 V
T
J
Junction temperature -45 125 °C
Pin connection L6386AD
4/17
2 Pin connection
Figure 2. Pin connection (Top view)
Table 4. Pin description
N° Pin Type Function
1 LIN I Low-side driver logic input
2 SD(1)
1. The circuit guarantees 0.3V maximum on the pin (@ Isink = 10 mA), with VCC >3V. This allows to omit the
"bleeder" resistor connected between the gate and the source of the external MOSFET normally used to
hold the pin low; the gate driver assures low impedance also in SD condition.
I Shut down logic input
3 HIN I High-side driver logic input
4 VCC Low voltage supply
5 DIAG O Open drain diagnostic output
6 CIN I Comparator input
7 SGND Ground
8 PGND Power ground
9 LVG
(1) O Low-side driver output
10, 11 N.C. Not connected
12 OUT O High-side driver floating driver
13 HVG
(1) O High-side driver output
14 Vboot Bootstrapped supply voltage
LIN
SD
HIN
VCC
DIAG
SGND
CIN
1
3
2
4
5
6
7 PGND
N.C.
LVG
N.C.
OUT
HVG
Vboot
14
13
12
11
10
8
9
D97IN521A
L6386AD Electrical characteristics
5/17
3 Electrical characteristics
3.1 AC operation
3.2 DC operation
Table 5. AC operation electrical characteristcs (V
CC
= 15 V; T
J
= 25 °C)
Symbol Pin Parameter Test condition Min Typ Max Unit
t
on
1,3 vs
9,13
High/low-side driver turn-on
propagation delay
V
out
= 0 V
110 150 ns
t
off
High/low-side driver turn-off
propagation delay 110 150 ns
t
sd
2 vs
9,13
Shut down to high/low side
propagation delay 105 150
t
r
9, 13 Rise time C
L
= 1000 pF 50 ns
t
f
Fall time C
L
= 1000 pF 30 ns
Table 6. DC operation electrical characteristcs (V
CC
= 15 V; T
J
= 25 °C)
Symbol Pin Parameter Test condition Min Typ Max Unit
Low supply voltage section
V
ccth1
4
Vcc UV turn on threshold 9.1 9.6 10.1 V
V
ccth2
Vcc UV turn off threshold 7.9 8.3 8.8 V
V
cchys
Vcc UV hysteresis 1.3 V
I
qccu
Undervoltage quiescent
supply current V
cc
≤ 9 V 200 µA
I
qcc
Quiescent current V
cc
= 15 V 250 320 µA
Bootstrapped supply section
Vbth1
14
Vboot UV turn on threshold 8.5 9.5 10.5 V
Vbth2 V
boot UV turn off threshold 7.2 8.2 9.2 V
Vbhys V
boot UV hysteresis 1.3 V
I
qboot
Vboot quiescent current HVG ON 200 µA
Ilk High voltage leakage current Vhvg = Vout = Vboot
= 600 V 10 µA
R
DS(on)
Bootstrap driver on
resistance (1) V
cc
≥ 12.5 V;
Vin = 0 V 125 Ω
Electrical characteristics L6386AD
6/17
Symbol Pin Parameter Test condition Min Typ Max Unit
Driving buffers section
I
so
9,
13
High/low side source short
circuit current V
IN
= V
ih
(t
p
< 10 µs) 300 400 mA
I
si
9,
13
High/low side sink short
circuit current V
IN
= V
il
(tp < 10 µs) 500 650 mA
Logic inputs
V
il
1,2,
3
Low level logic voltage 1.5 V
V
ih
High level logic voltage
3.6 V
I
ih
High level logic input current V
IN
= 15 V 50 70 µA
I
il
Low level logic input current V
IN
= 0 V 1 µA
Sense comparator
V
io
Input offset voltage -10 10 mV
I
io
6 Input bias current Vcin ≥ 0.5 0.2 µA
V
ol
2Open drain low level output
voltage Iod = -2.5 mA 0.8 V
V
ref
Comparator reference
voltage 0.46 0.50 0.54 V
1. RDS(on) is tested in the following way:
where I
1
is pin 14 current when V
CBOOT
= V
CBOOT1
, I
2
when V
CBOOT
= V
CBOOT2
Table 6. DC operation electrical characteristcs (continued)(V
CC
= 15 V; T
J
= 25 °C)
RDSON
VCC VCBOOT1
–()VCC VCBOOT2
–()–
I1VCC,VCBOOT1
()I2VCC,VCBOOT2
()–
-------------------------------------------------------------------------------------------------------=
L6386AD Electrical characteristics
7/17
3.3 Timing diagram
Figure 3. Input/output timing diagram
HIN
LIN
SD
HOUT
LOUT
V
REF
V
CIN
DIAG
Note: SD active condition is latched until next negative IN edge.
D97IN522A
Bootstrap driver L6386AD
8/17
4 Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 4 a). In the L6386AD a patented
integrated structure replaces the external diode. It is realized by a high voltage DMOS,
driven synchronously with the low side driver (LVG), with in series a diode, as shown in
Figure 4 b. An internal charge pump (Figure 4 b) provides the DMOS driving voltage. The
diode connected in series to the DMOS has been added to avoid undesirable turn on of it.
4.1 CBOOT selection and charging
To choose the proper C
BOOT
value the external MOS can be seen as an equivalent
capacitor. This capacitor C
EXT
is related to the MOS total gate charge:
The ratio between the capacitors C
EXT
and C
BOOT
is proportional to the cyclical voltage loss.
It has to be:
C
BOOT
>>>C
EXT
e.g.: if Q
gate
is 30 nC and V
gate
is 10 V, C
EXT
is 3 nF. With C
BOOT
= 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the C
BOOT
selection has to take into account also
the leakage losses.
e.g.: HVG steady state consumption is lower than 200 µA, so if HVG T
ON
is 5ms, C
BOOT
has
to supply 1 µC to C
EXT
. This charge on a 1 µF capacitor means a voltage drop of 1 V.
The internal bootstrap driver gives great advantages: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if V
OUT
is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (T
charge
) of the C
BOOT
is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS R
DS(on)
(typical value:
125 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
where Q
gate
is the gate charge of the external power MOS, R
dson
is the on resistance of the
bootstrap DMOS, and T
charge
is the charging time of the bootstrap capacitor.
CEXT
Qgate
Vgate
---------------=
Vdrop Ich earg Rdson Vdrop
→Qgate
Tch earg
------------------- Rdson
==
L6386AD Bootstrap driver
9/17
For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the T
charge
is 5 µs. In fact:
V
drop
has to be taken into account when the voltage drop on C
BOOT
is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 4. Bootstrap driver
Vdrop
30nC
5µs
---------------125Ω0.8V∼⋅=
TO LOAD
D99IN1056
H.V.
HVG
ab
LVG
HVG
LVG
C
BOOT
TO LOAD
H.V.
C
BOOT
D
BOOT
V
BOOT
V
S
V
S
V
OUT
V
BOOT
V
OUT
Typical characteristic L6386AD
10/17
5 Typical characteristic
Figure 5. Typical rise and fall times vs
load capacitance
Figure 6. Quiescent current vs supply
voltage
Figure 7. Turn on time vs temperature Figure 8. V
BOOT
UV turn on threshold
vs temperature
Figure 9. Turn Off time vs temperature Figure 10. V
BOOT
UV turn off threshold
vs temperature
For both high and low side buffers @25˚C Tamb
0 1 2 3 4 5 C (nF)
0
50
100
150
200
250
time
(nsec)
Tr
D99IN1054
Tf
0246810121416V
S
(V)
10
10
2
10
3
10
4
Iq
(µA)
D99IN1057
-45 -25 0 25 50 75 100 125
0
50
100
150
200
250
Ton (ns)
Tj (°C)
Typ.
@ Vcc = 15V
-45 -25 0 25 50 75 100 125
7
8
9
10
11
12
13
14
15
Vbth1 (V)
Tj (°C)
Typ.
@ Vcc = 15V
-45 -25 0 25 50 75 100 125
0
50
100
150
200
250
Toff (ns)
Tj (°C)
Typ.
@ Vcc = 15V
-45 -25 0 25 50 75 100 125
7
8
9
10
11
12
13
14
15
Vbth2 (V)
Tj (°C)
Typ.
@ Vcc = 15V
L6386AD Typical characteristic
11/17
Figure 11. Shutdown time vs
temperature
Figure 12. VBOOT UV hysteresis
Figure 13. VCC UV turn on threshold vs
temperature
Figure 14. Output source current vs
temperature
Figure 15. VCC UV turn off threshold vs
temperature
Figure 16. Output sink current vs
temperature
-45 -25 0 25 50 75 100 125
0
50
100
150
200
250
tsd (ns0
Tj (°C)
Typ.
@ Vcc = 15V
-45 -25 0 25 50 75 100 125
1
1.5
2
2.5
3
Vbhys (V)
Tj (°C)
Typ.
@ Vcc = 15V
-45 -25 0 25 50 75 100 125
9
10
11
12
13
14
15
Vccth1(V)
Tj (°C)
Typ.
-45 -25 0 25 50 75 100 125
0
200
400
600
800
1000
current (mA)
Tj (°C)
Typ.
@ Vcc = 15V
-45 -25 0 25 50 75 100 125
7
8
9
10
11
12
Vccth2(V)
Tj (°C)
Typ.
-45 -25 0 25 50 75 100 125
0
200
400
600
800
1000
current (mA)
Tj (°C)
Typ.
@ Vcc = 15V
Typical characteristic L6386AD
12/17
Figure 17. VCC UV hysteresis vs
temperature
-45 -25 0 25 50 75 100 125
1
1.5
2
2.5
3
Vcchys (V)
Tj (°C)
Typ.
L6386AD Package mechanical data
13/17
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Package mechanical data L6386AD
14/17
Figure 18. SO-14 mechanical data and package dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.35 1.75 0.053 0.069
A1 0.10 0.30 0.004 0.012
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.01
D
(1) 8.55 8.75 0.337 0.344
E 3.80 4.0 0.150 0.157
e 1.27 0.050
H 5.8 6.20 0.228 0.244
h 0.25 0.50 0.01 0.02
L 0.40 1.27 0.016 0.050
k 0° (min.), 8° (max.)
ddd 0.10 0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO-14
0016019 D
L6386AD Order codes
15/17
7 Order codes
Table 7. Order codes
Order codes Package Packaging
L6386AD SO-14 Tube
L6386AD013TR SO-14 Tape and reel
Revision history L6386AD
16/17
8 Revision history
Table 8. Document revision history
Date Revision Changes
14-Jul-2008 1 First release
L6386AD
17/17
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