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DESCRIPTION
The DS1315 Phantom Time Chip is a
combination of a CMOS timekeeper and a
nonvolatile memory controller. In the absence of
power, an external battery maintains the
timekeeping operation and provides power for a
CMOS static RAM. The watch keeps track of
hundredths of seconds, seconds, minutes, hours,
day, date, month, and year information. The last
day of the month is automatically adjusted for
months with fewer than 31 days, including leap
year correction. The watch operates in one of two
formats: a 12-hour mode with an AM/PM
indicator or a 24-hour mode. The nonvolatile
controller supplies all the necessary support
circuitry to convert a CMOS RAM to a
nonvolatile memory. The DS1315 can be
interfaced with either RAM or ROM without
leaving gaps in memory.
PIN CONFIGURATIONS
Pin Configurations continued at end of data sheet.
FEATURES
Real-Time Clock Keeps Track of Hundredths
of Seconds, Seconds, Minutes, Hours, Days,
Date of the Month, Months, and Years
Automatic Leap Year Correction Valid Up to
2100
No Address Space Required to Communicate
with RTC
Provides Nonvolatile Controller Functions for
Battery Backup of SRAM
Supports Redundant Battery Attachment for
High-Reliability Applications
Full ±10% VCC Operating Range
+3.3V or +5V Operation
Industrial (-40°C to +85°C) Operating
Temperature Ranges Available
PIN DESCRIPTION
X1, X2 - 32.768kHz Crystal Connection
WE
- Write Enable
BAT1 - Battery 1 Input
GND - Ground
D - Data Input
Q - Data Output
ROM/
RAM
- ROM/RAM Mode Select
CEO
- Chip Enable Output
CEI
- Chip Enable Input
OE
- Output Enable
RST
- Reset
BAT2 - Battery 2 Input
VCC0 - Switched Supply Output
VCC1 - Power Supply Input
19-6080; Rev 11/11
www.dalsemi.com
PDIP (300 mils)
16
15
14
12
11
10
9
VCC1
VCC0
BAT2
RST
OE
CEI
CEO
ROM/RAM
X1
X2
WE
BAT1
GND
D
Q
GND
DS1315
DS1315
Phant
om Time Chip
DS1315 Phantom Time Chip
2 of 21
ORDERING INFORMATION
PART TEMP RANGE
VOLTAGE
(V)
PIN-PACKAGE TOP MARK*
DS1315-33+ 0°C to +70°C 3.3 16 PDIP (300 mils) DS1315 336
DS1315N-33+ -40°C to +85°C 3.3 16 PDIP (300 mils) DS1315 336
DS1315-5+ 0°C to +70°C 5 16 PDIP (300 mils) DS1315 56
DS1315N-5+ -40°C to +85°C 5 16 PDIP (300 mils) DS1315 56
DS1315E-33+ 0°C to +70°C 3.3 20 TSSOP (4.4mm) DS1315E XXXX-336
DS1315EN-33+ -40°C to +85°C 3.3 20 TSSOP (4.4mm) DS1315E XXXX-336
DS1315EN-33+T&R -40°C to +85°C 3.3 20 TSSOP (4.4mm) DS1315E XXXX-336
DS1315E-5+ 0°C to +70°C 5 20 TSSOP (4.4mm) DS1315E XXXX-56
DS1315EN-5+ -40°C to +85°C 5 20 TSSOP (4.4mm) DS1315E XXXX-56
DS1315EN-5+T&R -40°C to +85°C 5 20 TSSOP (4.4mm) DS1315E XXXX-56
DS1315S-33+ 0°C to +70°C 3.3 16 SO (300 mils) DS1315 336
DS1315SN-33+ -40°C to +85°C 3.3 16 SO (300 mils) DS1315 336
DS1315S-5+ 0°C to +70°C 5 16 SO (300 mils) DS1315 56
DS1315SN-5+ -40°C to +85°C 5 16 SO (300 mils) DS1315S 56
DS1315S-5+T&R 0°C to +70°C 5 16 SO (300 mils) DS1315S 56
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*A “+” symbol located anywhere on the top mark indicates a lead-free device. An “N” located in the bottom right-hand corner of the top of the
package denotes an industrial device. “xxxx” can be any combination of characters.
DS1315 Phantom Time Chip
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Figure 1. Block Diagram
DS1315 Phantom Time Chip
4 of 21
Operation
Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits
which must be matched by executing 64 consecutive write cycles containing the proper data on data in
(D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the
chip enable output pin (
CEO
).
After recognition is established, the next 64 read or write cycles either extract or update data in the Time
Chip and
CEO
remains high during this time, disabling the connected memory.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable input (
CEI
), output enable (
OE
), and write enable (
WE
). Initially, a read cycle using the
CEI
and
OE
control of the Time Chip starts the pattern recognition sequence by moving pointer to the
first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the
CEI
and
WE
control of the Time Chip. These 64 write cycles are used only to gain access to the Time Chip.
When the first write cycle is executed, it is compared to bit 1 of the 64-bit comparison register. If a match
is found, the pointer increments to the next location of the comparison register and awaits the next write
cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If
a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the
comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as
described above until all the bits in the comparison register have been matched. (This bit pattern is shown
in Figure 2). With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the
timekeeping registers may proceed. The next 64 cycles will cause the Time Chip to either receive data on
D, or transmit data on Q, depending on the level of
OE
pin or the
WE
pin. Cycles to other locations
outside the memory block can be interleaved with
CEI
cycles without interrupting the pattern recognition
sequence or data transfer sequence to the Time Chip.
A standard 32.768kHz quartz crystal can be directly connected to the DS1315 via pins 1 and 2 (X1, X2).
The crystal selected for use should have a specified load capacitance (CL) of 6 pF. For more information
on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal
Considerations with Maxim Real-Time Clocks (RTCs).
DS1315 Phantom Time Chip
5 of 21
Figure 2. Time Chip Comparison Register Definition
Note: The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being
accidentally duplicated and causing inadvertent entry to the Phantom Time Chip are less than 1 in 1019.
DS1315 Phantom Time Chip
6 of 21
Nonvolatile Controller Operation
The operation of the nonvolatile controller circuits within the Time Chip is determined by the level of the
ROM/
RAM
select pin. When ROM/
RAM
is connected to ground, the controller is set in the RAM mode
and performs the circuit functions required to make CMOS RAM and the timekeeping function
nonvolatile. A switch is provided to direct power from the battery inputs or VCCI to VCCO with a
maximum voltage drop of 0.3 volts. The VCCO output pin is used to supply uninterrupted power to CMOS
SRAM. The DS1315 also performs redundant battery control for high reliability. On power-fail, the
battery with the highest voltage is automatically switched to VCCO. If only one battery is used in the
system, the unused battery input should be connected to ground.
The DS1315 safeguards the Time Chip and RAM data by power-fail detection and write protection.
Power-fail detection occurs when VCCI falls below VPF which is set by an internal bandgap reference. The
DS1315 constantly monitors the VCCI supply pin. When VCCI is less than VPF, power-fail circuitry forces
the chip enable output (
CEO
) to VCCI or VBAT-0.2 volts for external RAM write protection. During
nominal supply conditions,
CEO
will track
CEI
with a propagation delay. Internally, the DS1315 aborts
any data transfer in progress without changing any of the Time Chip registers and prevents future access
until VCCI exceeds VPF. A typical RAM/Time Chip interface is illustrated in Figure 3.
When the ROM/
RAM
pin is connected to VCCO, the controller is set in the ROM mode. Since ROM is a
read-only device that retains data in the absence of power, battery backup and write protection is not
required. As a result, the chip enable logic will force
CEO
low when power fails. However, the Time
Chip does retain the same internal nonvolatility and write protection as described in the RAM mode. A
typical ROM/Time Chip interface is illustrated in Figure 4.
Figure 3. DS1315-to-RAM/Time Chip Interface
DS1315 Phantom Time Chip
7 of 21
Figure 4. ROM/Time Chip Interface
Time Chip Register Information
Time Chip information is contained in eight registers of 8 bits, each of which is sequentially accessed 1
bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the Time
Chip registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a
register could produce erroneous results. These read/write registers are defined in Figure 5.
Data contained in the Time Chip registers is in binary coded decimal format (BCD). Reading and writing
the registers is always accomplished by stepping though all eight registers, starting with bit 0 of register 0
and ending with bit 7 of register 7.
AM/PM/12/24-Mode
Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode
is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode,
bit 5 is the 20-hour bit (20-23 hours).
Oscillator and Reset Bits
Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the
reset pin input. When the reset bit is set to logic 1, the reset input pin is ignored. When the reset bit is set
to logic 0, a low input on the reset pin will cause the Time Chip to abort data transfer without changing
data in the timekeeping registers. Reset operates independently of all other in-puts. Bit 5 controls the
oscillator. When set to logic 0, the oscillator turns on and the real time clock/calendar begins to
increment.
DS1315 Phantom Time Chip
8 of 21
Zero Bits
Registers 1, 2, 3, 4, 5, and 6 contain 1 or more bits that will always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.
Figure 5. Time Chip Register Definition
DS1315 Phantom Time Chip
9 of 21
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature Range, Commercial 0°C to +70°C
Operating Temperature Range, Industrial -40°C to +85°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature (reflow) +260°C
Lead Temperature (soldering, 10s) +260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Power-Supply Voltage
Operation
5V
VCC
4.5
5.0
5.5
V 1
3.3V
3.0
3.3
3.6
Input Logic 1
VIH
2.2
VCC + 0.3
V
1
Input Logic 0
VIL
-0.3
+0.6
V
1
Battery Voltage V
BAT1
or
VBAT2
V
BAT1,
VBAT2
2.5 3.7 V
DC OPERATING ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ±10%, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Average V
CC
Power-Supply
Current
ICC1 6 mA 6
V
CC
Power-Supply Current,
(VCC0 = VCCI - 0.3)
ICC01 150 mA 7
TTL Standby Current
(
CEI
= VIH)
ICC2 4 mA 6
CMOS Standby Current
(
CEI
= VCCI - 0.2)
ICC3 1.3 mA 6
Input Leakage Current
(any input)
IIL -1 +1 µA 10
Output Leakage Current
(any input)
IOL -1 +1 µA
Output Logic 1 Voltage
(IOUT = -1.0 mA)
VOH 2.4 V 2
Output Logic 0 Voltage
(IOUT = 4.0 mA)
VOL 0.4 V 2
Power-Fail Trip Point
VPF
4.25
4.5
V
Battery Switch Voltage VSW
V
BAT1
,
VBAT2
13
DS1315 Phantom Time Chip
10 of 21
DC POWER-DOWN ELECTRICAL CHARACTERISTICS
(VCC < 4.5V, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CEO
Output Voltage VCEO
V
CCI
- 0.2
or
VBAT1,2 -
0.2
V 8
V
BAT1
or V
BAT2
Battery
Current
IBAT 0.5 µA 6
Battery Backup Current
@ VCCO = VBAT-0.2V
ICCO2 10 µA 9
AC ELECTRICAL OPERATING CHARACTERISTICS—ROM/
RAM
= GND
(VCC = 5.0V ±10%, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Read Cycle Time
tRC
65
ns
CEI
Access Time
tCO
55
ns
OE
Access Time
tOE
55
ns
CEI
to Output Low-Z
tCOE
5
ns
OE
to Output Low-Z
tOEE
5
ns
CEI
to Output High-Z
tOD
25
ns
OE
to Output High-Z
tODO
25
ns
Read Recovery
tRR
10
ns
Write Cycle
tWC
65
ns
Write Pulse Width
tWP
55
ns
Write Recovery
tWR
10
ns
4
Data Setup
tDS
30
ns
5
Data Hold Time
tDH
0
ns
5
CEI
Pulse Width
tCW
55
ns
OE
Pulse Width
tOW
55
ns
RST
Pulse Width
tRST
65
ns
AC ELECTRICAL OPERATING CHARACTERISTICS—ROM/
RAM
= VCCO
(VCC = 5.0V ±10%, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Read Cycle Time
tRC
65
ns
CEI
Access Time
tCO
55
ns
OE
Access Time
t
OE
55
ns
CEI
to Output Low Z
tCOE
5
ns
OE
to Output Low Z
tOEE
5
ns
CEI
to Output High Z
tOD
25
ns
OE
to Output High Z
tODO
25
ns
Address Setup Time
tAS
5
ns
Address Hold Time
tAH
5
ns
Read Recovery
tRR
10
ns
DS1315 Phantom Time Chip
11 of 21
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Write Cycle
tWC
65
ns
CEI
Pulse Width
tCW
55
ns
OE
Pulse Width
tOW
55
ns
Write Recovery
tWR
10
ns
4
Data Setup
tDS
30
ns
5
Data Hold Time
tDH
0
ns
5
RST
Pulse Width
tRST
65
ns
DC OPERATING ELECTRICAL CHARACTERISTICS
(VCC = 3.3V ±10%, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Average V
CC
Power-Supply
Current
ICC1 3 mA 6
Average V
CC
Power-Supply
Current,
(VCCO = VCCI - 0.3)
ICC01 100 mA 7
TTL Standby Current
(
CEI
= VIH)
ICC2 2 mA 6
CMOS Standby Current
(
CEI
= VCCI - 0.2)
ICC3 1.1 mA 6
Input Leakage Current
(any input)
IIL -1 +1 µA
Output Leakage Current
(any input)
ILO -1 +1 µA
Output Logic 1 Voltage
(IOUT = 0.4 mA)
VOH 2.4 V 2
Output Logic 0 Voltage
(IOUT = 1.6 mA)
VOL 0.4 V 2
Power-Fail Trip Point
VPF
2.8
2.97
V
Battery Switch Voltage VSW
V
BAT1
,
VBAT2,
or VPF
14
DC POWER-DOWN ELECTRICAL CHARACTERISTICS
(VCC < 2.97V, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CEO
Output Voltage VCEO
V
CCI
or
VBAT1,2
- 0.2
V 8
VBAT1 OR VBAT2 Battery Current IBAT 0.5 µA 6
Battery Backup Current
at VCCO = VBAT - 0.2
ICCO2 10 µA 9
DS1315 Phantom Time Chip
12 of 21
AC ELECTRICAL OPERATING CHARACTERISTICS—ROM/
RAM
= GND
(VCC = 3.3V ±10%, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Read Cycle Time
tRC
120
ns
CEI
Access Time
tCO
100
ns
OE
Access Time
tOE
100
ns
CEI
to Output Low-Z
tCOE
5
ns
OE
to Output Low-Z
tOEE
5
ns
CEI
to Output High-Z
tOD
40
ns
OE
to Output High-Z
tODO
40
ns
Read Recovery
tRR
20
ns
Write Cycle
tWC
120
ns
Write Pulse Width
tWP
100
ns
Write Recovery
tWR
20
ns
4
Data Setup
tDS
45
ns
5
Data Hold Time
tDH
0
ns
5
CEI
Pulse Width
t
CW
100
ns
OE
Pulse Width
tOW
100
ns
RST
Pulse Width
t
RST
120
ns
DS1315 Phantom Time Chip
13 of 21
AC ELECTRICAL OPERATING CHARACTERISTICS—ROM/
RAM
= VCCO
(VCC = 3.3V ±10%, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Read Cycle Time
tRC
120
ns
CEI
Access Time
tCO
100
ns
OE
Access Time
tOE
100
ns
CEI
to Output Low-Z
tCOE
5
ns
OE
to Output Low-Z
tOEE
5
ns
CEI
to Output High-Z
tOD
40
ns
OE
to Output High-Z
tODO
40
ns
Address Setup Time
tAS
10
ns
Address Hold Time
tAH
10
ns
Read Recovery
tRR
20
ns
Write Cycle
tWC
120
ns
CEI
Pulse Width
tCW
100
ns
OE
Pulse Width
tOW
100
ns
Write Recovery
tWR
20
ns
4
Data Setup
tDS
45
ns
5
Data Hold Time
tDH
0
ns
5
RST
Pulse Width
tRST
120
ns
CAPACITANCE
(TA = +25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
10
pF
Output Capacitance
COUT
10
pF
DS1315 Phantom Time Chip
14 of 21
Figure 6. Timing Diagram: Read Cycle to Time Chip ROM/
RAM
= GND
Figure 7. Timing Diagram: Write Cycle to Time Chip ROM/
RAM
= GND
DS1315 Phantom Time Chip
15 of 21
Figure 8. Timing Diagram: Read Cycle to Time Chip ROM/
RAM
= VCCO
Figure 9. Timing Diagram: Write Cycle to Time Chip ROM/
RAM
= VCCO
DS1315 Phantom Time Chip
16 of 21
Figure 10. Timing Diagram: Reset Pulse
5V DEVICE POWER-UP/POWER-DOWN CHARACTERISTICS—
ROM/
RAM
= VCCO OR GND
(TA = 0°C to +70°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Recovery Time at Power-Up
tREC
1.5
2.5
ms
11
V
CC
Slew Rate
Power-Down
VPF(max) to VPF(min)
tF 300 µs 11
V
CC
Slew Rate
Power-Down
VPF(min) to VSW
tFB 10 µs 11
V
CC
Slew Rate
Power-Up
VPF(min) to VPF(max)
tR 0 µs 11
CEI
High to Power-Fail
tPF
0
µs
11
CEI
Propagation Delay
tPD
5
ns
2, 3, 11
Figure 11. 5V Power-Up Condition
RST
tRST
DS1315 Phantom Time Chip
17 of 21
Figure 12. 5V Power-Down Condition
3.3V DEVICE POWER-UP POWER-DOWN CHARACTERISTICS—
ROM/
RAM
= VCCO OR GND
(TA = 0°C to +70°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Recovery Time at Power-Up
tREC
1.5
2.5
ms
12
V
CC
Slew Rate
Power-Down
VPF(max) to VPF(min)
tF 300 µs 12
V
CC
Slew Rate
Power-Up
VPF(min) to VPF(max)
tR 0 µs 12
CEI
High to Power-Fail
tPF
0
µs
12
CEI
Propagation Delay
tPD
10
ns
2, 3, 11
DS1315 Phantom Time Chip
18 of 21
NOTES:
1) All voltages are referenced to ground.
2) Measured with load shown in Figure 15.
3) Input pulse rise and fall times equal 10ns.
4) tWR is a function of the latter occurring edge of
WE
or
CE
in RAM mode, or
OE
or
CE
in ROM
mode.
5) tDH and tDS are functions of the first occurring edge of
WE
or
CE
in RAM mode, or
OE
or
CE
in
ROM mode.
6) Measured without RAM connected.
7) ICCO1 is the maximum average load current the DS1315 can supply to external memory.
8) Applies to
CEO
with the ROM/
RAM
pin grounded. When the ROM/
RAM
pin is connected to VCCO,
CEO
will go to a low level as VCCI falls below VBAT.
9) ICCO2 is the maximum average load current that the DS1315 can supply to memory in the battery
backup mode.
10) Applies to all input pins except
RST
.
RST
is pulled internally to VCCI.
11) See Figures 11 and 12.
12) See Figures 13 and 14.
13) VSW is determined by the larger of VBAT1 and VBAT2.
14) VSW is determined by the smaller of VBAT1, VBAT2, and VPF.
Figure 13. 3.3V Power-Up Condition
DS1315 Phantom Time Chip
19 of 21
Figure 14. 3.3V Power-Down Condition
Figure 15. Output Load
DS1315 Phantom Time Chip
20 of 21
PIN CONFIGURATIONS (continued)
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
16 PDIP
P16+1
21-0043
—
16 TSSOP U20+1 21-0066 90-0116
16 SO W16+2 21-0042 90-0107
20-Pin TSSOP
X1
X2
WE
NC
BAT1
GND
NC
D
Q
GND
9
1
2
3
5
7
8
10
20
19
18
17
16
15
14
13
12
11
VCC1
V
CC0
BAT2
NC
RST
OE
NC
CEI
CEO
ROM/RAM
16-Pin SO (300 mil)
1
2
3
4
5
6
7
8
VCC1
VCC0
BAT2
RST
OE
CEI
CEO
ROM/RAM
X1
X2
WE
BAT1
GND
D
Q
GND
DS1315 Phantom Time Chip
21 of 21
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
11/11
Updated the Features, Ordering Information, AM/PM/12/24-MODE,
Absolute Maximum Ratings, and Package Information sections
1, 2, 7, 9, 20