LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
1
Document Feedback
TYPICAL APPLICATION
FEATURES DESCRIPTION
TimerBlox: Long Timer, Low
Frequency Oscillator
The LTC
®
6995 is a silicon oscillator with a programmable
period range of 1.024ms to 9.54 hours (29.1µHz to 977Hz),
specifically intended for long duration timing events. The
LTC6995 is part of the TimerBlox
®
family of versatile
silicon timing devices.
A single resistor, RSET
, programs the LTC6995’s internal
master oscillator frequency. The output clock period
is determined by this master oscillator and an internal
frequency divider, NDIV
, programmable to eight settings
from 1 to 221.
tOUT =
N
DIV
•R
SET
50kΩ
•1.024ms, NDIV =1,8,64,...,221
When oscillating, the LTC6995 generates a 50% duty
cycle square wave output. A reset function is provided
to stop the master oscillator and clear internal dividers.
Removing reset initiates a full output clock cycle which is
useful for programmable power-on reset and watchdog
timer applications.
The LTC6995 has two versions of reset functionality. The
reset input is active high for the LTC6995-1 and active low
for the LTC6995-2. The polarity of the output when reset
is selectable for both versions.
OUTPUT (OSCILLATOR START STATE)
RST/RST POLARITY LTC6995-1 LTC6995-2
0 0 Oscillating (Low) 0 (Reset)
1 0 0 (Reset) Oscillating (Low)
0 1 Oscillating (High) 1 (Reset)
1 1 1 (Reset) Oscillating (High)
APPLICATIONS
n Period Range: 1ms to 9.5 Hours
n Timing Reset by Power-On or Reset Input
n Configured with 1 to 3 Resistors
n <1.5% Maximum Frequency Error
n Programmable Output Polarity
n 2.25V to 5.5V Single Supply Operation
n 55µA to 80µA Supply Current
(2ms to 9.5hr Clock Period)
n 500µs Start-Up Time
n CMOS Output Driver Sources/Sinks 20mA
n –55°C to 125°C Operating Temperature Range
n Available in Low Profile (1mm) SOT-23 (ThinSOT™)
and 2mm × 3mm DFN Packages
n AEC-Q100 Qualified for Automotive Applications
n Power-On Reset Timer
n Long Time One Shot
n “Heartbeat” Timers
n Watchdog Timers
n Periodic “Wake-Up” Call
n High Vibration, High Acceleration Environments
All registered trademarks and trademarks are the property of their respective owners.
Active Low Power-On Reset Timer
LTC6995-1
0.1µF OUT
1M
392k
118k
RST
GND
SET
OUT
V+
DIV
V+
V+
699512 TA01
5 SECONDS
1/2 tOUT TIMER STOPPED
POWER-ON RESET
(1ms TO 4.8 HOURS)
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
2
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+) to GND ........................................6V
Maximum Voltage
on Any Pin ................(GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V)
Operating Temperature Range (Note 2)
LTC6995C ............................................ –40°C to 85°C
LTC6995I .............................................–40°C to 85°C
LTC6995H .......................................... –40°C to 125°C
LTC6995MP ....................................... –55°C to 125°C
(Note 1)
PIN CONFIGURATION
Specified Temperature Range (Note 3)
LTC6995C ................................................ 0°C to 70°C
LTC6995I .............................................–40°C to 85°C
LTC6995H .......................................... –40°C to 125°C
LTC6995MP ....................................... –55°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
S6 Package ........................................................... 300°C
LTC6995-1/LTC6995-2 LTC6995-1/LTC6995-2
TOP VIEW
OUT
GND
RST/
RST
V+
DIV
SET
DCB PACKAGE
6-LEAD (2mm × 3mm) PLASTIC DFN
4
5
7
GND
6
3
2
1
TJMAX = 150°C, θJA = 64°C/W, θJC = 9.6°C/W
EXPOSED PAD (PIN 7) CONNECTED TO GND,
PCB CONNECTION OPTIONAL
RST/
RST 1
GND 2
SET 3
6 OUT
5 V+
4 DIV
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 192°C/W, θJC = 51°C/W
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6995CDCB-1#TRMPBF LTC6995CDCB-1#TRPBF LGJM 6-Lead (2mm x 3mm) Plastic DFN 0°C to 70°C
LTC6995IDCB-1#TRMPBF LTC6995IDCB-1#TRPBF LGJM 6-Lead (2mm x 3mm) Plastic DFN –40°C to 85°C
LTC6995HDCB-1#TRMPBF LTC6995HDCB-1#TRPBF LGJM 6-Lead (2mm x 3mm) Plastic DFN –40°C to 125°C
LTC6995CS6-1#TRMPBF LTC6995CS6-1#TRPBF LTGJN 6-Lead Plastic TSOT-23 0°C to 70°C
LTC6995IS6-1#TRMPBF LTC6995IS6-1#TRPBF LTGJN 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6995HS6-1#TRMPBF LTC6995HS6-1#TRPBF LTGJN 6-Lead Plastic TSOT-23 –40°C to 125°C
LTC6995CDCB-2#TRMPBF LTC6995CDCB-2#TRPBF LGJP 6-Lead (2mm x 3mm) Plastic DFN 0°C to 70°C
LTC6995IDCB-2#TRMPBF LTC6995IDCB-2#TRPBF LGJP 6-Lead (2mm x 3mm) Plastic DFN –40°C to 85°C
LTC6995HDCB-2#TRMPBF LTC6995HDCB-2#TRPBF LGJP 6-Lead (2mm x 3mm) Plastic DFN –40°C to 125°C
LTC6995CS6-2#TRMPBF LTC6995CS6-2#TRPBF LTGJQ 6-Lead Plastic TSOT-23 0°C to 70°C
LTC6995IS6-2#TRMPBF LTC6995IS6-2#TRPBF LTGJQ 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6995HS6-2#TRMPBF LTC6995HS6-2#TRPBF LTGJQ 6-Lead Plastic TSOT-23 –40°C to 125°C
LTC6995MPS6-1#TRMPBF LTC6995MPS6-1#TRPBF LTGJN 6-Lead Plastic TSOT-23 –55°C to 125°C
LTC6995MPS6-2#TRMPBF LTC6995MPS6-2#TRPBF LTGJQ 6-Lead Plastic TSOT-23 –55°C to 125°C
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
3
ORDER INFORMATION
Lead Free Finish
AUTOMOTIVE PRODUCTS**
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6995IS6-1#WTRMPBF LTC6995IS6-1#WTRPBF LTGJN 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6995HS6-1#WTRMPBF LTC6995HS6-1#WTRPBF LTGJN 6-Lead Plastic TSOT-23 –40°C to 125°C
LTC6995IS6-2#WTRMPBF LTC6995IS6-2#WTRPBF LTGJQ 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6995HS6-2#WTRMPBF LTC6995HS6-2#WTRPBF LTGJQ 6-Lead Plastic TSOT-23 –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
thesemodels.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V for LTC6995-1,
RST = V+ for LTC6995-2, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tOUT Output Clock Period 1.024m 34,360 Seconds
fOUT Output Frequency 29.1µ 977 Hz
∆fOUT Frequency Accuracy (Note 4) 29.1µHz ≤ fOUT ≤ 977Hz
l
±0.8 ±1.5
±2.2 %
%
∆fOUT/∆T Frequency Drift Over Temperature l±0.005 %/°C
∆fOUT/∆V+Frequency Drift Over Supply V+ = 4.5V to 5.5V
V+ = 2.25V to 4.5V
l
l
0.23
0.06 0.55
0.16 %/V
%/V
Long-Term Frequency Stability (Note 11) 90 ppm/√kHr
Period Jitter (Note 10) NDIV = 1
NDIV = 8 15
7ppmRMS
ppmRMS
BW Frequency Modulation Bandwidth 0.4 • fOUT Hz
tSFrequency Change Settling Time (Note 9) 1 Cycle
Analog Inputs
VSET Voltage at SET Pin l0.97 1.00 1.03 V
∆VSET/∆T VSET Drift Over Temperature l±75 µV/°C
RSET Frequency-Setting Resistor l50 800 kΩ
VDIV DIV Pin Voltage l0 V+V
∆VDIV/∆V+DIV Pin Valid Code Range (Note 5) Deviation from Ideal
VDIV/V+ = (DIVCODE + 0.5)/16
l±1.5 %
DIV Pin Input Current l±10 nA
Power Supply
V+Operating Supply Voltage Range l2.25 5.5 V
Power-On Reset Voltage l1.95 V
ISSupply Current RL = ∞, RSET = 50k V+ = 5.5V
V+ = 2.25V
l
l
135
105 170
135 µA
µA
RL = ∞, RSET = 100k V+ = 5.5V
V+ = 2.25V
l
l
100
80 130
105 µA
µA
RL = ∞, RSET = 800k V+ = 5.5V
V+ = 2.25V
l
l
65
55 100
85 µA
µA
RL = ∞, ISET = 0µA V+ = 5.5V
V+ = 2.25V 60
52 µA
µA
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
4
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V for LTC6995-1,
RST = V+ for LTC6995-2, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital I/O
RST Pin Input Capacitance 2.5 pF
RST Pin Input Current RST = 0V to V+±10 nA
VIH High Level RST Pin Input Voltage (Note 6) l0.7 • V+V
VIL Low Level RST Pin Input Voltage (Note 6) l0.3 • V+V
IOUT(MAX) Output Current V+ = 2.7V to 5.5V ±20 mA
VOH High Level Output Voltage (Note 7) V+ = 5.5V IOUT = –1mA
IOUT = –16mA
l
l
5.45
4.84 5.48
5.15 V
V
V+ = 3.3V IOUT = –1mA
IOUT = –10mA
l
l
3.24
2.75 3.27
2.99 V
V
V+ = 2.25V IOUT = –1mA
IOUT = –8mA
l
l
2.17
1.58 2.21
1.88 V
V
VOL Low Level Output Voltage (Note 7) V+ = 5.5V IOUT = 1mA
IOUT = 16mA
l
l
0.02
0.26 0.04
0.54 V
V
V+ = 3.3V IOUT = 1mA
IOUT = 10mA
l
l
0.03
0.22 0.05
0.46 V
V
V+ = 2.25V IOUT = 1mA
IOUT = 8mA
l
l
0.03
0.26 0.07
0.54 V
V
tRST Reset Propagation Delay V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
16
24
40
ns
ns
ns
tWIDTH Minimum Input Pulse Width V+ = 3.3V 5 ns
trOutput Rise Time (Note 8) V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.1
1.7
2.7
ns
ns
ns
tfOutput Fall Time (Note 8) V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.0
1.6
2.4
ns
ns
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6995C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 3: The LTC6995C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6995C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6995I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6995H is guaranteed
to meet specified performance from –40°C to 125°C. The LTC6995MP is
guaranteed to meet specified performance from –55°C to 125°C.
Note 4: Frequency accuracy is defined as the deviation from the fOUT
equation, assuming RSET is used to program the frequency.
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
Note 6: The RST pin has hysteresis to accommodate slow rising or falling
signals. The threshold voltages are proportional to V+. Typical values can
be estimated at any supply voltage using VRST(RISING) ≈ 0.55 • V+ + 185mV
and VRST(FALLING) ≈ 0.48 • V+ – 155mV.
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Settling time is the amount of time required for the output to settle
within ±1% of the final frequency after a 0.5× or 2× change in ISET
.
Note 10: Jitter is the ratio of the deviation of the period to the mean of the
period. This specification is based on characterization and is not 100%
tested.
Note 11: Long-term drift of silicon oscillators is primarily due to the
movement of ions and impurities within the silicon and is tested at 30°C
under otherwise nominal operating conditions. Long-term drift is specified
as ppm/√kHr due to the typically nonlinear nature of the drift. To calculate
drift for a set time period, translate that time into thousands of hours, take
the square root and multiply by the typical drift number. For instance, a
year is 8.77kHr and would yield a drift of 266ppm at 90ppm/√kHr. Drift
without power applied to the device may be approximated as 1/10th of the
drift with power, or 9ppm/√kHr for a 90ppm/√kHr device.
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
5
TYPICAL PERFORMANCE CHARACTERISTICS
Frequency Error vs RSET Frequency Drift vs Supply Voltage Typical VSET Distribution
VSET Drift vs ISET VSET Drift vs Supply VSET vs Temperature
Frequency Error vs Temperature Frequency Error vs Temperature Frequency Error vs Temperature
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
VSET (V)
0.98
0
100
50
150
200
250
0.996 1.004 1.012
1.02
0.988
699512 G06
NUMBER OF UNITS
2 LOTS
DFN AND SOT-23
1274 UNITS
ISET (µA)
0
–1.0
0
0.4
0.2
0.6
0.8
1.0
10 15
20
–0.4
–0.2
–0.6
–0.8
5
699512 G07
V
SET
(mV)
REFERENCED TO ISET = 10µA
SUPPLY (V)
2
–1.0
0
0.4
0.2
0.6
0.8
1.0
4 5
6
–0.4
–0.2
–0.6
–0.8
3
699512 G08
DRIFT (mV)
REFERENCED TO V+ = 4V
TEMPERATURE (°C)
–50
0.980
1.000
1.010
1.005
1.015
1.020
0 25 50 100
125
0.995
0.990
0.985
–25 75
699512 G09
V
SET
(V)
3 PARTS
TEMPERATURE (°C)
–50
1
2
25 75
0
–1
–25 0 50 100
–2
–3
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MIN OVER TEMPERATURE
RSET = 50k
3 PARTS
TEMPERATURE (°C)
–50
1
2
25 75
0
–1
–25 0 50 100
–2
–3
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MIN OVER TEMPERATURE
RSET = 200k
3 PARTS
TEMPERATURE (°C)
–50
1
2
25 75
0
–1
–25 0 50 100
–2
–3
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MIN OVER TEMPERATURE
RSET = 800k
3 PARTS
RSET (kΩ)
0
–3
ERROR (%)
–2
–1
0
1
2
3
3 PARTS
200 400 600
800
699512 G04
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MIN OVER TEMPERATURE
SUPPLY VOLTAGE (V)
2
–0.5
DRIFT (%)
–0.4
–0.2
–0.1
0
0.5
0.2
34
699512 G05
–0.3
0.3
0.4
0.1
56
REFERENCED TO V+ = 4.5V
RSET = 50k
RSET = 200k
RSET = 800k
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
6
Supply Current vs RSET
RST Threshold Voltage
vs Supply VoltageTypical ISET Current Limit vs V+
Supply Current vs Supply Voltage Supply Current vs Temperature
Supply Current
vs RST Pin Voltage
Reset Propagation Delay (tRST)
vs Supply Voltage
Rise and Fall Time
vs Supply Voltage
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
SUPPLY VOLTAGE (V)
2
0
POWER SUPPLY CURRENT (µA)
25
50
75
100
125
150
3 4 5
6
699512 G10
RSET = 50k
RSET = 100k
RSET = 200k
RSET = 800k
TEMPERATURE (°C)
–50
100
125
25 75
75
50
–25 0 50 100
25
0
5V, RSET = 100k
2.5V, RSET = 100k
2.5V, RSET = 800k
5V, RSET = 800k
VRST/V+ (V/V)
0
POWER SUPPLY CURRENT (µA)
150
200
250
0.8
699512 G12
100
50
00.2 0.4 0.6
1.0
5V
RST FALLING 5V
RST RISING
3.3V
RST FALLING 3.3V
RST RISING
RSET = 800k
RSET (kΩ)
0
0
POWER SUPPLY CURRENT (µA)
25
50
75
100
125
150
200 400 600
800
699512 G13
V+ = 5V
V+ = 3.3V
V+ = 2.5V
SUPPLY VOLTAGE (V)
I
SET
(µA)
699512 G14
1000
400
800
200
600
02 43 5
6
SET PIN SHORTED TO GND
SUPPLY VOLTAGE (V)
RST PIN VOLTAGE (V)
699512 G15
3.5
1.0
2.0
3.0
0.5
1.5
2.5
02 43 5
6
POSITIVE-GOING
NEGATIVE-GOING
SUPPLY VOLTAGE (V)
2
0
PROPAGATION DELAY (ns)
5
15
20
25
50
35
34
699512 G16
10
40
45
30
56
CLOAD = 5pF
SUPPLY VOLTAGE (V)
RISE/FALL TIME (ns)
699512 G17
3.0
1.5
2.5
1.0
0.5
2.0
02 43 5
6
CLOAD = 5pF
tRISE
tFALL
Typical Frequency Error
vs Time (Long-Term Drift)
TIME (h)
DELTA FREQUENCY (ppm)
699512 G18
50
0
150
–150
–100
–50
100
200
–200 0 1200400 800 1600 2000 2400 2800
65 UNITS
SOT-23 AND DFN PARTS
TA = 30°C
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
7
Output Resistance
vs Supply Current
Typical LTC6995-1 Start-Up with
POL = 1
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
SUPPLY VOLTAGE (V)
OUTPUT RESISTANCE (Ω)
699512 G19
50
25
20
35
45
5
10
15
30
40
02 43 5
6
OUTPUT SOURCING CURRENT
OUTPUT SINKING CURRENT
V+
5V/DIV
OUT
5V/DIV
RST
5V/DIV
5ms/DIVV+ = 5V
DIVCODE = 15
RSET = 499k
699512 G20
4ms START-UP
OUTPUT RESET
RESET RELEASED,
100Hz OUTPUT CLOCK
PIN FUNCTIONS
(DCB/S6)
V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This sup-
ply should be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1µF capacitor.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. An internal A/D converter (referenced to V+) moni-
tors the DIV pin voltage (VDIV) to determine a 4-bit result
(DIVCODE). VDIV may be generated by a resistor divider
between V+ and GND. Use 1% resistors to ensure an ac-
curate result. The DIV pin and resistors should be shielded
from the OUT pin or any other traces that have fast edges.
Limit the capacitance on the DIV pin to less than 100pF
so that VDIV settles quickly. The MSB of DIVCODE (POL)
determines the polarity of the OUT pin.
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
on the SET pin (VSET) is regulated to 1V above GND. The
amount of current sourced from the SET pin (ISET) pro-
grams the master oscillator frequency. The ISET current
range is 1.25µA to 20µA. The output oscillation will stop
if ISET drops below approximately 500nA. A resistor con-
nected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance and
50ppm/°C or better temperature coefficient. For lower ac-
curacy applications an inexpensive 1% thick film resistor
may be used.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the VSET voltage.
699512 PF
LTC6995-1/
LTC6995-2
RST
GND
SET
OUT
V+
DIV
C1
0.1µF
RSET R2
R1
V+
RST or RST (Pin 4/Pin 1): Output Reset. The reset input
is used to stop the output oscillator and to clear internal
dividers. When reset is released the oscillator starts with
a full half period time interval. The output logic state when
reset is determined by the programmed DIVCODE. The
LTC6995-1 has an active high RST input. The LTC6995-2
has an active low RST input.
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
8
BLOCK DIAGRAM
(S6 Package Pin Numbers Shown)
699512 BD
PROGRAMMABLE
DIVIDER
FIXED
DIVIDER
÷ 1024
DIVIDER
RESET
÷1, 8, 64, 512
4096, 215, 218, 221
MASTER OSCILLATOR
POR
OUTPUT
POLARITY
DIGITAL
FILTER
4-BIT A/D
CONVERTER
POL BIT
R1
R2
DIV
V+
OUT
5
4
1
6
HALT OSCILLATOR
OUTPUT
IF ISET < 500nA
MCLK
tMASTER = 1µs
50kΩ
VSET
ISET
•
+
–
ISET
ISET
VSET = 1V
+
–
1V
3 22
GNDSET RST
LTC6995-2
ONLY
RSET
tOUT
PIN FUNCTIONS
(DCB/S6)
GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground
plane for best performance.
OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings
from GND to V+ with an output resistance of approximately
30Ω. When driving an LED or other low impedance load
a series output resistor should be used to limit source/
sink current to 20mA.
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
9
OPERATION
The LTC6995 is built around a master oscillator with a
1MHz maximum frequency. The oscillator is controlled
by the SET pin current (ISET) and voltage (VSET), with a
1MHz • 50k conversion factor that is accurate to ±0.8%
under typical conditions.
fMASTER =
1
tMASTER
=1MHz • 50kΩ•
I
SET
VSET
A feedback loop maintains VSET at 1V ±30mV, leaving ISET
as the primary means of controlling the output frequency.
The simplest way to generate ISET is to connect a resistor
(RSET) between SET and GND, such that ISET = VSET/RSET
.
The master oscillator equation reduces to:
fMASTER =
1
t
MASTER
=
1MHz • 50k
Ω
R
SET
From this equation, it is clear that VSET drift will not affect
the output frequency when using a single program resistor
(RSET). Error sources are limited to RSET tolerance and
the inherent frequency accuracy ∆fOUT of the LTC6995.
RSET may range from 50k to 800k (equivalent to ISET
between 1.25µA and 20µA).
Before reaching the OUT pin, the oscillator frequency
passes through a fixed ÷1024 divider. The LTC6995 also
includes a programmable frequency divider which can
further divide the frequency by 1, 8, 64, 512, 4096, 215,
218 or 221. The divider ratio NDIV is set by a resistor divider
attached to the DIV pin.
fOUT =1MHz • 50kΩ
1024 •NDIV
•ISET
VSET
, or
tOUT =1
f
OUT
=NDIV
50kΩ•VSET
I
SET
•1.024ms
with RSET in place of VSET/ISET the equation reduces to:
tOUT =
N
DIV
•R
SET
50kΩ
•1.024m
s
DIVCODE
The DIV pin connects to an internal, V+ referenced 4-bit A/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6995:
1. DIVCODE determines the output frequency divider set-
ting, NDIV
.
2. DIVCODE determines the polarity of the RST and OUT
pins, via the POL bit.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
Figure 1. Simple Technique for Setting DIVCODE
699512 F01
LTC6995
V+
DIV
GND
R1
R2
2.25V TO 5.5V
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding NDIV and POL values for the recommended
resistor pairs. Other values may be used as long as:
1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-
tor tolerances and temperature effects)
2. The driving impedance (R1||R2) does not exceed 500kΩ.
If the voltage is generated by other means (i.e., the output
of a DAC) it must track the V+ supply voltage. The last
column in Table 1 shows the ideal ratio of VDIV to the
supply voltage, which can also be calculated as:
V
DIV
V
+=
DIVCODE
+
0.5
16 ±1.5%
For example, if the supply is 3.3V and the desired DIVCODE
is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.
Figure 2 illustrates the information in Table 1, showing
that NDIV is symmetric around the DIVCODE midpoint.
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
10
OPERATION
Table 1. DIVCODE Programming
DIVCODE POL NDIV RECOMMENDED tOUT R1 (kΩ) R2 (kΩ) VDIV/V+
0 0 1 1.024ms to 16.384ms Open Short ≤0.03125 ±0.015
1 0 8 8.192ms to 131ms 976 102 0.09375 ±0.015
2 0 64 65.5ms to 1.05sec 976 182 0.15625 ±0.015
3 0 512 524ms to 8.39sec 1000 280 0.21875 ±0.015
4 0 4,096 4.19sec to 67.1sec 1000 392 0.28125 ±0.015
5 0 32,768 33.6sec to 537sec 1000 523 0.34375 ±0.015
6 0 262,144 268sec to 4,295sec 1000 681 0.40625 ±0.015
7 0 2,097,152 2,147sec to 34,360sec 1000 887 0.46875 ±0.015
8 1 2,097,152 2,147sec to 34,360sec 887 1000 0.53125 ±0.015
9 1 262,144 268sec to 4,295sec 681 1000 0.59375 ±0.015
10 1 32,768 33.6sec to 537sec 523 1000 0.65625 ±0.015
11 1 4,096 4.19sec to 67.1sec 392 1000 0.71875 ±0.015
12 1 512 524ms to 8.39sec 280 1000 0.78125 ±0.015
13 1 64 65.5ms to 1.05sec 182 976 0.84375 ±0.015
14 1 8 8.192ms to 131ms 102 976 0.90625 ±0.015
15 1 1 1.024ms to 16.384ms Short Open ≥0.96875 ±0.015
0.5•V+
t
OUT
(SECONDS)
699512 F02
1000
10000
100
10
1
0.001
0.1
0.01
INCREASING VDIV
V
+
0V
POL BIT = 0
0
1
2
3
4
5
6
7 8
9
10
11
12
13
14
15
POL BIT = 1
Figure 2. Frequency Range and POL Bit vs DIVCODE
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
11
tOUT 1/2 tOUT
RST
OUT
LTC6995-1
tRST
t
WIDTH
OUT REMAINS HIGH
WHILE RST IS HIGH
tOUT 1/2 tOUT
OUT
LTC6995-2
tRST
t
WIDTH
OUT REMAINS HIGH
WHILE RST IS LOW
RST
699512 F04
tOUT 1/2 tOUT
RST
OUT
LTC6995-1
tRST
tWIDTH
OUT REMAINS LOW
WHILE RST IS HIGH
tOUT 1/2 tOUT
OUT
LTC6995-2
tRST
tWIDTH
OUT REMAINS LOW
WHILE RST IS LOW
RST
699512 F03
OPERATION
Reset and Polarity Bit Functions
The Reset input, RST for the LTC6995-1 and RST for the
LTC6995-2, forces the output to a fixed state and resets
the internal clock dividers. The output state when reset is
determined by the polarity bit as selected by through the
DIVCODE setting.
OUTPUT (OSCILLATOR START STATE)
RST/RST POLARITY LTC6995-1 LTC6995-2
0 0 Oscillating (Low) 0 (Reset)
1 0 0 (Reset) Oscillating (Low)
0 1 Oscillating (High) 1 (Reset)
1 1 1 (Reset) Oscillating (High)
With the POL bit programmed to be 0, the output will be
forced low when reset. When reset is released by chang-
ing state, the oscillator starts. The next rising edge at the
output follows a precise half cycle delay.
With the POL bit programmed to be 1, the output will be
forced high when reset. When reset is released by chang-
ing state, the oscillator starts. The next falling edge at the
output follows a precise half cycle delay.
Figure 3. Reset Timing Diagram (POL Bit = 0)
Figure 4. Reset Timing Diagram (POL Bit = 1)
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
12
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue moni-
toring VDIV for changes. The LTC6995 will respond to
DIVCODE changes in less than one cycle.
tDIVCODE < 500 • tMASTER < tOUT
The output may have an inaccurate pulse width during the
frequency transition. But the transition will be glitch-free
and no high or low pulse can be shorter than the mas-
ter clock period. A digital filter is used to guarantee the
DIVCODE has settled to a new value before making changes
to the output.
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, tSTART
. A supply
voltage of typically 1.4V (1.2V to 1.5V over temperature)
initiates the start-up sequence. The OUT pin is held low
during this time. The typical value for tSTART ranges from
0.5ms to 8ms depending on the master oscillator frequency
(independent of NDIV):
tSTART(TYP) = 500 • tMASTER
During start-up, the DIV pin A/D converter must deter-
mine the correct DIVCODE before the output is enabled.
The start-up time may increase if the supply or DIV pin
voltages are not stable. For this reason, it is recommended
to minimize the capacitance on the DIV pin so it will prop-
erly track V+. Less than 100pF will not affect performance.
Start-Up Behavior
When first powered up, the output is held low. If the polarity
is set for non-inversion (POL = 0) and the output is enabled
at the end of the start-up time, OUT will begin oscillating.
If the output is being reset (RST = 1 for LTC6995-1 and
RST = 0 for LTC6995-2) at the end of the start-up time,
it will remain low due to the POL bit = 0. When reset is
released the oscillator starts and the output remains low
for precisely one half cycle of the programmed period.
In inverted operation (POL = 1), the start-up sequence is
similar. However, the LTC6995 does not know the correct
DIVCODE setting when first powered up, so the output
defaults low. At the end of tSTART
, the value of DIVCODE is
recognized and OUT goes high (inactive) because POL = 1.
If the output is being reset (RST = 1 for LTC6995-1 and
RST = 0 for LTC6995-2) at the end of the start-up time,
it will remain high due to the POL bit = 1. When reset is
released the oscillator starts and the output remains high
for precisely one half cycle of the programmed period.
Figure 7 to Figure 10 detail the possible start-up sequences.
DIV
200mV/DIV
OUT
1V/DIV
10ms/DIV
699512
F05
V+ = 3.3V
R
SET
= 200k
V+
1V/DIV
OUT
1V/DIV
250µs/DIV
699512 F06
V+ = 2.5V
DIVCODE = 15
R
SET
= 50k
500µs
Figure 5. DIVCODE Change from 1 to 0 Figure 6. Typical Start-Up LTC6995-1 with RST = 0V
OPERATION
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
13
Figure 7. Start-Up Timing Diagram (Reset = 0, POL Bit = 0)
Figure 8. Start-Up Timing Diagram (Reset = 1, POL Bit = 0)
Figure 9. Start-Up Timing Diagram (Reset = 0, POL Bit = 1)
Figure 10. Start-Up Timing Diagram (Reset = 1, POL Bit = 1)
OPERATION
tOUT
LTC6995-1
tSTART 1/2 tOUT
RST
OUT
tOUT
LTC6995-2
tSTART 1/2 tOUT
RST
OUT
699512 F07
tOUT
LTC6995-2
tSTART 1/2 tOUT
RST
OUT
tOUT
LTC6995-1
tSTART 1/2 tOUT
RST
OUT
699512 F08
tOUT
LTC6995-1
tSTART 1/2 tOUT
RST
OUT
tOUT
LTC6995-2
tSTART 1/2 tOUT
RST
OUT
699512 F09
tOUT
LTC6995-2
tSTART 1/2 tOUT
RST
OUT
RST
OUT
tOUT
LTC6995-1
tSTART 1/2 tOUT
699512 F10
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
14
APPLICATIONS INFORMATION
Basic Operation
The simplest and most accurate method to program the
LTC6995 is to use a single resistor, RSET
, between the
SET and GND pins. The design procedure is a 3-step
process. First select the POL bit setting and NDIV value,
then calculate the value for the RSET resistor.
Step 1: Select the LTC6995 Version and POL Bit Setting
Determine if the application requires an active-high,
LTC6995-1 or active-low, LTC6995-2 reset function.
Otherwise the two versions share identical functionality.
The OUT pin polarity depends on the setting of the POL
bit. To force OUT = 0 during reset, choose POL bit = 0. To
force OUT = 1 during reset, choose POL bit = 1.
Step 2: Select the NDIV Frequency Divider Value
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the NDIV
value. For a given output clock period, NDIV should be
selected to be within the following range.
t
OUT
16.384ms ≤NDIV ≤
t
OUT
1.024ms
(1)
To minimize supply current, choose the lowest NDIVvalue
(generally recommended). Alternatively, use
Table 1
as a guide to select the best NDIV value for the given
application.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
or VDIV/V+ ratio to apply to the DIV pin.
Step 3: Calculate and Select RSET
The final step is to calculate the correct value for RSET
using the following equation.
RSET =
50k
1.024ms •
t
OUT
N
DIV
1
(2)
Select the standard resistor value closest to the calculated
value.
Example: Design a 1Hz oscillator with minimum power
consumption, an active-high reset input, and the OUT pin
low during reset.
Step 1: Select the LTC6995 Version and POL Bit Setting
For active-high reset select the LTC6995-1. For OUT low
during reset choose POL bit = 0.
Step 2: Select the NDIV Frequency Divider Value
Choose an NDIV value that meets the requirements of
Equation (1), using tOUT = 1000ms:
61.04 ≤ NDIV ≤ 976.6
Potential settings for NDIV include 64 and 512. NDIV = 64
is the best choice, as it minimizes supply current by us-
ing a large RSET resistor. POL = 0 and NDIV = 64 requires
DIVCODE = 2. Using Table 1, choose R1 = 976k and
R2 = 182k values to program DIVCODE = 2.
Step 3: Select RSET
Calculate the correct value for RSET using Equation (2).
RSET =
50k
1.024ms •
1000ms
64 =763k
Since 763k is not available as a standard 1% resistor,
substitute 768k if a –0.7% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 576k + 187k to attain a more precise resistance.
The completed design is shown in Figure 11.
DIVCODE = 2
699512 F11
LTC6995-1
RST
GND
SET
RST OUT
V+
DIV
R1
976k
R2
182k
RSET
763k
2.25V TO 5.5V
Figure 11. 1Hz Oscillator
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
15
APPLICATIONS INFORMATION
Power-On Reset (POR) Function
When power is applied to the LTC6995 the output is held
low for tSTART, then takes on the value of the POL bit as the
clock cycle begins. If POL = 0 (DIVCODE < 8) the output
will remain low for a programmable interval of tSTART +
1/2 tOUT, assuming the RST pin is inactive. This makes the
LTC6995 useful as a programmable long-time power-on
reset (POR), with the low output used to hold a system
in reset for a fixed period after power is applied. Timing
begins when the V+ supply exceeds approximately 1.4V.
To prevent additional output transitions after the initial POR
time, the oscillator can be disabled by removing the SET
pin current. This prevents the internal master oscillator
output from clocking the frequency dividers or output,
while keeping it biased so it can resume operation quickly.
The easiest way to implement this feature is to connect
RSET between the SET and OUT pins.
Figure 12 shows the basic power-on reset function. When
the half cycle times out, the output goes high, eliminates
the SET pin current, and stops additional OUT pin transi-
tions. The output remains high until the device is reset by
driving the RST input or power is cycled off then back on.
The POR interval is only one half of an oscillator period so
component selection is slightly different. Table 2 provides
the component values required for one half cycle time
intervals. Timing starts after a short startup delay time
following the application of the V+ supply.
LTC6995-1
tPOR = 1 SECOND FOR VALUES SHOWN
POL = 0
DIVCODE = 3
NDIV = 512
RST = V+ FOR LTC6995-2
RST
GND
SET
OUT
V+
DIV
RSET
191k
R2
280k
R1
1M 0.1µF
2.25V TO 5.5V
POR
OUT
POL = 0
699512 F12
tDELAY
(1/2 tOUT)
tSTART
TIMER STOPPED
~1.4V STARTS TIMER
POWER-ON RESET
V+
Figure 12. Active Low Power-On Reset
(1 Second Interval Example)
Table 2. Power-On Reset (POR). One Shot, One Half Cycle Delay Programming
Output Low During Time Interval, POL = 0
DIVCODE tDELAY TIME INTERVAL (1/2 tOUT) R1 (kΩ) R2 (kΩ) ~RSET (kΩ)
0 512µs to 8.2ms Open Short tDELAY(MS) • 97.6
1 4.1ms to 65.5ms 976 102 tDELAY(MS) • 12.2
2 32.8ms to 524.3ms 976 182 tDELAY(MS) • 1.5
3 262.1ms to 4.2sec 1000 280 tDELAY(SEC) • 190.7
4 2.1sec to 33.6sec 1000 392 tDELAY(SEC) • 23.8
5 16.8sec to 4.5min 1000 523 tDELAY(MIN) • 178.6
6 2.2min to 35.8min 1000 681 tDELAY(MIN) • 22.7
7 17.9min to 4.8hrs 1000 887 tDELAY(HR) • 167.6
Note: Power-On Reset Time = tDELAY + tSTART
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
16
APPLICATIONS INFORMATION
For shorter power-on reset times (1ms to 73ms) the timer
startup delay becomes a significant part of the total POR
time. To take this delay into account the value for RSET can
be modified from the values shown in Table 2. For a POR
time in the range from 1ms to 16ms (DIVCODE = 0), RSET
should be tPOR(ms) • 49.5. For a POR time in the range
from 4.5ms to 73ms (DIVCODE = 1), RSET is tPOR(ms) •
10.9. For longer POR times (DIVCODE 2 through 7) the
startup time is insignificant. After power on, the delay fol-
lowing a reset condition will be in the same range as shown
for tDELAY in Table 2 for these two DIVCODE selections.
For short POR times, a more precise estimation of the
startup time can be found from the following:
tSTART(µs)=256+16 •(12 –DIVCODE)
( )
R
SET
(k
Ω
)
50
+80
Supply bounce resets the internal timer so the POR circuit
automatically debounces supply noise. POR timing starts
from the time that the V+ supply has reached approximately
1.4 volts.
Long Timer One Shots and Delay Generators
The POR circuit of Figure 12 is also useful when the reset
inputs are driven. This creates edge triggered timing events
that are active low and can either be re-triggered or can
stop after one programmed interval. The programmed
time interval can range from only 500µs to over 4 hours
with just resistor value changes.
The circuits in Figure 13 show how a POR or active low
interval can be re-started to provide a full system reset time.
The Figure 14 circuit requires an indication from the
system being reset that it is ready before timing out. The
LTC6995-2 can accommodate an active high OK signal.
By forcing a reset condition at power on the LTC6995 can
be used to create a long time delayed rising edge triggered
by either a falling edge signal (LTC6995-1) or a rising edge
signal (LTC6995-2) as show in Figure 15.
Figure 13. System Resets On Command with Full POR Time Interval. Reset Pulse Is Debounced Automatically
LTC6995-1
ACTIVE HIGH RESET
RST
GND
SET
OUT
V+
DIV
RSET
100k
R2
R1 0.1µF
V+
V
+
POR
OUT
POL = 0
RST
tSTART +
1/2 tOUT 1/2 tOUT
TIMER
STOPPED
TIMER
STOPPED
RESET
POR POR
V+
LTC6995-2
ACTIVE LOW RESET
RST
GND
SET
OUT
V+
DIV
RSET
100k
R2
R1 0.1µF
V+
V
+
POR
OUT
POL = 0
RST
699512 F13
tSTART +
1/2 tOUT 1/2 tOUT
TIMER
STOPPED
TIMER
STOPPED
RESET
POR POR
V+
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
17
APPLICATIONS INFORMATION
Figure 14. Extended POR. Timer Reset During Initial POR Interval. Full POR Interval Provided Once System Signals the OK
Figure 15. Long Time Delayed Rising Edge. Delay Time Can Range from 500µs to 4.8 Hours
LTC6995-1
SYSTEM
RST
GND
SET
OUT
V+
DIV
RSET
R2
R1 0.1µF
V+
POR
699512 F14
OUT
POL = 0
RST
tSTART +
1/2 tOUT 1/2 tOUT
TIMER
STOPPED
SYSTEM OK
SYSTEM OK
POR POR EXTENDED POR
V+
LTC6995-2
OUTPUT
RISING EDGE TRIGGERED
POL = 0
TRIGGER RST
GND
SET
OUT
V+
DIV
RSET
R2
R1 0.1µF
V+
699512 F15
OUTPUT
TRIGGER
1/2 tOUT 1/2 tOUT
V+
1/2 tOUT 1/2 tOUT
LTC6995-1
OUTPUT
FALLING EDGE TRIGGERED
POL = 0
TRIGGER RST
GND
SET
OUT
V+
DIV
RSET
R2
R1 0.1µF
V+
OUTPUT
TRIGGER
V+
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
18
APPLICATIONS INFORMATION
Watchdog Timers
Using the same circuits as shown in Figure 15 with pe-
riodic pulsing of the reset input can create an effective
watchdog timer. A watchdog pulse is required from a
system within each timing interval. The watchdog timeout
interval can be programmed from 500µs to 4.8 hours. If a
pulse is missed the output goes high to indicate that the
system software may be caught in an infinite loop. This
high level can be used to initiate software diagnostic or
restart procedures. The LTC6995 internal clock stops and
the output remains high until the software recovers and
returns to issuing watchdog pulses. Figure 16 shows the
timing for this application.
Watchdog timers are used to detect if a system operating
software is diverted from the designed program sequence
for any reason. It is always a possibility that the software
could get stuck in a way that keeps the watchdog pulse in
the state that holds the timer in the reset so it can never
time out. In this condition the watchdog timer is ineffective
and will never force corrective action. To help to prevent
this a second one shot can be used to reset the watchdog
timer as shown in Figure 17.
Figure 16. Watchdog Timer. Same Circuits as Shown in Figure 15
Figure 17. Extra-Reliable Watchdog Timer. Allows Timeout if System Watchdog Pulse Gets Stuck in the Timer Reset State.
Both Timer Devices Can Share the Same DIVCODE Setting
699512 F16
OUTPUT
RST (LTC6995-1)
RST (LTC6995-2)
SERVICE WATCHDOG
MISSED PULSE
WATCHDOG PULSES
RESUMETIMEOUTTIMER RESTARTS
V+
LTC6995-1
OUTPUT
FALLING EDGE TRIGGERED
POL = 0
DIVCODE = 1
RST
GND
SET
OUT
V+
DIV
RSET
604k
R2
102k
R1
976k 0.1µF
V
+
699512 F17
LTC6993-1
RISING EDGE TRIGGERED
POSITIVE OUTPUT PULSE
DIVCODE = 1
50ms WATCHDOG TIMER100µs ONE SHOT
SYSTEM POSITIVE
WATCHDOG PULSE
TRG
GND
SET
OUT
V+
DIV
RSET
619k
V+
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
19
APPLICATIONS INFORMATION
Figure 18. Gated Oscillators. First One-Half Cycle Time Always Accurate
Gated Oscillators
The reset input (RST) clears all internal dividers so that,
when released, the output will start clocking with a full
programmed period. This edge can be used to gate the
output ON and OFF at a known starting point for the clock.
Circuits which count clock cycles for further timing pur-
poses will always have an accurate count of full cycles
until reset. The output clock is always at 50% duty cycle
and the period of each cycle can range from 1ms to 9.5
hours. Depending on the polarity bit selection the output
clock can start high or low as shown in Figure 18.
Self-Resetting Circuits
The RST pin has hysteresis to accommodate slow-changing
input voltages. Furthermore, the trip points are proportional
to the supply voltage (see Note 6 and the RST Threshold
Voltage vs Supply Voltage curve in Typical Performance
Characteristics). This allows an RC time constant at the
RST input to generate a delay that is nearly independent
of the supply voltage.
699512 F18
OUT
POL = 0
OUT
POL = 1
1/2 tOUT
1/2 tOUT
RST
LTC6995-2
ACTIVE LOW RESET
RST RISING EDGE STARTS THE CLOCK
OUT
POL = 0
OUT
POL = 1
1/2 tOUT
1/2 tOUT
RST
LTC6995-1
ACTIVE HIGH RESET
RST FALLING EDGE STARTS THE CLOCK
A simple application of this technique allows the LTC6995
output to reset itself, producing a well-controlled pulse
once each cycle. Figure 19a and Figure 19b show circuits
that produce approximately 1µs pulses once a minute.
The only difference is the version of LTC6995 used and
the POL bit setting, which controls whether the pulse is
positive or negative.
Voltage Controlled Frequency
With one additional resistor, the LTC6995 output frequency
can be manipulated by an external voltage. As shown in
Figure 20, voltage VCTRL sources/sinks a current through
RVCO to vary the ISET current, which in turn modulates the
output frequency as described in Equation (3).
f
MHzk
NR
R
R
V
V
OUT
DIV VCO
VCO
SET
CTRL
S
=+
150
1024 1
•
•• •–
Ω
EET
(3)
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
20
Digital Frequency Control
The control voltage can be generated by a DAC (digital-
to-analog converter), resulting in a digitally-controlled
frequency. Many DACs allow for the use of an external
reference. If such a DAC is used to provide the VCTRL
voltage, the VSET dependency can be eliminated by buffer-
ing VSET and using it as the DAC’s reference voltage, as
shown in Figure 21. The DAC’s output voltage now tracks
any VSET variation and eliminates it as an error source.
The SET pin cannot be tied directly to the reference input
of the DAC because the current drawn by the DAC’s REF
input would affect the frequency.
ISET Extremes (Master Oscillator Frequency Extremes)
When operating with ISET outside of the recommended
1.25µA to 20µA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
The oscillator can still function with reduced accuracy for
ISET < 1.25µA. At approximately 500nA, the oscillator output
will be frozen in its current state. The output could halt in
a high or low state. This avoids introducing short pulses
when frequency modulating a very low frequency output.
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
APPLICATIONS INFORMATION
699512 F20
LTC6995-1
RST
GND
SET
OUT
V+
DIV
R1
C1
0.1µF
R2
RSET
RVCO
V
CTRL
V+
Figure 19.
Figure 20. Voltage-Controlled Oscillator
LTC6995-1 2.25V TO 5.5V
0.1µF
OUT
R1
1M
R2
523k
RSET
178k
RST
GND
SET
OUT
V+
DIV
CPW
470pF
RPW
2.26k
699512 F19a
60 SECONDS
1µs PULSE WIDTH
VRST(RISING)
V+
tPULSE = –RPW • CPW • In
tPULSE ≈ –2.26kΩ • 470pF • In(1 – 0.61)
tPULSE ≈ 1µs
1–
( )
(a) Self-Resetting Circuit (DIVCODE = 5)
LTC6995-2 2.25V TO 5.5V
0.1µF
699512 F19b
OUT
R1
523k
R2
1M
60 SECONDS
0.9µs PULSE WIDTH
VRST(FALLING)
V+
tPULSE = –RPW • CPW • In
tPULSE ≈ –2.26kΩ • 470pF • In(0.43)
tPULSE ≈ 0.9µs
RSET
178k
RST
GND
SET
OUT
V+
DIV
CPW
470pF
RPW
2.26k
( )
(b) Self-Resetting Circuit (DIVCODE = 10)
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
21
Frequency Modulation and Settling Time
The LTC6995 will respond to changes in ISET up to a –3dB
bandwidth of 0.4 • fOUT .
Following a 2× or 0.5× step change in ISET
, the output
frequency takes less than one cycle to settle to within 1%
of the final value.
Power Supply Current
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under
any condition using the following equation. This equation
ignores CLOAD (valid for CLOAD < 1nF) and assumes the
output has 50% duty cycle.
IS(TYP) ≈V+• fMASTER • 7.8pF +V+
420kΩ+V+
2 •RLOAD
+1.8 •I
SET
+50µA
Supply Bypassing and PCB Layout Guidelines
The LTC6995 is a 2.2% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
APPLICATIONS INFORMATION
–
+
699512 F21
LTC6995-1
RST
GND
SET
OUT
V+
DIV
C1
0.1µF R1
R2
RSET
V+
RVCO
V+
0.1µF
1/2
LTC6078
LTC1659
V+
VCC REF
GND
VOUT
µP
DIN
CLK
CS/LD
1MHz • 50kΩ
1024 • NDIV • RVCO
fOUT =
DIN = 0 TO 4095
• 1 + –
RVCO
RSET
DIN
4096
(
)
0.1µF
Figure 21. Digitally-Controlled Oscillator
and by following a few rules, the expected performance is
easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Figure 21 shows example PCB layouts for both the TSOT-23
and DFN packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6995. These layouts are
a guide and need not be followed exactly.
1. Connect the bypass capacitor, C1, directly to the V+ and
GND pins using a low inductance path. The connection
from C1 to the V+ pin is easily done directly on the top
layer. For the DFN package, C1’s connection to GND is
also simply done on the top layer. For the TSOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
22
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place RSET as close as possible to the SET pin and
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
4. Connect RSET directly to the GND pin. Using a long path
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
699512 F22
LTC6995-1
RST
GND
SET
OUT
V+
DIV
C1
0.1µF R1
R2
RSET
V+
V+
DIV
SET
OUT
GND
RST
C1R1
R2
V+
RSET
DFN PACKAGE
RST
GND
SET
OUT
V+
DIV
R2
V
+
RSET
TSOT-23 PACKAGE
R1
C1
Figure 22. Supply Bypassing and PCB Layout
APPLICATIONS INFORMATION
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
23
TYPICAL APPLICATIONS
Timed Power Switches, Auto Shutoff After One Hour
LTC6995-1
ACTIVE HIGH RESET
1/2 tOUT = 1 HOUR
RST
GND
SET
OUT
V+
DIV
RSET
169k
100k
R2
887k
R1
1M
0.1µF
5V
5V
PUSH TO ACTIVATE
LOW = ON
HIGH = OFF
699512 TA08
VIN
GND
CTL
SENSE
GATE
STAT
LTC4412HV
P-CHANNEL
MOSFET
3V TO 36V
2.6V TO 5.5V
COUT
*
TO LOAD
CURRENT DEPENDS
ON PMOS SELECTION
*DRAIN-SOURCE DIODE OF MOSFET
0.1µF
IN
GND
CTL
OUT
STAT
LTC4411
TO LOAD
UP TO 2.6A
COUT
4.7µF
1µF
5 Second On/Off Timed Relay Driver
R1
1M
R4
10k
RUN
RESET
D1
1N4148
12V
NO
COTO 1022 RELAY
9001-12-01
L
C2
0.1µF
0.1µF
Q1
2N2219A
R2
392k
699512 TA02
R3
118k
5V
RELAY ENABLE
C
1
LTC6995-1
RST
GND
SET
OUT
V+
DIV
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
24
TYPICAL APPLICATIONS
1.5ms Radio Control Servo Reference Pulse Generator
RESET = OPEN
RUN = GND
20ms
FRAME RATE
GENERATOR
1.5ms
REFERENCE
PULSE
5V
20ms PERIOD
5V
R4
976k
R7
10k
C1
0.01µF
R5
102k
R6
121k
1.5ms PULSE
699512 TA03
LTC6995-1
RST
GND
SET
OUT
V+
DIV
5V
R1
1M
C2
0.1µF
R2
280k
R3
146k
LTC6993-1
TRIG
GND
SET
OUT
V+
DIV
Cycling (10 Seconds On/Off) Symmetrical Power Supplies
R8
1M
R2
1k
R11
5k
R3
50k
R6
20k
–15VIN –15VOUT
C1
0.1µF
R9
392k R1
100k
M4
Si4435DY
M3
Si9410
M1
Si9410
15VIN 15V
OUT
M2
Si4435DY
699512 TA04
R10
237k
5V
LTC6995-1
RST
GND
SET
OUT
V+
DIV
Isolated AC Load Flasher
LTC6995-1
GND
SET
RSET
237k
V+
0.1µF
5V
5V
RST
5
2
10 SECONDS ON/OFF
6 6
4
2
1
43
1OUT
DIV
R3
10k
OPEN = OFF
GND = ON
R2
392k
R5
5.94k
U3
NTE5642
ISOLATION BARRIER = 7500V
HOT
117V AC
NEUTRAL
AC
R6
10k
R4
215Ω
R1
1M
C2
0.022µF
ZERO
CROSSING
U2
MOC3041M
R7
100Ω
40W LAMP
699512 TA05
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
25
TYPICAL APPLICATIONS
Interval (Wiper) Timer
LTC6995-1
0.1µF
2s
2s
5s
5s
15s
30s
1m
2m
4m
4m
OFF
24.9k
178k
59k
90.9k
29.4k
1M
V+
RST
GND
SET
OUT
V+
DIV
LTC6993-1
0.1µF
OUTPUT
1M tINTERVAL
2 SECONDS TO
4 MINUTES
V+
2s
TRIG
GND
SET
OUT
V+
DIV
681k
699512 TA06
383k 2s
2s
5s
15s
30s
5V
1m
2m
4m OFF
V+
15s
30s
1m
2m
OFF
280k
113k
133k
154k
Adjustable Time Lapse Photography Intervalometer
LTC6993-3
OUTPUT
NON-RETRIGGERABLE
ONE SHOT TIMER
0.3s TO 30s
EXPOSURE TIMETIME LAPSE
TIME LAPSE
SHUTTER
OPEN
TIME LAPSE
TRG
GND
SET
OUT
V+
DIV
56.2k 1M
681k
V+
699512 TA09
LTC6995-1
LONG TIMER
3s TO 3Hrs
RST
GND
SET
OUT
V+
DIV
V+
0.1µF
887k
1M
0.3s TO
3s
3s TO
30s
523k 681k
967k
30s TO
3m
3m TO
30m
30m TO
3Hrs
3s TO
30s
2M
1M
LONG
SHORT
66.5k
1M 2M
LONG
SHORT
392k
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
26
PACKAGE DESCRIPTION
3.00 ±0.10
(2 SIDES)
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
1.35 ±0.10
(2 SIDES)
1
3
64
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DCB6) DFN 0405
0.25 ±0.05
0.50 BSC
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
0.25 ±0.05
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)
2.15 ±0.05
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.50 BSC
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MA
X
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
27
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 09/13 Grammatical corrections
Correction to Master Oscillator, Block Diagram
DIVCODE changed from 4 to 5, Figure 19a
DIVCODE changed from 11 to 10, Figure 19b
LTC6995 block identified as LTC6995-1, Figure 21 and Figure 22
Replace V+ with 5V, Sentry Time schematic
1, 4, 8, 16
8
20
20
21, 22
28
B 12/19 Added AEC-Q100 Qualified Note to Front Page
Added W Grade Order Information
1
3
LTC6995-1/LTC6995-2
Rev. B
For more information www.analog.com
28
www.analog.com
ANALOG DEVICES, INC. 2013–2019
12/19
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LTC6992 TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM) Simple PWM with Wide Frequency Range
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LTC6994 TimerBlox: Delay Block/Debouncer Delays Rising, Falling or Both Edges 1µs to 34sec
Sentry Timer
699512 TA07
R2
49.9k 60.4k
800Hz
ALARM TONE
DIVCODE = 0
4 HOUR TIMER
DIVCODE = 7
PUSH BUTTON
EVERY 4 HOURS OR
ALARM SOUNDS LTC6995-2
RST
GND
SET
OUT
V+
DIV
FF
QCLK
CLR
Q D
100k
R1
887k
5V
5V
5V
5V
75k 332k
15Ω
32Ω