© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 3 1Publication Order Number:
NCV890100/D
NCV890100
1.2 A, 2 MHz Automotive
Buck Switching Regulator
The NCV890100 is a fixed−frequency, monolithic, Buck switching
regulator intended for Automotive, battery−connected applications
that must operate with up to a 36 V input supply. The regulator is
suitable for systems with low noise and small form factor
requirements often encountered in automotive driver information
systems. The NCV890100 is capable of converting the typical 4.5 V t o
18 V automotive input voltage range to outputs as low as 3.3 V at a
constant switching frequency above the sensitive AM band,
eliminating the need for costly filters and EMI countermeasures. The
NCV890100 also provides several protection features expected in
Automotive power supply systems such as current limit, short circuit
protection, and thermal shutdown. In addition, the high switching
frequency produces low output voltage ripple even when using small
inductor values and an all−ceramic output filter capacitor − forming a
space−efficient switching regulator solution.
Features
•Internal N−Channel Power Switch
•Low VIN Operation Down to 4.5 V
•High VIN Operation to 36 V
•Withstands Load Dump to 40 V
•2 MHz Free−running Switching Frequency
•Logic Level Enable Input Can be Directly Tied to Battery
•1.4 A (min) Cycle−by−Cycle Peak Current Limit
•Short Circuit Protection Enhanced by Frequency Foldback
•±1.75% Output Voltage Tolerance
•Output Voltage Adjustable Down to 0.8 V
•1.4 Millisecond Internal Soft−Start
•Thermal Shutdown (TSD)
•Low Shutdown Current
•Wettable Flanks DFN
•NCV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change
Requirements; AEC−Q100 Qualified and PPAP Capable
•These Devices are Pb−Free and are RoHS Compliant
Applications
•Audio
•Infotainment
•Safety − Vision Systems
•Instrumentation
VIN
DRV
GND
EN
SW
BST
FB
COMP
VIN
EN
VOUT
CIN CBST
DBST
DFW
RCOMP CCOMP
COUT
L1
CDRV
NCV890100
RFB2
RFB1
1
2
3
45
6
7
8
Figure 1. Typical Application
DFN8
CASE 506BY
MARKING
DIAGRAMS
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Device
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(Note: Microdot may be in either location)
V8901
00
ALYWG
G
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
ORDERING INFORMATION
1
SOIC−8 EP
CASE 751AC
1
8
1
8
NCV890100
ALYWX
G
NCV890100
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2
Figure 2. NCV890100 Block Diagram
VIN
DRV
GND
EN
SW
BST
FB
COMP
VIN
Enable
CIN CBST
DBST
DFW
RCOMP
CCOMP
COUT
L1
CDRV
PWM
LOGIC
OFF
ON
+
−
S
Oscillator
+
−
Soft−Start
RESET
3 V
Reg
VOLTAGES
MONITORS
TSD
+
+
+
1.2 A
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MAXIMUM RATINGS
Rating Symbol Value Unit
Min/Max Voltage VIN −0.3 to 40 V
Max Voltage VIN to SW 40 V
Min/Max Voltage SW −0.7 to 40 V
Min Voltage SW − 20ns −3.0 V
Min/Max Voltage BST −0.3 to 40
Min/Max Voltage BST to SW −0.3 to 3.6 V
Min/Max Voltage on EN −0.3 to 40 V
Min/Max Voltage COMP −0.3 to 2 V
Min/Max Voltage FB −0.3 to 18 V
Min/Max Voltage DRV −0.3 to 3.6 V
Thermal Resistance, 3x3 DFN Junction−to−Ambient* RqJA 50 °C/W
Thermal Resistance, SOIC−8 EP Junction−to−Ambient* RqJA 40 °C/W
Storage Temperature range −55 to +150 °C
Operating Junction Temperature Range TJ−40 to +150 °C
ESD withstand Voltage Human Body Model
Machine Model
Charge Device Model
VESD 2.0
200
>1.0
kV
V
kV
Moisture Sensitivity, DFN8 MSL Level 1
Moisture Sensitivity, SOIC−8 EP MSL Level 2
Peak Reflow Soldering Temperature 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
*Mounted on 1 sq. in. of a 4−layer PCB with 1 oz. copper thickness.
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Figure 3. Pin Connections
1
VIN SW
2
DRV
3
4
GND
BST
8
7
FB
(Top View)
5
EN
6
COMP
1
VIN SW
2
DRV 3
4
GND
BST
8
7
FB
(Top View)
5
EN
6
COMP
PIN FUNCTION DESCRIPTIONS
Pin No. Symbol Description
1 VIN Input voltage from battery. Place an input filter capacitor in close proximity to this pin.
2 DRV Output voltage to provide a regulated voltage to the Power Switch gate driver.
3 GND Battery return, and output voltage ground reference.
4 EN This TTL compatible Enable input allows the direct connection of Battery as the enable signal. Grounding
this input stops switching and reduces quiescent current draw to a minimum.
5 COMP Error Amplifier output, for tailoring transient response with external compensation components.
6 FB Feedback input pin to program output voltage, and detect pre−charged or shorted output conditions.
7 BST Bootstrap input provides drive voltage higher than VIN to the N−channel Power Switch for optimum
switch RDS(on) and highest efficiency.
8 SW Switching node of the Regulator. Connect the output inductor and cathode of the freewheeling diode to
this pin.
Exposed
Pad Connect to Pin 3 (electrical ground) and to a low thermal resistance path to the ambient temperature
environment.
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ELECTRICAL CHARACTERISTICS (VIN = 4.5 V to 28 V, VEN = 5 V, VBST = VSW + 3.0 V, CDRV = 0.1 mF, Min/Max values are valid
for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
Parameter Symbol Conditions Min Typ Max Unit
QUIESCENT CURRENT
Quiescent Current, shutdown IqSD VIN = 13.2 V, VEN = 0 V, TJ = 25°C5mA
Quiescent Current, enabled IqEN VIN = 13.2 V 3 mA
UNDERVOLTAGE LOCKOUT − VIN (UVLO)
UVLO Start Threshold VUVLSTT VIN rising 4.1 4.5 V
UVLO Stop Threshold VUVLSTP VIN falling 3.9 4.4 V
UVLO Hysteresis VUVLOHY 0.1 0.2 V
ENABLE (EN)
Logic Low VENLO 0.8 V
Logic High VENHI 2 V
Input Current IEN 8 30 mA
SOFT−START (SS)
Soft−Start Completion Time tSS 0.8 1.4 2.0 ms
VOLTAGE REFERENCE
FB Pin Voltage during regulation VFBR COMP shorted to FB 0.786 0.8 0.814 V
ERROR AMPLIFIER
FB Bias Current IFBBIAS VFB = 0.8 V 0.25 1 mA
Transconductance gm
gm(HV)
VCOMP = 1.3 V
4.5 V < VIN < 18 V
20 V < VIN < 28 V 0.6
0.3 1
0.5 1.5
0.75
mmho
Output Resistance ROUT 1.4 MW
COMP Source Current Limit ISOURCE VFB = 0.63 V, VCOMP = 1.3 V
4.5 V < VIN < 18 V
20 V < VIN < 28 V 75
40
mA
COMP Sink Current Limit ISINK VFB = 0.97 V, VCOMP = 1.3 V
4.5 V < VIN < 18 V
20 V < VIN < 28 V 75
40
mA
Minimum COMP voltage VCMPMIN VFB = 0.97 V 0.2 0.7 V
OSCILLATOR
Frequency FSW
FSW(HV) 4.5 < VIN < 18 V
20 V < VIN < 28 V 1.8
0.9 2.0
1.0 2.2
1.1 MHz
VIN FREQUENCY FOLDBACK MONITOR
Frequency Foldback Threshold
VIN rising
VIN falling VFLDUP
VFLDDN
VFB = 0.63 V 18.4
18 20
19.8
V
Frequency Foldback Hysteresis VFLDHY 0.2 0.3 0.4 V
SLOPE COMPENSATION
Ramp Slope (Note 1)
(With respect to switch current) Sramp
Sramp(HV) 4.5 < VIN < 18 V
20 V < VIN < 28 V 0.7
0.25 1.3
0.6 A/ms
1. Not tested in production. Limits are guaranteed by design.
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ELECTRICAL CHARACTERISTICS (VIN = 4.5 V to 28 V, VEN = 5 V, VBST = VSW + 3.0 V, CDRV = 0.1 mF, Min/Max values are valid
for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
Parameter UnitMaxTypMinConditionsSymbol
POWER SWITCH
ON Resistance RDSON VBST = VSW + 3.0 V 650 mW
Leakage current VIN to SW ILKSW VEN = 0 V, VSW = 0, VIN = 18 V 10 mA
Minimum ON Time tONMIN Measured at SW pin 45 70 ns
Minimum OFF Time tOFFMIN Measured at SW pin
At FSW = 2 MHz (normal)
At FSW = 500 kHz (max duty cycle) 30 30
50 70
ns
PEAK CURRENT LIMIT
Current Limit Threshold ILIM 1.4 1.55 1.7 A
SHORT CIRCUIT FREQUENCY FOLDBACK
Lowest Foldback Frequency
Lowest Foldback Frequency − High Vin
Hiccup Mode
FSWAF
FSWAFHV
FSWHIC
VFB = 0 V, 4.5 V < VIN < 18 V
VFB = 0 V, 20 V < VIN < 28 V
VFB = 0 V
400
200
24
500
250
32
600
300
40
kHz
GATE VOLTAGE SUPPLY (DRV pin)
Output Voltage VDRV 3.1 3.3 3.5 V
DRV POR Start Threshold VDRVSTT 2.7 2.9 3.05 V
DRV POR Stop Threshold VDRVSTP 2.5 2.8 3.0 V
DRV Current Limit IDRVLIM VDRV = 0 V 16 45 mA
OUTPUT PRECHARGE DETECTOR
Threshold Voltage VSSEN 20 35 50 mV
THERMAL SHUTDOWN
Activation Temperature (Note 1) TSD 150 190 °C
Hysteresis (Note 1) THYS 5 20 °C
1. Not tested in production. Limits are guaranteed by design.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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TYPICAL CHARACTERISTICS CUR VES
0
1
2
3
4
5
6
7
8
−50 −25 0 25 50 75 100 125 150
TJ. JUNCTION TEMPERATURE (°C)
IqSD. SHUTDOWN QUIESCENT CURRENT
(mA)
Figure 4. Shutdown Quiescent Current vs.
Junction Temperature
VIN = 13.2 V
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
−50 −25 0 25 50 75 100 125 150
TJ. JUNCTION TEMPERATURE (°C)
IqEN. ENABLED QUIESCENT CURRENT
(mA)
Figure 5. Enabled Quiescent Current vs.
Junction Temperature
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
−50 −25 0 25 50 75 100 125 150
TJ. JUNCTION TEMPERATURE (°C)
VUVLSTT. UVLO START THRESHOLD (V)
Figure 6. UVLO Start Threshold vs. Junction
Temperature
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
−50 −25 0 25 50 75 100 125 150
TJ. JUNCTION TEMPERATURE (°C)
VUVLSTP. UVLO STOP THRESHOLD (V)
Figure 7. UVLO Stop Threshold vs. Junction
Temperature
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
−50 −25 0 25 50 75 100 125 150
TJ. JUNCTION TEMPERATURE (°C)
tSS. SOFT−START DURATION (ms)
Figure 8. Soft−Start Duration vs. Junction
Temperature
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
−50 −25 0 25 50 75 100 125 150
VFBR. FB REGULATION VOLTAGE (V)
TJ. JUNCTION TEMPERATURE (°C)
Figure 9. FB Regulation Voltage vs. Junction
Temperature
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TYPICAL CHARACTERISTICS CUR VES
0.2
0.4
0.6
0.8
1.0
1.2
1.4
−50 −25 0 25 50 75 100 125 150
TJ. JUNCTION TEMPERATURE (°C)
g
m
. ERROR AMPLIFIER
TRANSCONDUCTANCE (mS)
Figure 10. Error Amplifier Transconductance
vs. Junction Temperature
VIN = 4.5 V
VIN = 28 V
20
30
40
50
60
70
80
90
100
−50 −25 0 25 50 75 100 125 15
0
TJ. JUNCTION TEMPERATURE (°C)
ISOURCE. ERROR AMPLIFIER
SOURCING CURRENT (mA)
Figure 11. Error Amplifier Max Sourcing
Current vs. Junction Temperature
VIN = 4.5 V
VIN = 28 V
20
30
40
50
60
70
80
90
100
−50 −25 0 25 50 75 100 125 150
TJ. JUNCTION TEMPERATURE (°C)
I
SINK
. ERROR AMPLIFIER SINKING
CURRENT (mA)
Figure 12. Error Amplifier Max Sinking Current
vs. Junction Temperature
VIN = 4.5 V
VIN = 28 V
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
−50 −25 0 25 50 75 100 125 15
0
TJ. JUNCTION TEMPERATURE (°C)
FSW. OSCILLATOR FREQENCY (MHz)
Figure 13. Oscillator Frequency vs. Junction
Temperature
VIN = 13.2 V
VIN = 28 V
18.2
18.4
18.6
18.8
19.0
19.2
19.4
19.6
−50 −25 0 25 50 75 100 125 150
TJ. JUNCTION TEMPERATURE (°C)
V
FLDUP
. V
FLDDN
, FREQ. FOLDBACK
THRESHOLD (V)
Figure 14. Rising Frequency Foldback
Threshold vs. Junction Temperature Figure 15. Power Switch RDS(on) vs. Junction
Temperature
VFLDUP
VFLDDN
0
100
200
300
400
500
600
700
800
900
−50 −25 0 25 50 75 100 125
0
15
RDS(on). POWER SWITCH ON
RESISTANCE (mW)
TJ. JUNCTION TEMPERATURE (°C)
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TYPICAL CHARACTERISTICS CUR VES
Figure 16. Minimum On Time vs. Junction
Temperature Figure 17. Minimum Off Time vs. Junction
Temperature
40
45
50
55
60
65
70
75
80
−50 −25 0 25 50 75 100 125 150
t
ONMIN
. MINIMUM TIME (ns)
TJ. JUNCTION TEMPERATURE (°C)
Figure 18. Current Limit Threshold vs.
Junction Temperature
35
40
45
50
55
60
65
70
75
−50 −25 0 25 50 75 100 125 15
0
tOFFMIN. MINIMUM TIME (ns)
TJ. JUNCTION TEMPERATURE (°C)
Figure 19. Short−Circuit Foldback Frequency
vs. Junction Temperature
1.40
1.45
1.50
1.55
1.60
1.65
1.70
−50 −25 0 25 50 75 100 125 150
I
LIM
. MINIMUM TIME (ns)
TJ. JUNCTION TEMPERATURE (°C)
Figure 20. Hiccup Mode Switching Frequency
vs. Junction Temperature
200
250
300
350
400
450
500
550
600
−50 −25 0 25 50 75 100 125 15
0
FSWAF. FOLDBACK MODE
SWITCHING FREQUENCY (kHz)
TJ. JUNCTION TEMPERATURE (°C)
Figure 21. DRV Voltage vs. Junction
Temperature
VIN = 4.5 V
VIN = 28 V
24
26
28
30
32
34
36
38
40
−50 −25 0 25 50 75 100 125 150
F
SWHC
. HICCUP MODE FREUQNCY
(kHz)
TJ. JUNCTION TEMPERATURE (°C)
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
−50 −25 0 25 50 75 100 125 15
0
VDRV. DRV VOLTAGE (V)
TJ. JUNCTION TEMPERATURE (°C)
IDRV = 0 mA
IDRV = 16 mA
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TYPICAL CHARACTERISTICS CUR VES
Figure 22. DRV Reset Threshold vs. Junction
Temperature
2.5
2.6
2.7
2.8
2.9
3.0
3.1
−50 −25 0 25 50 75 100 125 150
VDRVSTT. VDRVSTP, DRV RESET
THRESHOLDS (V)
TJ. JUNCTION TEMPERATURE (°C) Figure 23. DRV Current Limit vs. Junction
Temperature
VDRVSTT
VDRVSTP
21
22
23
24
25
26
27
28
29
30
−50 −25 0 25 50 75 100 125 150
IDRVLIM. DRV CURRENT LIMIT (mA)
20
25
30
35
40
45
50
55
−50 −25 0 25 50 75 100 125 150
VSSEN. OUTPUT PRECHARGE
DETECTOR THRESHOLD (V)
TJ. JUNCTION TEMPERATURE (°C)
Figure 24. Output Precharge Detector
Threshold vs. Junction Temperature
TJ. JUNCTION TEMPERATURE (°C)
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GENERAL INFORMATION
INPUT VOLTAGE
An Undervoltage Lockout (UVLO) circuit monitors the
input, and inhibits switching and resets the Soft−start circuit
if there is insufficient voltage for proper regulation. The
NCV890100 can regulate a 3.3 V output with input voltages
above 4.5 V and a 5.0 V output with an input above 6.5 V.
The NCV890100 withstands input voltages up to 40 V.
To limit the power lost in generating the drive voltage for
the Power Switch, the switching frequency is reduced by a
factor of 2 when the input voltage exceeds the VIN
Frequency Foldback threshold VFLDUP (see Figure 25).
Frequency reduction is automatically terminated when the
input voltage drops back below the VIN Frequency Foldback
threshold VFLDDN.
41820 36
VIN (V
)
1
2
Fsw
(MHz)
Figure 25. NCV890100 Switching Frequency
Reduction at High Input Voltage
ENABLE
The NCV890100 is designed to accept either a logic level
signal o r battery voltage as an Enable signal. EN low induces
a ’sleep mode’ which shuts off the regulator and minimizes
its supply current to a couple of mA typically (IqSD) by
disabling all functions. Upon enabling, voltage is
established at the DRV pin, followed by a soft−start of the
switching regulator output.
SOFT−START
Upon being enabled or released from a fault condition,
and after the DRV voltage is established, a soft−start circuit
ramps the switching regulator error amplifier reference
voltage to the final value. During soft−start, the average
switching frequency is lower than its normal mode value
(typically 2 MHz) until the output voltage approaches
regulation.
SLOPE COMPENSATION
A fixed slope compensation signal is generated internally
and added to the sensed current to avoid increased output
voltage ripple due to bifurcation of inductor ripple current
at duty cycles above 50%. The fixed amplitude of the slope
compensation signal requires the inductor to be greater than
a minimum value, depending on output voltage, in order to
avoid sub−harmonic oscillations. For 3.3 V and 5 V output
voltages, the recommended inductor value is 4.7 mH.
SHORT CIRCUIT FREQUENCY FOLDBACK
During severe output overloads or short circuits, the
NCV890100 automatically reduces its switching frequency.
This creates duty cycles small enough to limit the peak
current in the power components, while maintaining the
ability to automatically reestablish the output voltage if the
overload is removed. If the current is still too high after the
switching frequency folds back to 500 kHz, the regulator
enters an auto−recovery burst mode that further reduces the
dissipated power.
CURRENT LIMITING
Due to the ripple on the inductor current, the average
output current of a buck converter is lower than the peak
current setpoint of the regulator. Figure 26 shows − for a
4.7 mH inductor − how the variation of inductor peak current
with input voltage affects the maximum DC current the
NCV890100 can deliver to a load.
Figure 26. NCV890100 Load Current Capability
with 4.7 mH Inductor
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
MINIMUM CURRENT LIMIT (A)
(5 VOUT)
(3.3 VOUT)
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BOOTSTRAP
At the DRV pin an internal regulator provides a
ground−referenced voltage to an external capacitor ( C DRV),
to allow fast recharge of the external bootstrap capacitor
(CBST) used to supply power to the power switch gate driver .
If the voltage at the DRV pin goes below the DRV UVLO
Threshold VDRVSTP, switching is inhibited and the
Soft−start circuit is reset, until the DRV pin voltage goes
back up above VDRVSTT.
In order for the bootstrap capacitor to stay charged, the
Switch node needs to be pulled down to ground regularly. In
very light load condition, the NCV890100 skips switching
cycles t o ensure the output voltage stays regulated. When the
skip cycle repetition frequency gets too low, the bootstrap
voltage collapses and the regulator stops switching.
Practically, this means that the NCV890100 needs a
minimum load to operate correctly. Figure 27 shows the
minimum current requirements for different input and
output voltages.
INPUT VOLTAGE (V)
9.28.27.26.25.24.2
0
10
20
30
40
50
MINIMUM OUTPUT CURRENT (mA)
Minimum Load 5 V Out
INPUT VOLTAGE (V)
7.26.76.25.75.24.74.2
0
2
4
8
12
14
MINIMUM OUTPUT CURRENT (mA)
Minimum Load 3.3 V Out
6
10
16
INPUT VOLTAGE (V)
7.26.76.25.24.74.2
0
4
8
12
16
20
MINIMUM OUTPUT CURRENT (mA)
Minimum Load 3.7 V Out
INPUT VOLTAGE (V)
10.28.26.24.2
0
5
10
25
35
45
MINIMUM OUTPUT CURRENT (mA)
Minimum Load 5.5 V Out
15
30
50
Figure 27. Minimum Load Current with Different Input and Output Voltages
L = 2.2 mH
L = 4.7 mH
L = 2.2 mH
L = 4.7 mH
5.7
2
6
10
14
18
L = 2.2 mH
L = 4.7 mH
L = 2.2 mH
L = 4.7 mH
20
40
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OUTPUT PRECHARGE DETECTION
Prior to Soft−start, the FB pin is monitored to ensure the
SW voltage is low enough to have charged the external
bootstrap capacitor (CBST). If the FB pin is higher than
VSSEN, restart is delayed until the output has discharged.
Figure 28 shows the IC starts to switch after the voltage on
FB pin reaches VSSEN, even the EN pin is high. After the
IC is switching, the FB pin follows the soft starts reference
to reach the final set point.
Figure 28. Output Voltage Detection
EN
FB
SW
Time
Time
Time
VSSEN
THERMAL SHUTDOWN
A thermal shutdown circuit inhibits switching, resets the
Soft−start circuit, and removes DRV voltage if internal
temperature exceeds a safe level. Switching is automatically
restored when temperature returns to a safe level.
MINIMUM DROPOUT VOLTAGE
When operating at low input voltages, two parameters
play a major role in imposing a minimum voltage drop
across the regulator: the minimum off time (that sets the
maximum duty cycle), and the on state resistance.
When operating in continuous conduction mode (CCM),
the output voltage is equal to the input voltage multiplied by
the duty ratio. Because the NCV890100 needs a sufficient
bootstrap voltage to operate, its duty cycle cannot be 100%:
it needs a minimum off time (tOFFmin) to periodically re−fuel
the bootstrap capacitor CBST. This imposes a maximum duty
ratio DMAX = 1 − tOFFmin.FSW(min), with the switching
frequency being folded back down to FSW(min) = 500 kHz to
keep regulating at the lowest input voltage possible.
The drop due to the on−state resistance is simply the
voltage drop across the Switch resistance RDSON at the
given output current: VSWdrop = IOUT.RDSon.
Which leads to the maximum output voltage in low Vin
condition: VOUT = DMAX.VIN(min) − VSWdrop
EXPOSED PAD
The exposed pad (EPAD) on the back of the package must
be electrically connected t o the electrical ground (GND pin)
for proper, noise−free operation.
DESIGN METHODOLOGY
The NCV890100 being a fixed−frequency regulator with
the switching element integrated, is optimized for one value
of inductor. This value is set to 4.7 mH, and the slope
compensation is adjusted for this inductor. The only
components left to be designed are the input and output
capacitor and the freewheeling diode. Please refer to the
design spreadsheet www.onsemi.com NCV890100 page
that helps with the calculation.
Output capacitor:
The minimum output capacitor value can be calculated
based on the specification for output voltage ripple:
COUTmin +
DIL
8@DVOUT @FSW (eq. 1)
With
−DIL the inductor ripple current:
DIL+
VOUT @ǒ1*
VOUT
VIN Ǔ
L@FSW
(eq. 2)
−DVOUT the desired voltage ripple.
However, the ESR of the output capacitor also contributes
to the output voltage ripple, so to comply with the
requirement, the ESR cannot exceed RESRmax:
RESRmax +
DVOUT @L@FSW
VOUTǒ1*VOUT
VIN Ǔ(eq. 3)
Finally, the output capacitor must be able to sustain the ac
current (or RMS ripple current):
IOUTac +
DIL
23
Ǹ(eq. 4)
Typically, with the recommended 4.7 mH inductor, two
ceramic capacitors of 10 mF each in parallel give very good
results.
Freewheeling diode:
The diode must be chosen according to its maximum
current and voltage ratings, and to thermal considerations.
As far as max ratings are concerned, the maximum reverse
voltage the diode sees is the maximum input voltage (with
some ma rgin in case of ringing on the Switch node), and the
maximum forward current the peak current limit of the
NCV890100, ILIM.
The power dissipated in the diode is PDloss:
PDloss +IOUT @ǒ1*VOUT
VIN Ǔ@VF)IDRMS @RD(eq. 5)
NCV890100
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14
with:
−I
OUT the average (dc) output current
−V
F the forward voltage of the diode
−I
DRMS the RMS current in the diode:
IDRMS +(1*D)ǒIOUT 2)
DIL2
12 Ǔ
Ǹ(eq. 6)
−R
D the dynamic resistance of the diode (extracted from
the V/I curve of the diode in its datasheet).
Then, knowing the thermal resistance of the package and
the amount of heatsinking on the PCB, the temperature rise
corresponding to this power dissipation can be estimated.
Input capacitor:
The input capacitor must sustain the RMS input ripple
current IINac:
IINac +
DIL
2D
3
Ǹ(eq. 7)
It can be designed in combination with an inductor to build
an input filter to filter out the ripple current in the source, in
order to reduce EMI conducted emissions.
For example, using a 4.7 mH input capacitor, it is easy to
calculate that an inductor of 200 nH will ensure that the
input filter has a cut−off frequency below 200 kHz (low
enough to attenuate the 2 MHz ripple).
Error Amplifier and Loop Transfer Function
The error amplifier is a transconductance type amplifier.
The output voltage of the error amplifier controls the peak
inductor current at which the power switch shuts off. The
Current Mode control method employed allows the use of a
simple, type II compensation to optimize the dynamic
response according to system requirements.
Figure 29 shows the error amplifier with the
compensation components and the voltage feedback divider .
gm * V
Vref
VOUT
RFB1
RFB2RO
RCOMP
CCOMP
Cp
VFB
V
VCOMP
Figure 29. Feedback Compensator Network Model
The transfer function from VOUT to VCOMP is the
product of the feedback voltage divider and the error
amplifier.
Gdivider(s) +RFB2
RFB1 )RFB2 (eq. 8)
Gerramp(s) +gm @Ro @1)s
wz
ǒ1)s
wplǓǒ1)s
wphǓ(eq. 9)
wz+1
RCOMP @CCOMP (eq. 10)
wpl +1
Ro @CCOMP (eq. 11)
wph +1
RCOMP @Cp (eq. 12)
The output resistor Ro of the error amplifier is 1.4 MW and
gm is 1 mA/V. The capacitor Cp is for rejecting noise at high
frequency and is integrated inside the IC with a value of
18 pF.
The power stage transfer function (from Vcomp to output)
is shown below:
Gps(s) +Rload
Ri @1
1)Rload@Tsw
L@[Mc @(1 *D) *0.5]@1)s
wz
1)s
wp@Fh(s) (eq. 13)
wp+1
Resr @Cout (eq. 14)
wp+1
Rload @Cout )Mc @(1 *D) *0.5
L@Cout @Fsw (eq. 15)
NCV890100
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15
where
Mc +1)Se
Sn (eq. 16)
Sn +Vin *Vout
L@Ri (eq. 17)
Ri represents the equivalent sensing resistor which has a
value of 0.29 W, Se is the compensation slope which is
291.9 kV/S, Sn is the slope of the sensing resistor current
during on time. Fh(s) represents the sampling ef fect from the
current loop which has two poles at one half of the switching
frequency:
Fh(s) +1
1)s
wn@Qp )s2
wn2
(eq. 18)
wn+p@Fsw
Qp +1
p@[Mc @(1 *D) *0.5](eq. 19)
The total loop transfer function is the product of power
stage and feedback compensation network.
Gloop(s) +Gdivider(s) @Gerramp(s) @Gps(s) (eq. 20)
The bode plots of the open loop transfer function will
show the gain and phase margin of the system. The
compensation network is designed to make sure the system
has enough phase margin and bandwidth.
Design of the Compensation Network
The function of the compensation network is to provide
enough phase margin at crossover frequency to stabilize the
system as well as to provide high gain at low frequency to
eliminate the steady state error of the output voltage. Please
refer to the design spreadsheet www.onsemi.com
NCV890100 page that helps with the calculation.
The design steps will be introduced through an example.
Example:
Vin = 15.5 V, Vout = 3.3 V, Rload = 2.75 W, Iout = 1.2 A,
L = 4.7 mH, Cout = 20 mF (Resr = 7 mW)
The reference voltage of the feedback signal is 0.8 V and
to meet the minimum load requirements, select RFB1 =
100 W, RFB2 = 31.6 W.
From the specification, the power stage transfer function c a n
be plotted as below:
100 110
3
⋅110
4
⋅110
5
⋅110
6
⋅
90−
45−
0
45
90
180−
90−
0
90
180
(Hz)
(dB)
20 log Gps f m()
⎣⎣⎦
‧arg Gps fm
()()
180
p
‧
fm
Figure 30. Power Stage Bode Plots
The crossover frequency is chosen to be Fc = 70 kHz, the
power stage gain at this frequency is −8 dB (0.398) from
calculation. Then the gain of the feedback compensation
network must be 8 dB. Next is to decide the locations of one
zero and one pole of the compensator. The zero is to provide
phase boost at the crossover frequency and the pole is to
reject the noise of high frequency. In this example, a zero is
placed a t 1/10 of the crossover frequency and a pole is placed
at 1/5 of the switching frequency (Fsw = 2 MHz):
Fz = 7000 Hz, Fp = 400000 Hz,
RCOMP, CCOMP and Cp can be calculated from the
following equations:
RCOMP +Fp @gm
(Fp *Fz) @|Gps(Fc)|@Vout
Vref @
1)ǒFc
FpǓ2
Ǹ
1)ǒFz
FcǓ2
Ǹ
(eq. 21)
CCOMP +1
2p@Fz @RCOMP (eq. 22)
Cp +1
2p@Fp @RCOMP (eq. 23)
Note: there is an 18 pF capacitor at the output of the OTA
integrated in the IC, and if a larger capacitor needs to be
used, subtract this value from the calculated Cp. Figure 31
shows C p i s split into two capacitors. Cint is the 18 pF in the
IC. Cext is the extra capacitor added outside the IC.
NCV890100
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16
From the calculation:
RCOMP = 10.6 KW, CCOMP = 2 nF, Cp = 37 pF
So the feedback compensation network is as below:
Figure 31. Example of the Feedback Compensation Network
Vref
VOUT
RFB1
RFB2 RO
RCOMP
CCOMP
Cint
VFB
V
VCOMP
31.6 W
0.8 V
18 pF 10 KW
2 nF
Cext
19 pF
100 W
gm*V
Figure 32 shows the bode plot of the OTA compensator
100 110
3
⋅110
4
⋅110
5
⋅110
6
⋅
90−
45−
0
45
90
180−
90−
0
90
180
(Hz)
(dB)
20 log Gerr_amp f m()
⎣⎦⎣⎦
‧arg Gerr_amp fm
()()
180
p
‧
fm
Figure 32. Bode Plot of the OTA Compensator
The total loop bode plot is as below:
100 110
3
⋅110
4
⋅110
5
⋅110
6
⋅
90−
45−
0
45
90
180−
90−
0
90
180
(Hz)
(dB)
20 log Gloop f m()
⎣⎦⎣⎦
‧arg Gloop fm
()()
180
p
‧
fm
Figure 33. Bode Plot of the Total Loop
The crossover frequency is at 70 KHz and phase margin is 75 degrees.
NCV890100
http://onsemi.com
17
PCB LAYOUT RECOMMENDATION
As with any switching power supplies, there are some
guidelines to follow to optimize the layout of the printed
circuit board for the NCV890100. However, because of the
high switching frequency extra care has to be taken.
− Minimize the area of the power current loops:
♦Input capacitor ³ NCV890100 switch ³ Inductor
³ output capacitor ³ return through Ground
♦Freewheeling diode ³ inductor ³ Output capacitor
³ return through ground
− Minimize the length of high impedance signals, and
route them far away from the power loops:
♦Feedback trace
♦Comp trace
ORDERING INFORMATION
Device Package Shipping†
NCV890100MWTXG DFN8 with wettable flanks
(Pb−Free) 3000 / Tape & Reel
NCV890100PDR2G SOIC−8 EP
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCV890100
http://onsemi.com
18
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC
ISSUE B
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉ
ÉÉ
ÉÉ
ÇÇ
ÇÇ
ÇÇ
H
C0.10
D
E1
A
D
PIN ONE
2 X
8 X
SEATING
PLANE
EXPOSED
GAUGE
PLANE
14
58
D
C0.10 A-B
2 X
E
B
e
C0.10
2 X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
DETAIL A
END VIEW
SECTION A−A
8 X b
A-B0.25 D
C
C
C0.10
C0.20
A
A2
G
F
14
58
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS (ANGLES
IN DEGREES).
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
DIM MIN MAX
MILLIMETERS
A1.35 1.75
A1 0.00 0.10
A2 1.35 1.65
b0.31 0.51
b1 0.28 0.48
c0.17 0.25
c1 0.17 0.23
D4.90 BSC
E6.00 BSC
e1.27 BSC
L0.40 1.27
L1 1.04 REF
F2.24 3.20
G1.55 2.51
h0.25 0.50
q0 8
h
AA
DETAIL A
(b)
b1
c
c1
0.25 L
(L1) q
PAD
E1 3.90 BSC
__
A1
LOCATION
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Exposed
Pad
1.52
0.060
2.03
0.08
0.6
0.024 1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
7.0
0.275
2.72
0.107
NCV890100
http://onsemi.com
19
PACKAGE DIMENSIONS
DFN8, 3x3, 0.5P
CASE 506BY
ISSUE A
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Ç
Ç
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Ç
Ç
8X
0.53
2.46
1.66
0.40
1
0.65
PITCH
3.30
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
RECOMMENDED
8X
DIMENSIONS: MILLIMETERS
SOLDERING FOOTPRINT*
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
ÉÉÉ
ÉÉÉ
ÉÉÉ
A
B
E
D
D2
E2
BOTTOM VIEW
b
e
8X
0.10 B
0.05
AC
C
K
8X
NOTE 3
2X
0.10 C
PIN ONE
REFERENCE
TOP VIEW
2X 0.10 C
A
A1
(A3)
0.05 C
0.05 C
CSEATING
PLANE
SIDE VIEW
L
8X
14
58
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.25 0.35
D3.00 BSC
D2 2.20 2.40
E3.00 BSC
E2 1.40 1.60
e0.65 BSC
K0.20 −−−
L0.20 0.40
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
DETAIL B
DET AIL A
L1 0.00 0.15
NOTE 4
e/2
ÉÉ
ÇÇ
ÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
ÉÉ
ÉÉ
ÇÇ
A1
A3
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NCV890100/D
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