© Semiconductor Components Industries, LLC, 2013
October, 2020 − Rev. 3
1Publication Order Number:
NCS21911/D
Precision Operational
Amplifier, 25 mV Offset,
Zero-Drift, 36 V Supply,
2 MHz
NCS21911, NCV21911,
NCS21912, NCV21912,
NCS21914, NCV21914
The NCS2191x family of high precision op amps feature low input
offset voltage and near−zero drift over time and temperature. These op
amps operate over a wide supply range from 4 V to 36 V with low
quiescent current. The rail−to−rail output swings within 10 mV of the
rails. The family includes the single channel NCS(V)21911, the dual
channel NCS(V)21912, and the quad channel NCS(V)21914 in a
variety of packages. All versions are specified for operation from
−40°C to +125°C. Automotive qualified options are available under
the NCV prefix.
Features
•Input Offset Voltage: 25 mV max
•Zero−Drift Offset Voltage: 0.085 mV/°C max
•Voltage Noise Density: 22 nV/√Hz typical
•Unity Gain Bandwidth: 2 MHz typical
•Supply Voltage: 4 V to 36 V
•Quiescent Current: 570 mA max
•Rail−to−Rail Output
•NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These Devices are Pb−free, Halogen free/BFR free and are RoHS
compliant
Typical Applications
•Temperature Measurements
•Transducer Applications
•Electronic Scales
•Medical Instrumentation
•Current Sensing
•Automotive
SOIC−8 NB
CASE 751−07
See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
www.onsemi.com
MARKING
DIAGRAMS
1
8
912
AYWG
G
1
8
XXXXX = Specific Device Code
A = Assembly Location
L or WL = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
912
ALYWX
G
1
8
Micro8
CASE 846A−02
(Note: Microdot may be in either location)
1
5
1
14
TSOP−5
CASE 483
SOIC−14 NB
CASE 751A−03
XXXXXXXXXG
AWLYWW
1
14
1
5
AEZAYWG
G
1
14
TSSOP−14 WB
CASE 948G
XXXX
XXXX
ALYWG
G
1
14
1
8
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
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PIN CONNECTIONS
Single Channel Configuration
NCS21911
1
2
34
5
OUT
VSS
IN+ IN−
Dual Channel Configuration
NCS21912
Quad Channel Configuration
NCS21914
1
4
3
2
8
5
6
7
OUT 1
IN− 1
IN+ 1
VSS
VDD
OUT 2
IN− 2
IN+ 2
+
+−
1
4
3
2
14
11
12
13
OUT 1
IN− 1
IN+ 1
VDD
OUT 4
IN− 4
IN+ 4
VSS
7
6
5
8
9
10
IN+ 2
IN− 2
OUT 2
IN+ 3
IN− 3
OUT 3
+
−
+
−
−
++
VDD
−
−
ORDERING INFORMATION
Channels Device Package Shipping †
Single NCS21911SN2T1G SOT23−5 / TSOP−53000 / Tape & Reel
Dual NCS21912DR2G SOIC−82500 / Tape & Reel
NCS21912DMR2G MICRO−84000 / Tape & Reel
Quad NCS21914DR2G
(In Development*)
SOIC−14 2500 / Tape & Reel
NCS21914DTBR2G
(In Development*)
TSSOP−14 2500 / Tape & Reel
Automotive Qualified
Channels Device Package Shipping
†
Single NCV21911SN2T1G SOT23−5 / TSOP−53000 / Tape & Reel
Dual NCV21912DR2G
(In Development*)
SOIC−82500 / Tape & Reel
NCV21912DMR2G MICRO−84000 / Tape & Reel
Quad NCV21914DR2G
(In Development*)
SOIC−14 2500 / Tape & Reel
NCV21914DTBR2G
(In Development*)
TSSOP−14 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*Contact local sales office for more information.
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
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ABSOLUTE MAXIMUM RATINGS
Parameter Rating Unit
Supply Voltage (VDD− VSS) 40 V
INPUT AND OUTPUT PINS
Input Voltage (Note 1) VSS – 0.3 to VDD + 0.3 V
Differential Input Voltage (Note 2) ±17 V
Input Current (Notes 1 and 2) ±10 mA
Output Short Circuit Current (Note 3) Continuous mA
TEMPERATURE
Operating Temperature –40 to +125 °C
Storage Temperature –65 to +150 °C
Junction Temperature +150 °C
ESD RATINGS (Note 4)
Human Body Model (HBM) 3000 V
Charged Device Model (CDM) 2000 V
OTHER RATINGS
Latch−up Current (Note 5) 100 mA
MSL Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Input terminals are diode−clamped to the power−supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less.
2. The inputs are diode connected with a total input protection of 1.65 kW, increasing the absolute maximum differential voltage to ±17 VDC.
If the applied differential voltage is expected to exceed this rating, external resistors should be added in series with the inputs to limit the input
current to ±10 mA.
3. Short−circuit to VDD or VSS. Short circuits to either rail can cause an increase in the junction temperature. The total power dissipation must
be limited to prevent the junction temperature from exceeding the 150_C limit.
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard JS−001−2017 (AEC−Q100−002)
ESD Charged Device Model tested per JEDEC standard JS−002−2014 (AEC−Q100−011)
5. Latch−up Current tested per JEDEC standard JESD78E (AEC−Q100−004).
THERMAL INFORMATION (Note 6)
Rating Symbol Package Value Unit
Thermal Resistance, Junction to Ambient qJA TSOP−5 /
SOT23−5
170 °C/W
Micro8/MSOP8 116
SOIC−8 87
SOIC−14 59
TSSOP−14 78
6. As mounted on an 80x80x1.5 mm FR4 PCB with 2S2P, 2 oz copper, and a 200 mm2 heat spreader area. Following JEDEC JESD51−7
guidelines.
OPERATING CONDITIONS
Parameter Symbol Range Unit
Supply Voltage (VDD − VSS)VS4 to 36 V
Specified Operating Temperature Range TA −40 to 125 °C
Input Common Mode Voltage Range VCM VSS to VDD−1.5 V
Differential Voltage (Note 7) VDIFF ±17 V
7. The inputs are diode connected with a total input protection of 1.65 kW, increasing the absolute maximum differential voltage to ±17 VDC.
If the applied differential voltage is expected to exceed this rating, external resistors should be added in series with the inputs to limit the input
current to ±10 mA.
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
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ELECTRICAL CHARACTERISTICS VS = 4 V to 36 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified temperature range, TA = –40°C to 125°C, guaranteed by characterization and/or design.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS ±1±25 mV
Offset Voltage Drift vs Temp DVOS/DT±0.02 ±0.085 mV/°C
Input Bias Current (Note 8) IIB ±100 ±500 pA
±3500 pA
Input Offset Current (Note 8) IOS ±200 ±500 pA
±3500 pA
Common Mode Rejection Ratio CMRR VSS ≤ VCM ≤
VDD−1.5 V
VS = 36 V 140 150 dB
130
VS = 12 V
(Note 8)
130 150
120
VS = 8 V
(Note 8)
130 140
120
VS = 4 V 120 130
110
Input Capacitance CIN Common Mode 3 pF
EMI Rejection Ratio EMIRR f = 5 GHz 100 dB
f = 400 MHz 80
OUTPUT CHARACTERISTICS
Open Loop Voltage Gain AVOL VSS + 0.5 V < VO < VDD – 0.5 V 130 150 dB
125 135
Open Loop Output Impedance ZOUT_OL No Load See
Figure 23
W
Output Voltage High, Referenced to
Rail
VOH No Load 5 10 mV
RL = 10 kW100 210
140 250
Output Voltage Low, Referenced to
Rail
VOL No Load 5 10 mV
RL = 10 kW100 210
140 250
Short Circuit Current ISC Sinking Current 18 mA
Sourcing Current 16
Capacitive Load Drive CL1 nF
DYNAMIC PERFORMANCE
Gain Bandwidth Product GBW CL = 100 pF 2 MHz
Gain Margin AMCL = 100 pF 13 dB
Phase Margin ϕMCL = 100 pF 55 °
Slew Rate SR G = +1 1.6 V/ms
Settling Time tSVS = 36 V 0.1% 20 ms
0.01% 45 ms
Overload Recovery Time tOR VS = ±18 V, AV = −10,
VIN = ±2.5 V
1ms
8. Guaranteed by characterization and/or design.
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
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ELECTRICAL CHARACTERISTICS VS = 4 V to 36 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified temperature range, TA = –40°C to 125°C, guaranteed by characterization and/or design.
Parameter UnitMaxTypMinConditionsSymbol
NOISE PERFORMANCE
Total Harmonic Distortion + Noise THD+N fIN = 1 kHz, AV = 1, VOUT = 1
Vrms
0.0003 %
Voltage Noise Density eNf = 1 kHz 22 nV/
√
Hz
Current Noise Density iNf = 1 kHz 100 fA/
√
Hz
Voltage Noise, Peak−to−Peak ePP f = 0.1 Hz to 10 Hz 400 nVPP
Voltage Noise, RMS erms f = 0.1 Hz to 10 Hz 70 nVrms
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 4 V to 36 V 0.02 0.3 mV/V
130 154 dB
Quiescent Current IQPer channel 475 570 mA
570
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
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GRAPHS
Typical performance at TA = 25°C, unless otherwise noted.
Figure 1. Offset Voltage Distribution Figure 2. Offset Voltage Drift Distribution
0
5
10
15
20
25
30
35
−20 −16 −12 −8−4 0 4 8 12 16 20
NUMBER OF AMPLIFIERS
OFFSET VOLTAGE (mV)
16
14
12
10
8
6
4
2
0
−0.10 −0.06 −0.02 0.02 0.06 0.10
OFFSET VOLTAGE DRIFT (mV/°C)
NUMBER OF AMPLIFIERS
VS = 36 V
VCM = mid−supply
105 units
VS = 36 V
VCM = mid−supply
105 units
Figure 3. Offset Voltage vs. Temperature Figure 4. Offset Voltage vs. Common Mode
Voltage
−50 −25 0 25 50 75 100 125
VS = 36 V
VCM = mid−supply
5 typical units
OFFSET VOLTAGE (μV)
TEMPERATURE (°C)
0 0.5 1 1.5 2 2.5 3
COMMON MODE VOLTAGE (V)
OFFSET VOLTAGE (μV)
VS = 4 V
5 typical units
15
10
5
0
−5
−10
−15
15
10
5
0
−5
−10
−15
Figure 5. Offset Voltage vs. Common Mode
Voltage
Figure 6. Offset Voltage vs. Power Supply
VS = 36 V
5 typical units
OFFSET VOLTAGE (μV)
COMMON MODE VOLTAGE (V) SUPPLY VOLTAGE (V)
OFFSET VOLTAGE (μV)
VCM = mid−supply
5 typical units
0 5 10 15 20 25 30 35 4 8 12 16 20 24 28 32 36
15
10
5
0
−5
−10
−15
15
10
5
0
−5
−10
−15
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
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Figure 7. Open Loop Gain and Phase vs.
Frequency
Figure 8. Closed Loop Gain vs. Frequency
VS = 4 V, 36 V
RL = 10 kW
GAIN (dB) AND PHASE MARGIN (°)
FREQUENCY (Hz) FREQUENCY (Hz)
GAIN (dB)
VS = 36 V
RL = 10 kW
CL = 25 pF
GAIN
PHASE MARGIN
10 1k 100k 10M 10k 100k 1M 10M
25
20
15
10
5
0
−5
−10
−15
−20
AV = 1
AV = −1
AV = 10
120
100
80
60
40
20
0
−20
Figure 9. Input Current vs. Common Mode
Voltage
Figure 10. Input Current vs. Temperature
VS = 36 V
INPUT CURRENT (pA)
COMMON MODE VOLTAGE (V) TEMPERATURE (°C)
INPUT CURRENT (pA)
−300
−200
−100
0
100
200
300
0 5 10 15 20 25 30 35 −40 −20 0 20 40 60 80 100 120 140
VS = 36 V
VCM = mid−supply
IIB+
IIB−
IOS
IIB+
IIB−
IOS
1600
1200
800
400
0
−400
Figure 11. PSRR vs. Frequency Figure 12. CMRR vs. Frequency
140
POWER SUPPLY REJECTION (dB)
FREQUENCY (Hz) FREQUENCY (Hz)
120
COMMON MODE REJECTION (dB)
VS = ±2, PSRR+
VS = ±18, PSRR+
VS = ±2, PSRR−
VS = ±18, PSRR−
120
100
80
60
40
20
0
10 1k 100k 1M100 10k
PSRR+
PSRR−
RL = 10 kW
100
80
60
40
20
0
10 1k 100k 1M100 10k
VS = 4 V, 36 V
RL = 10 kW
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
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Figure 13. PSRR vs. Temperature Figure 14. CMRR vs. Temperature at VS = 4 V
0.5
PSRR (mV/V)
TEMPERATURE (°C) TEMPERATURE (°C)
5
CMRR (mV/V)
−50 0 125 150−25 100
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
755025
VS = 4 V, 36 V
5 typical units
−50 0 125 150−25 100755025
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
−0.5
VCM = VSS+0.5 to VDD−1.5 V
VCM = VSS to VDD−1.5 V
Figure 15. CMRR vs. Temperature at VS = 36 V Figure 16. 0.1 Hz to 10 Hz Noise
2
CMRR (mV/V)
TEMPERATURE (°C) TIME (s)
400
VOLTAGE (nV)
−50 0 125 150−25 100755025
VS = 36 V
04 91038765
VCM = VSS+0.5 to VDD−1.5 V
VCM = VSS to VDD−1.5 V
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−0.2
−0.4
300
200
100
0
−100
−200
−300
−400 12
Figure 17. Voltage Noise Density vs.
Frequency
Figure 18. THD+N vs. Frequency
1k
VOLTAGE NOISE (nV/√Hz)
FREQUENCY (Hz) FREQUENCY (Hz)
0.01
THD + N (%)
1 10 10k 100k1k
VS = 36 V
100
10
1100
0.001
0.0001
10 10k1k100
VS = 36 V
RL = 10 kW
BW = 80 kHz
VIN = 1 Vrms
AV = 1
AV = −1
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Figure 19. THD+N vs. Output Amplitude Figure 20. Quiescent Current vs. Supply
Voltage
10
THD + N (%)
OUTPUT AMPLITUDE (Vrms)SUPPLY VOLTAGE (V)
0.50
QUIESCENT CURRENT (mA)
0.01 0.1 101 4 12 32 36828242016
1
0.1
0.01
0.001
0.0001
VS = 36 V
RL = 10 kW
BW = 80 kHz
f = 1 kHz
AV = 1
AV = −10.48
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.300
Figure 21. Quiescent Current vs. Temperature Figure 22. Open Loop Gain vs. Temperature
0.50
QUIESCENT CURRENT (mA)
TEMPERATURE (°C) TEMPERATURE (°C)
3.0
OPEN LOOP GAIN (mV/V)
−50 −25 150125 −50 0 125 150−25 100755025
2.5
2.0
1.5
1.0
0.5
0.0
AV = 1
AV = −1
VS = 4 V
VS = 36 V
0.48
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
1007502550
Figure 23. Open Loop Output Impedance vs.
Frequency
Figure 24. Small Signal Overshoot vs.
Capacitive Load (100 mV Output Step)
10k
OUTPUT IMPEDANCE (W)
FREQUENCY (Hz) CAPACITIVE LOAD (pF)
50
OVERSHOOT (%)
1 1k 10M10k 0 800 1000200 600400
45
40
35
30
25
20
15
10
5
0
1k
100
0.1
10
1
10 100 100k 1M
Riso = 0 W
Riso = 25 W
Riso = 50 W
VS = 36 V
RL = 10 kW
AV = 1 V/V
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Figure 25. Small Signal Overshoot vs.
Capacitive Load (100 mV Output Step)
Figure 26. No Phase Reversal
70
OVERSHOOT (%)
CAPACITIVE LOAD (pF) TIME (100 ms/div)
5
VOLTAGE (V)
0 200 1000400
60
50
40
30
20
10
0
600 800
Riso = 0 W
Riso = 25 W
Riso = 50 W
RL = 10 kW
AV = −1
100 mV Step
4
3
2
1
0
−1
−2
−3
−4
−5
Input
Output
VS = 8 V
RL = 10 kW
CL = 15 pF
Figure 27. Positive Overload Recovery
4
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3
2
1
0
−1
−2
−3
−4
20
15
10
5
0
−5
−10
−15
−20
TIME (1 ms/div)
Input
Output
VS = ±18 V
RL = 10 kW
CL = 15 pF
AV = −10
Figure 28. Negative Overload Recovery
4
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3
2
1
0
−1
−2
−3
−4
20
15
10
5
0
−5
−10
−15
−20
TIME (1 ms/div)
Input
Output
VS = ±18 V
RL = 10 kW
CL = 15 pF
AV = −10
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Figure 29. Non−Inverting Small Signal Step
Response
Figure 30. Inverting Small Signal Step
Response
0.1
VOLTAGE (V)
TIME (10 ms/div) TIME (10 ms/div)
VOLTAGE (V)
0.08
0.06
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
−0.1
VS = 36 V
RL = 10 kW
CL = 15 pF
AV = 1
Input
Output
VS = 36 V
RL = 10 kW
CL = 15 pF
AV = −1
Input
Output
0.1
0.08
0.06
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
−0.1
Figure 31. Non−Inverting Large Signal Step
Response
Figure 32. Inverting Large Signal Step
Response
10
VOLTAGE (V)
TIME (10 ms/div) TIME (10 ms/div)
VOLTAGE (V)
8
6
4
2
0
−2
−4
−8
−10
VS = 36 V
RL = 10 kW
CL = 15 pF
AV = 1
Input
Output
10
8
6
4
2
0
−2
−4
−8
−10
VS = 36 V
RL = 10 kW
CL = 15 pF
AV = −1
Input
Output
−6
−6
Figure 33. Large Signal Settling Time,
Low−to−High
Figure 34. Large Signal Settling Time,
High−to−Low
0.01
VOLTAGE (V)
TIME (5 ms/div) TIME (5 ms/div)
VOLTAGE (V)
0.008
0.006
0.004
0.002
0
−0.002
−0.004
−0.006
−0.008
−0.01
VS = 36 V
RL = 10 kW
CL = 15 pF
VIN = 10 V Step
Output
Input
0.01
0.008
0.006
0.004
0.002
0
−0.002
−0.004
−0.006
−0.008
−0.01
VS = 36 V
RL = 10 kW
CL = 15 pF
VIN = 10 V Step
Output
Input
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Figure 35. Short Circuit Current vs.
Temperature
Figure 36. Maximum Output Voltage vs.
Frequency (AV = 1 for VS = +2.5 V, +5 V, +9 V;
AV = 2 for VS = +18 V)
25
SHORT CIRCUIT CURRENT (mA)
TEMPERATURE (°C) FREQUENCY (Hz)
35
OUTPUT VOLTAGE (Vpp)
−50 0 15050 1k 10M10k 1M100k
VS = 36 V
20
15
10
5
0
−5
−10
−15
−20
−25
100
VS = ±18 V
VS = ±9 V
VS = ±5 V
VS = ±2.5 V
ISC, Source
ISC, Sink 30
25
20
15
10
5
0
Figure 37. Output Voltage Low vs. Output
Current
Figure 38. Output Voltage High vs. Output
Current
3
OUTPUT VOLTAGE LOW (V)
OUTPUT CURRENT (mA) OUTPUT CURRENT (mA)
36
OUTPUT VOLTAGE HIGH (V)
02 2410
2.5
2
1.5
1
0.5
0
TA = −40°C
TA = 0°C
TA = 25°C
TA = 85°C
TA = 125°C
VS = 36 V
4861214162018 22 02 104861214162018
35.5
35
34.5
34
33.5
33
TA = −40°C
TA = 0°C
TA = 25°C
TA = 85°C
TA = 125°C
VS = 36 V
Figure 39. EMIRR IN+ vs. Frequency
160
EMI REJECTION (dB)
FREQUENCY (Hz)
10M 100M 10G1G
140
120
100
80
60
40
20
0
VS = 36 V
VIN = 100 mVp
AV = 1
Figure 40. Channel−to−Channel Crosstalk
0
CROSSTALK (dB)
FREQUENCY (Hz)
10 1K 1M100K
−20
−40
−60
−80
−100
−120
−140
−160
100 10K 10M
VS = 36 V
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
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APPLICATION INFORMATION
Overview
The NCS21911, NCS21912, and NCS21914 precision op
amps provide low offset voltage and zero drift over
temperature. With a maximum offset voltage of 25 mV and
input common mode voltage range that includes ground, the
NCS21911 series is well−suited for applications where
precision is required, such as low side current sensing and
interfacing with sensors.
The NCS21911 series of amplifiers uses a
chopper−stabilized architecture, which provides the
advantage of minimizing offset voltage drift over
temperature and time. The simplified block diagram is
shown in Figure 41. Unlike the classical chopper
architecture, the chopper stabilized architecture has two
signal paths.
+
−
−
+
+
−+−
IN+
IN−
OUT
RC notch filterChopper
Chopper
Main amp
Figure 41. Simplified NCS21911 Block Diagram
RC notch filter
In Figure 41, the lower signal path is where the chopper
samples the input offset voltage, which is then used to
correct the offset at the output. The offset correction occurs
at a frequency of 250 kHz. The chopper−stabilized
architecture is optimized for best performance at
frequencies up to the related Nyquist frequency (1/2 of the
offset correction frequency). As the signal frequency
exceeds the Nyquist frequency, 125 kHz, aliasing may occur
at the output. This is an inherent limitation of all chopper and
chopper−stabilized architectures. Nevertheless, the
NCS21911 series op amps have minimal aliasing up to
200 kHz and are less susceptible to aliasing effects when
compared to competitor parts from other manufacturers.
ON Semiconductor’s patented approach utilizes two
cascaded, symmetrical, RC notch filters tuned to the
chopper frequency and its fifth harmonic to reduce aliasing
effects.
The chopper−stabilized architecture also benefits from
the feed−forward path, which is shown as the upper signal
path of the block diagram in Figure 41. This is the high speed
signal path that extends the gain bandwidth up to 2 MHz. Not
only does this help retain high frequency components of the
input signal, but it also improves the loop gain at low
frequencies. This is especially useful for low−side current
sensing and sensor interface applications where the signal is
low frequency and the differential voltage is relatively
small.
Application Circuits
Low−Side Current Sensing
Low−side current sensing is used to monitor the current
through a load. This method can be used to detect
over−current conditions and is often used in feedback
control, as shown in Figure 42. A sense resistor is placed in
series with the load to ground. Typically, the value of the
sense resistor is less than 100 mW to reduce power loss
across the resistor. The op amp amplifies the voltage drop
across the sense resistor with a gain set by external resistors
R1, R2, R3, and R4 (where R1 = R2, R3 = R4). Precision
resistors are required for high accuracy, and the gain is set
to utilize the full scale of the ADC for the highest resolution.
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
www.onsemi.com
14
Figure 42. Low−Side Current Sensing
+
−
Load
VDD
ADC
Microcontroller
control
RSENSE
R1
R2
R3
R4
VDD
VDD
VLOAD
Differential Amplifier for Bridged Circuits
Sensors to measure strain, pressure, and temperature are
often configured in a Wheatstone bridge circuit as shown in
Figure 43. In the measurement, the voltage change that is
produced is relatively small and needs to be amplified before
going into an ADC. Precision amplifiers are recommended
in these types of applications due to their high gain, low
noise, and low offset voltage.
Figure 43. Wheatstone Bridge Circuit Amplification
+
−
VDD
VDD
R1R3
R3Rx
RF
EMI Susceptibility and Input Filtering
Op amps have varying amounts of EMI susceptibility.
Semiconductor junctions can pick up and rectify EMI
signals, creating an EMI−induced voltage offset at the
output, adding another component to the total error. Input
pins are the most sensitive to EMI. The NCS2191x
integrates low−pass filters to decrease its sensitivity to EMI.
Figure 39 shows the EMIRR performance.
General Layout Guidelines
To ensure optimum device performance, it is important to
follow good PCB design practices. Place 0.1 mF decoupling
capacitors as close as possible to the supply pins. Keep traces
short, utilize a ground plane, choose surface−mount
components, and place components as close as possible to
the device pins. These techniques will reduce susceptibility
to electromagnetic interference (EMI). Thermoelectric
effects can create an additional temperature dependent
offset voltage at the input pins. To reduce these effects, use
metals with low thermoelectric coefficients and prevent
temperature gradients from heat sources or cooling fans.
TSOP−5
CASE 483
ISSUE N
DATE 12 AUG 2020
SCALE 2:1
1
5
XXX MG
G
GENERIC
MARKING DIAGRAM*
1
5
0.7
0.028
1.0
0.039
ǒmm
inchesǓ
SCALE 10:1
0.95
0.037
2.4
0.094
1.9
0.074
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
1
5
XXXAYWG
G
Discrete/Logic
Analog
(Note: Microdot may be in either location)
XXX = Specific Device Code
M = Date Code
G= Pb−Free Package
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
DIM MIN MAX
MILLIMETERS
A
B
C0.90 1.10
D0.25 0.50
G0.95 BSC
H0.01 0.10
J0.10 0.26
K0.20 0.60
M0 10
S2.50 3.00
123
54 S
A
G
B
D
H
C
J
__
0.20
5X
CAB
T0.10
2X
2X T0.20
NOTE 5
CSEATING
PLANE
0.05
K
M
DETAIL Z
DETAIL Z
TOP VIEW
SIDE VIEW
A
B
END VIEW
1.35 1.65
2.85 3.15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ARB18753C
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
TSOP−5
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
SCALE 1:1
STYLES ON PAGE 2
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
1
8
XXXXX
ALYWX
1
8
IC Discrete
XXXXXX
AYWW
G
1
8
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Discrete
XXXXXX
AYWW
1
8
(Pb−Free)
XXXXX
ALYWX
G
1
8
IC
(Pb−Free)
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−14 NB
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
SCALE 1:1
1
14
GENERIC
MARKING DIAGRAM*
XXXXXXXXXG
AWLYWW
1
14
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
STYLES ON PAGE 2
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
H
14 8
71
M
0.25 B M
C
h
X 45
SEATING
PLANE
A1
A
M
_
S
A
M
0.25 B S
C
b
13X
B
A
E
D
e
DETAIL A
L
A3
DETAIL A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
D8.55 8.75 0.337 0.344
E3.80 4.00 0.150 0.157
A1.35 1.75 0.054 0.068
b0.35 0.49 0.014 0.019
L0.40 1.25 0.016 0.049
e1.27 BSC 0.050 BSC
A3 0.19 0.25 0.008 0.010
A1 0.10 0.25 0.004 0.010
M0 7 0 7
H5.80 6.20 0.228 0.244
h0.25 0.50 0.010 0.019
__ __
6.50
14X
0.58
14X
1.18
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
0.10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42565B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOIC−14 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
STYLE 2:
CANCELLED
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42565B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOIC−14 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 3:
PIN 1. N-SOURCE
2. N-GATE
3. P-SOURCE
4. P-GATE
5. P-DRAIN
6. P-DRAIN
7. N-DRAIN
8. N-DRAIN
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
XXXX
AYWG
G
1
8
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
(Note: Microdot may be in either location)
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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98ASB14087C
DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
MICRO8
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
TSSOP−14 WB
CASE 948G
ISSUE C
DATE 17 FEB 2016
SCALE 2:1
1
14
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇ
ÇÇÇ
SECTION N−N
DETAIL E
JJ1
K
K1
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
14X REFK
N
N
GENERIC
MARKING DIAGRAM*
XXXX
XXXX
ALYWG
G
1
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
(Note: Microdot may be in either location)
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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98ASH70246A
DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
TSSOP−14 WB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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