4-Channel, 24 GHz,
Receiver Downconverter
Data Sheet
ADF5904
Rev. A Document Feedback
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FEATURES
Integrated baluns for single-ended receiver (Rx) inputs and
local oscillator (LO) input
Rx channel gain: 22 dB
Noise figure (NF): 10 dB
P1dB: −10 dBm
LO input range: −8 dBm to +5 dBm
Rx to IF isolation: 30 dB
RF signal bandwidth: 250 MHz
Rx output impedance: 900 Ω differential
LO input buffer: 24 GHz
RF and LO S11 at 50 Ω: −5 dB
Temperature sensor with analog output: ±5°
Electrostatic discharge (ESD) performance
Human body model (HBM): 2000 V
Charged device model (CDM): 500 V
Qualified for automotive applications
APPLICATIONS
Automotive radars
Industrial radars
Microwave (µW) radar sensors
GENERAL DESCRIPTION
The ADF5904 is a 4-channel, 24 GHz, receiver downconverter.
Each channel contains a single-ended RF input with an on-chip
balun followed by a differential low noise amplifier (LNA) and a
downconverter mixer with differential output buffers. The RF
LO path also has an on-chip balun.
Control of the on-chip registers is through a simple 3-wire
interface.
The ADF5904 comes in a compact 32-lead, 5 mm × 5 mm
LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
DATA
LE
CLK
CE
AVDD
GND
RX1_RF RX2_RF RX3_RF
LO_IN
RX1_O
RX1_OB
RX2_O
RX2_OB
RX3_O
RX3_OB
RX4_O
RX4_OB
ATEST
BALUN
LNA
BALUN
LNA
BALUN
LNA
BALUN
LNA
RX4_RF
TEMP
SENSOR
BALUN
DOUT
32-BIT DATA
REGISTER
12885-001
ADF5904
Figure 1.
ADF5904 Data Sheet
Rev. A | Page 2 of 15
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
RF Path ........................................................................................... 9
LO Path .......................................................................................... 9
Input Shift Register .......................................................................9
Program Modes .............................................................................9
Register Map ................................................................................... 10
Register 0 ..................................................................................... 11
Register 1 ..................................................................................... 12
Register 2 ..................................................................................... 12
Initialization Sequence .............................................................. 13
Temperature Sensor ................................................................... 13
Application Information ................................................................ 14
Application of the ADF5904 in FMCW Radar ...................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
Automotive Products ................................................................. 15
REVISION HISTORY
2/16—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Change to Parameter HBM, Table 3 .............................................. 5
Change to Temperature Sensor Section....................................... 13
Changes to Ordering Guide .......................................................... 15
3/15—Revision 0: Initial Version
Data Sheet ADF5904
Rev. A | Page 3 of 15
SPECIFICATIONS
AVDD = 3.3 V ± 5%, GND = 0 V, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Operating temperature range is −40°C
to +105°C.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
OPERATING CONDITIONS
LO and RF Frequency Range 24 24.25 GHz
LO INPUT
Input Return Loss (S11) −5 dB
LO Input Level −8 −5 +5 dBm
BASEBAND OUTPUTS
Voltage Conversion Gain 22 dB Measured differentially
Demodulation Bandwidth
10
MHz
Maximum capacitance = 10 pF
Output DC Offset (Differential) ±20 mV
Output Common Mode AVDD − 1.0 V
Output Swing 2 V peak Differential 900 Ω load
Channel to Channel Phase Mismatch over
Temperature
±5 Degrees
DYNAMIC PERFORMANCE, RF = 24.125 GHz
Conversion Gain 22 dB
Input P1dB −10 dBm
RF Input Return Loss −5 dB
Second-Order Input Intercept IIP2 20 dBm
Third-Order Input Intercept IIP3 0 dBm
LO to RF Isolation 30 dB Terminated in 50 Ω
RF to IF Isolation 30 dB
Noise Figure 10 dB Double sideband (DSB) at 100 kHz
Noise Figure Under Blocking Conditions 15 dB With a −30 dBm input interferer at
5 MHz offset from carrier (DSB)
LOGIC INPUTS
Input Voltage
High VIH 1.4 V
Low VIL 0.6 V
Input Current IINH, IINL ±1 µA
Input Capacitance CIN 10 pF
LOGIC OUTPUTS
Output Voltage
High
V
OH
V
DD
− 0.4
V
V
DD
selected from the DOUT VSEL
bit (Bit DB8, Register 0)
Low VOL 0.4 V
Output Current
High IOH 500 µA
Low IOL 500 µA
TEMPERATURE SENSOR
Analog Accuracy ±5 °C Following one-point calibration
Sensitivity 4.243 mV/°C
POWER SUPPLIES
AVDD 170 mA
Power-Down Current
100
µA
ADF5904 Data Sheet
Rev. A | Page 4 of 15
TIMING CHARACTERISTICS
AVDD = 3.3 V ± 5%, GND = 0 V, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Operating temperature range is −40°C
to +105°C.
Table 2.
Parameter Limit at TMIN to TMAX Unit Description
t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width
t8 10 ns max LE setup time to DOUT
t9 15 ns max CLK setup time to DOUT
Timing Diagrams
CLK
DATA
LE
DB30 DB1
(CONTROL BIT C2)
DB2
(CONTROL BIT C3)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
8
t
9
t
2
t
3
t
4
t
5
t
6
t
7
DB31 (MSB)
DB0
DB1
DB31
(MSB) DB30
DOUT
12885-002
Figure 2. Timing Diagram
TO DOUT PIN
CL
10pF
500µA IOL
500µA IOH
VDD/2
12885-003
Figure 3. Load Circuit for DOUT Timing, CL = 10 pF
Data Sheet ADF5904
Rev. A | Page 5 of 15
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to GND –0.3 V to +3.9 V
Digital Input/Output Voltage to GND –0.3 V to AVDD + 0.3 V
Analog Input/Output Voltage to GND –0.3 V to AVDD + 0.3 V
RXx_RF, LO_IN to GND –0.3 V to AVDD + 0.3 V
Operating Temperature Range –40°C to +105°C
Storage Temperature Range –65°C to +125°C
Maximum Junction Temperature
150°C
θJA Thermal Impedance1 (Pad Soldered) 40.83°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
Transistor Count
CMOS 65,100
Bipolar 2280
ESD
CDM 500 V
HBM 2000 V
1 Two signal planes (that is, on the top and the bottom surfaces of the board),
two buried planes, and nine vias.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
ADF5904 Data Sheet
Rev. A | Page 6 of 15
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 GND
23 RX3_RF
22 GND
21 AV
DD
20 GND
19 RX4_RF
18 GND
17 RX4_O
1
2
3
4
5
6
7
8
GND
RX1_RF
GND
AV
DD
GND
RX2_RF
GND
RX2_O
9
10
11
12
13
14
15
16
RX2_OB
LE
CLK
DATA
CE
DOUT
ATEST
RX4_OB
32
31
30
29
28
27
26
25
RX1_O
RX1_OB
GND
LO_IN
GND
AV
DD
RX3_OB
RX3_O
TOP VIEW
(Not to Scale)
ADF5904
NOTES
1. THE LFCSP HAS AN EXPOSED PAD
THAT MUST BE CONNECTED TO GND.
12885-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 3, 5, 7, 18, 20,
22, 24, 28, 30
GND Ground Pins.
2 RX1_RF Channel 1 RF Input.
4, 21, 27 AVDD Analog Power Supply. The supply range is 3.3 V ± 5%. Place decoupling capacitors (0.1 µF, 1 nF, and 10 pF)
to the ground plane as close as possible to this pin.
6 RX2_RF Channel 2 RF Input.
8 RX2_O Channel 2 Baseband Output.
9 RX2_OB Channel 2 Complementary Baseband Output.
10 LE Load Enable, CMOS Input. When LE goes high, data stored in the shift registers is loaded into one of the
four latches; the control bits select the latch.
11 CLK Serial Clock Input. This serial clock clocks in the serial data to the registers. Data latches into the 32-bit
shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 DATA Serial Data Input. The serial data loads MSB first and the two LSBs are the control bits.
This input is a high impedance CMOS input.
13 CE Chip Enable. A logic low on this pin powers down the device.
14
DOUT
Serial Data Output.
15 ATEST Analog Test Output
16 RX4_OB Channel 4 Complementary Baseband Output.
17 RX4_O Channel 4 Baseband Output.
19 RX4_RF Channel 4 RF Input.
23 RX3_RF Channel 3 RF Input.
25 RX3_O Channel 3 Baseband Output.
26 RX3_OB Channel 3 Complementary Baseband Output.
29 LO_IN Local Oscillator Input.
31 RX1_OB Channel 1 Complementary Baseband Output.
32 RX1_O Channel 1 Baseband Output.
EPAD Exposed Pad. The LFCSP has an exposed pad that must connect to GND.
Data Sheet ADF5904
Rev. A | Page 7 of 15
TYPICAL PERFORMANCE CHARACTERISTICS
12885-005
IF OUTPUT POWER (V p-p)
RF INPUT POWER (dBm)
0.01
0.1
1
10
–50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0
–40°C
+25°C
+105°C
Figure 5. IF Output Power vs. RF Input Power,
LO Frequency = 24 GHz at −5 dBm and IF Frequency = 100 kHz
12885-006
CONVERSION GAIN (dB)
RF INPUT POWER (dBm)
0
5
10
15
20
25
30
–50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0
–40°C
+25°C
+105°C
Figure 6. Conversion Gain vs. RF Input Power,
LO Frequency = 24 GHz at −5 dBm, and IF Frequency = 100 kHz
12885-007
IF OUTPUT POWER (dBm)
RF INPUT POWER (dBm)
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
–50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0
–40°C
+25°C
+105°C
Figure 7. IF Output Power vs. RF Input Power,
LO Frequency = 24 GHz at −5 dBm, and IF Frequency = 100 kHz
12885-008
CHANNEL GAIN (dB)
RF FREQUENCY (Hz)
0
5
10
15
20
25
30
23.90 23.95 24.00 24.05 24.10 24.15 24.20 24.25 24.30 24.35
–40°C
+25°C
+105°C
Figure 8. Channel Gain vs. RF Frequency,
Rx Input = −50 dBm, LO Power = −5 dBm, and IF Frequency = 100 kHz
12885-009
CHANNEL GAIN (dB)
LO INPUT POWER (dB)
0
5
10
15
20
25
30
–20 –15 –10 –5 0 5
–40°C
+25°C
+105°C
Figure 9. Channel Gain vs. LO Input Power, Rx Input = −50 dBm,
LO Frequency = 24 GHz, and IF Frequency = 100 kHz
12885-010
NOISE FIGURE (dB)
IF FREQUENCY (Hz)
0
2
4
6
8
10
12
14
16
18
20
10k 100k 1M 10M
–40°C
+25°C
+105°C
Figure 10. Noise Figure vs. IF Frequency, LO Frequency = 24.125 GHz at −5 dBm
ADF5904 Data Sheet
Rev. A | Page 8 of 15
12885-011
P1dB (dBm)
IF FREQUENCY (Hz)
–15
–10
–5
0
5
10
15
20
1k 10k 100k 1M 10M
OP1dB
IP1dB
–40°C
+25°C
+105°C
Figure 11. P1dB vs. IF Frequency, LO Frequency = 24 GHz at −5 dBm
12885-012
OUTPUT POWER (dBm)
INPUT POWER (dBm)
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10
IIP3 5dBm
Figure 12. Output Power vs. Input Power, IIP3 LO Frequency = 24.125 GHz at
−5 dBm, Rx Frequency = LO + 100 kHz and LO + 200 kHz
12855-013
GAIN (dB)
IF FREQUENCY (Hz)
0
5
10
15
20
25
30
100 1k 10k 100k 1M 10M
–40°C
+25°C
+105°C
Figure 13. Gain vs. IF Frequency, Rx Power = −50 dBm and
LO Frequency = 24 GHz at −5 dBm
12885-014
V
ATEST
(V)
TEMPERATURE (°C)
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
–40 –20 020 40 60 80 100 120
Figure 14. Temperature Sensor Voltage on ATEST
Data Sheet ADF5904
Rev. A | Page 9 of 15
THEORY OF OPERATION
RF PATH
The ADF5904 contains four identical 24 GHz downconverter
channels. Each channel contains a balun that converts the
single-ended input into a differential signal for the rest of the
downconverter path (see Figure 15). This balun is followed by
a LNA that feeds the downconverter mixer.
AV
DD
2kΩ 2kΩ
RXx_RF
GND
GND
AV
DD
AV
DD
12885-015
BALUN
Figure 15. RF Input Stage
LO PATH
The four downconverter channels share the same LO path. The
LO path contains a balun that converts the single-ended input
to a differential signal to drive the mixer (see Figure 16).
AVDD
400Ω 400Ω
20Ω 20Ω
LO_IN
GND
GND
AVDD
AVDD
BALUN
12885-016
Figure 16. LO Input Stage
INPUT SHIFT REGISTER
The ADF5904 digital section includes power-down bits and test
modes to read back registers. Data is clocked into the 32-bit
input shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the input shift
register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2 and C1) in the input shift register. These are the two
LSBs (DB1 and DB0, respectively), as shown in Table 5. The
truth table for these bits is shown in Table 5. Figure 18 to Figure 20
show a summary of how the latches are programmed.
PROGRAM MODES
Table 5 and Figure 18 through Figure 20 show how to set up the
program modes in the ADF5904.
Table 5. C2 and C1 Truth Table
Control Bits
C2 (DB1) C1 (DB0) Register
0 0 R0
0 1 R1
1 0 R2
1
1
R3
ADF5904 Data Sheet
Rev. A | Page 10 of 15
REGISTER MAP
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0
0
0 0 0 0 0
RESERVED RESERVED
0 0 0 0 0 0 0 00PC4 PC3 PC2 PC1 PLO LPB DIO 1 0 1 0 0 C2(0) C1(0)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CS2 CS1 CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 C2(0) C1(1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 C2(1) C1(1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 C2(1) C1(0)
REGISTER 2 (R2)
1
0
RESERVED
RESERVED
RESERVED
DOUT VSEL
LO PIN BIAS
PUP LO
PUP CH1
PUP CH2
PUP CH3
PUP CH4
REGISTER 3 (R3)
REGISTER 1 (R1)
REGISTER 0 (R0)
DB14 DB13 DB12 DB11 DB10
TC4 TC3 TC2 TC1 TC0
5-BIT
CHANNEL TEST SELECT RESERVED
CHANNEL
SELECT
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
12885-017
Figure 17. Latch Summary
Data Sheet ADF5904
Rev. A | Page 11 of 15
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
10
0
00000
RESERVED RESERVED CONTROL
BITS
000 0 0 0 000PC4 PC3 PC2 PC1 PLO LPB DIO 10100C2(0) C1(0)
0
DOUT VSEL
LO_IN PIN BIAS
PUP LO
PUP CH1
PUP CH2
PUP CH3
PUP CH4
REGISTER 0 (R0)
PC4 PUP CH4
0
1
POWER DOWN
POWER UP
PC3 PUP CH3
0
1
POWER DOWN
POWER UP
PC2 PUP CH2
0
1
POWER DOWN
POWER UP
PC1 PUP CH1
0
1
POWER DOWN
POWER UP
PLO PUP LO
0
1
POWER DOWN
POWER UP
DIO DOUT VSEL
0
1
3.3V
1.8V
LPB LO_IN PIN BIAS
0
1
NO DC BIAS
1.5V DC BIAS
12885-018
Figure 18. Register 0
REGISTER 0
Register 0 Control Bits
With Bits[C2:C1] set to 00, Register R0 is programmed. Figure 18
shows the input data format for programming this register.
DOUT VSEL
DB8 controls the DOUT logic levels. Set this bit to 0 to set the
DOUT logic level to 3.3 V, an d s et this bit to 1 to sets the
DOUT logic level to 1.8 V.
LO_IN Pin Bias
DB9 controls the dc bias voltage on the LO_IN pin (Pin 29). Set
this bit to 0 to set no dc bias on the LO_IN pin, and set this bit
to 1 to set the dc bias to 1.5 V. AC couple the LO signal to the
LO_IN pin.
PUP LO
DB10 provides the power-up bit for the LO block. Set this bit to
0 to power down the LO block, and set this bit to 1 to return the
LO block to normal operation.
PUP CH1
DB11 provides the power-up bit for RF Receiver Channel 1. Setting
this bit to 0 performs a power-down of Channel 1 blocks. Setting
this bit to 1 returns Channel 1 blocks to normal operation.
PUP CH2
DB12 provides the power-up bit for RF Receiver Channel 2. Set
this bit to 0 to power down the Channel 2 blocks, and set this
bit to 1 to return the Channel 2 blocks to normal operation.
PUP CH3
DB13 provides the power-up bit for RF Receiver Channel 3. Set
this bit to 0 to power down the Channel 3 blocks, and set this
bit to 1 to return the Channel 3 blocks to normal operation.
PUP CH4
DB14 provides the power-up bit for RF Receiver Channel 4. Set
this bit to 0 to power down the Channel 4 blocks, and set this
bit to 1 to return the Channel 4 blocks to normal operation.
ADF5904 Data Sheet
Rev. A | Page 12 of 15
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CS2 CS1 CS0 0 0 0 0 0
CONTROL
BITS
0 0 00 0 0000001 0 1 0 0 1 0 0 1 0 C2(0) C1(1)1
RESERVED
CHANNEL
SELECT
REGISTER 1 (R1)
12885-019
CS2
CS1
CS0 CHANNE L SELECT
NONE
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
LO
RESERVED
RESERVED
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
Figure 19. Register 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00 0 0 0 0 0 0 0
CONTROL
BITS
00 0 0 0 1 0 0 TC4 TC3 TC2 TC1 TC0 00 0 0 0 0 0 1 C2(1) C1(0)
REGISTER 2 (R2)
RESERVED
5-BIT
CHANNEL TEST SELECT RESERVED
CHANNEL TEST SELECT
NONE SELECTED
TEMPERATURE SENSOR TO ATEST
RESERVED
RESERVED
RESERVED
REGISTER 0 READBACK
REGISTER 1 CHANNEL 1 READBACK
REGISTER 1 CHANNEL 2 READBACK
REGISTER 1 CHANNEL 3 READBACK
REGISTER 1 CHANNEL 4 READBACK
REGISTER 1 LO READBACK
REGISTER 2 READBACK
RESERVED
RESERVED
TC4 TC3 TC1 TC0
TC2
0
1
0
-
1
0
1
0
1
0
1
0
1
x
0
0
1
-
1
0
0
1
1
0
0
1
1
x
0
0
0
-
1
0
0
0
0
1
1
1
1
x
0
0
0
-
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
12855-020
Figure 20. Register 2
REGISTER 1
Register 1 Control Bits
With Bits[C2:C1] set to 01, Register R1 is programmed.
Register 1 contains the internal controls for the four RF channels
and the LO path. During the initialization sequence, the default
conditions are loaded. See Step 3 to Step 7 in Table 6.
REGISTER 2
Register 2 Control Bits
With Bits[C2:C1] set to 10, Register R2 is programmed. Figure 20
shows the input data format for programming this register.
5-Bit Channel Test Select
Bits[DB14:DB10] control the ADF5904 test modes. These bits
allow access to the temperature sensor on the ATEST pin and
the register readback on the DOUT pin. See Figure 20 for the
truth table.
Data Sheet ADF5904
Rev. A | Page 13 of 15
INITIALIZATION SEQUENCE
After powering up the device, administer the initialization
sequence in Table 6 to set the register with the code to configure
the device.
Table 6. Initialization Sequence
Step Register Hex Code Description
1 R3 0x00000003 Reserved
2 R2 0x00020406 Temperature sensor to ATEST
3 R1 0x20001499 Configure Channel 1
4 R1 0x40001499 Configure Channel 2
5 R1 0x60001499 Configure Channel 3
6 R1 0x80001499 Configure Channel 4
7 R1 0xA0000019 Configure LO
8 R0 0x80007CA0 Power up
TEMPERATURE SENSOR
The on-chip temperature sensor of the ADF5904 is accessed on
the ATEST pin. The temperature sensor operates over the full
operating temperature range of −40°C to +105°C. To improve
accuracy, conduct a one-point calibration at room temperature
and store the result in the external memory. Convert the ATEST
voltage to temperature by using the following equation:
Temperature (°C) = (VATEST − VOFF)/VGAIN
where:
VATEST is the voltage on the ATEST pin.
VOFF is the offset voltage and it is 1.212 V.
VGAIN is the voltage gain and it is 4.072e−3.
ADF5904 Data Sheet
Rev. A | Page 14 of 15
APPLICATION INFORMATION
APPLICATION OF THE ADF5904 IN FMCW RADAR
Figure 21 shows the application of the ADF5904 in a frequency
modulated continuous wave (FMCW) radar system.
In the FMCW radar system, the ADF4159 generates the
sawtooth or triangle ramps necessary for this type of radar to
operate.
The ADF4159 controls the VTUNE pin on the transceiver (Tx)
monolithic microwave integrated circuit (MMIC) and thus the
frequency of the voltage controlled oscillator (VCO) and the Tx
output signal on TXOUT1 or TXOUT2. The LO signal from the
Tx MMIC is fed to the LO input on the ADF5904.
The ADF5904 downconverts the signal from the four receiver
antennas to baseband with the LO signal from the Tx MMIC.
The downconverted baseband signals from the four receiver
channels on the ADF5904 are fed to the ADAR7251 4-channel,
continuous time (CT), sigma-delta (Σ-Δ) analog-to-digital
converter (ADC).
A digital signal processor (DSP) follows the ADC to handle the
target information processing.
TX_MMIC
ADF5904
ADF4159
TXOUT1
TXOUT2
RX3_RF
RX2_RF
RX1_RF
RX4_RF
LO_IN
LO_OUT
RF
IN
A
RF
IN
B
AUX
AUX
ADAR7251DSP RX BASEBAND
VTUNECP
LOOP
FILTER
12885-021
Figure 21. FMCW Radar with ADF5904
Data Sheet ADF5904
Rev. A | Page 15 of 15
OUTLINE DIMENSIONS
08-16-2010-B
1
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDI
C
ATOR
32
916
17
2425
8
EXPOSED
PAD
PIN 1
INDICATOR
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 RE F
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.80
0.75
0.70
FOR PROPER CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURAT IO N A ND
FUNCTI ON DESCRIPTIONS
SECT IO N OF T HIS DATA SHEE T.
0.50
0.40
0.30
0.25 MIN
*3.75
3.60 SQ
3.55
*COM P LI ANT TO JEDEC STANDARDS MO- 220 -WHHD-5
WITH T HE EXCEPTION O F THE EXPOSED PAD DIMENSION.
Figure 22. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5mm Body, Very Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option
ADF5904WCCPZ –40°C to + 105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADF5904WCCPZ-RL7 –40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADF5904ACPZ –40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADF5904ACPZ-RL7 –40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
EV-ADF5904SD2Z Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADF5904W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12885-0-2/16(A)
