This is information on a product in full production.
March 2012 Doc ID 14134 Rev 6 1/25
1
STWD100
Watchdog timer circuit
Datasheet − production data
Features
■Current consumption 13 µA typ.
■Available watchdog timeout periods are
3.4 ms, 6.3 ms, 102 ms and 1.6 s
■Chip enable input
■Open drain or push-pull WDO output
■Operating temperature range: –40 to +125 °C
■Package SOT23-5, SC70-5 (SOT323-5)
Applications
■Telecommunications
■Alarm systems
■Industrial equipment
■Networking
■Medical equipment
■UPS (uninterruptible power supply)
SOT23-5 (WY) SC70-5,
SOT323-5 (W8)
www.st.com
Contents STWD100
2/25 Doc ID 14134 Rev 6
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Watchdog input (WDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Watchdog output (WDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Chip enable input (EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Interfacing to microprocessors with bidirectional reset pins. . . . . . . . . . . . . . . . . . . 8
3 Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STWD100 List of tables
Doc ID 14134 Rev 6 3/25
List of tables
Table 1. SOT23-5 and SC70-5 (SOT323-5) pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. SOT23-5 - 5-lead small outline transistor package mechanical data . . . . . . . . . . . . . . . . . 19
Table 6. SC70 (SOT323-5) – 5-lead small outline transistor package mechanical data . . . . . . . . . 21
Table 7. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Device versions with marking descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
List of figures STWD100
4/25 Doc ID 14134 Rev 6
List of figures
Figure 1. SOT23-5 and SC70-5 (SOT323-5) package connections . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Open drain WDO output connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Interfacing to microprocessors with bidirectional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Normal triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Timeout without re-trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Trigger after timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Enable pin, EN, triggering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. SOT23-5 - 5-lead small outline transistor package outline . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. SC70 (SOT323-5) - 5-lead small outline transistor package outline. . . . . . . . . . . . . . . . . . 20
STWD100 Description
Doc ID 14134 Rev 6 5/25
1 Description
The STWD100 watchdog timer circuits are self-contained devices which prevent system
failures that are caused by certain types of hardware errors (non-responding peripherals,
bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).
The STWD100 watchdog timer has an input, WDI, and an output, WDO. The input is used to
clear the internal watchdog timer periodically within the specified timeout period, twd. While
the system is operating correctly, it periodically toggles the watchdog input, WDI. If the
system fails, the watchdog timer is not reset, a system alert is generated and the watchdog
output, WDO, is asserted.
The STWD100 circuit also has an enable pin, EN, which can enable or disable the watchdog
functionality. The EN pin is connected to the internal pull-down resistor. The device is
enabled if the EN pin is left floating.
Figure 1. SOT23-5 and SC70-5 (SOT323-5) package connections
1VCC
GND
WDO
EN
AI12639b
2
3
5
4WDI
Table 1. SOT23-5 and SC70-5 (SOT323-5) pin description
Pin number Name Description
1WDO
Watchdog output
2 GND Ground
3EN
Enable pin
4 WDI Watchdog input
5V
CC Supply voltage
Description STWD100
6/25 Doc ID 14134 Rev 6
Figure 2. Logic diagram
Note: WDO output is available in open drain or push-pull configuration.
Figure 3. Block diagram
Note: Positive pulse on enable pin EN longer than 1 µs resets the watchdog timer.
AI12640a
VCC
STWD100
GND
WDO
WDI
EN
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STWD100 Operation
Doc ID 14134 Rev 6 7/25
2 Operation
The STWD100 device is used to detect an out-of-control MCU. The user has to ensure
watchdog reset within the watchdog timeout period, otherwise the watchdog output is
asserted and MCU is restarted. The STWD100 can be also enabled or disabled by the
chip enable pin.
2.1 Watchdog input (WDI)
The WDI input has to be toggled within the watchdog timeout period, tWD, otherwise the
watchdog output, WDO, is asserted. The internal watchdog timer, which counts the tWD
period, is cleared either:
1. by a transition on watchdog output, WDO (see Figure 8) or
2. by a pulse on enable pin, EN (see Figure 10) or
3. by toggling WDI input (low-to-high on all versions and high-to-low on STWD100xW,
STWD100xX and STWD100xY only).
The pulses on WDI input with a duration of at least 1 µs are detected and glitches shorter
than 100 ns are ignored.
If WDI is permanently tied high or low and EN is tied low, the WDO toggles every 3.4 ms
(tWD) on STWD100xP and every tWD and tPW on STWD100xW, STWD100xX and
STWD100xY (see Figure 8).
2.2 Watchdog output (WDO)
When the VCC exceeds the timer startup voltage VSTART after power-up, the internal
watchdog timer starts counting. If the timer is not cleared within the tWD, the WDO will go
low (see Figure 6).
After exceeding the tWD, the WDO is asserted for tPW on STWD100xW, STWD100xX and
STWD100xY regardless of possible WDI transitions (see Figure 9). On STWD100xP WDO
is asserted for a minimum of 10 µs and a maximum of tWD after exceeding the tWD period
(see Figure 8 and Figure 9).
The STWD100 has an active low open drain or push-pull output. An external pull-up resistor
connected to any supply voltage up to 6 V is required in case of open drain WDO output
(see Figure 4). Select a resistor value large enough to register a logic low, and small enough
to register a logic high while supplying all input current and leakage paths connected to the
reset output line. A 10 kΩ pull-up resistor is sufficient in most applications.
Operation STWD100
8/25 Doc ID 14134 Rev 6
Figure 4. Open drain WDO output connection
2.3 Chip enable input (EN)
All states mentioned in Section 2.1: Watchdog input (WDI) and Section 2.2: Watchdog
output (WDO) are valid under the condition that EN is in logical low state.
The behavior of EN is common to all versions (i.e. STWD100xP, STWD100xW, STWD100xX
and STWD100xY).
If the EN goes high after power-up in less than tWD from the moment that VCC exceeds the
timer startup voltage, VSTART
, the WDO will stay high for the same time period as EN, plus
tWD (see Figure 10).
If the EN goes high anytime during normal operation, the WDO will go high as well, but the
minimum possible WDO pulse width is 10 µs (see Figure 10).
The pulses on the EN pin with a duration of at least 1 µs are detected and glitches shorter
than 100 ns are ignored.
2.4 Applications information
Interfacing to microprocessors with bidirectional reset pins
Microprocessors with bidirectional reset pins can contend with the STWD100 watchdog
output, WDO. For example, if the WDO output is driven high and the micro wants to pull it
low, signal contention will result. To prevent this from occurring, connect a 4.7 kΩ resistor
between the WDO output and the microprocessors reset I/O as in Figure 5.
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STWD100 Operation
Doc ID 14134 Rev 6 9/25
Figure 5. Interfacing to microprocessors with bidirectional reset I/O
!)6
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6## 6##
"UFFEREDRESETTOOTHER
SYSTEMCOMPONENTS
-ICROPROCESSOR
Watchdog timing STWD100
10/25 Doc ID 14134 Rev 6
3 Watchdog timing
Figure 6. Power-up
8
8
!)6
0OWERUPWATCHDOGTIMERSTARTSRUNNINGASSOONAS6##
RISESABOVE^6
0OWERUP WATCHDOGTIMERSTARTSRUNNINGASSOONAS6##
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"UTNOINPUTTRANSITIONISREQUIREDTOBEGINTIMING
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STWD100 Watchdog timing
Doc ID 14134 Rev 6 11/25
Figure 7. Normal triggering
X
X
<
STWD100xP
STWD100xW, STWD100xX, STWD100xY
AI12663
Trigger only on rising edge.
Falling edge is ignored.
Trigger on rising and falling edge of WDI.
VCC
VCC
WDI
WDI
WDO
WDO
EN
EN
tWD
tWD
tWD
Watchdog timing STWD100
12/25 Doc ID 14134 Rev 6
Figure 8. Timeout without re-trigger
X
X
STWD100xP
STWD100xW,
STWD100xX,
STWD100xY
AI12664
After a timeout and WDO is
asserted, it will stay low for
tPW time period, then
return high. If no WDI trigger
event occurs within tWD
time period, WDO will again
assert low. This cycle repeats
until a WDI trigger event
occurs while WDO is high.
After a timeout and WDO is
asserted, it will stay low for
tWD time period, then
return high. If no WDI trigger
event occurs, WDO will again
assert low after tWD time
period. This cycle repeats
until a WDI trigger event
occurs.
VCC
VCC
WDI
WDI
WDO
WDO
EN
EN
tWD tWD tWD tWD tWD tWD
tWD tWD tWD tWD
tPW tPW tPW
STWD100 Watchdog timing
Doc ID 14134 Rev 6 13/25
Figure 9. Trigger after timeout
>10 µs min.
X
X
STWD100xP
STWD100xW, STWD100xX, STWD100xY
AI12665
If a WDI trigger occurs after the WDO output
has asserted, it is ignored, and the output
remains asserted for the specified time, tPW.
If a WDI trigger occurs after the WDO output
has asserted, the output will de-assert, but
with a pulse width of at least 10
µs (min)
.
VCC
VCC
WDI
WDI
WDO
WDO
EN
EN
Trigger ignored while
WDO is low.
tPW
tWD
Watchdog timing STWD100
14/25 Doc ID 14134 Rev 6
Figure 10. Enable pin, EN, triggering
X
DISABLED
XDISABLED
STWD100xx
STWD100xx
AI12666
Whenever EN is high, all timing is
reset, and the part is disabled.
Timing commences from 0 when
EN goes low.
If EN goes high while WDO is
asserted, WDO will de-assert but
only after the nominal minimum
pulse width of 10 µs has elapsed.
VCC
VCC
WDI
WDI
WDO
WDO
EN
EN
~ 2.2 V
X (ie, 1 or 0 but not floating)
>10 µs min.
X (ie, 1 or 0 but not floating)
< tWD tWD
tWD
tWD
STWD100 Maximum ratings
Doc ID 14134 Rev 6 15/25
4 Maximum ratings
Stressing the device above the rating listed in Ta b l e 2 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in Table 3 of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Refer
also to the STMicroelectronics SURE program and other relevant quality documents.
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
TSTG Storage temperature (VCC off) –55 to 150 °C
TSLD(1)
1. Reflow at peak temperature of 260 °C (total thermal budget not to exceed 245 °C for greater than 30 seconds).
Lead solder temperature for 10 seconds 260 °C
VIO Input or output voltage –0.3 to VCC +0.3 V
VCC Supply voltage –0.3 to 7.0 V
IOOutput current 20 mA
PDPower dissipation 320 mW
DC and AC parameters STWD100
16/25 Doc ID 14134 Rev 6
5 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in Table 4 that follows, are derived from tests
performed under the measurement conditions summarized in Table 3. Designers should
check that the operating conditions in their circuit match the operating conditions when
relying on the quoted parameters.
Table 3. Operating and AC measurement conditions
Parameter Value Unit
VCC supply voltage 2.7 to 5.5 V
Ambient operating temperature (TA) –40 to 125 °C
Input rise and fall times ≤
5ns
Input pulse voltages 0.2 to 0.8 VCC V
Input and output timing ref. voltages 0.3 to 0.7 VCC V
STWD100 DC and AC parameters
Doc ID 14134 Rev 6 17/25
Table 4. DC and AC characteristics
Symbol Description Test condition(1) Min. Typ. Max. Unit
VCC Operating voltage 2.7 5 5.5 V
ICC VCC supply current 13 26 µA
ILO Open drain output leakage current From output to the GND or VCC –1 +1 µA
Input leakage current (WDI) –1 +1 µA
VIH Input high voltage (WDI, EN)0.7 V
CC V
VIL Input low voltage (WDI, EN) 0.3 VCC V
VOL Output low voltage (WDO)VCC ≥ 2.7 V, ISINK = 1.2 mA 0.3 V
VCC ≥ 4.5 V, ISINK = 3.2 mA 0.4 V
VOH
Output high voltage (WDO) (push-pull
only)
VCC ≥ 2.7 V, ISOURCE = 500 µA 0.8 VCC V
VCC ≥ 4.5 V, ISOURCE = 800 µA 0.8 VCC V
Enable pin ( EN)
EN input pulse width 1 µs
EN glitch rejection 100 ns
EN-to-WDO delay(2) 200 ns
EN pull-down resistance 32 63 100 kΩ
Watchdog Timer
VSTART Timer startup voltage 1.9 2.2 2.7 V
tWD Watchdog timeout period
STWD100xP 2.3 3.4 4.6 ms
STWD100xW 4.3 6.3 8.6 ms
STWD100xX 71 102 142 ms
STWD100xY 1.12 1.6 2.24 s
tPW Watchdog active time 140 210 280 ms
WDI-to-WDO delay(3) 150 ns
WDI pulse width 1 µs
WDI glitch rejection 100 ns
1. Valid for ambient operating temperature: TA = –40 to 125 °C; VCC = 2.7 V to 5.5 V except where noted.
2. WDO will assert for minimum of 10 µs even if EN transitions high.
3. WDO will assert for minimum of 10 µs regardless of transition on WDI (valid for STWD100xP only).
Package mechanical data STWD100
18/25 Doc ID 14134 Rev 6
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
The maximum ratings related to soldering conditions are also marked on the inner box label.
Figure 11. SOT23-5 - 5-lead small outline transistor package outline
STWD100 Package mechanical data
Doc ID 14134 Rev 6 19/25
Table 5. SOT23-5 - 5-lead small outline transistor package mechanical data
Symbol
Dimensions
mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.20 0.90 1.45 0.047 0.035 0.057
A1 0.15 0.006
A2 1.05 0.90 1.30 0.041 0.035 0.051
B 0.40 0.35 0.50 0.016 0.014 0.020
C 0.15 0.09 0.20 0.006 0.004 0.008
D 2.90 2.80 3.00 0.114 0.110 0.118
D1 1.90 0.075
E 2.80 2.60 3.00 0.110 0.102 0.118
e 0.95 0.037
F 1.60 1.50 1.75 0.063 0.059 0.069
K 0° 10° 0° 10°
L 0.35 0.10 0.60 0.014 0.004 0.024
Package mechanical data STWD100
20/25 Doc ID 14134 Rev 6
Figure 12. SC70 (SOT323-5) - 5-lead small outline transistor package outline
SC70(SOT323-5)
STWD100 Package mechanical data
Doc ID 14134 Rev 6 21/25
Table 6. SC70 (SOT323-5) – 5-lead small outline transistor package mechanical
data
Symbol
Dimensions
mm inches
Typ. Min. Max. Typ. Min. Max.
A 0.80 1.10 0.031 0.043
A1 0.00 0.10 0.000 0.004
A2 0.90 0.80 1.00 0.035 0.031 0.039
b 0.15 0.30 0.006 0.012
c 0.10 0.22 0.004 0.009
D 2.00 1.80 2.20 0.079 0.071 0.087
E 2.10 1.80 2.40 0.083 0.071 0.094
E1 1.25 1.15 1.35 0.049 0.045 0.053
e 0.65 0.026
e1 1.30 0.051
L 0.36 0.26 0.46 0.014 0.010 0.018
< – 0° 8° – 0° 8°
N5 5
Part numbering STWD100
22/25 Doc ID 14134 Rev 6
7 Part numbering
Table 7. Ordering information scheme
Note: Please check device version availability on www.st.com.
Please contact local ST sales office for new device version request.
Example: STWD100 N P WY 3 F
Device type
STWD100
Output type
N: open drain (active low)
P: push-pull (active low)
Device version
P: tWD = 3.4 ms, tPW = tWD = 3.4 ms
W: tWD = 6.3 ms, tPW = 210 ms
X: tWD = 102 ms, tPW = 210 ms
Y: tWD = 1.6 s, tPW = 210 ms
Package
WY: SOT23-5
W8: SC70-5 (SOT323-5)
Temperature range
3: –40 to +125 °C
Shipping method
E: ECOPACK® package, tubes
F: ECOPACK® package, tape and reel
STWD100 Package marking information
Doc ID 14134 Rev 6 23/25
8 Package marking information
Table 8. Device versions with marking descriptions
Part number
Watchdog
timing period Output configuration Topside marking Bottomside
marking(1)
twd tpw
STWD100NPxxxx 3.4 ms 3.4 ms open drain WNP PYWW
STWD100NWxxxx 6.3 ms 210 ms open drain WNW PYWW
STWD100NXxxxx 102 ms 210 ms open drain WNX PYWW
STWD100NYxxxx 1.6 s 210 ms open drain WNY PYWW
STWD100PWxxxx 6.3 ms 210 ms push-pull WPW PYWW
STWD100PXxxxx 102 ms 210 ms push-pull WPX PYWW
STWD100PYxxxx 1.6 s 210 ms push-pull WPY PYWW
1. Description: P = assembly plant code, Y = assembly year (0 to 9), WW = assembly work week (01 to 52).
Revision history STWD100
24/25 Doc ID 14134 Rev 6
9 Revision history
Table 9. Document revision history
Date Revision Changes
08-Nov-2007 1 Initial release.
23-Jan-2008 2 Updated cover page and Ta bl e 4 ; document status upgraded to full
datasheet.
28-Jan-2008 3 Updated cover page.
17-Mar-2008 4 Updated cover page, Figure 4, 7, 9, and Ta b l e 4 , 8.
31-Jul-2008 5 Updated Features on cover page and Ta bl e 4 .
05-Mar-2012 6
Added product maturity information and section Applications,
updated Section 1, Section 2.4, Section 4, Section 5, Section 7 and
Section 8, ECOPACK® text, minor text corrections throughout
document.
STWD100
Doc ID 14134 Rev 6 25/25
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