576Mb: x18, x36 RLDRAM 3 Features RLDRAM 3 MT44K32M18 - 2 Meg x 18 x 16 Banks MT44K16M36 - 1 Meg x 36 x 16 Banks Options1 Features * Clock cycle and tRC timing - 0.93ns and tRC (MIN) = 8ns (RL3-2133) - 0.93ns and tRC (MIN) = 10ns (RL3-2133) - 1.07ns and tRC (MIN) = 8ns (RL3-1866) - 1.07ns and tRC (MIN) = 10ns (RL3-1866) - 1.25ns and tRC (MIN) = 8ns (RL3-1600) - 1.25ns and tRC (MIN) = 10ns (RL3-1600) - 1.25ns and tRC (MIN) = 12ns (RL3-1600) * Configuration - 32 Meg x 18 - 16 Meg x 36 * Operating temperature - Commercial (TC = 0 to +95C) - Industrial (TC = -40C to +95C) * Package - 168-ball FBGA - 168-ball FBGA (Pb-free) * Revision * 1066 MHz DDR operation (2133 Mb/s/ball data rate) * 76.8 Gb/s peak bandwidth (x36 at 1066 MHz clock frequency) * Organization - 32 Meg x 18, and 16 Meg x 36 common I/O (CIO) - 16 banks * 1.2V center-terminated push/pull I/O * 2.5V V EXT, 1.35V V DD, 1.2V V DDQ I/O * Reduced cycle time (tRC (MIN) = 8 - 12ns) * SDR addressing * Programmable READ/WRITE latency (RL/WL) and burst length * Data mask for WRITE commands * Differential input clocks (CK, CK#) * Free-running differential input data clocks (DKx, DKx#) and output data clocks (QKx, QKx#) * On-die DLL generates CK edge-aligned data and differential output data clock signals * 64ms refresh (128K refresh per 64ms) * 168-ball FBGA package * or 60 matched impedance outputs * Integrated on-die termination (ODT) * Single or multibank writes * Extended operating range (200-1066 MHz) * READ training register * Multiplexed and non-multiplexed addressing capabilities * Mirror function * Output driver and ODT calibration * JTAG interface (IEEE 1149.1-2001) PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Notes: 1 Marking -093E -093 -107E -107 -125F -125E -125 32M18 16M36 None IT PA2 RB :A 1. Not all options listed can be combined to define an offered product. Use the part catalog search on www.micron.com for available offerings. 2. Consult factory. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 576Mb: x18, x36 RLDRAM 3 Features Figure 1: 576Mb RLDRAM 3 Part Numbers Example Part Number: MT44K16M36PA-093E MT44K Configuration Package Speed Temp Temperature Configuration Commercial 32 Meg x 18 32M18 16 Meg x 36 16M36 Industrial None IT Speed Grade -093E tCK = 0.93ns (8ns tRC) Package tCK = 0.93ns (10ns tRC) 168-ball FBGA PA -093 168-ball FBGA (Pb-free) RB -107E tCK = 1.07ns (8ns tRC) -107 tCK = 1.07ns (10ns tRC) -125F tCK = 1.25ns (8ns tRC) -125E tCK = 1.25ns (10ns tRC) -125 tCK = 1.25ns (12ns tRC) BGA Part Marking Decoder Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the part number. Micron's BGA Part Marking Decoder is available on Micron's Web site at www.micron.com. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Features Contents General Description ......................................................................................................................................... 8 General Notes .............................................................................................................................................. 8 State Diagram .................................................................................................................................................. 9 Functional Block Diagrams ............................................................................................................................. 10 Ball Assignments and Descriptions ................................................................................................................. 12 Package Dimensions ....................................................................................................................................... 16 Electrical Characteristics - IDD Specifications .................................................................................................. 17 Electrical Specifications - Absolute Ratings and I/O Capacitance ..................................................................... 21 Absolute Maximum Ratings ........................................................................................................................ 21 Input/Output Capacitance .......................................................................................................................... 21 AC and DC Operating Conditions .................................................................................................................... 22 AC Overshoot/Undershoot Specifications .................................................................................................... 24 Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 27 Slew Rate Definitions for Differential Input Signals ...................................................................................... 29 ODT Characteristics ....................................................................................................................................... 30 ODT Resistors ............................................................................................................................................ 30 ODT Sensitivity .......................................................................................................................................... 32 Output Driver Impedance ............................................................................................................................... 33 Output Driver Sensitivity ............................................................................................................................ 35 Output Characteristics and Operating Conditions ............................................................................................ 36 Reference Output Load ............................................................................................................................... 39 Slew Rate Definitions for Single-Ended Output Signals ..................................................................................... 40 Slew Rate Definitions for Differential Output Signals ........................................................................................ 41 Speed Bin Tables ............................................................................................................................................ 42 AC Electrical Characteristics ........................................................................................................................... 44 Temperature and Thermal Impedance Characteristics ..................................................................................... 49 Command and Address Setup, Hold, and Derating ........................................................................................... 51 Data Setup, Hold, and Derating ....................................................................................................................... 57 Commands .................................................................................................................................................... 63 MODE REGISTER SET (MRS) Command ......................................................................................................... 64 Mode Register 0 (MR0) .................................................................................................................................... 65 tRC ............................................................................................................................................................. 66 Data Latency .............................................................................................................................................. 66 DLL Enable/Disable ................................................................................................................................... 66 Address Multiplexing .................................................................................................................................. 66 Mode Register 1 (MR1) .................................................................................................................................... 68 Output Drive Impedance ............................................................................................................................ 68 DQ On-Die Termination (ODT) ................................................................................................................... 68 DLL Reset ................................................................................................................................................... 68 ZQ Calibration ............................................................................................................................................ 69 ZQ Calibration Long ................................................................................................................................... 70 ZQ Calibration Short ................................................................................................................................... 70 AUTO REFRESH Protocol ............................................................................................................................ 71 Burst Length (BL) ....................................................................................................................................... 71 Mode Register 2 (MR2) .................................................................................................................................... 73 READ Training Register (RTR) ..................................................................................................................... 73 WRITE Protocol .......................................................................................................................................... 75 WRITE Command .......................................................................................................................................... 75 Multibank WRITE ....................................................................................................................................... 76 READ Command ............................................................................................................................................ 76 PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Features AUTO REFRESH Command ............................................................................................................................ 78 INITIALIZATION Operation ............................................................................................................................ 80 WRITE Operation ........................................................................................................................................... 83 READ Operation ............................................................................................................................................. 87 AUTO REFRESH Operation ............................................................................................................................. 90 Multiplexed Address Mode .............................................................................................................................. 93 Data Latency in Multiplexed Address Mode ................................................................................................. 98 REFRESH Command in Multiplexed Address Mode ..................................................................................... 98 Mirror Function ............................................................................................................................................ 102 RESET Operation ........................................................................................................................................... 102 IEEE 1149.1 Serial Boundary Scan (JTAG) ....................................................................................................... 103 Disabling the JTAG Feature ........................................................................................................................ 103 Test Access Port (TAP) ................................................................................................................................ 103 TAP Controller ........................................................................................................................................... 104 Performing a TAP RESET ............................................................................................................................ 106 TAP Registers ............................................................................................................................................ 106 TAP Instruction Set .................................................................................................................................... 107 Revision History ............................................................................................................................................ 113 Rev. C, Production - 12/12 ......................................................................................................................... 113 Rev. B, Advance - 1/12 ............................................................................................................................... 113 Rev. A, Advance - 6/11 ............................................................................................................................... 114 PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Features List of Figures Figure 1: 576Mb RLDRAM 3 Part Numbers ..................................................................................................... 2 Figure 2: Simplified State Diagram ................................................................................................................... 9 Figure 3: 32 Meg x 18 Functional Block Diagram ............................................................................................. 10 Figure 4: 16 Meg x 36 Functional Block Diagram ............................................................................................. 11 Figure 5: 168-Ball FBGA ................................................................................................................................. 16 Figure 6: Single-Ended Input Signal ............................................................................................................... 23 Figure 7: Overshoot ....................................................................................................................................... 24 Figure 8: Undershoot .................................................................................................................................... 24 Figure 9: V IX for Differential Signals ................................................................................................................ 25 Figure 10: Single-Ended Requirements for Differential Signals ........................................................................ 26 Figure 11: Definition of Differential AC Swing and tDVAC ................................................................................ 26 Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 28 Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# .................................. 29 Figure 14: ODT Levels and I-V Characteristics ................................................................................................ 30 Figure 15: Output Driver ................................................................................................................................ 33 Figure 16: DQ Output Signal .......................................................................................................................... 38 Figure 17: Differential Output Signal .............................................................................................................. 39 Figure 18: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 39 Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 40 Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx# ..................................................... 41 Figure 21: Example Temperature Test Point Location ...................................................................................... 50 Figure 22: Nominal Slew Rate and tVAC for tIS (Command and Address - Clock) ............................................... 53 Figure 23: Nominal Slew Rate for tIH (Command and Address - Clock) ............................................................ 54 Figure 24: Tangent Line for tIS (Command and Address - Clock) ...................................................................... 55 Figure 25: Tangent Line for tIH (Command and Address - Clock) ..................................................................... 56 Figure 26: Nominal Slew Rate and tVAC for tDS (DQ - Strobe) .......................................................................... 59 Figure 27: Nominal Slew Rate for tDH (DQ - Strobe) ........................................................................................ 60 Figure 28: Tangent Line for tDS (DQ - Strobe) ................................................................................................. 61 Figure 29: Tangent Line for tDH (DQ - Strobe) ................................................................................................ 62 Figure 30: MRS Command Protocol ............................................................................................................... 64 Figure 31: MR0 Definition for Non-Multiplexed Address Mode ........................................................................ 65 Figure 32: MR1 Definition for Non-Multiplexed Address Mode ........................................................................ 68 Figure 33: ZQ Calibration Timing (ZQCL and ZQCS) ....................................................................................... 70 Figure 34: Read Burst Lengths ........................................................................................................................ 72 Figure 35: MR2 Definition for Non-Multiplexed Address Mode ........................................................................ 73 Figure 36: READ Training Function - Back-to-Back Readout ............................................................................ 74 Figure 37: WRITE Command ......................................................................................................................... 75 Figure 38: READ Command ........................................................................................................................... 77 Figure 39: Bank Address-Controlled AUTO REFRESH Command ..................................................................... 78 Figure 40: Multibank AUTO REFRESH Command ........................................................................................... 79 Figure 41: Power-Up/Initialization Sequence ................................................................................................. 81 Figure 42: WRITE Burst ................................................................................................................................. 83 Figure 43: Consecutive WRITE Bursts ............................................................................................................. 84 Figure 44: WRITE-to-READ ............................................................................................................................ 84 Figure 45: WRITE - DM Operation .................................................................................................................. 85 Figure 46: Consecutive Quad Bank WRITE Bursts ........................................................................................... 86 Figure 47: Interleaved READ and Quad Bank WRITE Bursts ............................................................................. 86 Figure 48: Basic READ Burst .......................................................................................................................... 87 Figure 49: Consecutive READ Bursts (BL = 2) .................................................................................................. 88 Figure 50: Consecutive READ Bursts (BL = 4) .................................................................................................. 88 PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Features Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56: Figure 57: Figure 58: Figure 59: Figure 60: Figure 61: Figure 62: Figure 63: Figure 64: Figure 65: Figure 66: Figure 67: Figure 68: Figure 69: Figure 70: Figure 71: READ-to-WRITE (BL = 2) ............................................................................................................... 89 Read Data Valid Window ................................................................................................................ 89 Bank Address-Controlled AUTO REFRESH Cycle ............................................................................. 90 Multibank AUTO REFRESH Cycle ................................................................................................... 90 READ Burst with ODT .................................................................................................................... 91 READ-NOP-READ with ODT .......................................................................................................... 92 Command Description in Multiplexed Address Mode ..................................................................... 93 Power-Up/Initialization Sequence in Multiplexed Address Mode ..................................................... 94 MR0 Definition for Multiplexed Address Mode ................................................................................ 95 MR1 Definition for Multiplexed Address Mode ................................................................................ 96 MR2 Definition for Multiplexed Address Mode ................................................................................ 97 Bank Address-Controlled AUTO REFRESH Operation with Multiplexed Addressing .......................... 98 Multibank AUTO REFRESH Operation with Multiplexed Addressing ................................................ 98 Consecutive WRITE Bursts with Multiplexed Addressing ................................................................. 99 WRITE-to-READ with Multiplexed Addressing ............................................................................... 100 Consecutive READ Bursts with Multiplexed Addressing .................................................................. 100 READ-to-WRITE with Multiplexed Addressing ............................................................................... 101 TAP Controller State Diagram ........................................................................................................ 105 TAP Controller Functional Block Diagram ..................................................................................... 105 JTAG Operation - Loading Instruction Code and Shifting Out Data ................................................. 108 TAP Timing .................................................................................................................................. 109 PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Features List of Tables Table 1: 32 Meg x 18 Ball Assignments - 168-Ball FBGA (Top View) .................................................................. 12 Table 2: 16 Meg x 36 Ball Assignments - 168-Ball FBGA (Top View) .................................................................. 13 Table 3: Ball Descriptions .............................................................................................................................. 14 Table 4: IDD Operating Conditions and Maximum Limits ................................................................................ 17 Table 5: Absolute Maximum Ratings .............................................................................................................. 21 Table 6: Input/Output Capacitance ................................................................................................................ 21 Table 7: DC Electrical Characteristics and Operating Conditions ..................................................................... 22 Table 8: Input AC Logic Levels ........................................................................................................................ 22 Table 9: Control and Address Balls ................................................................................................................. 24 Table 10: Clock, Data, Strobe, and Mask Balls ................................................................................................. 24 Table 11: Differential Input Operating Conditions (CK, CK# and DKx, DKx#) ................................................... 25 Table 12: Allowed Time Before Ringback ( tDVAC) for CK, CK#, DKx, and DKx# ................................................. 27 Table 13: Single-Ended Input Slew Rate Definition .......................................................................................... 27 Table 14: Differential Input Slew Rate Definition ............................................................................................. 29 Table 15: ODT DC Electrical Characteristics ................................................................................................... 30 Table 16: RTT Effective Impedances ................................................................................................................ 31 Table 17: ODT Sensitivity Definition .............................................................................................................. 32 Table 18: ODT Temperature and Voltage Sensitivity ........................................................................................ 32 Table 19: Driver Pull-Up and Pull-Down Impedance Calculations ................................................................... 34 Table 20: Output Driver Sensitivity Definition ................................................................................................. 35 Table 21: Output Driver Voltage and Temperature Sensitivity .......................................................................... 35 Table 22: Single-Ended Output Driver Characteristics ..................................................................................... 36 Table 23: Differential Output Driver Characteristics ........................................................................................ 37 Table 24: Single-Ended Output Slew Rate Definition ....................................................................................... 40 Table 25: Differential Output Slew Rate Definition .......................................................................................... 41 Table 26: RL3 2133/1866 Speed Bins ............................................................................................................... 42 Table 27: RL3 1600 Speed Bins ....................................................................................................................... 43 Table 28: AC Electrical Characteristics ............................................................................................................ 44 Table 29: Temperature Limits ......................................................................................................................... 49 Table 30: Thermal Impedance ........................................................................................................................ 49 Table 31: Command and Address Setup and Hold Values Referenced at 1 V/ns - AC/DC-Based ........................ 51 Table 32: Derating Values for tIS/tIH - AC150/DC100-Based ............................................................................ 52 Table 33: Minimum Required Time tVAC Above V IH(AC) (or Below V IL(AC)) for Valid Transition ............................ 52 Table 34: Data Setup and Hold Values at 1 V/ns (DKx, DKx# at 2V/ns) - AC/DC-Based ..................................... 57 Table 35: Derating Values for tDS/tDH - AC150/DC100-Based ......................................................................... 58 Table 36: Minimum Required Time tVAC Above V IH(AC) (or Below V IL(AC)) for Valid Transition ............................ 58 Table 37: Command Descriptions .................................................................................................................. 63 Table 38: Command Table ............................................................................................................................. 63 Table 39: tRC_MRS MR0[3:0] values ................................................................................................................ 66 Table 40: Address Widths of Different Burst Lengths ....................................................................................... 71 Table 41: Address Mapping in Multiplexed Address Mode ............................................................................... 97 Table 42: 32 Meg x 18 Ball Assignments with MF Ball Tied HIGH ..................................................................... 102 Table 43: TAP Input AC Logic Levels .............................................................................................................. 109 Table 44: TAP AC Electrical Characteristics .................................................................................................... 109 Table 45: TAP DC Electrical Characteristics and Operating Conditions ............................................................ 110 Table 46: Identification Register Definitions .................................................................................................. 110 Table 47: Scan Register Sizes ......................................................................................................................... 111 Table 48: Instruction Codes .......................................................................................................................... 111 Table 49: Boundary Scan (Exit) ..................................................................................................................... 111 PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 General Description General Description The Micron RLDRAM 3 is a high-speed memory device designed for high-bandwidth data storage--telecommunications, networking, cache applications, etc. The chip's 16bank architecture is optimized for sustainable high-speed operation. The DDR I/O interface transfers two data bits per clock cycle at the I/O balls. Output data is referenced to the READ strobes. Commands, addresses, and control signals are also registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data strobes. Read and write accesses to the RL3 device are burst-oriented. The burst length (BL) is programmable to 2, 4, or 8 by a setting in the mode register. The device is supplied with 1.35V for the core and 1.2V for the output drivers. The 2.5V supply is used for an internal supply. Bank-scheduled refresh is supported with the row address generated internally. The 168-ball FBGA package is used to enable ultra-high-speed data transfer rates. General Notes * The functionality and the timing specifications discussed in this data sheet are for the DLL enable mode of operation. * Any functionality not specifically stated is considered undefined, illegal, and not supported, and can result in unknown operation. * Nominal conditions are assumed for specifications not defined within the figures shown in this data sheet. * Throughout this data sheet, the terms "RLDRAM," "DRAM," and "RLDRAM 3" are all used interchangeably and refer to the RLDRAM 3 SDRAM device. * References to DQ, DK, QK, DM, and QVLD are to be interpeted as each group collectively, unless specifically stated otherwise. This includes true and complement signals of differential signals. * Non-multiplexed operation is assumed if not specified as multiplexed. * A X36 Device supplies four QK/QK# sets. One per 9 DQs. If a user only wants to use two QK/QK# sets, this is allowed. The user needs to use QK0/QK0# and QK1/QK1#. QK0/QK0# will control DQ[8:0] & DQ[26:18]. QK1/QK1# will control DQ[17:9] & DQ[35:27]. The QK to DQ timing parameter to be used would be tQKQ02, tQKQ13. The unused QK/QK# pins should be left floating. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 State Diagram State Diagram Figure 2: Simplified State Diagram Initialization sequence NOP READ WRITE RESET# MRS AREF Automatic sequence Command sequence PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 10 TDI TMS TCK A[19:0]1 BA[3:0] RESET# MF WE# REF# CS# CK# CK RZQ ZQ 24 JTAG Logic and Boundary Scan Register Address register 24 Notes: Mode register Control logic ODT control 13 13 71 Rowaddress MUX Columnaddress counter/ latch Bank control logic 13 71 16 16 Bank 0 rowaddress latch and decoder ZQ CAL 5 8192 Column decoder 32 I/O gating DQM mask logic 8192 SENSE AMPLIFIERS Sense amplifiers 21 Bank 15 Bank 14 Bank 0 memory array (8192 x 32 x 8 x 18)2 Bank 1 Bank 0 ZQ CAL 144 144 144 CLK in WRITE FIFO and drivers 2 1 READ n logic n 18 18 18 18 DQ latch ZQ CAL 4 2 ODT control 18 ODT control QK/QK# generator 18 ODT control 4 RTT VDDQ/2 RCVRS RTT RTT (0 ....17) VDDQ/2 (0...3) VDDQ/2 READ Drivers DLL CK/CK# 1. Example for BL = 2; column address will be reduced with an increase in burst length. 2. 8 = (length of burst) x 2^ (number of column addresses to WRITE FIFO and READ logic). 8 4 Refresh counter ZQCL, ZQCS Figure 3: 32 Meg x 18 Functional Block Diagram Command decode PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Input logic Functional Block Diagrams TDO DM[1:0] DK0/DK0#, DK1/DK1# DQ[17:0] QK0/QK0#,QK1/QK1# QVLD 576Mb: x18, x36 RLDRAM 3 Functional Block Diagrams Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 11 ZQ TDI TMS TCK A[18:0]1 RESET# MF WE# REF# CS# CK# CK RZQ 23 JTAG Logic and Boundary Scan Register Address register 23 Mode register Control logic Notes: ODT control 13 13 61 Rowaddress MUX Columnaddress counter/ latch Bank control logic 13 61 16 16 Bank 0 rowaddress latch and decoder ZQ CAL 5 8192 Column decoder 32 I/O gating DQM mask logic 8192 SENSEamplifiers AMPLIFIERS Sense 11 Bank 15 Bank 14 Bank 0 memory array (8192 x 32 x 4 x 36)2 Bank 1 Bank 0 ZQ CAL 144 144 144 CLK in WRITE FIFO and drivers 11 READ n logic n 36 36 36 36 DQ latch ZQ CAL 2 ODT control 36 4 ODT control QK/QK# generator 36 ODT control 8 RTT VDDQ/2 RCVRS RTT VDDQ/2 READ Drivers DLL CK/CK# 1. Example for BL = 2; column address will be reduced with an increase in burst length. 2. 4 = (length of burst) x 2^ (number of column addresses to WRITE FIFO and READ logic). 8 4 Refresh counter ZQCL, ZQCS Figure 4: 16 Meg x 36 Functional Block Diagram Command decode PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Input logic Functional Block Diagrams (0...3) RTT (0 ....35) VDDQ/2 TDO DM[1:0] DK0/DK0#, DK1/DK1# DQ[35:0] QK0/QK0#, QK1/QK1# QK2/QK2#, QK3/QK3# QVLD[1:0] 576Mb: x18, x36 RLDRAM 3 Functional Block Diagrams Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Ball Assignments and Descriptions Ball Assignments and Descriptions Table 1: 32 Meg x 18 Ball Assignments - 168-Ball FBGA (Top View) 1 A 2 3 4 5 6 7 8 9 10 11 12 13 VSS VDD NF VDDQ NF VREF DQ7 VDDQ DQ8 VDD VSS RESET# B VEXT VSS NF VSSQ NF VDDQ DM0 VDDQ DQ5 VSSQ DQ6 VSS VEXT C VDD NF VDDQ NF VSSQ NF DK0# DQ2 VSSQ DQ3 VDDQ DQ4 VDD D A11 VSSQ NF VDDQ NF VSSQ DK0 VSSQ QK0 VDDQ DQ0 VSSQ A13 E VSS A0 VSSQ NF VDDQ NF MF QK0# VDDQ DQ1 VSSQ CS# VSS 1 F A7 NF(CS1) VDD A2 A1 WE# ZQ REF# A3 A4 VDD A5 A9 G VSS(A20)1 A15 A6 VSS BA1 VSS CK# VSS BA0 VSS A8 A18 VSS(A21)1 H A19 VDD A14 A16 VDD BA3 CK BA2 VDD A17 A12 VDD A10 J VDDQ NF VSSQ NF VDDQ NF VSS QK1# VDDQ DQ9 VSSQ QVLD VDDQ K NF VSSQ NF VDDQ NF VSSQ DK1 VSSQ QK1 VDDQ DQ10 VSSQ DQ11 L VDD NF VDDQ NF VSSQ NF DK1# DQ12 VSSQ DQ13 VDDQ DQ14 VDD M VEXT VSS NF VSSQ NF VDDQ DM1 VDDQ DQ15 VSSQ DQ16 VSS VEXT N VSS TCK VDD TDO VDDQ NF VREF DQ17 VDDQ TDI VDD TMS VSS Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 1. F2 is the Location of the extra CS (CS1) needed to support the x18 DDP device. G1 & G13 are the locations of the additional address signals (A20 & A21 respectfully) needed to support the 2Gb monolithic device. F2 is Internally connected and will mirror the A5 address signal when MF is asserted HIGH and has parasitic characteristics of an address pin. G1 & G13 are VSS pins for this device, but have been designated as the location of A20 & A21 for the future 2Gb device. 2. NF balls for the x18 configuration are internally connected and have parasitic characteristics of an I/O. Balls may be connected to VSSQ. 3. MF is assumed to be tied LOW for this ball assignment. 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Ball Assignments and Descriptions Table 2: 16 Meg x 36 Ball Assignments - 168-Ball FBGA (Top View) 1 A 2 3 4 5 6 7 8 9 10 11 12 13 VSS VDD DQ26 VDDQ DQ25 VREF DQ7 VDDQ DQ8 VDD VSS RESET# B VEXT VSS DQ24 VSSQ DQ23 VDDQ DM0 VDDQ DQ5 VSSQ DQ6 VSS VEXT C VDD DQ22 VDDQ DQ21 VSSQ DQ20 DK0# DQ2 VSSQ DQ3 VDDQ DQ4 VDD D A11 VSSQ DQ18 VDDQ QK2 VSSQ DK0 VSSQ QK0 VDDQ DQ0 VSSQ A13 E VSS A0 VSSQ DQ19 VDDQ QK2# MF QK0# VDDQ DQ1 VSSQ CS# VSS 1 F A7 NF(CS1) VDD A2 A1 WE# ZQ REF# A3 A4 VDD A5 A9 G VSS(A20)1 A15 A6 VSS BA1 VSS CK# VSS BA0 VSS A8 A18 VSS(A21)1 H NF(A19)2 VDD A14 A16 VDD BA3 CK BA2 VDD A17 A12 VDD A10 J VDDQ QVLD1 VSSQ DQ27 VDDQ QK3# VSS QK1# VDDQ DQ9 VSSQ QVLD0 VDDQ K DQ29 VSSQ DQ28 VDDQ QK3 VSSQ DK1 VSSQ QK1 VDDQ DQ10 VSSQ DQ11 L VDD DQ32 VDDQ DQ31 VSSQ DQ30 DK1# DQ12 VSSQ DQ13 VDDQ DQ14 VDD M VEXT VSS DQ34 VSSQ DQ33 VDDQ DM1 VDDQ DQ15 VSSQ DQ16 VSS VEXT N VSS TCK VDD TDO VDDQ DQ35 VREF DQ17 VDDQ TDI VDD TMS VSS Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 1. F2 is the Location of the extra CS (CS1) needed to support the x18 DDP device. G1 & G13 are the locations of the additional address signals (A20 & A21 respectfully) needed to support the 2Gb monolithic device. F2 is Internally connected so it can mirror the A5 address signal when MF is asserted HIGH and has parasitic characteristics of an address pin. G1 & G13 are just place holders for the future device. 2. NF ball for x36 configuration is internally connected and has parasitic characteristics of an address (A19 for x18 configuration). Ball may be connected to VSSQ. 3. MF is assumed to be tied LOW for this ball assignment. 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Ball Assignments and Descriptions Table 3: Ball Descriptions Symbol Type Description A[19:0] Input Address inputs: A[19:0] define the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings along with BA[3:0]. They are sampled at the rising edge of CK. BA[3:0] Input Bank address inputs: Select the internal bank to which a command is being applied. CK/CK# Input Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising edge of CK. CS# Input Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When the command decoder is disabled, new commands are ignored, but internal operations continue. DQ[35:0] I/O Data input: The DQ signals form the 36-bit data bus. During READ commands, the data is referenced to both edges of QK. During WRITE commands, the data is sampled at both edges of DK. DKx, DKx# Input Input data clock: DKx and DKx# are differential input data clocks. All input data is referenced to both edges of DKx. For the x36 device, DQ[8:0] and DQ[26:18] are referenced to DK0 and DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1 and DK1#. For the x18 device, DQ[8:0] are referenced to DK0 and DK0#, and DQ[17:9] are referenced to DK1 and DK1#. DKx and DKx# are free-running signals and must always be supplied to the device. DM[1:0] Input Input data mask: DM is the input mask signal for WRITE data. Input data is masked when DM is sampled HIGH. DM0 is used to mask the lower byte for the x18 device and DQ[8:0] and DQ[26:18] for the x36 device. DM1 is used to mask the upper byte for the x18 device and DQ[17:9] and DQ[35:27] for the x36 device. Tie DM[1:0] to VSS if not used. TCK Input IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used. TMS, TDI Input IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used. WE#, REF# Input Command inputs: Sampled at the positive edge of CK, WE# and REF# (together with CS#) define the command to be executed. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. RESET# assertion and deassertion are asynchronous. RESET# is a CMOS input defined with DC HIGH 0.8 x VDD and DC LOW 0.2 x VDDQ. ZQ Input External impedance: This signal is used to tune the device's output impedance and ODT. RZQ needs to be 240, where RZQ is a resistor from this signal to ground. QKx, QKx# Output Output data clocks: QK and QK# are opposite-polarity output data clocks. They are free-running signals and during READ commands are edge-aligned with the DQs. For the x36 device, QK0, QK0# align with DQ[8:0]; QK1, QK1# align with DQ[17:9]; QK2, QK2# align with DQ[26:18]; QK3, QK3# align with DQ[35:27]. For the x18 device, QK0, QK0# align with DQ[8:0]; QK1, QK1# align with DQ[17:9]. QVLDx Output Data valid: The QVLD ball indicates that valid output data will be available on the subsequent rising clock edge. There is a single QVLD ball for the x18 device and two, QVLD0 and QVLD1, for the x36 device. QVLD0 aligns with DQ[17:0]; QVLD1 aligns with DQ[35:18]. MF Input Mirror function: The mirror function ball is a DC input used to create mirrored ballouts for simple dual-loaded clamshell mounting. If the ball is tied to VSS, the address and command balls are in their true layout. If the ball is tied to VDDQ, they are in the complement location. MF must be tied HIGH or LOW and cannot be left floating. MF is a CMOS input defined with DC HIGH 0.8 x VDD and DC LOW 0.2 x VDDQ. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Ball Assignments and Descriptions Table 3: Ball Descriptions (Continued) Symbol Type TDO Output IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function is not used. VDD Supply Power supply: 1.35V nominal. See Table 7 (page 22) for range. VDDQ Supply DQ power supply: 1.2V nominal. Isolated on the device for improved noise immunity. See Table 7 (page 22) for range. VEXT Supply Power supply: 2.5V nominal. See Table 7 (page 22) for range. VREF Supply Input reference voltage: VDDQ/2 nominal. Provides a reference voltage for the input buffers. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. NC - No connect: These balls are not connected to the DRAM. NF - No function: These balls are connected to the DRAM, but provide no functionality. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Description 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Package Dimensions Package Dimensions Figure 5: 168-Ball FBGA Seating plane A 168X O0.55 Dimensions apply to solder balls postreflow on O0.40 NSMD ball pads. 0.12 A Ball A1 ID 13 12 11 10 9 8 7 6 5 4 3 2 Ball A1 ID 1 A B C D 13.5 0.1 E F G 12 CTR H J K L M 1 TYP N 1 TYP 1.1 0.1 12 CTR 0.325 MIN 13.5 0.1 Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 1. All dimensions are in millimeters. 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. tCK = idle; All banks idle; No inputs toggling CS# = 1; No commands; Bank address incremented and half address/ data change once every four clock cycles BL = 2; Sequential bank access; Bank transitions once every tRC; Half address transitions once every tRC; Read followed by write sequence; Continuous data during WRITE commands BL = 4; Sequential bank access; Bank transitions once every tRC; Half address transitions once every tRC; Read followed by write sequence; Continuous data during WRITE commands BL = 8; Sequential bank access; Bank transitions once every tRC; Half address transitions once every tRC; Read followed by write sequence; Continuous data during WRITE commands Sixteen bank cyclic refresh using Bank Address Control AREF protocol; Command bus remains in refresh for all sixteen banks; DQs are High-Z and at VDDQ/2; Addresses are at VDDQ/2 Standby current Clock active standby current Operational current: BL2 Operational current: BL4 Operational current: BL8 Burst refresh current Notes 1-6 apply to the entire table Description Condition PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 17 1215 35 IDD2 (VDD) x36 IDD2 (VEXT) 1550 1570 80 IREF1 (VDD) x18 IREF1 (VDD) x36 IREF1 (VEXT) 35 1205 IDD2 (VDD) x18 NA 35 IDD1 (VEXT) IDD3 (VEXT) 1185 IDD3 (VDD) x36 1175 IDD1 (VDD) x18 IDD1 (VDD) x36 1300 30 ISB2 (VEXT) IDD3 (VDD) x18 895 ISB2 (VDD) x36 80 1570 1550 35 NA 1220 35 1155 1145 35 1125 1115 30 895 870 30 30 870 ISB1 (VEXT) ISB2 (VDD) x18 125 125 ISB1 (VDD) x36 125 -093 125 -093E ISB1 (VDD) x18 Symbol Table 4: IDD Operating Conditions and Maximum Limits Electrical Characteristics - IDD Specifications 75 1420 1400 35 NA 1200 35 1140 1130 35 1110 1100 30 835 815 30 125 125 -107E 75 1420 1400 35 NA 1130 35 1080 1075 35 1055 1045 30 835 815 30 125 125 -107 70 1245 1230 35 N/A 1085 35 1030 1020 35 1000 990 30 740 725 30 125 125 -125F 70 1245 1230 35 NA 1030 35 980 970 35 950 940 30 740 725 30 125 125 -125E 70 1245 1230 35 NA 1000 35 950 945 35 925 915 30 740 725 30 125 125 -125 mA mA mA mA mA mA Units 7 Notes 576Mb: x18, x36 RLDRAM 3 Electrical Characteristics - IDD Specifications Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 18 BL = 4; Cyclic bank access using Dual Bank WRITE; Half of address bits change every two clock cycles; Continuous data; Measurement is taken during continuous WRITE BL = 4; Cyclic bank access using Quad Bank WRITE; Half of address bits change every two clock cycles; Continuous data; Measurement is taken during continuous WRITE; Subject to tSAW specification Multibank write current: Dual bank write Multibank write current: Quad bank write BL = 8; Cyclic bank access; Half of Operating burst write cur- address bits change every four clock cycles; Continuous data; Measurerent :BL8 ment is taken during continuous WRITE BL = 4; Cyclic bank access; Half of Operating burst write cur- address bits change every two clock cycles; Continuous data; Measurerent : BL4 ment is taken during continuous WRITE BL = 2; Cyclic bank access; Half of Operating burst write cur- address bits change every clock cycle; Continuous data; Measurement rent : BL2 is taken during continuous WRITE Multibank re- Quad bank refresh using Multibank fresh current: AREF protocol; BL = 4; Cyclic bank 4 bank refresh access; Subject to tSAW and tMMD specifications; DQs are High-Z and at VDDQ/2; Bank addresses are at VDDQ/2 Distributed Single bank refresh using Bank Adrefresh current dress Control AREF protocol; Sequential bank access every 0.489s; DQs are High-Z and at VDDQ/2; Addresses are at VDDQ/2 Notes 1-6 apply to the entire table Description Condition 2965 3195 130 IQBWR (VEXT) 80 IDBWR (VEXT) IQBWR (VDD) x18 2400 IDBWR (VDD) x36 IQBWR (VDD) x36 2305 55 IDD4W (VEXT) IDBWR (VDD) x18 1815 IDD4W (VDD) x36 45 1730 IDD4W (VDD) x18 IDD8W (VEXT) 80 IDD2W (VEXT) NA 2290 IDD2W (VDD) x36 IDD8W (VDD) x36 2110 IDD2W (VDD) x18 1475 130 IMBREF4 (VEXT) IDD8W (VDD) x18 2155 30 IREF2 (VEXT) IMBREF4 (VDD) x36 900 IREF2 (VDD) x36 2130 875 IREF2 (VDD) x18 IMBREF4 (VDD) x18 -093E Symbol Table 4: IDD Operating Conditions and Maximum Limits (Continued) 130 3195 2965 80 2400 2305 45 NA 1475 55 1815 1730 80 2290 2110 130 1950 1925 30 900 875 -093 115 3000 2890 75 2250 2170 40 NA 1335 55 1665 1590 75 2070 1910 115 2050 2030 30 840 820 -107E 115 3000 2890 75 2250 2170 40 NA 1335 55 1665 1590 75 2070 1910 115 1830 1810 30 840 820 -107 100 2615 2525 70 1960 1885 40 NA 1190 50 1460 1395 70 1805 1665 105 1900 1885 30 745 730 -125F 100 2615 2525 70 1960 1885 40 NA 1190 50 1460 1395 70 1805 1665 105 1900 1885 30 745 730 -125E 100 2615 2525 70 1960 1885 40 NA 1190 50 1460 1395 70 1805 1665 105 1660 1645 30 745 730 -125 mA mA mA mA mA mA mA Units Notes 576Mb: x18, x36 RLDRAM 3 Electrical Characteristics - IDD Specifications Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. BL = 2; Cyclic bank access; Half of address bits change every clock cycle; Continuous data; Measurement is taken during continuous READ BL = 4; Cyclic bank access; Half of address bits change every two clock cycles; Continuous data; Measurement is taken during continuous READ BL = 8; Cyclic bank access; Half of address bits change every four clock cycles; Continuous data; Measurement is taken during continuous READ Operating burst read current example Operating burst read current example Operating burst read current example Notes 1-6 apply to the entire table Description Condition 2250 2395 80 1740 1835 55 1450 NA 45 IDD2R (VDD) x18 IDD2R (VDD) x36 IDD2R (VEXT) IDD4R (VDD) x18 IDD4R (VDD) x36 IDD4R (VEXT) IDD8R (VDD) x18 IDD8R (VDD) x36 IDD8R (VEXT) -093E Symbol Table 4: IDD Operating Conditions and Maximum Limits (Continued) PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 45 NA 1450 55 1835 1740 80 2395 2250 -093 40 NA 1315 55 1685 1595 75 2180 2045 -107E 40 NA 1315 55 1685 1595 75 2180 2045 -107 40 NA 1175 50 1475 1400 70 1895 1785 -125F 40 NA 1175 50 1475 1400 70 1895 1785 -125E 40 NA 1175 50 1475 1400 70 1895 1785 -125 mA mA mA Units Notes 576Mb: x18, x36 RLDRAM 3 Electrical Characteristics - IDD Specifications 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Electrical Characteristics - IDD Specifications Notes: 1. IDD specifications are tested after the device is properly initialized. 0C TC +95C; +1.28V VDD +1.42V,+1.14V VDDQ +1.26V,+2.38V VEXT +2.63V,VREF = VDDQ/2. 2. IDD mesurements use tCK (MIN), tRC (MIN), and minimum data latency (RL and WL). 3. Input slew rate is 1V/ns for single ended signals and 2V/ns for differential signals. 4. Definitions for IDD conditions: * LOW is defined as VIN VIL(AC)MAX. * HIGH is defined as VIN VIH(AC)MIN. * Continuous data is defined as half the DQ signals changing between HIGH and LOW every half clock cycle (twice per clock). * Continuous address is defined as half the address signals changing between HIGH and LOW every clock cycle (once per clock). * Sequential bank access is defined as the bank address incrementing by one every tRC. * Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL = 4 this is every other clock, and for BL = 8 this is every fourth clock. 5. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions more than once per clock cycle. 6. IDD parameters are specified with ODT disabled. 7. Upon exiting standby current conditions, at least one NOP command must be issued with stable clock prior to issuing any other valid command. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Electrical Specifications - Absolute Ratings and I/O Capacitance Electrical Specifications - Absolute Ratings and I/O Capacitance Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 5: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD VDD supply voltage relative to VSS -0.4 1.975 V VDDQ Voltage on VDDQ supply relative to VSS -0.4 1.66 V Voltage on any ball relative to VSS -0.4 1.66 V Voltage on VEXT supply relative to VSS -0.4 2.8 V VIN,VOUT VEXT Input/Output Capacitance Table 6: Input/Output Capacitance Notes 1 and 2 apply to entire table RL3-2133 Capacitance Parameters Symbol Min CK/CK# CCK C: CK to CK# CDCK Single-ended I/O: DQ, DM Input strobe: DK/DK# RL3-1866 Max Min 1.3 2.1 0 0.15 CIO 1.9 CIO 1.9 RL3-1600 Max Min Max Units 1.3 2.1 1.3 2.2 pF 0 0.15 0 0.15 pF 2.9 1.9 3.0 2.0 3.1 pF 2.9 1.9 3.0 2.0 3.1 pF Notes 3 CIO 1.9 2.9 1.9 3.0 2.0 3.1 pF C: DK to DK# CDDK 0 0.15 0 0.15 0 0.15 pF C: QK to QK# CDQK 0 0.15 0 0.15 0 0.15 pF C: DQ to QK or DQ to DK CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 4 Output strobe: QK/QK#, QVLD Inputs (CMD, ADDR) C: CMD_ADDR to CK JTAG balls RESET#, MF balls Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN CI 1.25 2.25 1.25 2.25 1.25 2.25 pF 5 CDI_CMD_ADDR -0.5 0.3 -0.5 0.3 -0.4 0.4 pF 6 CJTAG 1.5 4.5 1.5 4.5 1.5 4.5 pF 7 CI - 3.0 - 3.0 - 3.0 pF 1. +1.28V VDD +1.42V, +1.14V VDDQ 1.26V, +2.38V VEXT +2.63V, VREF = VSS, f = 100 MHz, TC = 25C, VOUT(DC) = 0.5 x VDDQ, VOUT (peak-to-peak) = 0.1V. 2. Capacitance is not tested on ZQ ball. 3. DM input is grouped with the I/O balls, because they are matched in loading. 4. CDIO = CIO(DQ) - 0.5 x (CIO [QK] + CIO [QK#]). 5. Includes CS#, REF#, WE#, A[19:0], and BA[3:0]. 6. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 x (CCK [CK] + CCK [CK#]). 7. JTAG balls are tested at 50 MHz. 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC and DC Operating Conditions AC and DC Operating Conditions Table 7: DC Electrical Characteristics and Operating Conditions Note 1 applies to the entire table; Unless otherwise noted: 0C TC +95C; +1.28V VDD +1.42V Description Symbol Min Max Units Supply voltage VEXT 2.38 2.63 V Supply voltage VDD 1.28 1.42 V Isolated output buffer supply VDDQ 1.14 1.26 V Reference voltage VREF 0.49 x VDDQ 0.51 x VDDQ V Input HIGH (logic 1) voltage VIH(DC) VREF + 0.10 VDDQ V Input LOW (logic 0) voltage VIL(DC) VSS VREF - 0.10 V Input leakage current: Any input 0V VIN VDD, VREF ball 0V VIN 1.1V (All other balls not under test = 0V) ILI -2 2 A Reference voltage current (All other balls not under test = 0V) IREF -5 5 A Notes: Notes 2, 3 1. All voltages referenced to VSS (GND). 2. The nominal value of VREF is expected to be 0.5 x VDDQ of the transmitting device. VREF is expected to track variations in VDDQ. 3. Peak-to-peak noise (non-common mode) on VREF may not exceed 2% of the DC value. DC values are determined to be less than 20 MHz. Peak-to-peak AC noise on VREF should not exceed 2% of VREF(DC). Thus, from VDDQ/2, VREF is allowed 2% VDDQ/2 for DC error and an additional 2% VDDQ/2 for AC noise. The measurement is to be taken at the nearest VREF bypass capacitor. Table 8: Input AC Logic Levels Notes 1-3 apply to entire table; Unless otherwise noted: 0C TC +95C; +1.28V VDD +1.42V Description Symbol Min Max Units Input HIGH (logic 1) voltage VIH(AC) VREF + 0.15 - V Input LOW (logic 0) voltage VIL(AC) - VREF - 0.15 V Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 1. All voltages referenced to VSS (GND). 2. The receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above/below the DC input LOW/HIGH level. 3. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak). 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC and DC Operating Conditions Figure 6: Single-Ended Input Signal VIL and VIH levels with ringback 1.60V VDDQ + 0.4V narrow pulse width 1.20V VDDQ Minimum VIL and VIH levels 0.750V 0.70V VIH(AC) VIH(DC) 0.624V 0.612V 0.60V 0.588V 0.576V 0.50V 0.45V 0.750V VIH(AC) 0.70V VIH(DC) 0.624V 0.612V 0.60V 0.588V 0.576V VIL(DC) VIL(AC) VREF + AC noise VREF + DC error VREF - DC error VREF - AC noise 0.50V VIL(DC) 0.450V VIL(AC) VSS 0.0V VSS - 0.4V narrow pulse width -0.40V PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC and DC Operating Conditions AC Overshoot/Undershoot Specifications Table 9: Control and Address Balls Parameter RL3-2133 RL3-1866 RL3-1600 Maximum peak amplitude allowed for overshoot area 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area 0.4V 0.4V 0.4V Maximum overshoot area above VDDQ 0.25 Vns 0.28 Vns 0.33 Vns Maximum undershoot area below VSS/VSSQ 0.25 Vns 0.28 Vns 0.33 Vns RL3-2133 RL3-1866 RL3-1600 Maximum peak amplitude allowed for overshoot area 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area 0.4V 0.4V 0.4V Maximum overshoot area above VDDQ 0.10 Vns 0.11 Vns 0.13 Vns Maximum undershoot area below VSS/VSSQ 0.10 Vns 0.11 Vns 0.13 Vns Table 10: Clock, Data, Strobe, and Mask Balls Parameter Figure 7: Overshoot Maximum amplitude Overshoot area Volts (V) VDDQ Time (ns) Figure 8: Undershoot VSS/VSSQ Volts (V) Undershoot area Maximum amplitude Time (ns) PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC and DC Operating Conditions Table 11: Differential Input Operating Conditions (CK, CK# and DKx, DKx#) Notes 1 and 2 apply to entire table Parameter/Condition Symbol Min Differential input voltage logic HIGH - slew VIH,diff_slew +200 n/a mV 3 Differential input voltage logic LOW - slew VIL,diff_slew n/a -200 mV 3 Differential input voltage logic HIGH VIH,diff(AC) 2 x (VIH(AC) - VREF) VDDQ mV 4 Differential input voltage logic LOW VIL,diff(AC) VSSQ 2 x (VIL(AC) - VREF ) mV 5 Differential input crossing voltage relative to VDD/2 Max Units Notes VIX VREF(DC) - 150 VREF(DC) + 150 mV 6 Single-ended HIGH level VSEH VIH(AC) VDDQ mV 4 Single-ended LOW level VSEL VSSQ VIL(AC) mV 5 Notes: 1. 2. 3. 4. CK/CK# and DKx/DKx# are referenced to VDDQ and VSSQ. Differential input slew rate = 2 V/ns. Defines slew rate reference points, relative to input crossing voltages. Maximum limit is relative to single-ended signals; overshoot specifications are applicable. 5. Minimum limit is relative to single-ended signals; undershoot specifications are applicable. 6. The typical value of VIX is expected to be about 0.5 x VDDQ of the transmitting device and VIX is expected to track variations in VDDQ. VIX indicates the voltage at which differential input signals must cross. Figure 9: VIX for Differential Signals VDDQ VDDQ CK#, DKx# CK#, DKx# X VIX VIX VDDQ/2 X X VDDQ/2 VIX X CK, DKx CK, DKx VSSQ PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN VIX VSSQ 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC and DC Operating Conditions Figure 10: Single-Ended Requirements for Differential Signals VDDQ VSEH,min VDDQ/2 VSEH CK or DKx VSEL,max VSEL VSS Figure 11: Definition of Differential AC Swing and tDVAC tDVAC VIH,diff(AC)min VIH,diff_slew,min CK - CK# DKx - DKx# 0.0 VIL,diff_slew,max VIL,diff(AC)max half cycle PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 26 tDVAC Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC and DC Operating Conditions Table 12: Allowed Time Before Ringback (tDVAC) for CK, CK#, DKx, and DKx# Slew Rate (V/ns) MIN tDVAC (ps) at |VIH/VIL,diff(AC)| >4.0 175 4.0 170 3.0 167 2.0 163 1.9 162 1.6 161 1.4 159 1.2 155 1.0 150 <1.0 150 Slew Rate Definitions for Single-Ended Input Signals Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V REF and the first crossing of V IH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V REF and the first crossing of V IL(AC)max. Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V IL(DC)max and the first crossing of V REF. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min and the first crossing of V REF (see Figure 12 (page 28)). Table 13: Single-Ended Input Slew Rate Definition Input Slew Rates (Linear Signals) Measured Input Edge From To Calculation Setup Rising VREF VIH(AC)min [VIH(AC)min - VREF@TRS Falling VREF VIL(AC)max [VREF - VIL(AC)max@TFS Rising VIL(DC)max VREF [VREF - VIL(DC)max@TRH Falling VIH(DC)min VREF [VIH(DC)min - VREF@TFH Hold PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC and DC Operating Conditions Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals TRS Setup Single-ended input voltage (DQ, CMD, ADDR) VIH(AC)min VIH(DC)min VREF VIL(DC)max VIL(AC)max TFS TRH Hold Single-ended input voltage (DQ, CMD, ADDR) VIH(AC)min VIH(DC)min VREF VIL(DC)max VIL(AC)max TFH PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC and DC Operating Conditions Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK# and DKx, DKx#) are defined and measured as shown in the following two tables. The nominal slew rate for a rising signal is defined as the slew rate between V IL,diff,max and V IH,diff,min. The nominal slew rate for a falling signal is defined as the slew rate between V IH,diff,min and V IL,diff,max. Table 14: Differential Input Slew Rate Definition Differential Input Slew Rates (Linear Signals) Input Edge CK and DK reference Measured From To Calculation Rising VIL,diff_slew,max VIH,diff_slew,min [VIH,diff_slew,min - VIL,diff_slew,max@TRdiff Falling VIH,diff_slew,min VIL,diff_slew,max [VIH,diff_slew,min - VIL,diff_slew,max@TFdiff Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# Differential input voltage (CK, CK#; DKx, DKx#) TRdiff VIH,diff_slew,min 0 VIL,diff_slew,max TFdiff PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 ODT Characteristics ODT Characteristics ODT effective resistance, RTT, is defined by MR1[4:2]. ODT is applied to the DQ, DM, and DKx, DKx# balls. The individual pull-up and pull-down resistors (R TTPU and RTTPD) are defined as follows: RTTPU =(VDDQ - VOUT) / |IOUT|, under the condition that RTTPD is turned off RTTPD = (VOUT) / |IOUT|, under the condition that RTTPU is turned off Figure 14: ODT Levels and I-V Characteristics Chip in termination mode ODT VDDQ IPU To other circuitry such as RCV, . . . IOUT = IPD - IPU RTTPU DQ IOUT RTTPD VOUT IPD VSSQ Table 15: ODT DC Electrical Characteristics Parameter/Condition Symbol RTT effective impedance from VIL(AC) to VIH(AC) Deviation of VM with respect to VDDQ/2 Notes: Min RTT_EFF Nom Max Units See Table 16 (page 31). Vm -5 - +5 Notes 1, 2 % 3 1. Tolerance limits are applicable after proper ZQ calibration has been performed at a stable temperature and voltage. Refer to ODT Sensitivity (page 32) if either the temperature or voltage changes after calibration. 2. Measurement definition for RTT: Apply VIH(AC) to ball under test and measure current I[VIH(AC)], then apply VIL(AC) to ball under test and measure current I[VIL(AC)]: RTT VIH(AC) - VIL(AC) |I[VIH(AC)] - I[VIL(AC)]| 3. Measure voltage (VM) at the tested ball with no load: VM 2 x VM - 1 x 100 VDDQ ODT Resistors The on-die termination resistance is selected by MR1[4:2]. The following table provides an overview of the ODT DC electrical characteristics. The values provided are not speciPDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 ODT Characteristics fication requirements; however, they can be used as design guidelines to indicate what RTT is targeted to provide: * RTT is made up of RTT120(PD240) and RTT120(PU240). * RTT is made up of RTT60(PD120) and RTT60(PU120). * RTT is made up of RTT40(PD80) and RTT40(PU80). Table 16: RTT Effective Impedances RTT Resistor VOUT Min Nom Max Units RTT120(PD240) 0.2 x VDDQ 0.6 1.0 1.1 RZQ/1 0.5 x VDDQ 0.9 1.0 1.1 RZQ/1 0.8 x VDDQ 0.9 1.0 1.4 RZQ/1 RTT120(PU240) RTT60(PD120) RTT60(PU120) RTT40(PD80) RTT40(PU80) PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 31 0.2 x VDDQ 0.9 1.0 1.4 RZQ/1 0.5 x VDDQ 0.9 1.0 1.1 RZQ/1 0.8 x VDDQ 0.6 1.0 1.1 RZQ/1 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2 0.2 x VDDQ 0.6 1.0 1.1 RZQ/2 0.5 x VDDQ 0.9 1.0 1.1 RZQ/2 0.8 x VDDQ 0.9 1.0 1.4 RZQ/2 0.2 x VDDQ 0.9 1.0 1.4 RZQ/2 0.5 x VDDQ 0.9 1.0 1.1 RZQ/2 0.8 x VDDQ 0.6 1.0 1.1 RZQ/2 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/4 0.2 x VDDQ 0.6 1.0 1.1 RZQ/3 0.5 x VDDQ 0.9 1.0 1.1 RZQ/3 0.8 x VDDQ 0.9 1.0 1.4 RZQ/3 0.2 x VDDQ 0.9 1.0 1.4 RZQ/3 0.5 x VDDQ 0.9 1.0 1.1 RZQ/3 0.8 x VDDQ 0.6 1.0 1.1 RZQ/3 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/6 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 ODT Characteristics ODT Sensitivity If either temperature or voltage changes after I/O calibration, then the tolerance limits listed in Table 15 (page 30) and Table 16 (page 31) can be expected to widen according to Table 17 (page 32) and Table 18 (page 32). Table 17: ODT Sensitivity Definition Symbol Min Max Units RTT 0.9 - dRTTdT x |DT| - dRTTdV x |DV| 1.6 + dRTTdT x |DT| + dRTTdV x | DV| RZQ/(2,4,6) Note: 1. DT = T - T(@ calibration), DV = VDDQ - VDDQ(@ calibration) or VDD - VDD(@ calibration). Table 18: ODT Temperature and Voltage Sensitivity Change Min Max Units dRTTdT 0 1.5 %/C dRTTdV 0 0.15 %/mV PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Output Driver Impedance Output Driver Impedance The output driver impedance is selected by MR1[1:0] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is performed. Output specifications refer to the default output driver unless specifically stated otherwise. A functional representation of the output buffer is shown below. The output driver impedance RON is defined by the value of the external reference resistor RZQ as follows: * RON,x = RZQ/y (with RZQ = 240 rx or 60 with y = 6 or 4, respectively) The individual pull-up and pull-down resistors (RON(PU) and RON(PD)) are defined as follows: * RON(PU) = (VDDQ - V OUT)/|IOUT|, when RON(PD) is turned off * RON(PD) = (VOUT)/|IOUT|, when RON(PU) is turned off Figure 15: Output Driver Chip in drive mode Output Driver VDDQ IPU To other circuitry such as RCV, . . . RON(PU) DQ IOUT RON(PD) VOUT IPD VSSQ PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Output Driver Impedance Table 19: Driver Pull-Up and Pull-Down Impedance Calculations RON Min Nom Max Units RZQ/6 = (240 r 39.6 40 40.4 59.4 60 60.6 Driver VOUT Min Nom Max Units pull-down 0.2 x VDDQ 24 40 44 0.5 x VDDQ 36 40 44 RZQ/4 = (240 r pull-up pull-down pull-up PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 0.8 x VDDQ 36 40 56 0.2 x VDDQ 36 40 56 0.5 x VDDQ 36 40 44 0.8 x VDDQ 24 40 44 0.2 x VDDQ 36 60 66 0.5 x VDDQ 54 60 66 0.8 x VDDQ 54 60 84 0.2 x VDDQ 54 60 84 0.5 x VDDQ 54 60 66 0.8 x VDDQ 36 60 66 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Output Driver Impedance Output Driver Sensitivity If either the temperature or the voltage changes after ZQ calibration, then the tolerance limits listed in Table 19 (page 34) can be expected to widen according to Table 20 (page 35) and Table 21 (page 35). Table 20: Output Driver Sensitivity Definition Symbol Min Max Units RON(PD) @ 0.2 x VDDQ 0.6 - dRONdTH x DT - dRONdVH x DV 1.1 + dRONdTH x DT + dRONdVH x DV RZQ/(6, 4) RON(PD) @ 0.5 x VDDQ 0.9 - dRONdTM x DT - dRONdVM x DV 1.1 + dRONdTM x DT + dRONdVM x DV RZQ/(6, 4) RON(PD) @ 0.8 x VDDQ 0.9 - dRONdTL x DT - dRONdVL x DV 1.4 + dRONdTL x DT + dRONdVL x D RZQ/(6, 4) RON(PU) @ 0.2 x VDDQ 0.9 - dRONdTH x DT - dRONdVH x DV 1.4 + dRONdTH x DT + dRONdVH x DV RZQ/(6, 4) RON(PU) @ 0.5 x VDDQ 0.9 - dRONdTM x DT - dRONdVM x DV 1.1 + dRONdTM x DT + dRONdVM x DV RZQ/(6, 4) RON(PU) @ 0.8 x VDDQ 0.6 - dRONdTL x DT - dRONdVL x DV Note: 1.1 + dRONdTL x DT + dRONdVL x DV RZQ/(6, 4) 1. DT = T - T(@ calibration), DV = VDDQ - VDDQ(@ calibration) or VDD - VDD(@ calibration). Table 21: Output Driver Voltage and Temperature Sensitivity PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Change Min Max Unit dRONdTM 0 1.5 %/C dRONdVM 0 0.15 %/mV dRONdTL 0 1.5 %/C dRONdVL 0 0.15 %/mV dRONdTH 0 1.5 %/C dRONdVH 0 0.15 %/mV 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Output Characteristics and Operating Conditions Output Characteristics and Operating Conditions Table 22: Single-Ended Output Driver Characteristics Note 1 and 2 apply to entire table Parameter/Condition Symbol Min Max Units Notes Output leakage current; DQ are disabled; Any output ball 0V VOUT VDDQ; ODT is disabled; All other balls not under test = 0V IOZ -5 5 A Output slew rate: Single-ended; For rising and falling edges, measures between VOL(AC) = VREF - 0.1 x VDDQ and VOH(AC) = VREF + 0.1 x VDDQ SRQSE 2.5 6 V/ns 4, 5 Single-ended DC high-level output voltage VOH(DC) 0.8 x VDDQ V 6 Single-ended DC mid-point level output voltage VOM(DC) 0.5 x VDDQ V 6 Single-ended DC low-level output voltage VOL(DC) 0.2 x VDDQ V 6 Single-ended AC high-level output voltage VOH(AC) VTT + 0.1 x VDDQ V 7, 8, 9 Single-ended AC low-level output voltage VOL(AC) VTT - 0.1 x VDDQ V 7, 8, 9 -10 % 3 Impedance delta between pull-up and pull-down for DQ and QVLD MMPUPD Test load for AC timing and output slew rates Notes: 10 Output to VTT (VDDQ/2) via 25 resistor 9 1. All voltages are referenced to VSS. 2. RZQ is 240 (1%) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage. 3. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RON(PU) and RON(PD) at 0.5 x VDDQ: MMPUPD RonPU - RonPD RonNOM x 100 4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are either all static or switching the opposite direction. For all other DQ signal switching combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns. 5. See Table 24 (page 40) for output slew rate. 6. See the Driver Pull-Up and Pull-Down Impedance Calculations table for IV curve linearity. Do not use AC test load. 7. VTT = VDDQ/2 8. See Figure 16 (page 38) for an example of a single-ended output signal. 9. See Figure 18 (page 39) for the test load configuration. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Output Characteristics and Operating Conditions Table 23: Differential Output Driver Characteristics Notes 1 and 2 apply to entire table Parameter/Condition Symbol Min Max Units IOZ -5 5 A Output slew rate: Differential; For rising and falling edges, measures between VOL,diff(AC) = -0.2 x VDDQ and VOH,diff(AC) = +0.2 x VDDQ SRQdiff 5 12 V/ns 5 Output differential cross-point voltage VOX(AC) VREF - 150 VREF + 150 mV 6 Differential high-level output voltage VOH,diff(AC) V 6 Differential low-level output voltage VOL,diff(AC) V 6 % 3 Output leakage current; DQ are disabled; Any output ball 0V VOUT VDDQ; ODT is disabled; All other balls not under test = 0V Delta resistance between pull-up and pull-down for QK/QK# -0.2 x VDDQ -10 MMPUPD Test load for AC timing and output slew rates Notes: +0.2 x VDDQ 10 Output to VTT (VDDQ/2) via 25 resistor Notes 4 1. All voltages are referenced to VSS. 2. RZQ is 240 (1%) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage. 3. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RON(PU) and RON(PD) at 0.5 x VDDQ: MMPUPD RonPU - RonPD RonNOM x 100 4. See Figure 18 (page 39) for the test load configuration. 5. See Table 25 (page 41) for the output slew rate. 6. See Figure 17 (page 39) for an example of a differential output signal. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Output Characteristics and Operating Conditions Figure 16: DQ Output Signal MAX output VOH(AC) VOL(AC) MIN output PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Output Characteristics and Operating Conditions Figure 17: Differential Output Signal MAX output VOH,diff X X VOX(AC)max X VOX(AC)min X VOL,diff MIN output Reference Output Load The following figure represents the effective reference load of 25 used in defining the relevant device AC timing parameters as well as the output slew rate measurements. It is not intended to be a precise representation of a particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Figure 18: Reference Output Load for AC Timing and Output Slew Rate DUT VREF DQ QKx QKx# QVLD ZQ VDDQ/2 RTT = 25 VTT = VDDQ/2 Timing reference point RZQ = 240 VSS PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Slew Rate Definitions for Single-Ended Output Signals Slew Rate Definitions for Single-Ended Output Signals The single-ended output driver is summarized in the following table. With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between V OL(AC) and V OH(AC) for single-ended signals. Table 24: Single-Ended Output Slew Rate Definition Single-Ended Output Slew Rates (Linear Signals) Measured Output Edge From To Calculation DQ and QVLD Rising VOL(AC) VOH(AC) VOH(AC) - VOL(AC) VOH(AC) VOL(AC) VOH(AC) - VOL(AC) Falling TRSE TFSE Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals TRSE VOH(AC) VTT VOL(AC) TFSE PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Slew Rate Definitions for Differential Output Signals Slew Rate Definitions for Differential Output Signals The differential output driver is summarized in the following table. With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between V OL(AC) and V OH(AC) for differential signals. Table 25: Differential Output Slew Rate Definition Differential Output Slew Rates (Linear Signals) Measured Output Edge From To Calculation QKx, QKx# Rising VOL,diff(AC) VOH,diff(AC) VOH,diff(AC)max - VOL,diff(AC) VOH,diff(AC) VOL,diff(AC) VOH,diff(AC) - VOL,diff(AC) Falling TRdiff TFdiff Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx# TRdiff VOH,diff(AC) 0 VOL,diff(AC) TFdiff PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Speed Bin Tables Speed Bin Tables Table 26: RL3 2133/1866 Speed Bins The MIN tCK value for a given RL/WL parameter must be used to determine the tRC mode register setting. -093E -093 -107E -107 Parameter Symbol Min Max Min Max Min Max Min Max Units Clock Timing RL = 3 ; WL = 4 tCK (avg) 5 5 5 5 Reserved Reserved ns RL = 4 ; WL = 5 tCK (avg) 4 5 4 5 4 4 ns RL = 5 ; WL = 6 tCK (avg) 3 4.3 3 4.3 3.5 4.3 4 4.3 ns RL = 6 ; WL = 7 tCK (avg) 2.5 3.5 2.5 4 3 3.5 3 4.3 ns RL = 7 ; WL = 8 tCK (avg) 2.5 3 2.5 3 2.5 3 2.5 3 ns RL = 8 ; WL = 9 tCK (avg) 1.875 2.5 1.875 3 2 2.5 2 3 ns RL = 9 ; WL = 10 tCK (avg) 1.875 2 1.875 2 1.875 2 1.875 2 ns RL = 10 ; WL = 11 tCK (avg) 1.5 2 1.5 2 1.875 2 1.875 2 ns RL = 11 ; WL = 12 tCK (avg) 1.5 1.875 1.5 2 1.5 1.875 1.5 2 ns RL = 12 ; WL = 13 tCK (avg) 1.25 1.5 1.25 1.875 1.5 1.66 1.5 1.875 ns RL = 13 ; WL = 14 tCK (avg) 1.25 1.5 1.25 1.5 1.25 1.5 1.25 1.5 ns RL = 14 ; WL = 15 tCK (avg) 1.07 1.25 1.07 1.5 1.25 1.33 1.25 1.5 ns RL = 15 ; WL = 16 tCK (avg) 1.0 1.25 1.0 1.25 1.07 1.33 1.07 1.25 ns RL = 16 ; WL = 17 tCK (avg) 0.9375 1.25 0.9375 1.25 5 Reserved 5 Reserved ns Row Cycle Timing Row cycle time PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN tRC 8 - 10 42 - 8 - 10 - ns Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Speed Bin Tables Table 27: RL3 1600 Speed Bins The MIN tCK value for a given RL/WL parameter must be used to determine the tRC mode register setting. -125F 125E -125 Parameter Symbol Min Max Min Max Min Max Units Clock Timing RL = 3 ; WL = 4 tCK (avg) Reserved RL = 4 ; WL = 5 tCK (avg) Reserved 4 5 RL = 5 ; WL = 6 tCK (avg) Reserved 4 4.3 RL = 6 ; WL = 7 tCK (avg) Reserved 3 4.3 RL = 7 ; WL = 8 tCK (avg) Reserved 2.5 3 RL = 8 ; WL = 9 tCK (avg) Reserved 2 RL = 9 ; WL = 10 tCK (avg) Reserved RL = 10 ; WL = 11 tCK (avg) Reserved RL = 11 ; WL = 12 tCK (avg) Reserved RL = 12 ; WL = 13 tCK (avg) 1.33 RL = 13 ; WL = 14 tCK (avg) 1.25 RL = 14 ; WL = 15 tCK (avg) Reserved Reserved RL = 15 ; WL = 16 tCK (avg) Reserved Reserved RL = 16 ; WL = 17 tCK (avg) Reserved Reserved Reserved Reserved 5 ns 5 ns 4 5 ns 3.5 4.3 ns 3 3.5 ns 3 2.5 3 ns 1.875 2 2.33 2.66 ns 1.875 2 2 2.33 ns 1.5 2 1.875 2.33 ns 1.66 1.5 1.875 1.875 2 ns 1.5 1.25 1.5 1.5 1.875 ns 1.4 1.66 ns 1.33 1.66 ns 1.25 1.33 ns 12 - ns Row Cycle Timing Row cycle time PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN tRC 8 - 43 10 - Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC Electrical Characteristics AC Electrical Characteristics Table 28: AC Electrical Characteristics Notes 1-7 apply to entire table RL3-2133 Parameter Symbol Min RL3-1866 Max Min RL3-1600 Max Min Max Units Notes 488 8 488 ns 8 ns 9, 10 Clock Timing Clock period average: DLL disable mode tCK(DLL_DIS Clock period average: DLL enable mode tCK(avg) High pulse width average tCH(avg) 0.47 0.53 0.47 0.53 0.47 0.53 CK 11 Low pulse width average tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 CK 11 DLL locked tJIT(per) -50 50 -60 60 -70 70 ps 12 DLL locking tJIT(per),lck -40 40 -50 50 -60 60 ps 12 Clock period jitter ) 8 488 See tCK 8 values in the RL3 Speed Bins table. Clock absolute period tCK(abs) Clock absolute high pulse width tCH(abs) 0.43 - 0.43 - 0.43 - tCK(avg) 13 Clock absolute low pulse width tCL(abs) 0.43 - 0.43 - 0.43 - tCK(avg) 14 Cycle-tocycle jitter Cumulative error across MIN = tCK(avg),min + tJIT(per),min; MAX = tCK(avg),max + tJIT(per),max ps DLL locked tJIT(cc) 100 120 140 ps 15 DLL locking tJIT(cc),lck 80 100 120 ps 15 2 cycles tERR(2per) -74 74 -88 88 -103 103 ps 16 3 cycles tERR(3per) -87 87 -105 105 -122 122 ps 16 4 cycles tERR(4per) -97 97 -117 117 -136 136 ps 16 5 cycles tERR(5per) -105 105 -126 126 -147 147 ps 16 6 cycles tERR(6per) -111 111 -133 133 -155 155 ps 16 7 cycles tERR(7per) -116 116 -139 139 -163 163 ps 16 8 cycles tERR(8per) -121 121 -145 145 -169 169 ps 16 9 cycles tERR(9per) -125 125 -150 150 -175 175 ps 16 10 cycles tERR(10per) -128 128 -154 154 -180 180 ps 16 11 cycles tERR(11per) -132 132 -158 158 -184 184 ps 16 12 cycles tERR(12per) -134 134 -161 161 -188 188 ps 16 n = 13, 14 ... 49, 50 cycles tERR(nper) tJIT(per),min ps 16 Base (specification) tDS(AC150) tERR(nper),min tERR(nper),max = [1 + 0.68LN(n)] x = [1 + 0.68LN(n)] x tJIT(per),max DQ Input Timing Data setup time to DK, DK# VREF @ 1 V/ns PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN -30 - -15 - 10 - ps 17, 18 120 - 135 - 160 - ps 18, 19 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC Electrical Characteristics Table 28: AC Electrical Characteristics (Continued) Notes 1-7 apply to entire table RL3-2133 Parameter Data hold time from DK, DK# Base (specification) RL3-1866 RL3-1600 Symbol Min Max Min Max Min Max Units Notes tDH(DC100) 5 - 20 - 45 - ps 17, 18 105 - 120 - 145 - ps 280 - 320 - 360 - ps VREF @ 1 V/ns Minimum data pulse width tDIPW QK, QK# edge to output data edge within byte group tQKQ x - 75 - 85 - 100 ps QK, QK# edge to any output data edge within specific data word grouping (only for x36) tQKQ02, - 125 - 135 - 150 ps 22 20 DQ Output Timing tQKQ13 DQ output hold time from QK, QK# tQH 0.38 - 0.38 - 0.38 - tCK(avg) 23 DQ Low-Z time from CK, CK# tLZ -360 180 -390 195 -450 225 ps 24, 26 DQ High-Z time from CK, CK# tHZ - 180 - 195 - 225 ps 24, 26 DK (rising), DK# (falling) edge to/from CK (rising), CK# (falling) edge tCKDK -0.27 0.27 -0.27 0.27 -0.27 0.27 CK 29 DK, DK# differential input HIGH width tDKH 0.45 0.55 0.45 0.55 0.45 0.55 CK DK, DK# differential input LOW width tDKL 0.45 0.55 0.45 0.55 0.45 0.55 CK QK (rising), QK# (falling) edge to CK (rising), CK# (falling) edge tCKQK -135 135 -140 140 -160 160 ps 26 - 5% tCK + 5% tCK - 5% tCK + 5% tCK - 5% tCK + 5% tCK QK (rising), QK# (falling) edge to CK (rising), CK# (falling) edge with DLL disabled tCKQK 1 10 1 10 1 10 ns 27 Input and Output Strobe Timing DLL_DIS QK, QK# differential output HIGH time tQKH 0.4 - 0.4 - 0.4 - CK 23 QK, QK# differential output LOW time tQKL 0.4 - 0.4 - 0.4 - CK 23 tQKVLD - 125 - 135 - 150 ps 25 QK (falling), QK# (rising) edge to QVLD edge Command and Address Timing CTRL, CMD, ADDR, setup to CK,CK# Base (specification) VREF @ 1 V/ns PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN tIS(AC150) 85 - 120 - 170 - ps 28, 30 235 - 270 - 320 - ps 19, 30 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC Electrical Characteristics Table 28: AC Electrical Characteristics (Continued) Notes 1-7 apply to entire table RL3-2133 RL3-1866 RL3-1600 Parameter Symbol Min Max Min Max Min Max Units Notes CTRL, CMD, ADDR, hold from CK,CK# tIH(DC100) 65 - 100 - 120 - ps 28, 30 165 - 200 - 220 - ps 19, 30 470 - 535 - 560 - ps 20 ns 21 Base (specification) VREF @ 1 V/ns tIPW Minimum CTRL, CMD, ADDR pulse width Row cycle time tRC See minimum tRC values in the RL3 Speed Bins table. Refresh rate tREF 64 - Sixteen-bank access window tSAW 8 - 8 - 8 - ns Multibank access delay tMMD 2 - 2 - 2 - CK 33 WRITE-to-READ to same address tWTR WL + BL/2 - WL + BL/2 - WL + BL/2 - CK 32 Mode register set cycle time to any command tMRSC 12 - 12 - 12 - CK READ training register minimum READ time tRTRS 2 - 2 - 2 - CK READ training register burst end to mode register set for training register exit tRTRE 1 - 1 - 1 - CK - CK 64 - 64 - ms Calibration Timing ZQCL: Long POWER-UP and calibration RESET operation time Normal operation ZQCS: Short calibration time tZQinit 512 - 512 - 512 tZQoper 256 - 256 - 256 - CK tZQcs 64 - 64 - 64 - CK Initialization and Reset Timing Begin power-supply ramp to power supplies stable tV DDPR - 200 - 200 - 200 ms RESET# LOW to power supplies stable tRPS - 200 - 200 - 200 ms RESET# LOW to I/O and RTT High-Z tIOz - 20 - 20 - 20 ns Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 31 1. Parameters are applicable with 0C TC +95C; +1.28V VDD +1.42V, +2.38V VEXT +2.63V, +1.14V VDDQ 1.26V. 2. All voltages are referenced to VSS. 3. The unit tCK(avg) represents the actual tCK(avg) of the input clock under operation. The unit CK represents one clock cycle of the input clock, counting the actual clock edges. 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/DC trip points and CK,CK# and DKx, DKx# use their crossing points). The minimum slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs and 2 V/ns for differential inputs in the range between VIL(AC) and VIH(AC). 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC Electrical Characteristics 5. All timings that use time-based values (ns, s, ms) should use tCK(avg) to determine the correct number of clocks. In the case of noninteger results, all minimum limits should be rounded up to the nearest whole integer, and all maximum limits should be rounded down to the nearest whole integer. 6. The term "strobe" refers to the DK and DK# or QK and QK# differential crossing point when DK and QK, respectively, is the rising edge. Clock, or CK, refers to the CK and CK# differential crossing point when CK is the rising edge. 7. The output load defined in Figure 18 (page 39) is used for all AC timing and slew rates. The actual test load may be different. The output signal voltage reference point is VDDQ/2 for single-ended signals and the crossing point for differential signals. 8. When operating in DLL disable mode, Micron does not warrant compliance with normal mode timings or functionality. 9. The clock's tCK(avg) is the average clock over any 200 consecutive clocks and tCK(avg),min is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. 10. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread spectrum at a sweep rate in the range of 20-60 kHz with an additional 1% of tCK(avg) as a long-term jitter component; however, the spread spectrum may not use a clock rate below tCK(avg),min. 11. The clock's tCH(avg) and tCL(avg) are the average half-clock period over any 200 consecutive clocks and is the smallest clock half-period allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. 12. The period jitter, tJIT(per), is the maximum deviation in the clock period from the average or nominal clock. It is allowed in either the positive or negative direction. 13. tCH(abs) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. 14. tCL(abs) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge. 15. The cycle-to-cyle jitter, tJIT(cc), is the amount the clock period can deviate from one cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time. 16. The cumulative jitter error, tERR(nper), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. 17. tDS(base) and tDH(base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns differential DK, DK# slew rate. 18. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DK, DK#) crossing. 19. The setup and hold times are listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate of 1 V/ns, are for reference only. 20. Pulse width of an input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC). 21. Bits MR0[3:0] select the number of clock cycles required to satisfy the minimum tRC value. Minimum tRC value must be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge that the subsequent command can be issued to the bank. 22. tQKQ02 defines the skew between QK0 and DQ[26:18] and between QK2 and DQ[8:0]. tQKQ13 defines the skew between QK1 and DQ[35:27] and between QK3 and DQ[17:9]. 23. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) (the larger of tJIT(per),min or tJIT(per),max of the input clock; output deratings are relative to the SDRAM input clock). PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AC Electrical Characteristics 24. Single-ended signal parameter. 25. For x36 device this specification references the skew between the falling edge of QK0 and QK1 to QVLD0 and the falling edge of QK2 and QK3 to QVLD1. 26. The DRAM output timing is aligned to the nominal or average clock. The following output parameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR(10per),max: tCKQK (MIN), and tLZ (MIN). The following parameters are required to be derated by subtracting tERR(10per),min: tCKQK (MAX), tHZ (MAX), and tLZ (MAX). 27. The tDQSCKdll_dis parameter begins RL - 1 cycles after the READ command. 28. tIS(base) and tIH(base) values are for a single-ended 1 V/ns control/command/address slew rate and 2 V/ns CK, CK# differential slew rate. 29. These parameters are measured from the input data strobe signal (DK/DK#) crossing to its respective clock signal crossing (CK/CK#). The specification values are not affected by the amount of clock jitter applied as they are relative to the clock signal crossing. These parameters should be met whether or not clock jitter is present. 30. These parameters are measured from a command/address signal transition edge to its respective clock (CK, CK#) signal crossing. The specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be met whether or not clock jitter is present. 31. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current, depending on bus activity. 32. If tWTR is violated, the data just written will not be read out when a READ command is issued to the same address. Whatever data was previously written to the address will be output with the READ command. 33. This specification is defined as any bank command (READ, WRITE, AREF) to a multi-bank command or a multi-bank command to any bank command. This specification only applies to quad bank WRITE, 3-bank AREF and 4-bank AREF commands. Dual bank WRITE, 2-bank AREF, and all single bank access commands are not bound by this specification. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Temperature and Thermal Impedance Characteristics Temperature and Thermal Impedance Characteristics It is imperative that the device's temperature specifications be maintained in order to ensure that the junction temperature is in the proper operating range to meet data sheet specifications. An important way to maintain the proper junction temperature is to use the device's thermal impedances correctly. Thermal impedances are listed for the available packages. Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, "Thermal Applications" prior to using thermal impedances listed below. The device's safe junction temperature range can be maintained when the T C specification is not exceeded. In applications where the device's ambient temperature is too high, use of forced air and/or heat sinks may be required in order to meet the case temperature specifications. Table 29: Temperature Limits Parameter Storage temperature Reliability junction temperature Commercial Symbol Min Max Units Notes TSTG -55 150 C 1 TJ(REL) - 110 C 2 - 110 C 2 Industrial Operating junction temperature Commercial TJ(OP) Industrial Operating case temperature Commercial TC Industrial Notes: 0 100 C 3 -40 100 C 3 0 95 C 4, 5 -40 95 C 4, 5 1. MAX storage case temperature; TSTG is measured in the center of the package (see Figure 21 (page 50)). This case temperature limit is allowed to be exceeded briefly during package reflow, as noted in Micron technical note TN-00-15. 2. Temperatures greater than 110C may cause permanent damage to the device. This is a stress rating only and functional operation of the device at or above this is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect the reliability of the part. 3. Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow. 4. MAX operating case temperature; TC is measured in the center of the package (see Figure 21 (page 50)). 5. Device functionality is not guaranteed if the device exceeds maximum TC during operation. Table 30: Thermal Impedance JA (C/W) Airflow = 0m/s JA (C/W) Airflow = 1m/s JA (C/W) Airflow = 2m/s JB (C/W) JC (C/W) 2-layer 39.3 28.8 25.2 16.3 2.0 4-layer 22.0 17.2 15.9 10.3 Package Substrate FBGA Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 1. Thermal impedance data is based on a number of samples from multiple lots, and should be viewed as a typical number. 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Temperature and Thermal Impedance Characteristics Figure 21: Example Temperature Test Point Location Test point 13.5mm 6.75mm 6.75mm 13.5mm PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Command and Address Setup, Hold, and Derating Command and Address Setup, Hold, and Derating The total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS (base) and tIH (base) values (see Table 31 (page 51); values come from Table 28 (page 44)) to the tIS and tIH derating values (see Table 32 (page 52)), respectively. Example: tIS (total setup time) = tIS (base) + tIS. For a valid transition, the input signal must remain above/below V IH(AC)/VIL(AC) for some time tVAC (see Table 33 (page 52)). Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached V IH(AC)/VIL(AC) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach V IH(AC)/ VIL(AC). For slew rates which fall between the values listed in Table 32 (page 52) and Table 33 (page 52) for Valid Transition, the derating values may be obtained by linear interpolation. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V REF(DC) and the first crossing of V IL(AC)max. If the actual signal is always earlier than the nominal slew rate line between the shaded V REF(DC)-to-AC region, use the nominal slew rate for derating value (see Figure 22 (page 53)). If the actual signal is later than the nominal slew rate line anywhere between the shaded V REF(DC)-to-AC region, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value (see Figure 24 (page 55)). Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min and the first crossing of V REF(DC). If the actual signal is always later than the nominal slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derating value (see Figure 23 (page 54)). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual signal from the DC level to the V REF(DC) level is used for derating value (see Figure 25 (page 56)). Table 31: Command and Address Setup and Hold Values Referenced at 1 V/ns - AC/DC-Based Symbol RL3-2133 RL3-1866 RL3-1600 Units Reference tIS(base),AC150 85 120 170 ps VIH(AC)/VIL(AC) tIH(base),DC100 65 100 120 ps VIH(DC)/VIL(DC) PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Command and Address Setup, Hold, and Derating Table 32: Derating Values for tIS/tIH - AC150/DC100-Based tIS, tIH Derating (ps) - AC/DC-Based AC 150 Threshold: VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV CK, CK# Differential Slew Rate CMD/ADDR Slew Rate (V/ns) tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH 2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40 0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns Table 33: Minimum Required Time tVAC Above VIH(AC) (or Below VIL(AC)) for Valid Transition tVAC Slew Rate (V/ns) PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN (ps) >2.0 175 2.0 170 1.5 167 1.0 163 0.9 162 0.8 161 0.7 159 0.6 155 0.5 150 <0.5 150 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Command and Address Setup, Hold, and Derating Figure 22: Nominal Slew Rate and tVAC for tIS (Command and Address - Clock) tIS tIH tIS tIH CK CK# DK# DK VDDQ tVAC VIH(AC)min VREF to AC region VIH(DC)min Nominal slew rate VREF(DC) Nominal slew rate VIL(DC)max VREF to AC region VIL(AC)max tVAC VSS 'TR 'TF Setup slew rate falling signal = Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN VREF(DC) - VIL(AC)max Setup slew rate = rising signal 'TF VIH(AC)min - VREF(DC) 'TR 1. Both the clock and the data strobe are drawn on different time scales. 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Command and Address Setup, Hold, and Derating Figure 23: Nominal Slew Rate for tIH (Command and Address - Clock) tIS tIS tIH tIH CK CK# DK# DK VDDQ VIH(AC)min VIH(DC)min Nominal slew rate DC to VREF region VREF(DC) DC to VREF region Nominal slew rate VIL(DC)max VIL(AC)max VSS 'TR Hold slew rate rising signal = Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN VREF(DC) - VIL(DC)max 'TF Hold slew rate falling signal = 'TR VIH(DC)min - VREF(DC) 'TF 1. Both the clock and the data strobe are drawn on different time scales. 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Command and Address Setup, Hold, and Derating Figure 24: Tangent Line for tIS (Command and Address - Clock) tIS tIS tIH tIH CK CK# DK# DK VDDQ tVAC Nominal line VIH(AC)min VREF to AC region VIH(DC)min Tangent line VREF(DC) Tangent line VIL(DC)max VREF to AC region VIL(AC)max Nominal line 'TR tVAC VSS 'TF Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Setup slew rate rising signal = Tangent line [V IH(DC)min - VREF(DC)] Setup slew rate falling signal = Tangent line[ V REF(DC) - VIL(AC)max] 'TR 'TF 1. Both the clock and the data strobe are drawn on different time scales. 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Command and Address Setup, Hold, and Derating Figure 25: Tangent Line for tIH (Command and Address - Clock) tIS tIH tIS tIH CK CK# DK# DK VDDQ VIH(AC)min Nominal line VIH(DC)min DC to VREF region Tangen t line VREF(DC) DC to VREF region Tangen t line Nominal line VIL(DC)max VIL(AC)max VSS 'TR Hold slew rate rising signal = Hold slew rate falling signal = Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 'TF Tangent line [V REF(DC) - VIL(DC)max] 'TR Tangent line [V IH(DC)min - VREF(DC)] 'TF 1. Both the clock and the data strobe are drawn on different time scales. 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Data Setup, Hold, and Derating Data Setup, Hold, and Derating The total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS (base) and tDH (base) values (see the table below; values come from Table 28 (page 44)) to the tDS and tDH derating values (see Table 35 (page 58)), respectively. Example: tDS (total setup time) = tDS (base) + tDS. For a valid transition, the input signal has to remain above/below V IH(AC)/VIL(AC) for some time tVAC (see Table 36 (page 58)). Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached V IH(AC)/VIL(AC)) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach V IH/ VIL(AC). For slew rates which fall between the values listed in Table 35 (page 58) and Table 36 (page 58), the derating values may obtained by linear interpolation. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V REF(DC) and the first crossing of V IL(AC)max. If the actual signal is always earlier than the nominal slew rate line between the shaded V REF(DC)-to-AC region, use the nominal slew rate for derating value (see Figure 26 (page 59)). If the actual signal is later than the nominal slew rate line anywhere between the shaded V REF(DC)-to-AC region, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value (see Figure 28 (page 61)). Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min and the first crossing of V REF(DC). If the actual signal is always later than the nominal slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derating value (see Figure 27 (page 60)). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual signal from the DC-to-VREF(DC) region is used for derating value (see Figure 29 (page 62)). Table 34: Data Setup and Hold Values at 1 V/ns (DKx, DKx# at 2V/ns) - AC/DC-Based Symbol RL3-2133 RL3-1866 RL3-1600 Units Reference tDS(base),AC150 -30 -15 10 ps VIH(AC)/VIL(AC) tDH(base),DC100 5 20 45 ps VIH(DC)/VIL(DC) PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Data Setup, Hold, and Derating Table 35: Derating Values for tDS/tDH - AC150/DC100-Based Empty cells indicate slew rate combinations not supported tDS, tDH Derating (ps) - AC/DC-Based DKx, DKx# Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns DQ Slew t t t t t t t t t t t t t t t Rate (V/ns) DS DH DS DH DS DH DS DH DS DH DS DH DS DH DS tDH 2.0 75 50 75 50 75 50 1.5 50 34 50 34 50 34 58 42 1.0 0 0 0 0 0 0 8 8 16 16 0 -4 0 -4 8 4 16 12 24 20 0 -10 8 -2 16 6 24 14 8 -8 0.9 0.8 0.7 0.6 0.5 32 24 16 0 24 8 32 18 40 34 15 -10 23 -2 31 8 39 24 14 -16 22 -6 30 10 7 -26 15 -10 0.4 Table 36: Minimum Required Time tVAC Above VIH(AC) (or Below VIL(AC)) for Valid Transition tVAC Slew Rate (V/ns) PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN (ps) >2.0 175 2.0 170 1.5 167 1.0 163 0.9 162 0.8 161 0.7 159 0.6 155 0.5 150 <0.5 150 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Data Setup, Hold, and Derating Figure 26: Nominal Slew Rate and tVAC for tDS (DQ - Strobe) CK CK# DK# DK tDS tDH tDS tDH VDDQ tVAC VIH(AC)min VREF to AC region VIH(DC)min Nominal slew rate VREF(DC) Nominal slew rate VIL(DC)max VREF to AC region VIL(AC)max tVAC VSS 'TF Setup slew rate = falling signal Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 'TR VREF(DC) - VIL(AC)max 'TF Setup slew rate = rising signal VIH(AC)min - VREF(DC) 'TR 1. Both the clock and the strobe are drawn on different time scales. 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Data Setup, Hold, and Derating Figure 27: Nominal Slew Rate for tDH (DQ - Strobe) CK CK# DK# DK tDS tDH tDS tDH VDDQ VIH(AC)min VIH(DC)min Nominal slew rate DC to VREF region VREF(DC) Nominal slew rate DC to VREF region VIL(DC)max VIL(AC)max VSS 'TR Hold slew rate = rising signal Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN VREF(DC) - VIL(DC)max 'TF Hold slew rate falling signal = 'TR VIH(DC)min - VREF(DC) 'TF 1. Both the clock and the strobe are drawn on different time scales. 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Data Setup, Hold, and Derating Figure 28: Tangent Line for tDS (DQ - Strobe) CK CK# DK# DK tDS tDH tDS tDH VDDQ Nominal line tVAC VIH(AC)min VREF to AC region VIH(DC)min Tangent line VREF(DC) Tangent line VIL(DC)max VREF to AC region VIL(AC)max Nominal line 'TR tVAC VSS 'TF Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Setup slew rate rising signal = Tangent line [V IH(AC)min - VREF(DC)] Setup slew rate falling signal = Tangent line [V REF(DC) - VIL(AC)max ] 'TR 'TF 1. Both the clock and the strobe are drawn on different time scales. 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Data Setup, Hold, and Derating Figure 29: Tangent Line for tDH (DQ - Strobe) CK CK# DK# DK tDS tDH tDS tDH VDDQ VIH(AC)min Nominal line VIH(DC)min DC to VREF region Tangent line VREF(DC) DC to VREF region Tangent line Nominal line VIL(DC)max VIL(AC)max VSS 'TR Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 'TF Hold slew rate rising signal = Tangent line [V REF(DC) - VIL(DC)max] Hold slew rate falling signal = Tangent line [V IH(DC)min - VREF(DC)] 'TR 'TF 1. Both the clock and the strobe are drawn on different time scales. 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Commands Commands The following table provides descriptions of the valid commands of the RLDRAM 3 device. All command and address inputs must meet setup and hold times with respect to the rising edge of CK. Table 37: Command Descriptions Command Description NOP The NOP command prevents new commands from being executed by the DRAM. Operations already in progress are not affected by NOP commands. Output values depend on command history. MRS Mode registers MR0, MR1, and MR2 are used to define various modes of programmable operations of the DRAM. A mode register is programmed via the MODE REGISTER SET (MRS) command during initialization and retains the stored information until it is reprogrammed, RESET# goes LOW, or until the device loses power. The MRS command can be issued only when all banks are idle, and no bursts are in progress. READ The READ command is used to initiate a burst read access to a bank. The BA[3:0] inputs select a bank, and the address provided on inputs A[19:0] select a specific location within a bank. WRITE The WRITE command is used to initiate a burst write access to a bank (or banks). MRS bits MR2[4:3] select single, dual, or quad bank WRITE protocol. The BA[x:0] inputs select the bank(s) (x = 3, 2, or 1 for single, dual, or quad bank WRITE, respectively). The address provided on inputs A[19:0] select a specific location within the bank. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If the DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored (that is, this part of the data word will not be written). AREF The AREF command is used during normal operation of the RLDRAM 3 to refresh the memory content of a bank. There are two methods by which the RLDRAM 3 can be refreshed, both of which are selected within the mode register. The first method, bank address-controlled AREF, is identical to the method used in RLDRAM2. The second method, multibank AREF, enables refreshing of up to four banks simultaneously. More info is available in the Auto Refresh section. For both methods, the command is nonpersistent, so it must be issued each time a refresh is required. Table 38: Command Table Note 1 applies to the entire table Operation Code CS# WE# REF# A[19:0] BA[3:0] Notes NOP NOP H H H X X MRS MRS L L L OPCODE OPCODE READ READ L H H A BA 2 WRITE WRITE L L H A BA 2 AREF L H L A BA 3 AUTO REFRESH Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 1. X = "Don't Care;" H = logic HIGH; L = logic LOW; A = valid address; BA = valid bank address; OPCODE = mode register bits 2. Address width varies with burst length and configuration; see the Address Widths of Different Burst Lengths table for more information. 3. Bank address signals (BA) are used only during bank address-controlled AREF; Address signals (A) are used only during multibank AREF. 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 MODE REGISTER SET (MRS) Command MODE REGISTER SET (MRS) Command The mode registers, MR0, MR1, and MR2, store the data for controlling the operating modes of the memory. The MODE REGISTER SET (MRS) command programs the RLDRAM 3 operating modes and I/O options. During an MRS command, the address inputs are sampled and stored in the mode registers. The BA[1:0] signals select between mode registers 0-2 (MR0-MR2). After the MRS command is issued, each mode register retains the stored information until it is reprogrammed, until RESET# goes LOW, or until the device loses power. After issuing a valid MRS command, tMRSC must be met before any command can be issued to the RLDRAM 3. The MRS command can be issued only when all banks are idle, and no bursts are in progress. Figure 30: MRS Command Protocol CK# CK CS# WE# REF# Address OPCODE Bank Address OPCODE Don't Care PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Mode Register 0 (MR0) Mode Register 0 (MR0) Figure 31: MR0 Definition for Non-Multiplexed Address Mode BA3 BA2 BA1 BA0 A17 ... A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 21 20 19 18 01 01 MRS 9 8 7 6 5 4 AM DLL Data Latency 17-10 Reserved 3 2 1 0 Address Bus Mode Register (Mx) tRC_MRS M7 M6 M5 M4 Data Latency (RL & WL) M19 M18 0 0 0 1 Mode Register Definition 0 Mode Register 2 (MR2) 1 Reserved Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 0 0 RL = 3 ; WL = 4 0 0 1 RL = 4 ; WL = 5 Enable 0 0 1 0 RL = 5 ; WL = 6 0 0 0 0 Disable 0 0 1 1 RL = 6 ; WL = 7 0 0 0 1 32 0 1 0 0 RL = 7 ; WL = 8 0 0 1 0 42 0 1 0 1 RL = 8 ; WL = 9 0 0 1 1 5 0 1 1 0 RL = 9 ; WL = 10 0 1 0 0 6 0 1 1 0 1 0 1 0 RL = 10 ; WL = 11 RL = 11 ; WL = 12 0 1 0 1 7 0 1 1 0 8 1 0 0 1 RL = 12 ; WL = 13 1 0 1 0 RL = 13 ; WL = 14 0 1 1 0 1 0 1 0 10 1 0 1 1 RL = 14 ; WL = 15 1 0 0 1 1 1 0 0 RL = 15 ; WL = 16 1 0 1 0 11 12 1 1 0 1 RL = 16 ; WL = 17 1 0 1 1 Reserved 1 1 1 0 Reserved 1 1 0 0 Reserved 1 1 1 1 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved 0 1 Mode Register 1 (MR1) 1 0 0 DLL Enable Mode Register 0 (MR0) 1 0 M8 M9 Address MUX 0 Non-multiplexed 1 Multiplexed M3 M2 M1 M0 t RC_MRS 22,3 9 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during the MRS command. 2. BL8 not allowed. 3. BL4 not allowed. 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Mode Register 0 (MR0) tRC Bits MR0[3:0] select the number of clock cycles required to satisfy the tRC specifications. After a READ, WRITE, or AREF command is issued to a bank, a subsequent READ, WRITE, or AREF cannot be issued to the same bank until tRC has been satisfied. The correct value (tRC_MRS) to program into MR0[3:0] is shown in the table below. Table 39: tRC_MRS MR0[3:0] values Parameter -093E -093 -107E -107 -125F -125E -125 RL = 3; WL = 4 2 2 Reserved Reserved Reserved Reserved Reserved RL = 4; WL = 5 2 3 2 3 Reserved 3 3 RL = 5; WL = 6 3 4 3 3 Reserved 3 3 RL = 6; WL = 7 4 4 3 4 Reserved 4 4 RL = 7; WL = 8 4 4 4 4 Reserved 4 4 RL = 8; WL = 9 5 6 4 5 Reserved 5 5 RL = 9; WL = 10 5 6 5 6 Reserved 6 6 RL = 10; WL = 11 6 7 5 6 Reserved 6 6 RL = 11; WL = 12 6 7 6 7 Reserved 7 7 RL = 12; WL = 13 7 8 6 7 6 7 7 RL = 13; WL = 14 7 8 7 8 7 8 8 RL = 14; WL = 15 8 10 7 8 Reserved Reserved 9 RL = 15; WL = 16 8 10 8 10 Reserved Reserved 10 RL = 16; WL = 17 9 11 Reserved Reserved Reserved Reserved 10 Data Latency The data latency register uses MR0[7:4] to set both the READ and WRITE latency (RL and WL). The valid operating frequencies for each data latency register setting can be found in Table 28 (page 44). DLL Enable/Disable Through the programming of MR0[8], the DLL can be enabled or disabled. The DLL must be enabled for normal operation. The DLL must be enabled during the initialization routine and upon returning to normal operation after having been disabled for the purpose of debugging or evaluation. To operate the RLDRAM with the DLL disabled, the tRC MRS setting must equal the read latency (RL) setting. Enabling the DLL should always be followed by resetting the DLL using the appropriate MR1 command. Address Multiplexing Although the RLDRAM has the ability to operate similar to an SRAM interface by accepting the entire address in one clock (non-multiplexed, or broadside addressing), MR0[9] can be set to 1 so that it functions with multiplexed addressing, similar to a traditional DRAM. In multiplexed address mode, the address is provided to the RLDRAM in two parts that are latched into the memory with two consecutive rising edges of CK. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Mode Register 0 (MR0) When in multiplexed address mode, only 11 address balls are required to control the RLDRAM, as opposed to 20 address balls when in non-multiplexed address mode. The data bus efficiency in continuous burst mode is only affected when using the BL = 2 setting because the device requires two clocks to read and write data. During multiplexed mode, the bank addresses as well as WRITE and READ commands are issued during the first address part, Ax. The Address Mapping in Multiplexed Address Mode table shows the addresses needed for both the first and second rising clock edges (Ax and Ay, respectively). After MR0[9] is set HIGH, READ, WRITE, and MRS commands follow the format described in the Command Description in Multiplexed Address Mode figure. Refer to Multiplexed Address Mode for further information on operation with multiplexed addressing. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Mode Register 1 (MR1) Mode Register 1 (MR1) Figure 32: MR1 Definition for Non-Multiplexed Address Mode BA3 BA2 BA1 BA0 A17 ... A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 21 20 19 18 17-11 01 MRS Reserved 01 M19 M18 Mode Register Definition 10 9 8 7 6 5 BL Ref ZQe ZQ DLL 4 3 ODT M5 DLL Reset M10 M9 Burst Length 2 1 0 Mode Register (Mx) Drive M4 M3 M2 ODT M1 M0 Output Drive 0 0 Mode Register 0 (MR0) 0 0 2 0 No 0 0 0 Off 0 0 RZQ/6 (40: 0 1 Mode Register 1 (MR1) 0 1 1 Yes 0 0 1 RZQ/6 (40: 0 1 RZQ/4 (60: 1 0 Mode Register 2 (MR2) 1 0 0 1 0 RZQ/4 (60: 1 0 Reserved 1 1 Reserved 1 Reserved RZQ/2 (120: 1 1 Reserved 1 M6 ZQ Calibration Selection 0 1 1 0 Short ZQ Calibration 1 0 0 Reserved 1 Long ZQ Calibration 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 AREF P rotocol M7 0 Bank Address Control 0 Disabled - Default 1 Multibank 1 Enable ZQ Calibration Enable 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during the MRS command. 2. BL8 not available in x36. Notes: Output Drive Impedance The RLDRAM 3 uses programmable impedance output buffers, which enable the user to match the driver impedance to the system. MR1[0] and MR1[1] are used to select 40 or 60 output impedance, but the device powers up with an output impedance of 40. The drivers have symmetrical output impedance. To calibrate the impedance a 240 1% external precision resistor (RZQ) is connected between the ZQ ball and V SSQ. The output impedance is calibrated during initialization through the ZQCL mode register setting. Subsequent periodic calibrations (ZQCS) may be performed to compensate for shifts in output impedance due to changes in temperature and voltage. More detailed information on calibration can be found in the ZQ Calibration section. DQ On-Die Termination (ODT) MR1[4:2] are used to select the value of the on-die termination (ODT) for the DQ, DKx and DM balls. When enabled, ODT terminates these balls to V DDQ/2. The RLDRAM 3 device supports 40, or 120 ODT. The ODT function is dynamically switched off when a DQ begins to drive after a READ command has been issued. Similarly, ODT is designed to switch on at the DQs after the RLDRAM has issued the last piece of data. The DM and DKx balls are always terminated after ODT is enabled. DLL Reset Programming MR1[5] to 1 activates the DLL RESET function. MR1[5] is self-clearing, meaning it returns to a value of 0 after the DLL RESET function has been initiated. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Mode Register 1 (MR1) Whenever the DLL RESET function is initiated, CK/CK# must be held stable for 512 clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may cause output timing specifications, such as tCKQK, to be invalid . ZQ Calibration The ZQ CALIBRATION mode register command is used to calibrate the DRAM output drivers (RON) and ODT values (RTT) over process, voltage, and temperature, provided a dedicated 240 (1%) external resistor is connected from the DRAM's RZQ ball to V SSQ. Bit MR1[6] selects between ZQ calibration long (ZQCL) and ZQ calibration short (ZQCS), each of which are described in detail below. When bit MR1[7] is set HIGH, it enables the calibration sequence. Upon completion of the ZQ calibration sequence, MR1[7] automatically resets LOW. The RLDRAM 3 needs a longer time to calibrate RON and ODT at power-up initialization and a relatively shorter time to perform periodic calibrations. An example of ZQ calibration timing is shown below. All banks must have tRC met before ZQCL or ZQCS mode register settings can be issued to the DRAM. No other activities (other than loading another ZQCL or ZQCS mode register setting may be issued to another DRAM) can be performed on the DRAM channel by the controller for the duration of tZQinit or tZQoper. The quiet time on the DRAM channel helps accurately calibrate RON and ODT. After DRAM calibration is achieved, the DRAM will disable the ZQ ball's current consumption path to reduce power. ZQ CALIBRATION mode register settings can be loaded in parallel to DLL reset and locking time. In systems that share the ZQ resistor between devices, the controller must not allow overlap of tZQinit, tZQoper, or tZQcs between devices. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Mode Register 1 (MR1) Figure 33: ZQ Calibration Timing (ZQCL and ZQCS) T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 Command MRS NOP NOP NOP Valid Valid MRS NOP NOP NOP Valid Address ZQCL Valid Valid ZQCS CK# CK DQ Valid Activities Activities Activities Activities QK# QK QVLD tZQinit or tZQoper tZQCS Indicates a break in time scale Don't Care or Unknown 1. All devices connected to the DQ bus should be held High-Z during calibration. 2. The state of QK and QK# are unknown during ZQ calibration. 3. tMRSC after loading the MR1 settings, QVLD output drive strength will be at the value selected or higher (lower resistance) until ZQ calibration is complete. Notes: ZQ Calibration Long The ZQ calibration long (ZQCL) mode register setting is used to perform the initial calibration during a power-up initialization and reset sequence. It may be loaded at any time by the controller depending on the system environment. ZQCL triggers the calibration engine inside the DRAM. After calibration is achieved, the calibrated values are transferred from the calibration engine to the DRAM I/O, which are reflected as updated RON and ODT values. The DRAM is allowed a timing window defined by either tZQinit or tZQoper to perform the full calibration and transfer of values. When ZQCL is issued during the initialization sequence, the timing parameter tZQinit must be satisfied. When initialization is complete, subsequent loading of the ZQCL mode register setting requires the timing parameter tZQoper to be satisfied. ZQ Calibration Short The ZQ calibration short (ZQCS) mode register setting is used to perform periodic calibrations to account for small voltage and temperature variations. The shorter timing window is provided to perform the reduced calibration and transfer of values as defined by timing parameter tZQCS. ZQCS can effectively correct a minimum of 0.5% RON and RTT impedance error within 64 clock cycles, assuming the maximum sensitivities specified in the ODT Temperature and Voltage Sensitivity and the Output Driver Voltage and Temperature Sensitivity tables. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Mode Register 1 (MR1) AUTO REFRESH Protocol The AUTO REFRESH (AREF) protocol is selected with bit MR1[8]. There are two ways in which AREF commands can be issued to the RLDRAM. Depending upon how bit MR1[8] is programmed, the memory controller can issue either bank address-controlled or multibank AREF commands. Bank address-controlled AREF uses the BA[3:0] inputs to refresh a single bank per command. Multibank AREF is enabled by setting bit MR1[8] HIGH during an MRS command. This refresh protocol enables the simultaneous refreshing of a row in up to four banks. In this method, the address pins A[15:0] represent banks 0-15, respectively. More information on both AREF protocols can be found in AUTO REFRESH Command (page 78). Burst Length (BL) Burst length is defined by MR1[9] and MR1[10]. Read and write accesses to the RLDRAM are burst-oriented, with the burst length being programmable to 2, 4, or 8. Figure 34 (page 72) shows the different burst lengths with respect to a READ command. Changes in the burst length affect the width of the address bus (see the following table for details). The data written by the prior burst length is not guaranteed to be accurate when the burst length of the device is changed. Table 40: Address Widths of Different Burst Lengths Configuration PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Burst Length x18 x36 2 A[19:0] A[18:0] 4 A[18:0] A[17:0] 8 A[17:0] NA 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Mode Register 1 (MR1) Figure 34: Read Burst Lengths CK# T0 T1 T2 T3 T4 T4n READ NOP NOP NOP NOP T5 T5n T6 T6n T7 T7n CK Command Address NOP NOP NOP NOP Bank a, Col n RL = 4 QK# BL = 2 QK QVLD DO an DQ QK# BL = 4 QK QVLD DO an DQ QK# BL = 8 QK QVLD DO an DQ Transitioning Data Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Don't Care 1. DO an = data-out from bank a and address an. 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Mode Register 2 (MR2) Mode Register 2 (MR2) Figure 35: MR2 Definition for Non-Multiplexed Address Mode BA3 BA2 BA1 BA0 A17 ... A4 A3 A2 A1 A0 Address Bus 21 20 19 18 4 3 2 17-5 01 01 MRS Reserved WRITE En M19 M18 Mode Register (Mx) Mode Register Definition 0 0 Mode Register 0 (MR0) 0 1 Mode Register 1 (MR1) 1 0 Mode Register 2 (MR2) 1 1 0 RTR 1 M1 M0 Reserved M4 M3 Note: WRITE Protocol READ Training Register 0 0 0-1-0-1 on all DQs 0 1 Even DQs: 0-1-0-1 ; Odd DQs: 1-0-1-0 1 0 Reserved 1 1 Reserved 0 0 Single Bank 0 1 Dual Bank 1 0 Quad Bank 0 Normal RLDRAM Operation 1 1 Reserved 1 READ Training Enabled M2 READ Training Register Enable 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during the MRS command. READ Training Register (RTR) The READ training register (RTR) is controlled through MR2[2:0]. It is used to output a predefined bit sequence on the output balls to aid in system timing calibration. MR2[2] is the master bit that enables or disables access to the READ training register, and MR2[1:0] determine which predefined pattern for system calibration is selected. If MR2[2] is set to 0, the RTR is disabled, and the DRAM operates in normal mode. When MR2[2] is set to 1, the DRAM no longer outputs normal read data, but a predefined pattern that is defined by MR2[1:0]. Prior to enabling the RTR, all banks must be in the idle state (tRC met). When the RTR is enabled, all subsequent READ commands will output four bits of a predefined sequence from the RTR on all DQs. The READ latency during RTR is defined with the Data Latency bits in MR0. To loop on the predefined pattern when the RTR is enabled, successive READ commands must be issued and satisfy tRTRS. Address balls A[19:0] are considered "Don't Care" during RTR READ commands. Bank address bits BA[3:0] must access Bank 0 with each RTR READ command. tRC does not need to be met in between RTR READ commands to Bank 0. When the RTR is enabled, only READ commands are allowed. When the last RTR READ burst has completed and tRTRE has been satisfied, an MRS command can be issued to exit the RTR. Standard RLDRAM 3 operation may then start after tMRSC has been met. The RESET function is supported when the RTR is enabled. If MR2[1:0] is set to 00 a 0-1-0-1 pattern will be output on all DQs with each RTR READ command. If MR2[1:0] is set to 01, a 0-1-0-1 pattern will output on all even DQs and the opposite pattern, a 1-0-1-0, will output on all odd DQs with each RTR READ command. Note: Enabling RTR may corrupt previously written data. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN MR2[21:18] Bank DQ QVLD DK DK# QK QK# DM MR2[17:0] MRS T0 Address Command CK CK# RL NOP T4 READ T5 NOP T6 READ T7 NOP T8 READ NOP T9 (( )) (( )) NOP ( T10 ( )) (( )) tRTRS tRTRS tRTRS tRTRS Transitioning Data BANK 0 (( )) (( )) (( )) (( )) (( )) (( )) tMRSC Note: 1. RL = READ latency defined with data latency MR0 setting. Don't Care (( ) ) Indicates a break (( ) ) in time scale (( )) (( )) tMRSC (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) tRTRE MR2[21:18] MR2[17:0] MRS T12 (( )) (( )) NOP T11 (( )) (( )) (( )) (( )) BANK 0 (( )) (( )) BANK 0 (( )) (( )) BANK 0 (( )) (( )) (( )) (( )) BANK 0 (( )) (( )) READ T3 (( )) (( )) NOP T2 (( )) (( )) READ T1 (( )) (( )) (( )) (( )) (( )) (( )) Figure 36: READ Training Function - Back-to-Back Readout VALID T13 576Mb: x18, x36 RLDRAM 3 Mode Register 2 (MR2) 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 WRITE Command WRITE Protocol Single or multibank WRITE operation is programmed with bits MR2[4:3]. The purpose of multibank WRITE operation is to reduce the effective tRC during READ commands. When dual- or quad-bank WRITE protocol is selected, identical data is written to two or four banks, respectively. With the same data stored in multiple banks on the RLDRAM, the memory controller can select the appropriate bank to READ the data from and minimize tRC delay. Detailed information on the multibank WRITE protocol can be found in Multibank WRITE (page 76). WRITE Command Write accesses are initiated with a WRITE command. The address needs to be provided concurrent with the WRITE command. During WRITE commands, data will be registered at both edges of DK, according to the programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) determined by the data latency bits within MR0. The first valid data is registered at the first rising DK edge WL cycles after the WRITE command. Any WRITE burst may be followed by a subsequent READ command (assuming tRC is met). Depending on the amount of input timing skew, an additional NOP command might be necessary between WRITE and READ commands to avoid external data bus contention (see Figure 44 (page 84)). Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and tDH. The input data is masked if the corresponding DM signal is HIGH. Figure 37: WRITE Command CK# CK CS# WE# REF# Address A Bank Address BA Don't Care PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 READ Command Multibank WRITE All the information provided above in the WRITE section is applicable to a multibank WRITE operation as well. Either two or four banks can be simultaneously written to when the appropriate MR2[4:3] mode register bits are selected. If a dual-bank WRITE has been selected through the mode register, both banks x and x +8 will be written to simultaneously with identical data provided during the WRITE command. For example, when a dual-bank WRITE has been loaded and the bank address for Bank 1 has been provided during the WRITE command, Bank 9 will also be written to at the same time. When a dual-bank WRITE command is issued, only bank address bits BA[2:0] are valid and BA3 is considered a "Don't Care." The same methodology is used if the quad-bank WRITE has been selected through the mode register. Under these conditions, when a WRITE command is issued to Bank x, the data provided on the DQs will be issued to banks x, x+4, x+8, and x+12. When a quad-bank WRITE command is issued, only bank address bits BA[1:0] are valid and BA[3:2] are considered "Don't Care." The timing parameter tSAW must be adhered to when operating with multibank WRITE commands. This parameter limits the number of active banks at 16 within an 8ns window. The tMMD specification must also be followed if the quad-bank WRITE is being used. This specification requires two clock cycles between any bank command (READ, WRITE, or AREF) to a quad-bank WRITE or a quad-bank WRITE to any bank command. The data bus efficiency is not compromised if BL4 or BL8 is being utilized. READ Command Read accesses are initiated with a READ command (see the figure below). Addresses are provided with the READ command. During READ bursts, the memory device drives the read data so it is edge-aligned with the QK signals. After a programmable READ latency, data is available at the outputs. One half clock cycle prior to valid data on the read bus, the data valid signal(s), QVLD, transitions from LOW to HIGH. QVLD is also edge-aligned with the QK signals. The skew between QK and the crossing point of CK is specified as tCKQK. tQKQx is the skew between a QK pair and the last valid data edge generated at the DQ signals in the associated byte group, such as DQ[7:0] and QK0. tQKQx is derived at each QK clock edge and is not cumulative over time. For the x36 device, the tQKQ02 and tQKQ13 specifications define the relationship between the DQs and QK signals within specific data word groupings. tQKQ02 defines the skew between QK0 and DQ[26:18] and between QK2 and DQ[8:0]. tQKQ13 defines the skew between QK1 and DQ[35:17] and between QK3 and DQ[17:9]. After completion of a burst, assuming no other commands have been initiated, output data (DQ) will go High-Z. The QVLD signal transitions LOW on the last bit of the READ burst. The QK clocks are free-running and will continue to cycle after the read burst is complete. Back-to-back READ commands are possible, producing a continuous flow of output data. Any READ burst may be followed by a subsequent WRITE command. Some systems having long line lengths or severe skews may need an additional idle cycle inserted between READ and WRITE commands to prevent data bus contention. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 READ Command Figure 38: READ Command CK# CK CS# WE# REF# Address A Bank Address BA Don't Care PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AUTO REFRESH Command AUTO REFRESH Command The RLDRAM 3 device uses two unique AUTO REFRESH (AREF) command protocols, bank address-controlled AREF and multibank AREF. The desired protocol is selected by setting MR1[8] LOW (for bank address-controlled AREF) or HIGH (for multibank AREF) during an MRS command. Bank address-controlled AREF is identical to the method used in RLDRAM2 devices, whereby banks are refreshed independently. The value on bank addresses BA[3:0], issued concurrently with the AREF command, define which bank is to be refreshed. The array address is generated by an internal refresh counter, effectively making each address bit a "Don't Care" during the AREF command. The delay between the AREF command and a subsequent command to the same bank must be at least tRC. Figure 39: Bank Address-Controlled AUTO REFRESH Command CK# CK CS# WE# REF# Address Bank Address BA[3:0] Don't Care The multibank AREF protocol, enabled by setting bit MR1[8] HIGH during an MRS command, enables the simultaneous refresh of a row in up to four banks. In this method, address balls A[15:0] represent banks [15:0], respectively. The row addresses are generated by an internal refresh counter for each bank; therefore, the purpose of the address balls during an AREF command is only to identify the banks to be refreshed. The bank address balls BA[3:0] are considered "Don't Care" during a multibank AREF command. A multibank AUTO REFRESH is performed for a given bank when its corresponding address ball is asserted HIGH during an AREF command. Any combination of up to four address balls can be asserted HIGH during the rising clock edge of an AREF command to simultaneously refresh a row in each corresponding bank. The delay between an AREF command and subsequent commands to the banks refreshed must be at least tRC. Adherence to tSAW must be followed when simultaneously refreshing multiple banks. If refreshing three or four banks with the multibank AREF command, tMMD must be followed. This specification requires two clock cycles between any bank command (READ, WRITE, AREF) to the multibank AREF or the multibank AREF to any bank PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 78 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AUTO REFRESH Command command. Note that refreshing one or two banks with the multibank AREF command is not subject to the tMMD specification. The entire device must be refreshed every 64ms (tREF). The RLDRAM device requires 128K cycles at an average periodic interval of 0.489s MAX (64ms/[8K rows x 16 banks]). Figure 40: Multibank AUTO REFRESH Command CK# CK CS# WE# REF# Address A[15:0] Bank Address Don't Care PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 79 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 INITIALIZATION Operation INITIALIZATION Operation The RLDRAM 3 device must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operations or permanent damage to the device. The following sequence is used for power-up: 1. Apply power (VEXT, V DD, V DDQ). Apply V DD and V EXT before, or at the same time as, VDDQ. V DD must not exceed V EXT during power supply ramp. V EXT, V DD, V DDQ must all ramp to their respective minimum DC levels within 200ms. 2. Ensure that RESET# is below 0.2 x V DDQ during power ramp to ensure the outputs remain disabled (High-Z) and ODT is off (RTT is also High-Z). DQs, and QK signals will remain High-Z until MR0 command. All other inputs may be undefined during the power ramp. 3. After the power is stable, RESET# must be LOW for at least 200s to begin the initialization process. 4. After 100 or more stable input clock cycles with NOP commands, bring RESET# HIGH. 5. After RESET# goes HIGH, a stable clock must be applied in conjunction with NOP commands and all Address pins (A[19:0] & BA[3:0]) to be held low for 10,000 cycles. 6. Load desired settings into MR0. 7. tMRSC after loading the MR0 settings, load operating parameters in MR1, including DLL Reset and Long ZQ Calibration. 8. After the DLL is reset and Long ZQ Calibration is enabled, the input clock must be stable for 512 clock cycles while NOPs are issued. 9. Load desired settings into MR2. If using the RTR, follow the procedure outlined in the READ Training Function - Back-to-Back Readout figure prior to entering normal operation. 10. The RLDRAM 3 is ready for normal operation. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 80 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 INITIALIZATION Operation Figure 41: Power-Up/Initialization Sequence T (MAX) = 200ms VDD See power-up conditions in the initialization sequence text VDDQ VEXT VREF Power-up ramp Stable and valid clock tCK CK# CK tCH 100 cycles tIOZ tCL = 20ns RESET# tDK DK# DK tDKH Command NOP NOP NOP tDKL MRS MRS MR0 MR1 MRS Valid DM Address MR2 Valid QK# QK QVLD1 DQ RTT T = 200s (MIN) 10,000 CK cycles (MIN) All voltage supplies valid and stable Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN tMRSC 512 clock cycles for DLL Reset & ZQ Calibration READ Training register specs apply Indicates a break in time scale Normal operation Don't Care or Unknown 1. QVLD output drive status during power-up and initialization: a. QVLD remains High-Z until 20ns after power supplies are stable and TCK or CK have cycled 4 times. b. QVLD will then drive LOW with 40 or lower until the output drive value selected in MR1 is enabled. 81 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 INITIALIZATION Operation c. tMRSC after loading the MR1 settings, QVLD output drive strength will be at the value selected or lower until ZQ calibration is complete. d. QVLD will meet the output drive strength specifications upon completion of the ZQ calibration timing. 2. After MR2 has been issued, Rtt is either High-Z or enabled to the ODT value selected in MR1. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 WRITE Operation WRITE Operation Figure 42: WRITE Burst T0 T1 T2 T3 T4 T5 T5n Command WRITE NOP NOP NOP NOP NOP Address Bank a, Add n T6 T6n T7 CK# CK t CKDKnom NOP NOP WL = 5 DK# DK DI an DQ DM t CKDKmin WL - tCKDK DK# DK DI an DQ DM t CKDKmax WL + tCKDK DK# DK DI an DQ DM Transitioning Data Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Don't Care 1. DI an = data-in for bank a and address n. 83 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 WRITE Operation Figure 43: Consecutive WRITE Bursts T0 T1 T2 T3 WRITE NOP WRITE NOP T4 T5 T5n T6 T6n T7 T7n T8 T8n T9 CK# CK Command Address Bank a, Add n Bank b, Add n WRITE NOP NOP NOP NOP NOP Bank a, Add n DK# DK tRC WL WL DI an DQ DI bn DI an DM Transitioning Data Indicates a break in time scale Note: Don't Care 1. DI an (or bn or cn) = data-in for bank a (or b or c) and address n. Figure 44: WRITE-to-READ T0 T1 T2 T3 T4 T5 Command WRITE NOP READ NOP NOP NOP Address Bank a, Add n T5n T6 T6n T7 CK# CK NOP NOP Bank b, Add n WL = 5 RL = 4 QK# QK DK# DK QVLD DI an DQ DO bn DM Don't Care Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Transitioning Data 1. DI an = data-in for bank a and address n. 2. DO bn = data-out from bank b and address n. 84 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 WRITE Operation Figure 45: WRITE - DM Operation T0 T1 T2 T3 T4 NOP NOP T5 T6 T6n T7 T7n T8 CK# CK tCK Command NOP Address WRITE tCH NOP tCL NOP NOP NOP NOP Bank a, Add n DK# DK tDKL WL = 5 tDKH DI an DQ DM tDS tDH Transitioning Data Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Don't Care 1. DI an = data-in for bank a and address n. 85 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 WRITE Operation Figure 46: Consecutive Quad Bank WRITE Bursts T0 T1 T2 Quad-Bank WRITE NOP Quad-Bank WRITE T3 T4 T5 NOP NOP NOP T6 T5n T6n T7 T7n CK# CK Command Bank a, Add n Address NOP NOP Bank b, Add n tMMD = 2 WL = 5 DK# DK DI an DQ DI bn DM Transitioning Data Notes: Don't Care 1. DI an = data-in for bank a, a+4, a+8, and a+12 and address n. 2. DI bn = data-in for bank b, b+4, b+8, and b+12 and address n. Figure 47: Interleaved READ and Quad Bank WRITE Bursts T0 T1 T2 READ NOP Quad-Bank WRITE T3 T4 T5 T5n NOP READ NOP T6 T6n T7 T8 NOP NOP T8n T9 T9n CK# CK Command Address Bank a, Add n Bank b, Add n tMMD = 2 Bank c, Add n tMMD = 2 Quad-Bank WRITE NOP Bank d, Add n tMMD = 2 RL = 5 WL = 6 QK# QK DK# DK QVLD DO an DQ DI bn DM Transitioning Data Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Don't Care 1. DO an = data-out for bank a and address n. 2. DI bn = data-in for bank b, b+4, b+8, and b+12 and address n. 86 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 READ Operation READ Operation Figure 48: Basic READ Burst T1 T0 T2 T3 T4 T5 NOP NOP T5n T6 T6n T7 CK# CK tCK Command READ NOP Address tCH tCL NOP READ Bank a Add n NOP NOP Bank a Add n RL = 4 tRC =4 DM tCKQKmin tCKQKmin QK# QK tQK tQKH tQKVLD tQKL tQKVLD QVLD DO an DQ tCKQKmax tCKQKmax QK QK# tQK tQKH tQKL QVLD DO an DQ Transitioning Data Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Don't Care 1. DO an = data-out from bank a and address an. 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 READ Operation Figure 49: Consecutive READ Bursts (BL = 2) T5n T6n T0 T1 T2 T3 T4 Command READ READ READ READ READ READ READ Address Bank a Add n Bank b Add n Bank c Add n Bank d Add n Bank e Add n Bank f Add n Bank g Add n CK# T4n T5 T6 CK RL = 4 QVLD QK# QK DO an DQ DO bn DO cn Transitioning Data Note: Don't Care 1. DO an (or bn, cn) = data-out from bank a (or bank b, c) and address n. Figure 50: Consecutive READ Bursts (BL = 4) T0 T1 T2 T3 T4 Command READ NOP READ NOP READ Address Bank a Add n CK# T4n T5 T5n T6n T6 CK Bank b Add n NOP Bank c Add n READ Bank d Add n RL = 4 QVLD QK# QK DO an DQ Transitioning Data Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN DO bn Don't Care 1. DO an (or bn) = data-out from bank a (or bank b) and address n. 88 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 READ Operation Figure 51: READ-to-WRITE (BL = 2) T0 T1 Command READ WRITE Address Bank a, Add n Bank b, Add n T2 T3 T4 T5 T6 T7 T8 NOP NOP NOP NOP NOP NOP NOP CK# CK NOP DM QK# QK DK# DK RL = 4 WL = 5 QVLD DO an DQ DI bn Transitioning Data Notes: Don't Care 1. DO an = data-out from bank a and address n. 2. DI bn = data-in for bank b and address n. Figure 52: Read Data Valid Window CK# T0 T1 T2 READ NOP NOP T3 T4 T5 T6 T7 T8 T9 T10 NOP NOP NOP NOP NOP NOP NOP NOP CK Command RL = 5 Address Bank, Addr n QVLD tQKQx,max tQKQx,max tHZmax tLZmin QKx, QKx# tQH DQ (last data valid)2 DO n DO n DQ (first data no longer valid)2 All DQ collectively2 tQH DO DO DO DO DO DO DO n+1 n+2 n+3 n+4 n+5 n+6 n+7 DO DO DO DO DO DO DO n+3 n+1 n+2 n+4 n+5 n+6 n+7 DO n Data valid DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 Data valid Transitioning Data Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Don't Care 1. 2. 3. 4. DO n = data-out from bank a and address n. Represents DQs associated with a specific QK, QK# pair. Output timings are referenced to VDDQ/2 and DLL on and locked. tQKQx defines the skew between the QK0, QK0# pair to its respective DQs. tQKQx does not define the skew between QK and CK. 5. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst. 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AUTO REFRESH Operation AUTO REFRESH Operation Figure 53: Bank Address-Controlled AUTO REFRESH Cycle T0 CK# CK T1 (( )) tCK AREFx Command AREFy BAx T3 tCH tCL ACx ACy (( )) (( )) Address Bank (( )) T2 BAy (( )) (( )) DK, DK# DQ (( )) DM tRC Indicates a break in time scale Notes: Don't' Care 1. AREFx (or AREFy)= AUTO REFRESH command to bank x (or bank y). 2. ACx = any command to bank x; ACy = any command to bank y. 3. BAx = bank address to bank x; BAy = bank address to bank y. Figure 54: Multibank AUTO REFRESH Cycle T0 T1 T2 T3 T4 T5 T6 T7 CK# CK Command Address AREF AREF AREF AC Bank 0,4,8,12 Bank 1,5,9,13 Bank 2, 3 Bank 0 tMMD tMMD Bank DK, DK# DQ DM tRC Indicates a break in time scale PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Don't Care 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AUTO REFRESH Operation Figure 55: READ Burst with ODT CK# T0 T1 T2 T3 T4 T4n READ NOP NOP NOP NOP T5 T5n T6 T6n T7 T7n CK Command Address NOP NOP NOP NOP Bank a, Col n RL = 4 QK# %/ QK QVLD DO an DQ ODT ODT on ODT on ODT off QK# %/ QK QVLD DO an DQ ODT ODT on ODT off ODT on QK# %/ QK QVLD DO an DQ ODT off ODT on ODT Transitioning Data Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN on Don't Care 1. DO an = data out from bank a and address n. 91 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 AUTO REFRESH Operation Figure 56: READ-NOP-READ with ODT CK# T0 T1 T2 T3 T4 T4n READ NOP READ NOP NOP T5 T6 T6n NOP NOP T7 CK Command Address Bank a, Col n NOP NOP Bank b, Col n RL = 4 QK# QK QVLD DO an DQ ODT on ODT ODT off DO bn ODT on ODT off Transitioning Data Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN ODT on Don't Care 1. DO an (or bn) = data-out from bank a (or bank b) and address n. 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Multiplexed Address Mode Multiplexed Address Mode Figure 57: Command Description in Multiplexed Address Mode READ WRITE MRS AREF CK# CK CS# WE# REF# Address Ax Bank Address BA Ay Ax Ay Ax BA BA Ay Ax1 Ay1 BA2 Don't Care Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 1. Addresses valid only during a multibank AUTO REFRESH command. 2. Bank addresses valid only during a bank address-controlled AUTO REFRESH command. 3. The minimum setup and hold times of the two address parts are defined as tIS and tIH. 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Multiplexed Address Mode Figure 58: Power-Up/Initialization Sequence in Multiplexed Address Mode T (MAX) = 200ms VDD VDDQ VEXT See power-up conditions in the initialization sequence text VREF Power-up ramp Stable and valid clock tCK CK# CK tCL tCH 100 cycles tIOZ = 20ns RESET# tDK DK# DK tDKH Command NOP NOP NOP tDKL MRS MRS NOP MRS NOP MRS MR01 MR02 (Ax) MR0 (Ay) MR1 (Ax) MR1 (Ay) MR2 (Ax) NOP Va DM Address MR2 (Ay) V QK# QK QVLD5 DQ RTT High-Z T = 200s (MIN) 10,000 CK cycles (MIN) tMRSC All voltage supplies valid and stable 512 clock cycles for DLL Reset & ZQ Calibration Indicates a break in time scale Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN tMRSC READ Training register specs apply Don't Care or Unknown 1. Set address bit MR0[9] HIGH. This enables the device to enter multiplexed address mode when in non-multiplexed mode operation. Multiplexed address mode can also be entered at a later time by issuing an MRS command with MR0[9] HIGH. After address bit MR0[9] is set HIGH, tMRSC must be satisfied before the two-cycle multiplexed mode MRS command is issued. 2. Address MR0[9] must be set HIGH. This and the following step set the desired MR0 setting after the RLDRAM device is in multiplexed address mode. 3. MR1 (Ax), MR1 (Ay), MR2 (Ax), and MR2 (Ay) represent MR1 and MR2 settings in multiplexed address mode. 4. The above sequence must be followed in order to power up the RLDRAM device in the multiplexed address mode. 5. See QVLD output drive strength status during power up and initialization in non-multiplexed initialization operation section. 6. After MR2 has been issued, RTT is either High-Z or enabled to the ODT value selected in MR1. 94 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Multiplexed Address Mode Figure 59: MR0 Definition for Multiplexed Address Mode A5 A4 A3 Ax A18.......A10 A9 A8 A0 Ay A18.......A10 A9 A8 A4 A3 Address Bus BA3 BA2 BA1 BA0 21 20 19 18 01 01 MRS 9 8 7 6 5 4 AM DLL Data Latency 17-10 Reserved 3 2 1 0 Mode Register (Mx) tRC_MRS M7 M6 M5 M4 Data Latency (RL & WL) M19 M18 0 0 1 1 0 1 0 Mode Register Definition 0 0 0 0 RL = 3 ; WL = 4 0 0 0 1 RL = 4 ; WL = 5 Enable 0 0 1 0 RL = 5 ; WL = 6 0 0 0 0 22,3 Disable 0 0 1 1 RL = 6 ; WL = 7 0 0 0 1 32 0 1 0 0 RL = 7 ; WL = 8 0 0 1 0 42 0 1 0 1 RL = 8 ; WL = 9 0 0 1 1 5 0 1 1 0 RL = 9 ; WL = 10 0 1 0 0 6 0 1 1 0 1 0 1 0 RL = 10 ; WL = 11 RL = 11 ; WL = 12 0 1 0 1 7 0 1 1 0 8 1 0 0 1 RL = 12 ; WL = 13 1 0 1 0 RL = 13 ; WL = 14 0 1 1 0 1 0 1 0 10 1 0 1 1 RL = 14 ; WL = 15 1 0 0 1 1 1 0 0 RL = 15 ; WL = 16 1 0 1 0 11 12 1 1 0 1 RL = 16 ; WL = 17 1 0 1 1 Reserved 1 1 1 0 Reserved 1 1 0 0 Reserved 1 1 1 1 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved M8 DLL Enable 0 1 Mode Register 0 (MR0) Mode Register 1 (MR1) Mode Register 2 (MR2) 1 Reserved Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN M9 Address MUX 0 Non-multiplexed 1 Multiplexed M3 M2 M1 M0 t RC_MRS 9 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during the MRS command. 2. BL8 not allowed. 3. BL4 not allowed. 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Multiplexed Address Mode Figure 60: MR1 Definition for Multiplexed Address Mode Ax A18.......A13 Ay A18.......A13 A10 A9 A8 A5 A4 A3 A0 A4 A3 A9 A8 Address Bus BA3 BA2 BA1 BA0 21 20 19 18 17-11 MRS Reserved 01 01 M19 M18 Mode Register Definition 0 Mode Register 0 (MR0) 0 1 Mode Register 1 (MR1) 0 1 0 Mode Register 2 (MR2) 1 1 1 Reserved 1 PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 0 4 3 ODT M5 DLL Reset M10 M9 Burst Length 0 Notes: 10 9 8 7 6 5 BL2 Ref ZQe ZQ DLL 2 1 0 Mode Register (Mx) Drive M4 M3 M2 ODT M1 M0 Output Drive 2 0 No 0 0 0 Off 0 0 RZQ/6 (40: 1 1 Yes 0 0 1 RZQ/6 (40: 0 1 RZQ/4 (60: 0 0 1 0 RZQ/4 (60: 1 0 Reserved 1 Reserved M6 ZQ Calibration Selection 0 1 1 RZQ/2 (120: 1 1 Reserved 0 Short ZQ Calibration 1 0 0 Reserved 1 Long ZQ Calibration 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 0 M8 AREF Protocol M7 0 Bank Address Control 0 Disabled - Default 1 Multibank 1 Enable ZQ Calibration Enable 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during the MRS command. 2. BL8 not available in x36. 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Multiplexed Address Mode Figure 61: MR2 Definition for Multiplexed Address Mode A0 Ax A18.......A5 A4 A3 Ay A18.......A5 A4 A3 BA3 BA2 BA1 BA0 21 20 19 18 17-5 4 3 2 01 01 MRS Reserved WRITE En M19 M18 1 0 RTR Address Bus Mode Register (Mx) Mode Register Definition 0 0 Mode Register 0 (MR0) 0 1 Mode Register 1 (MR1) 1 0 Mode Register 2 (MR2) 0 0 0-1-0-1 on all DQs 1 1 Reserved 0 1 Even DQs: 0-1-0-1 ; Odd DQs: 1-0-1-0 1 0 Reserved 1 1 Reserved M4 M3 Note: READ Training Register M1 M0 WRITE Protocol 0 0 Single Bank 0 1 Dual Bank 1 0 Quad Bank 1 1 Reserved M2 READ Training Register Enable 0 Normal RLDRAM Operation 1 READ Training Enabled 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during the MRS command. Table 41: Address Mapping in Multiplexed Address Mode Address Data Width Burst Length Ball A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 x36 2 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay X A1 A2 X A6 A7 X A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 X Ay X A1 A2 X A6 A7 X A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay X A1 A2 X A6 A7 A19 A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay X A1 A2 X A6 A7 X A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 X Ay X A1 A2 X A6 A7 X A11 A12 A16 A15 4 x18 2 4 8 Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 1. X = "Don't Care" 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Multiplexed Address Mode Data Latency in Multiplexed Address Mode When in multiplexed address mode, data latency (READ and WRITE) begins when the Ay part of the address is issued with any READ or WRITE command. tRC is measured from the clock edge in which the command and Ax part of the address is issued in both multiplexed and non-multiplexed address mode. REFRESH Command in Multiplexed Address Mode Similar to other commands when in multiplexed address mode, both modes of AREF (single and multibank) are executed on the rising clock edge, following the one on which the command is issued. However, when in bank address-controlled AREF, as only the bank address is required, the next command can be applied on the following clock. When using multibank AREF, the bank addresses are mapped across Ax and Ay so a subsequent command cannot be issued until two clock cycles later. Figure 62: Bank Address-Controlled AUTO REFRESH Operation with Multiplexed Addressing T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Command AC1 NOP AREF AREF AREF AREF AREF AREF AREF AREF Address Ax Ay T11 CK# CK Ay Ax Bank n Bank AC1 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank n Don't Care Note: 1. Any command subject to tRC specification. Figure 63: Multibank AUTO REFRESH Operation with Multiplexed Addressing T0 T1 T2 T3 T4 T5 T6 T7 AREF1 NOP AREF1 NOP AREF1 NOP AC2 NOP Ax Ay Ax Ay Ax Ay Ax Ay CK# CK Command Address Bank Bank n Don't Care Notes: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 1. Usage of multibank AREF subject to tSAW and tMMD specifications. 2. Any command subject to tRC specification. 98 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Multiplexed Address Mode Figure 64: Consecutive WRITE Bursts with Multiplexed Addressing T0 T1 T2 T3 T4 WRITE NOP WRITE NOP Ax Ay Ax Ay T5 T6 WRITE NOP NOP Ax Ay T6n T7 T7n T8 T8n T9 CK# CK Command Address Bank Bank a Bank b NOP NOP NOP Bank a DK# DK tRC WL DI a DQ DI b DM Indicates a break in time scale Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Transitioning Data Don't Care 1. DI a = data-in for bank a; DI b = data-in for bank b. 99 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Multiplexed Address Mode Figure 65: WRITE-to-READ with Multiplexed Addressing T0 T1 T2 T3 T4 T5 T6 WRITE NOP READ NOP NOP NOP NOP Ax Ay Ax Ay T6n T7 T7n T8 T8n CK# CK Command Address NOP NOP WL Bank Bank a Bank b RL QK# QK DK# DK QVLD DI a DQ DO b DM Indicates a break in time scale Note: Transitioning Data Don't Care 1. DI a = data-in for bank a; DI b = data-in for bank b. Figure 66: Consecutive READ Bursts with Multiplexed Addressing T0 T1 T2 T3 T4 T5 T5n T6 T6n READ NOP READ NOP READ NOP READ Ax Ay Ax Ay Ax Ay Ax CK# CK Command Address Bank Bank a Bank b Bank c Bank d RL QVLD QK# QK DO a DQ Indicates a break in time scale Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Transitioning Data Don't Care 1. DO a = data-out for bank a. 100 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Multiplexed Address Mode Figure 67: READ-to-WRITE with Multiplexed Addressing CK# T0 T1 T2 T3 T4 T5 T6 READ NOP WRITE NOP NOP NOP NOP Ax Ay Ax Ay T6n T7 T7n T8 T9 NOP NOP NOP T9n CK Command Address Bank NOP Bank b Bank a DM QK# QK DK# DK RL WL QVLD DO an DQ Indicates a break in time scale Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN DI bn Transitioning Data Don't Care 1. DO a = data-out for bank a; DI b = data-in for bank b. 101 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Mirror Function Mirror Function The mirror function ball (MF) is a DC input used to create mirrored ballouts for simple dual-loaded clamshell mounting. If the MF ball is tied LOW, the address and command balls are in their true layout. If the MF ball is tied HIGH, the address and command balls are mirrored around the central y-axis (column 7). The following table shows the ball assignments when the MF ball is tied HIGH for a x18 device. Compare that table to Table 1 (page 12) to see how the address and command balls are mirrored. The same balls are mirrored on the x36 device. Table 42: 32 Meg x 18 Ball Assignments with MF Ball Tied HIGH 1 A 2 3 4 5 6 7 8 9 10 11 12 13 VSS VDD NF VDDQ NF VREF DQ7 VDDQ DQ8 VDD VSS RESET# B VEXT VSS NF VSSQ NF VDDQ DM0 VDDQ DQ5 VSSQ DQ6 VSS VEXT C VDD NF VDDQ NF VSSQ NF DK0# DQ2 VSSQ DQ3 VDDQ DQ4 VDD D A13 VSSQ NF VDDQ NF VSSQ DK0 VSSQ QK0 VDDQ DQ0 VSSQ A11 E VSS CS# VSSQ NF VDDQ NF MF QK0# VDDQ DQ1 VSSQ A0 VSS A7 VSS F A9 A5 VDD A4 A3 REF# ZQ WE# A1 A2 VDD NC1 G VSS A18 A8 VSS BA0 VSS CK# VSS BA1 VSS A6 A15 H A10 VDD A12 A17 VDD BA2 CK BA3 VDD A16 A14 VDD A19 J VDDQ NF VSSQ NF VDDQ NF VSS QK1# VDDQ DQ9 VSSQ QVLD VDDQ K NF VSSQ NF VDDQ NF VSSQ DK1 VSSQ QK1 VDDQ DQ10 VSSQ DQ11 L VDD NF VDDQ NF VSSQ NF DK1# DQ12 VSSQ DQ13 VDDQ DQ14 VDD M VEXT VSS NF VSSQ NF VDDQ DM1 VDDQ DQ15 VSSQ DQ16 VSS VEXT N VSS TCK VDD TDO VDDQ NF VREF DQ17 VDDQ TDI VDD TMS VSS RESET Operation The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops LOW. There are no restrictions for when it can go LOW. After RESET# goes LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT (RTT) turns off (High-Z), and the DRAM resets itself. Prior to RESET# going HIGH, at least 100 stable CK cycles with NOP commands must be given to the RLDRAM. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed. All refresh counters on the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET# has gone LOW. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 102 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 IEEE 1149.1 Serial Boundary Scan (JTAG) IEEE 1149.1 Serial Boundary Scan (JTAG) The RLDRAM 3 device incorporates a serial boundary-scan test access port (TAP) for the purpose of testing the connectivity of the device after it has been mounted on a printed circuit board (PCB). As the complexity of PCB high-density surface mounting techniques increases, the boundary-scan architecture is a valuable resource for interconnectivity debug. This port operates in accordance with IEEE Standard 1149.1-2001 (JTAG) with the exception of the ZQ pin. To ensure proper boundary-scan testing of the ZQ pin, MR1[7] needs to be set to 0 until the JTAG testing of the pin is complete. Note that upon power up, the default state of the MRS bit M1[7] is low. The JTAG test access port utilizes the TAP controller on the device, from which the instruction register, boundary-scan register, bypass register, and ID register can be selected. Each of these functions of the TAP controller is described in detail below. Disabling the JTAG Feature It is possible to operate an RLDRAM 3 device without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V SS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to V DDQ through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state, which will not interfere with the operation of the device. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. All the states in Figure 68 (page 105) are entered through the serial input of the TMS ball. A 0 in the diagram represents a LOW on the TMS ball during the rising edge of TCK, while a 1 represents a HIGH on TMS. Test Data-In (TDI) The TDI ball is used to serially input test instructions and data into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure 68 (page 105). TDI is connected to the most significant bit (MSB) of any register (see Figure 69 (page 105)). Test Data-Out (TDO) The TDO output ball is used to serially clock test instructions and data out from the registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP controller states. In all other states, the TDO ball is in a High-Z state. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register (see Figure 69 (page 105)). PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 103 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller The TAP controller is a finite state machine that uses the state of the TMS ball at the rising edge of TCK to navigate through its various modes of operation (see Figure 68 (page 105)). Each state is described in detail below. Test-Logic-Reset The test-logic-reset controller state is entered when TMS is held HIGH for at least five consecutive rising edges of TCK. As long as TMS remains HIGH, the TAP controller will remain in the test-logic-reset state. The test logic is inactive during this state. Run-Test/Idle The run-test/idle is a controller state in between scan operations. This state can be maintained by holding TMS LOW. From there, either the data register scan, or subsequently, the instruction register scan, can be selected. Select-DR-Scan Select-DR-scan is a temporary controller state. All test data registers retain their previous state while here. Capture-DR The capture-DR state is where the data is parallel-loaded into the test data registers. If the boundary-scan register is the currently selected register, then the data currently on the balls is latched into the test data registers. Shift-DR Data is shifted serially through the data register while in this state. As new data is input through the TDI ball, data is shifted out of the TDO ball. Exit1-DR, Pause-DR, and Exit2-DR The purpose of exit1-DR is used to provide a path to return back to the run-test/idle state (through the update-DR state). The pause-DR state is entered when the shifting of data through the test registers needs to be suspended. When shifting is to reconvene, the controller enters the exit2-DR state and then can re-enter the shift-DR state. Update-DR When the EXTEST instruction is selected, there are latched parallel outputs of the boundary-scan shift register that only change state during the update-DR controller state. Instruction Register States The instruction register states of the TAP controller are similar to the data register states. The desired instruction is serially shifted into the instruction register during the shift-IR state and is loaded during the update-IR state. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 104 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 IEEE 1149.1 Serial Boundary Scan (JTAG) Figure 68: TAP Controller State Diagram 1 Test-logic reset 0 Run-test/ Idle 0 1 1 Select DR-scan Select IR-scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 1 Exit1-IR 0 1 0 Pause-DR Pause-IR 0 1 0 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 1 Exit1-DR 0 1 Update-IR 1 0 0 Figure 69: TAP Controller Functional Block Diagram 0 Bypass register 7 6 5 4 3 2 1 0 TDI Selection circuitry Instruction register 31 30 29 . . Selection circuitry . 2 1 0 TDO Identification register x1 . . . . . 2 1 0 Boundry scan register TCK TMS Note: PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN TAP controller 1. x = 121 for all configurations. 105 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 IEEE 1149.1 Serial Boundary Scan (JTAG) Performing a TAP RESET A reset is performed by forcing TMS HIGH (V DDQ) for five rising edges of tCK. This RESET does not affect the operation of the device and may be performed while the device is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. If JTAG inputs cannot be guaranteed to be stable during power-up it is recommended that TMS be held HIGH for at least 5 consecutive TCK cycles prior to boundary scan testing. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the RLDRAM 3 device test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Eight-bit instructions can be serially loaded into the instruction register. This register is loaded during the update-IR state of the TAP controller. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the capture-IR state, the two LSBs are loaded with a binary 01 pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This enables data to be shifted through the device with minimal delay. The bypass register is set LOW (V SS) when the BYPASS instruction is executed. Boundary-Scan Register The boundary-scan register is connected to all the input and bidirectional balls on the device. Several balls are also included in the scan register to reserved balls. The device has a 121-bit register. The boundary-scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the shift-DR state. The order in which the bits are connected is shown in Table 49 (page 111). Each bit corresponds to one of the balls on the RLDRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the RLDRAM 3 and can be shifted out when the TAP controller is in the shift-DR state. The ID register has a vendor code and other information described in Table 46 (page 110). PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 106 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Instruction Set Overview There are 28 different instructions possible with the 8-bit instruction register. All combinations used are listed in Table 48 (page 111). These six instructions are described in detail below. The remaining instructions are reserved and should not be used. The TAP controller used in this RLDRAM 3 device is fully compliant to the IEEE 1149.1 convention. Instructions are loaded into the TAP controller during the shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller needs to be moved into the update-IR state. EXTEST The EXTEST instruction enables circuitry external to the component package to be tested. Boundary-scan register cells at output balls are used to apply a test vector, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary-scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output driver is turned on, and the PRELOAD data is driven onto the output balls. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. High-Z The High-Z instruction causes the bypass register to be connected between the TDI and TDO. This places all RLDRAM outputs into a High-Z state. CLAMP When the CLAMP instruction is loaded into the instruction register, the data driven by the output balls are determined from the values held in the boundary-scan register. SAMPLE/PRELOAD When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the capture-DR state, a snapshot can be taken of the states of the component's input and output signals without interfering with the normal operation of the assembled board. The snapshot is taken on the rising edge of TCK and is captured in the boundry-scan register. The data can then be viewed by shifting through the component's TDO output. The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while the RLDRAM 3 clock operates significantly faster. Because there is a large difference between the clock frequencies, it is possible that during the capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 IEEE 1149.1 Serial Boundary Scan (JTAG) no guarantee as to the value that will be captured. Repeatable results may not be possible. To ensure that the boundary-scan register will capture the correct value of a signal, the RLDRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The RLDRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary-scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the shift-DR state. This places the boundary-scan register between the TDI and TDO balls. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the bypass register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary-scan path when multiple devices are connected together on a board. Reserved for Future Use The remaining instructions are not implemented but are reserved for future use. Do not use these instructions. Figure 70: JTAG Operation - Loading Instruction Code and Shifting Out Data T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TCK TMS TDI TAP Controller State Run-Test Idle Test-LogicReset Select-DRSCAN Select-IRSCAN Capture-IR Shift-IR Shift IR Exit 1-IR Pause-IR Pause-IR TDO 8-bit instruction code T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 TCK TMS TDI TAP Controller State Exit 2-IR Update-IR Select-DRScan Capture-DR Shift-DR Shift DR Exit1-DR Update-DR Run-Test Idle Run-Test Idle TDO n-bit register between TDI and TDO Transitioning Data PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 108 Don't Care Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 IEEE 1149.1 Serial Boundary Scan (JTAG) Figure 71: TAP Timing T2 T1 T3 T4 T6 T5 Test clock (TCK) tTHTL tTLTH tTHTH tMVTH tTHMX Test mode select (TMS) tDVTH tTHDX Test data-in (TDI) tTLOV tTLOX Test data-out (TDO) Undefined Don't Care Table 43: TAP Input AC Logic Levels 0C TC +95C; +1.28V VDD +1.42V, unless otherwise noted Description Symbol Min Max Units Input HIGH (logic 1) voltage VIH VREF + 0.225 - V Input LOW (logic 0) voltage VIL - VREF - 0.225 V Note: 1. All voltages referenced to VSS (GND). Table 44: TAP AC Electrical Characteristics 0C TC +95C; +1.28V VDD +1.42V Description Symbol Min Max Units Clock cycle time tTHTH 20 Clock frequency fTF 50 MHz Clock HIGH time tTHTL 10 ns Clock LOW time tTLTH 10 ns TCK LOW to TDO unknown tTLOX 0 ns TCK LOW to TDO valid tTLOV TDI valid to TCK HIGH tDVTH 5 ns TCK HIGH to TDI invalid tTHDX 5 ns tMVTH 5 ns Clock ns TDI/TDO times 10 ns Setup times TMS setup PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 109 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 IEEE 1149.1 Serial Boundary Scan (JTAG) Table 44: TAP AC Electrical Characteristics (Continued) 0C TC +95C; +1.28V VDD +1.42V Description Symbol Min tCS 5 Capture setup Max Units ns Hold times TMS hold tTHMX 5 ns tCH 5 ns Capture hold Note: 1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary-scan register. Table 45: TAP DC Electrical Characteristics and Operating Conditions 0C TC +95C; +1.28V VDD +1.42V, unless otherwise noted Description Condition Symbol Min Max Units Notes Input HIGH (logic 1) voltage VIH VREF + 0.15 VDDQ V 1, 2 Input LOW (logic 0) voltage VIL VSSQ VREF - 0.15 V 1, 2 0V VIN VDD ILI -5.0 5.0 A Output disabled, 0V VIN VDDQ ILO -5.0 5.0 A Input leakage current Output leakage current Output low voltage IOLC = 100A VOL1 0.2 V 1 Output low voltage IOLT = 2mA VOL2 0.4 V 1 Output high voltage |IOHC| = 100A VOH1 VDDQ - 0.2 V 1 |IOHT| = 2mA VOH2 VDDQ - 0.4 V 1 OUTPUT HIGH VOLTAGE Notes: 1. All voltages referenced to VSS (GND). 2. See AC Overshoot/Undershoot Specifications section for overshoot and undershoot limits. Table 46: Identification Register Definitions Instruction Field Revision number (31:28) All Devices abcd Description ab = 00 for Die Revision A cd = 00 for x18, 01 for x36 Device ID (27:12) 00jkidef10100111 def = 000 for 576Mb, 001 for 1Gb Double Die Package, 010 for 1Gb Monolithic i = 0 for common I/O jk = 10 for RLDRAM 3 Micron JEDEC ID code (11:1) ID register presence indicator (0) PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 00000101100 1 Enables unique identification of RLDRAM vendor Indicates the presence of an ID register 110 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 IEEE 1149.1 Serial Boundary Scan (JTAG) Table 47: Scan Register Sizes Register Name Bit Size Instruction 8 Bypass 1 ID 32 Boundary scan 121 Table 48: Instruction Codes Instruction Code Description Extest 0000 0000 Captures I/O ring contents; Places the boundary-scan register between TDI and TDO; This operation does not affect RLDRAM 3 operations. ID code 0010 0001 Loads the ID register with the vendor ID code and places the register between TDI and TDO; This operation does not affect RLDRAM 3 operations. Sample/preload 0000 0101 Captures I/O ring contents; Places the boundary-scan register between TDI and TDO. Clamp 0000 0111 Selects the bypass register to be connected between TDI and TDO; Data driven by output balls are determined from values held in the boundary-scan register. High-Z 0000 0011 Selects the bypass register to be connected between TDI and TDO; All outputs are forced into High-Z. Bypass 1111 1111 Places the bypass register between TDI and TDO; This operation does not affect RLDRAM operations. Table 49: Boundary Scan (Exit) Bit# Ball Bit# Ball Bit# Ball 1 N8 42 L7 83 M3 2 N8 43 K7 84 M3 3 M11 44 H1 85 M5 4 M11 45 H4 86 M5 5 M9 46 G2 87 L2 6 M9 47 G3 88 L2 7 L12 48 F1 89 L4 8 L12 49 F5 90 L4 9 L10 50 F4 91 L6 10 L10 51 F2 92 L6 11 L8 52 D1 93 K1 12 L8 53 F7 94 K1 13 K13 54 D7 95 K3 14 K13 55 C7 96 K3 15 K11 56 A13 97 J4 16 K11 57 B7 98 J4 PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 111 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 IEEE 1149.1 Serial Boundary Scan (JTAG) Table 49: Boundary Scan (Exit) (Continued) Bit# Ball Bit# Ball Bit# Ball 17 J10 58 E7 99 J6 18 J10 59 D13 100 K5 19 J8 60 F12 101 J2 20 K9 61 F10 102 A4 21 J12 62 F9 103 A4 22 A10 63 E2 104 A6 23 A10 64 E12 105 A6 24 A8 65 F6 106 B3 25 A8 66 F8 107 B3 26 B11 67 G7 108 B5 27 B11 68 H7 109 B5 28 B9 69 G5 110 C2 29 B9 70 G9 111 C2 30 C12 71 H6 112 C4 31 C12 72 H8 113 C4 32 C10 73 F13 114 C6 33 C10 74 G11 115 C6 34 C8 75 G12 116 E4 35 C8 76 H10 117 E4 36 E10 77 H3 118 D3 37 E10 78 H11 119 D3 38 D11 79 H13 120 E6 39 D11 80 M7 121 D5 40 E8 81 N6 - - 41 D9 82 N6 - - PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 112 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Revision History Revision History Rev. C, Production - 12/12 * Changed the units from nS to CK for tWTR specification * Corrected values from 0.935 to 0.9375 in the speed bin table * Added reference to -125F on front page, part number guide, speed bin table, and tRC_MRS table * Added a -125F column into the IDD table * Updated the Imbref4 IDD values for most fields. This increase is necessary because a mistake in the char test used to set these limits caused the values to be incorrect * Corrected typo in the tIS/tIH derating table. (tIH - 0.4 CMD/ADDR slew rate, CK/CK# 4.0 V/ns) * Changed definition of NOP command to specify the states of WE# & REF# * Added note on the leaded (PA) package to "Consult factory" * Updated READ-to-WRITE timing diagram from BL = 4 to BL = 2. The WRITE-to-READ timing diagram is BL = 2 (I did not want customers to think that a NOP was required when transitioning from a READ to a WRITE ) * Changed wording in Note 3 of ZQ calibration description * Added note to general description, which explains using a X36 devices with only 2 QK/QK# sets instead of all 4. * Modified ball out to reflect the ballout required to support the X18 DDP and the 2Gb monolithic devices * Added note to Iref that states: "all other balls not under test = 0V" * Added updates to -125F speed bin table and tRC_MRS table to meet customer request to support CL=12, tRC_MRS = 6 for tCK=1.334ns Rev. B, Advance - 1/12 * * * * * * * * * * * * * * * * PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN Changed tQKQx,min to tQKQx,max in figure 52 read data valid window Added Vext information to Note 1 of Input/Output Capacitance table Added Table 38 tRC_MRS values Updated tIS/tIH(base) values on page 50 to 85,120,170 & 65,100, 120 Corrected error in High-Z description. replaced "boundry-scan" with "bypass" Added verbage in SAMPLE/PRELOAD description, specifying which edge of TCK is used to capture the states of the pins. Changed JTAG boundary scan order. Now L7=bit 42, K7=bit 43, J6=bit 99, K5=bit 100 Updated Figure 70 "JTAG Operation" to match actual operation of the device. Changed QKx, QKx# to DKx, DKx# in table 33 & 34 Derating values for tDS/tDH. Changed Cjtag min from 2.0 to 1.5. Corrected typo in X36 functional block diagram. Changed DQ1/DK1# to DK1/DK1#. Added RESET# and MF pin Ci Max spec into Input/Output Capacitance table 6. Listed QVLD with the QK/QK# signals in Table 6. Changed tDS Base value from 15 to -15 in Table 33. Corrected errors in VSEH min, VSEL max and VILdiff(AC) max definitions. Updated Speed bin table 26 to fill in tCK gaps by adjusting tCKmin values for -107E, RL=5, -125, RL=6,9,14,15. 113 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 576Mb: x18, x36 RLDRAM 3 Revision History * * * * * * Updated table 38 tRC_MRS values to reflect the speed bin table changes Changed the Cimax (CMD, ADDR) spec from 2.1 to 2.25 Changed the Cjtag max from 5.3 to 4.5 Added X18 & X36 IDD values. updated tCKQK AC timing specifications. Added in the thermal impedance values Rev. A, Advance - 6/11 * Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef84003617 576mb_rldram3.pdf - Rev. C 12/12 EN 114 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.