RLDRAM 3
MT44K32M18 – 2 Meg x 18 x 16 Banks
MT44K16M36 – 1 Meg x 36 x 16 Banks
Features
• 1066 MHz DDR operation (2133 Mb/s/ball data
rate)
• 76.8 Gb/s peak bandwidth (x36 at 1066 MHz clock
frequency)
• Organization
– 32 Meg x 18, and 16 Meg x 36 common I/O (CIO)
– 16 banks
• 1.2V center-terminated push/pull I/O
• 2.5V VEXT, 1.35V VDD, 1.2V VDDQ I/O
• Reduced cycle time (tRC (MIN) = 8 - 12ns)
• SDR addressing
• Programmable READ/WRITE latency (RL/WL) and
burst length
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Free-running differential input data clocks (DKx,
DKx#) and output data clocks (QKx, QKx#)
• On-die DLL generates CK edge-aligned data and
differential output data clock signals
• 64ms refresh (128K refresh per 64ms)
• 168-ball FBGA package
•Ω or 60Ω matched impedance outputs
• Integrated on-die termination (ODT)
• Single or multibank writes
• Extended operating range (200–1066 MHz)
• READ training register
• Multiplexed and non-multiplexed addressing capa-
bilities
• Mirror function
• Output driver and ODT calibration
• JTAG interface (IEEE 1149.1-2001)
Options1Marking
• Clock cycle and tRC timing
– 0.93ns and tRC (MIN) = 8ns
(RL3-2133)
-093E
– 0.93ns and tRC (MIN) = 10ns
(RL3-2133)
-093
– 1.07ns and tRC (MIN) = 8ns
(RL3-1866)
-107E
– 1.07ns and tRC (MIN) = 10ns
(RL3-1866)
-107
– 1.25ns and tRC (MIN) = 8ns
(RL3-1600)
-125F
– 1.25ns and tRC (MIN) = 10ns
(RL3-1600)
-125E
– 1.25ns and tRC (MIN) = 12ns
(RL3-1600)
-125
• Configuration
– 32 Meg x 18 32M18
– 16 Meg x 36 16M36
• Operating temperature
– Commercial (TC = 0° to +95°C) None
– Industrial (TC = –40°C to +95°C) IT
• Package
– 168-ball FBGA PA2
– 168-ball FBGA (Pb-free) RB
• Revision :A
Notes: 1. Not all options listed can be combined to
define an offered product. Use the part cat-
alog search on www.micron.com for availa-
ble offerings.
2. Consult factory.
576Mb: x18, x36 RLDRAM 3
Features
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. C 12/12 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.
2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Figure 1: 576Mb RLDRAM 3 Part Numbers
Package
168-ball FBGA
168-ball FBGA (Pb-free)
Example Part Number: MT44K16M36PA-093E
tCK = 0.93ns (8ns tRC)
tCK = 0.93ns (10ns tRC)
tCK = 1.07ns (8ns tRC)
tCK = 1.07ns (10ns tRC)
tCK = 1.25ns (8ns tRC)
tCK = 1.25ns (10ns tRC)
tCK = 1.25ns (12ns tRC)
Speed Grade
-093E
-093
-107E
-107
-125F
-125E
-125
-
Configuration
MT44K Package Speed Temp
Temperature
Commercial
Industrial
None
IT
Configuration
32 Meg x 18
16 Meg x 36
32M18
16M36
PA
RB
BGA Part Marking Decoder
Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s BGA Part Marking Decoder is available on Micron’s Web site at www.micron.com.
576Mb: x18, x36 RLDRAM 3
Features
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. C 12/12 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.
2011 Micron Technology, Inc. All rights reserved.
Contents
General Description ......................................................................................................................................... 8
General Notes .............................................................................................................................................. 8
State Diagram .................................................................................................................................................. 9
Functional Block Diagrams ............................................................................................................................. 10
Ball Assignments and Descriptions ................................................................................................................. 12
Package Dimensions ....................................................................................................................................... 16
Electrical Characteristics – IDD Specifications .................................................................................................. 17
Electrical Specifications – Absolute Ratings and I/O Capacitance ..................................................................... 21
Absolute Maximum Ratings ........................................................................................................................ 21
Input/Output Capacitance .......................................................................................................................... 21
AC and DC Operating Conditions .................................................................................................................... 22
AC Overshoot/Undershoot Specifications .................................................................................................... 24
Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 27
Slew Rate Definitions for Differential Input Signals ...................................................................................... 29
ODT Characteristics ....................................................................................................................................... 30
ODT Resistors ............................................................................................................................................ 30
ODT Sensitivity .......................................................................................................................................... 32
Output Driver Impedance ............................................................................................................................... 33
Output Driver Sensitivity ............................................................................................................................ 35
Output Characteristics and Operating Conditions ............................................................................................ 36
Reference Output Load ............................................................................................................................... 39
Slew Rate Definitions for Single-Ended Output Signals ..................................................................................... 40
Slew Rate Definitions for Differential Output Signals ........................................................................................ 41
Speed Bin Tables ............................................................................................................................................ 42
AC Electrical Characteristics ........................................................................................................................... 44
Temperature and Thermal Impedance Characteristics ..................................................................................... 49
Command and Address Setup, Hold, and Derating ........................................................................................... 51
Data Setup, Hold, and Derating ....................................................................................................................... 57
Commands .................................................................................................................................................... 63
MODE REGISTER SET (MRS) Command ......................................................................................................... 64
Mode Register 0 (MR0) .................................................................................................................................... 65
tRC ............................................................................................................................................................. 66
Data Latency .............................................................................................................................................. 66
DLL Enable/Disable ................................................................................................................................... 66
Address Multiplexing .................................................................................................................................. 66
Mode Register 1 (MR1) .................................................................................................................................... 68
Output Drive Impedance ............................................................................................................................ 68
DQ On-Die Termination (ODT) ................................................................................................................... 68
DLL Reset ................................................................................................................................................... 68
ZQ Calibration ............................................................................................................................................ 69
ZQ Calibration Long ................................................................................................................................... 70
ZQ Calibration Short ................................................................................................................................... 70
AUTO REFRESH Protocol ............................................................................................................................ 71
Burst Length (BL) ....................................................................................................................................... 71
Mode Register 2 (MR2) .................................................................................................................................... 73
READ Training Register (RTR) ..................................................................................................................... 73
WRITE Protocol .......................................................................................................................................... 75
WRITE Command .......................................................................................................................................... 75
Multibank WRITE ....................................................................................................................................... 76
READ Command ............................................................................................................................................ 76
576Mb: x18, x36 RLDRAM 3
Features
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. C 12/12 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.
2011 Micron Technology, Inc. All rights reserved.
AUTO REFRESH Command ............................................................................................................................ 78
INITIALIZATION Operation ............................................................................................................................ 80
WRITE Operation ........................................................................................................................................... 83
READ Operation ............................................................................................................................................. 87
AUTO REFRESH Operation ............................................................................................................................. 90
Multiplexed Address Mode .............................................................................................................................. 93
Data Latency in Multiplexed Address Mode ................................................................................................. 98
REFRESH Command in Multiplexed Address Mode ..................................................................................... 98
Mirror Function ............................................................................................................................................ 102
RESET Operation ........................................................................................................................................... 102
IEEE 1149.1 Serial Boundary Scan (JTAG) ....................................................................................................... 103
Disabling the JTAG Feature ........................................................................................................................ 103
Test Access Port (TAP) ................................................................................................................................ 103
TAP Controller ........................................................................................................................................... 104
Performing a TAP RESET ............................................................................................................................ 106
TAP Registers ............................................................................................................................................ 106
TAP Instruction Set .................................................................................................................................... 107
Revision History ............................................................................................................................................ 113
Rev. C, Production – 12/12 ......................................................................................................................... 113
Rev. B, Advance – 1/12 ............................................................................................................................... 113
Rev. A, Advance – 6/11 ............................................................................................................................... 114
576Mb: x18, x36 RLDRAM 3
Features
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. C 12/12 EN 4Micron Technology, Inc. reserves the right to change products or specifications without notice.
2011 Micron Technology, Inc. All rights reserved.
List of Figures
Figure 1: 576Mb RLDRAM 3 Part Numbers ..................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: 32 Meg x 18 Functional Block Diagram ............................................................................................. 10
Figure 4: 16 Meg x 36 Functional Block Diagram ............................................................................................. 11
Figure 5: 168-Ball FBGA ................................................................................................................................. 16
Figure 6: Single-Ended Input Signal ............................................................................................................... 23
Figure 7: Overshoot ....................................................................................................................................... 24
Figure 8: Undershoot .................................................................................................................................... 24
Figure 9: VIX for Differential Signals ................................................................................................................ 25
Figure 10: Single-Ended Requirements for Differential Signals ........................................................................ 26
Figure 11: Definition of Differential AC Swing and tDVAC ................................................................................ 26
Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 28
Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# .................................. 29
Figure 14: ODT Levels and I-V Characteristics ................................................................................................ 30
Figure 15: Output Driver ................................................................................................................................ 33
Figure 16: DQ Output Signal .......................................................................................................................... 38
Figure 17: Differential Output Signal .............................................................................................................. 39
Figure 18: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 39
Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 40
Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx# ..................................................... 41
Figure 21: Example Temperature Test Point Location ...................................................................................... 50
Figure 22: Nominal Slew Rate and tVAC for tIS (Command and Address - Clock) ............................................... 53
Figure 23: Nominal Slew Rate for tIH (Command and Address - Clock) ............................................................ 54
Figure 24: Tangent Line for tIS (Command and Address - Clock) ...................................................................... 55
Figure 25: Tangent Line for tIH (Command and Address - Clock) ..................................................................... 56
Figure 26: Nominal Slew Rate and tVAC for tDS (DQ - Strobe) .......................................................................... 59
Figure 27: Nominal Slew Rate for tDH (DQ - Strobe) ........................................................................................ 60
Figure 28: Tangent Line for tDS (DQ - Strobe) ................................................................................................. 61
Figure 29: Tangent Line for tDH (DQ - Strobe) ................................................................................................ 62
Figure 30: MRS Command Protocol ............................................................................................................... 64
Figure 31: MR0 Definition for Non-Multiplexed Address Mode ........................................................................ 65
Figure 32: MR1 Definition for Non-Multiplexed Address Mode ........................................................................ 68
Figure 33: ZQ Calibration Timing (ZQCL and ZQCS) ....................................................................................... 70
Figure 34: Read Burst Lengths ........................................................................................................................ 72
Figure 35: MR2 Definition for Non-Multiplexed Address Mode ........................................................................ 73
Figure 36: READ Training Function - Back-to-Back Readout ............................................................................ 74
Figure 37: WRITE Command ......................................................................................................................... 75
Figure 38: READ Command ........................................................................................................................... 77
Figure 39: Bank Address-Controlled AUTO REFRESH Command ..................................................................... 78
Figure 40: Multibank AUTO REFRESH Command ........................................................................................... 79
Figure 41: Power-Up/Initialization Sequence ................................................................................................. 81
Figure 42: WRITE Burst ................................................................................................................................. 83
Figure 43: Consecutive WRITE Bursts ............................................................................................................. 84
Figure 44: WRITE-to-READ ............................................................................................................................ 84
Figure 45: WRITE - DM Operation .................................................................................................................. 85
Figure 46: Consecutive Quad Bank WRITE Bursts ........................................................................................... 86
Figure 47: Interleaved READ and Quad Bank WRITE Bursts ............................................................................. 86
Figure 48: Basic READ Burst .......................................................................................................................... 87
Figure 49: Consecutive READ Bursts (BL = 2) .................................................................................................. 88
Figure 50: Consecutive READ Bursts (BL = 4) .................................................................................................. 88
576Mb: x18, x36 RLDRAM 3
Features
PDF: 09005aef84003617
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2011 Micron Technology, Inc. All rights reserved.
Figure 51: READ-to-WRITE (BL = 2) ............................................................................................................... 89
Figure 52: Read Data Valid Window ................................................................................................................ 89
Figure 53: Bank Address-Controlled AUTO REFRESH Cycle ............................................................................. 90
Figure 54: Multibank AUTO REFRESH Cycle ................................................................................................... 90
Figure 55: READ Burst with ODT .................................................................................................................... 91
Figure 56: READ-NOP-READ with ODT .......................................................................................................... 92
Figure 57: Command Description in Multiplexed Address Mode ..................................................................... 93
Figure 58: Power-Up/Initialization Sequence in Multiplexed Address Mode ..................................................... 94
Figure 59: MR0 Definition for Multiplexed Address Mode ................................................................................ 95
Figure 60: MR1 Definition for Multiplexed Address Mode ................................................................................ 96
Figure 61: MR2 Definition for Multiplexed Address Mode ................................................................................ 97
Figure 62: Bank Address-Controlled AUTO REFRESH Operation with Multiplexed Addressing .......................... 98
Figure 63: Multibank AUTO REFRESH Operation with Multiplexed Addressing ................................................ 98
Figure 64: Consecutive WRITE Bursts with Multiplexed Addressing ................................................................. 99
Figure 65: WRITE-to-READ with Multiplexed Addressing ............................................................................... 100
Figure 66: Consecutive READ Bursts with Multiplexed Addressing .................................................................. 100
Figure 67: READ-to-WRITE with Multiplexed Addressing ............................................................................... 101
Figure 68: TAP Controller State Diagram ........................................................................................................ 105
Figure 69: TAP Controller Functional Block Diagram ..................................................................................... 105
Figure 70: JTAG Operation - Loading Instruction Code and Shifting Out Data ................................................. 108
Figure 71: TAP Timing .................................................................................................................................. 109
576Mb: x18, x36 RLDRAM 3
Features
PDF: 09005aef84003617
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2011 Micron Technology, Inc. All rights reserved.
List of Tables
Table 1: 32 Meg x 18 Ball Assignments – 168-Ball FBGA (Top View) .................................................................. 12
Table 2: 16 Meg x 36 Ball Assignments – 168-Ball FBGA (Top View) .................................................................. 13
Table 3: Ball Descriptions .............................................................................................................................. 14
Table 4: IDD Operating Conditions and Maximum Limits ................................................................................ 17
Table 5: Absolute Maximum Ratings .............................................................................................................. 21
Table 6: Input/Output Capacitance ................................................................................................................ 21
Table 7: DC Electrical Characteristics and Operating Conditions ..................................................................... 22
Table 8: Input AC Logic Levels ........................................................................................................................ 22
Table 9: Control and Address Balls ................................................................................................................. 24
Table 10: Clock, Data, Strobe, and Mask Balls ................................................................................................. 24
Table 11: Differential Input Operating Conditions (CK, CK# and DKx, DKx#) ................................................... 25
Table 12: Allowed Time Before Ringback (tDVAC) for CK, CK#, DKx, and DKx# ................................................. 27
Table 13: Single-Ended Input Slew Rate Definition .......................................................................................... 27
Table 14: Differential Input Slew Rate Definition ............................................................................................. 29
Table 15: ODT DC Electrical Characteristics ................................................................................................... 30
Table 16: RTT Effective Impedances ................................................................................................................ 31
Table 17: ODT Sensitivity Definition .............................................................................................................. 32
Table 18: ODT Temperature and Voltage Sensitivity ........................................................................................ 32
Table 19: Driver Pull-Up and Pull-Down Impedance Calculations ................................................................... 34
Table 20: Output Driver Sensitivity Definition ................................................................................................. 35
Table 21: Output Driver Voltage and Temperature Sensitivity .......................................................................... 35
Table 22: Single-Ended Output Driver Characteristics ..................................................................................... 36
Table 23: Differential Output Driver Characteristics ........................................................................................ 37
Table 24: Single-Ended Output Slew Rate Definition ....................................................................................... 40
Table 25: Differential Output Slew Rate Definition .......................................................................................... 41
Table 26: RL3 2133/1866 Speed Bins ............................................................................................................... 42
Table 27: RL3 1600 Speed Bins ....................................................................................................................... 43
Table 28: AC Electrical Characteristics ............................................................................................................ 44
Table 29: Temperature Limits ......................................................................................................................... 49
Table 30: Thermal Impedance ........................................................................................................................ 49
Table 31: Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based ........................ 51
Table 32: Derating Values for tIS/tIH – AC150/DC100-Based ............................................................................ 52
Table 33: Minimum Required Time tVAC Above VIH(AC) (or Below VIL(AC)) for Valid Transition ............................ 52
Table 34: Data Setup and Hold Values at 1 V/ns (DKx, DKx# at 2V/ns) – AC/DC-Based ..................................... 57
Table 35: Derating Values for tDS/tDH – AC150/DC100-Based ......................................................................... 58
Table 36: Minimum Required Time tVAC Above VIH(AC) (or Below VIL(AC)) for Valid Transition ............................ 58
Table 37: Command Descriptions .................................................................................................................. 63
Table 38: Command Table ............................................................................................................................. 63
Table 39: tRC_MRS MR0[3:0] values ................................................................................................................ 66
Table 40: Address Widths of Different Burst Lengths ....................................................................................... 71
Table 41: Address Mapping in Multiplexed Address Mode ............................................................................... 97
Table 42: 32 Meg x 18 Ball Assignments with MF Ball Tied HIGH ..................................................................... 102
Table 43: TAP Input AC Logic Levels .............................................................................................................. 109
Table 44: TAP AC Electrical Characteristics .................................................................................................... 109
Table 45: TAP DC Electrical Characteristics and Operating Conditions ............................................................ 110
Table 46: Identification Register Definitions .................................................................................................. 110
Table 47: Scan Register Sizes ......................................................................................................................... 111
Table 48: Instruction Codes .......................................................................................................................... 111
Table 49: Boundary Scan (Exit) ..................................................................................................................... 111
576Mb: x18, x36 RLDRAM 3
Features
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. C 12/12 EN 7Micron Technology, Inc. reserves the right to change products or specifications without notice.
2011 Micron Technology, Inc. All rights reserved.
General Description
The Micron RLDRAM 3 is a high-speed memory device designed for high-bandwidth
data storage—telecommunications, networking, cache applications, etc. The chip’s 16-
bank architecture is optimized for sustainable high-speed operation.
The DDR I/O interface transfers two data bits per clock cycle at the I/O balls. Output
data is referenced to the READ strobes.
Commands, addresses, and control signals are also registered at every positive edge of
the differential input clock, while input data is registered at both positive and negative
edges of the input data strobes.
Read and write accesses to the RL3 device are burst-oriented. The burst length (BL) is
programmable to 2, 4, or 8 by a setting in the mode register.
The device is supplied with 1.35V for the core and 1.2V for the output drivers. The 2.5V
supply is used for an internal supply.
Bank-scheduled refresh is supported with the row address generated internally.
The 168-ball FBGA package is used to enable ultra-high-speed data transfer rates.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation.
• Any functionality not specifically stated is considered undefined, illegal, and not sup-
ported, and can result in unknown operation.
• Nominal conditions are assumed for specifications not defined within the figures
shown in this data sheet.
• Throughout this data sheet, the terms "RLDRAM," "DRAM,” and "RLDRAM 3" are all
used interchangeably and refer to the RLDRAM 3 SDRAM device.
• References to DQ, DK, QK, DM, and QVLD are to be interpeted as each group collec-
tively, unless specifically stated otherwise. This includes true and complement signals
of differential signals.
• Non-multiplexed operation is assumed if not specified as multiplexed.
• A X36 Device supplies four QK/QK# sets. One per 9 DQs. If a user only wants to use
two QK/QK# sets, this is allowed. The user needs to use QK0/QK0# and QK1/QK1#.
QK0/QK0# will control DQ[8:0] & DQ[26:18]. QK1/QK1# will control DQ[17:9] &
DQ[35:27]. The QK to DQ timing parameter to be used would be tQKQ02, tQKQ13. The
unused QK/QK# pins should be left floating.
576Mb: x18, x36 RLDRAM 3
General Description
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. C 12/12 EN 8Micron Technology, Inc. reserves the right to change products or specifications without notice.
2011 Micron Technology, Inc. All rights reserved.
State Diagram
Figure 2: Simplified State Diagram
Initialization
sequence
NOP
READ
WRITE
RESET#
MRS AREF
Automatic sequence
Command sequence
576Mb: x18, x36 RLDRAM 3
State Diagram
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. C 12/12 EN 9Micron Technology, Inc. reserves the right to change products or specifications without notice.
2011 Micron Technology, Inc. All rights reserved.
Functional Block Diagrams
Figure 3: 32 Meg x 18 Functional Block Diagram
13
CK#
CS#
CK
8
A[19:0]1
BA[3:0]
ZQ
ZQCL, ZQCS
RZQ
REF#
WE#
MF
TCK
TMS
TDI
RESET#
24
32
I/O gating
DQM mask logic
Column
decoder
Bank 0
memory
array
(8192 x 32 x 8 x 18)2
8192
Bank
control
logic
Bank 1
Bank 0
Bank 14
Bank 15
13
71
416
16
Refresh
counter
13
24
Mode register
Command
decode
Control
logic
Row-
address
MUX
Address
register
JTAG
Logic and
Boundary
Scan Register
Column-
address
counter/
latch
71
144
READ
logic
WRITE
FIFO
and
drivers
CLK
in
144
144
n
n
18
18
18
4
18
4
2
DQ
latch
QK/QK#
generator
READ
Drivers
DLL
CK/CK#
RCVRS
Input
logic
(0 ....17)
(0...3)
VDDQ/2
RTT
VDDQ/2
RTT
ODT control
ODT control
RTT
ODT control
ODT control
DQ[17:0]
QVLD
TDO
QK0/QK0#,QK1/QK1#
DK0/DK0#, DK1/DK1#
DM[1:0]
ZQ CAL
ZQ CAL
ZQ CAL
5
21
21
SENSE AMPLIFIERS
Sense amplifiers
8192
18
18
Bank 0
row-
address
latch
and
decoder
VDDQ/2
Notes: 1. Example for BL = 2; column address will be reduced with an increase in burst length.
2. 8 = (length of burst) x 2^ (number of column addresses to WRITE FIFO and READ logic).
576Mb: x18, x36 RLDRAM 3
Functional Block Diagrams
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. C 12/12 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2011 Micron Technology, Inc. All rights reserved.
Functional Block Diagrams
Figure 4: 16 Meg x 36 Functional Block Diagram
13
CK#
CS#
CK
8
A[18:0]1
TCK
TMS
TDI
ZQ
ZQCL, ZQCS
RZQ
REF#
WE#
MF
RESET#
23
32
I/O gating
DQM mask logic
Column
decoder
Bank 0
memory
array
(8192 x 32 x 4 x 36)2
8192
Bank
control
logic
Bank 1
Bank 0
Bank 14
Bank 15
13
61
416
16
Refresh
counter
13
23
Mode register
Command
decode
Control
logic
Row-
address
MUX
Address
register
JTAG
Logic and
Boundary
Scan Register
Column-
address
counter/
latch
61
144
READ
logic
WRITE
FIFO
and
drivers
CLK
in
144
144
n
n
36
36
36
8
4
2
36
DQ
latch
QK/QK#
generator
READ
Drivers
DLL
CK/CK#
RCVRS
Input
logic
(0 ....35)
(0...3)
VDDQ/2
VDDQ/2
RTT
RTT
VDDQ/2
ODT control
ODT control
ODT control
ODT control
RTT
DQ[35:0]
QK0/QK0#, QK1/QK1#
QK2/QK2#, QK3/QK3#
QVLD[1:0]
DK0/DK0#, DK1/DK1#
DM[1:0]
TDO
ZQ CAL
ZQ CAL
ZQ CAL
5
11
11
SENSE AMPLIFIERS
Sense amplifiers
8192
36
36
Bank 0
row-
address
latch
and
decoder
Notes: 1. Example for BL = 2; column address will be reduced with an increase in burst length.
2. 4 = (length of burst) x 2^ (number of column addresses to WRITE FIFO and READ logic).
576Mb: x18, x36 RLDRAM 3
Functional Block Diagrams
PDF: 09005aef84003617
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2011 Micron Technology, Inc. All rights reserved.
Ball Assignments and Descriptions
Table 1: 32 Meg x 18 Ball Assignments – 168-Ball FBGA (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13
A V
SS VDD NF VDDQ NF VREF DQ7 VDDQ DQ8 VDD VSS RESET#
BVEXT VSS NF VSSQ NF VDDQ DM0 VDDQ DQ5 VSSQ DQ6 VSS VEXT
CVDD NF VDDQ NF VSSQ NF DK0# DQ2 VSSQ DQ3 VDDQ DQ4 VDD
DA11 VSSQ NF VDDQ NF VSSQ DK0 VSSQ QK0 VDDQ DQ0 VSSQ A13
EVSS A0 VSSQ NF VDDQ NF MF QK0# VDDQ DQ1 VSSQ CS# VSS
FA7 NF(CS1)1VDD A2 A1 WE# ZQ REF# A3 A4 VDD A5 A9
GVSS(A20)1A15 A6 VSS BA1 VSS CK# VSS BA0 VSS A8 A18 VSS(A21)1
HA19 VDD A14 A16 VDD BA3 CK BA2 VDD A17 A12 VDD A10
JVDDQ NF VSSQ NF VDDQ NF VSS QK1# VDDQ DQ9 VSSQ QVLD VDDQ
KNF VSSQ NF VDDQ NF VSSQ DK1 VSSQ QK1 VDDQ DQ10 VSSQ DQ11
LVDD NF VDDQ NF VSSQ NF DK1# DQ12 VSSQ DQ13 VDDQ DQ14 VDD
MVEXT VSS NF VSSQ NF VDDQ DM1 VDDQ DQ15 VSSQ DQ16 VSS VEXT
NVSS TCK VDD TDO VDDQ NF VREF DQ17 VDDQ TDI VDD TMS VSS
Notes: 1. F2 is the Location of the extra CS (CS1) needed to support the x18 DDP device. G1 & G13
are the locations of the additional address signals (A20 & A21 respectfully) needed to
support the 2Gb monolithic device. F2 is Internally connected and will mirror the A5 ad-
dress signal when MF is asserted HIGH and has parasitic characteristics of an address pin.
G1 & G13 are VSS pins for this device, but have been designated as the location of A20
& A21 for the future 2Gb device.
2. NF balls for the x18 configuration are internally connected and have parasitic character-
istics of an I/O. Balls may be connected to VSSQ.
3. MF is assumed to be tied LOW for this ball assignment.
576Mb: x18, x36 RLDRAM 3
Ball Assignments and Descriptions
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Table 2: 16 Meg x 36 Ball Assignments – 168-Ball FBGA (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13
A V
SS VDD DQ26 VDDQ DQ25 VREF DQ7 VDDQ DQ8 VDD VSS RESET#
BVEXT VSS DQ24 VSSQ DQ23 VDDQ DM0 VDDQ DQ5 VSSQ DQ6 VSS VEXT
CVDD DQ22 VDDQ DQ21 VSSQ DQ20 DK0# DQ2 VSSQ DQ3 VDDQ DQ4 VDD
DA11 VSSQ DQ18 VDDQ QK2 VSSQ DK0 VSSQ QK0 VDDQ DQ0 VSSQ A13
EVSS A0 VSSQ DQ19 VDDQ QK2# MF QK0# VDDQ DQ1 VSSQ CS# VSS
FA7 NF(CS1)1VDD A2 A1 WE# ZQ REF# A3 A4 VDD A5 A9
GVSS(A20)1A15 A6 VSS BA1 VSS CK# VSS BA0 VSS A8 A18 VSS(A21)1
HNF(A19)2VDD A14 A16 VDD BA3 CK BA2 VDD A17 A12 VDD A10
JVDDQ QVLD1 VSSQ DQ27 VDDQ QK3# VSS QK1# VDDQ DQ9 VSSQ QVLD0 VDDQ
KDQ29 VSSQ DQ28 VDDQ QK3 VSSQ DK1 VSSQ QK1 VDDQ DQ10 VSSQ DQ11
LVDD DQ32 VDDQ DQ31 VSSQ DQ30 DK1# DQ12 VSSQ DQ13 VDDQ DQ14 VDD
MVEXT VSS DQ34 VSSQ DQ33 VDDQ DM1 VDDQ DQ15 VSSQ DQ16 VSS VEXT
NVSS TCK VDD TDO VDDQ DQ35 VREF DQ17 VDDQ TDI VDD TMS VSS
Notes: 1. F2 is the Location of the extra CS (CS1) needed to support the x18 DDP device. G1 & G13
are the locations of the additional address signals (A20 & A21 respectfully) needed to
support the 2Gb monolithic device. F2 is Internally connected so it can mirror the A5 ad-
dress signal when MF is asserted HIGH and has parasitic characteristics of an address pin.
G1 & G13 are just place holders for the future device.
2. NF ball for x36 configuration is internally connected and has parasitic characteristics of
an address (A19 for x18 configuration). Ball may be connected to VSSQ.
3. MF is assumed to be tied LOW for this ball assignment.
576Mb: x18, x36 RLDRAM 3
Ball Assignments and Descriptions
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Table 3: Ball Descriptions
Symbol Type Description
A[19:0] Input Address inputs: A[19:0] define the row and column addresses for READ and WRITE operations.
During a MODE REGISTER SET, the address inputs define the register settings along with BA[3:0].
They are sampled at the rising edge of CK.
BA[3:0] Input Bank address inputs: Select the internal bank to which a command is being applied.
CK/CK# Input Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on
the rising edge of CK.
CS# Input Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When
the command decoder is disabled, new commands are ignored, but internal operations contin-
ue.
DQ[35:0] I/O Data input: The DQ signals form the 36-bit data bus. During READ commands, the data is refer-
enced to both edges of QK. During WRITE commands, the data is sampled at both edges of DK.
DKx, DKx# Input Input data clock: DKx and DKx# are differential input data clocks. All input data is referenced
to both edges of DKx. For the x36 device, DQ[8:0] and DQ[26:18] are referenced to DK0 and
DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1 and DK1#. For the x18 device, DQ[8:0]
are referenced to DK0 and DK0#, and DQ[17:9] are referenced to DK1 and DK1#. DKx and DKx#
are free-running signals and must always be supplied to the device.
DM[1:0] Input Input data mask: DM is the input mask signal for WRITE data. Input data is masked when DM
is sampled HIGH. DM0 is used to mask the lower byte for the x18 device and DQ[8:0] and
DQ[26:18] for the x36 device. DM1 is used to mask the upper byte for the x18 device and
DQ[17:9] and DQ[35:27] for the x36 device. Tie DM[1:0] to VSS if not used.
TCK Input IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used.
TMS, TDI Input IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
WE#, REF# Input Command inputs: Sampled at the positive edge of CK, WE# and REF# (together with CS#) de-
fine the command to be executed.
RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. RESET# assertion and deassertion
are asynchronous. RESET# is a CMOS input defined with DC HIGH ≥ 0.8 x VDD and DC LOW ≤ 0.2 x
VDDQ.
ZQ Input External impedance: This signal is used to tune the device’s output impedance and ODT. RZQ
needs to be 240Ω, where RZQ is a resistor from this signal to ground.
QKx, QKx# Output Output data clocks: QK and QK# are opposite-polarity output data clocks. They are free-run-
ning signals and during READ commands are edge-aligned with the DQs. For the x36 device,
QK0, QK0# align with DQ[8:0]; QK1, QK1# align with DQ[17:9]; QK2, QK2# align with DQ[26:18];
QK3, QK3# align with DQ[35:27]. For the x18 device, QK0, QK0# align with DQ[8:0]; QK1, QK1#
align with DQ[17:9].
QVLDxOutput Data valid: The QVLD ball indicates that valid output data will be available on the subsequent
rising clock edge. There is a single QVLD ball for the x18 device and two, QVLD0 and QVLD1, for
the x36 device. QVLD0 aligns with DQ[17:0]; QVLD1 aligns with DQ[35:18].
MF Input Mirror function: The mirror function ball is a DC input used to create mirrored ballouts for sim-
ple dual-loaded clamshell mounting. If the ball is tied to VSS, the address and command balls are
in their true layout. If the ball is tied to VDDQ, they are in the complement location. MF must be
tied HIGH or LOW and cannot be left floating. MF is a CMOS input defined with DC HIGH ≥ 0.8 x
VDD and DC LOW ≤ 0.2 x VDDQ.
576Mb: x18, x36 RLDRAM 3
Ball Assignments and Descriptions
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Table 3: Ball Descriptions (Continued)
Symbol Type Description
TDO Output IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function
is not used.
VDD Supply Power supply: 1.35V nominal. See Table 7 (page 22) for range.
VDDQ Supply DQ power supply: 1.2V nominal. Isolated on the device for improved noise immunity. See Ta-
ble 7 (page 22) for range.
VEXT Supply Power supply: 2.5V nominal. See Table 7 (page 22) for range.
VREF Supply Input reference voltage: VDDQ/2 nominal. Provides a reference voltage for the input buffers.
VSS Supply Ground.
VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.
NC – No connect: These balls are not connected to the DRAM.
NF – No function: These balls are connected to the DRAM, but provide no functionality.
576Mb: x18, x36 RLDRAM 3
Ball Assignments and Descriptions
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Package Dimensions
Figure 5: 168-Ball FBGA
Seating plane
0.12 A
13
Ball A1 ID Ball A1 ID
A
0.325 MIN
1.1 ±0.1
12 CTR
13.5 ±0.1
1 TYP
12 CTR
13.5 ±0.1
168X Ø0.55
Dimensions apply
to solder balls post-
reflow on Ø0.40 NSMD
ball pads.
1 TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
12 11 10 9 8 7 6 5 4 3 2 1
Note: 1. All dimensions are in millimeters.
576Mb: x18, x36 RLDRAM 3
Package Dimensions
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Electrical Characteristics – IDD Specifications
Table 4: IDD Operating Conditions and Maximum Limits
Notes 1–6 apply to the entire table
Description Condition Symbol -093E -093 -107E -107 -125F -125E -125 Units Notes
Standby
current
tCK = idle; All banks idle; No inputs
toggling
ISB1 (VDD) x18 125 125 125 125 125 125 125 mA 7
ISB1 (VDD) x36 125 125 125 125 125 125 125
ISB1 (VEXT) 30303030303030
Clock active
standby cur-
rent
CS# = 1; No commands; Bank ad-
dress incremented and half address/
data change once every four clock
cycles
ISB2 (VDD) x18 870 870 815 815 725 725 725 mA
ISB2 (VDD) x36 895 895 835 835 740 740 740
ISB2 (VEXT) 30303030303030
Operational
current: BL2
BL = 2; Sequential bank access; Bank
transitions once every tRC; Half ad-
dress transitions once every tRC;
Read followed by write sequence;
Continuous data during WRITE com-
mands
IDD1 (VDD) x18 1175 1115 1100 1045 990 940 915 mA
IDD1 (VDD) x36 1185 1125 1110 1055 1000 950 925
IDD1 (VEXT) 35353535353535
Operational
current: BL4
BL = 4; Sequential bank access; Bank
transitions once every tRC; Half ad-
dress transitions once every tRC;
Read followed by write sequence;
Continuous data during WRITE com-
mands
IDD2 (VDD) x18 1205 1145 1130 1075 1020 970 945 mA
IDD2 (VDD) x36 1215 1155 1140 1080 1030 980 950
IDD2 (VEXT) 35353535353535
Operational
current: BL8
BL = 8; Sequential bank access; Bank
transitions once every tRC; Half ad-
dress transitions once every tRC;
Read followed by write sequence;
Continuous data during WRITE com-
mands
IDD3 (VDD) x18 1300 1220 1200 1130 1085 1030 1000 mA
IDD3 (VDD) x36 NA NA NA NA N/A NA NA
IDD3 (VEXT) 35353535353535
Burst refresh
current
Sixteen bank cyclic refresh using
Bank Address Control AREF proto-
col; Command bus remains in re-
fresh for all sixteen banks; DQs are
High-Z and at VDDQ/2; Addresses are
at VDDQ/2
IREF1 (VDD) x18 1550 1550 1400 1400 1230 1230 1230 mA
IREF1 (VDD) x36 1570 1570 1420 1420 1245 1245 1245
IREF1 (VEXT) 80807575707070
576Mb: x18, x36 RLDRAM 3
Electrical Characteristics – IDD Specifications
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Table 4: IDD Operating Conditions and Maximum Limits (Continued)
Notes 1–6 apply to the entire table
Description Condition Symbol -093E -093 -107E -107 -125F -125E -125 Units Notes
Distributed
refresh current
Single bank refresh using Bank Ad-
dress Control AREF protocol; Se-
quential bank access every 0.489μs;
DQs are High-Z and at VDDQ/2; Ad-
dresses are at VDDQ/2
IREF2 (VDD) x18 875 875 820 820 730 730 730 mA
IREF2 (VDD) x36 900 900 840 840 745 745 745
IREF2 (VEXT) 30303030303030
Multibank re-
fresh current:
4 bank refresh
Quad bank refresh using Multibank
AREF protocol; BL = 4; Cyclic bank
access; Subject to tSAW and tMMD
specifications; DQs are High-Z and
at VDDQ/2; Bank addresses are at
VDDQ/2
IMBREF4 (VDD) x18 2130 1925 2030 1810 1885 1885 1645 mA
IMBREF4 (VDD) x36 2155 1950 2050 1830 1900 1900 1660
IMBREF4 (VEXT) 130 130 115 115 105 105 105
Operating
burst write cur-
rent : BL2
BL = 2; Cyclic bank access; Half of
address bits change every clock cy-
cle; Continuous data; Measurement
is taken during continuous WRITE
IDD2W (VDD) x18 2110 2110 1910 1910 1665 1665 1665 mA
IDD2W (VDD) x36 2290 2290 2070 2070 1805 1805 1805
IDD2W (VEXT) 80807575707070
Operating
burst write cur-
rent : BL4
BL = 4; Cyclic bank access; Half of
address bits change every two clock
cycles; Continuous data; Measure-
ment is taken during continuous
WRITE
IDD4W (VDD) x18 1730 1730 1590 1590 1395 1395 1395 mA
IDD4W (VDD) x36 1815 1815 1665 1665 1460 1460 1460
IDD4W (VEXT) 55555555505050
Operating
burst write cur-
rent :BL8
BL = 8; Cyclic bank access; Half of
address bits change every four clock
cycles; Continuous data; Measure-
ment is taken during continuous
WRITE
IDD8W (VDD) x18 1475 1475 1335 1335 1190 1190 1190 mA
IDD8W (VDD) x36 NA NA NA NA NA NA NA
IDD8W (VEXT) 45454040404040
Multibank
write current:
Dual bank
write
BL = 4; Cyclic bank access using Dual
Bank WRITE; Half of address bits
change every two clock cycles; Con-
tinuous data; Measurement is taken
during continuous WRITE
IDBWR (VDD) x18 2305 2305 2170 2170 1885 1885 1885 mA
IDBWR (VDD) x36 2400 2400 2250 2250 1960 1960 1960
IDBWR (VEXT) 80807575707070
Multibank
write current:
Quad bank
write
BL = 4; Cyclic bank access using
Quad Bank WRITE; Half of address
bits change every two clock cycles;
Continuous data; Measurement is
taken during continuous WRITE;
Subject to tSAW specification
IQBWR (VDD) x18 2965 2965 2890 2890 2525 2525 2525 mA
IQBWR (VDD) x36 3195 3195 3000 3000 2615 2615 2615
IQBWR (VEXT) 130 130 115 115 100 100 100
576Mb: x18, x36 RLDRAM 3
Electrical Characteristics – IDD Specifications
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Table 4: IDD Operating Conditions and Maximum Limits (Continued)
Notes 1–6 apply to the entire table
Description Condition Symbol -093E -093 -107E -107 -125F -125E -125 Units Notes
Operating
burst read cur-
rent
example
BL = 2; Cyclic bank access; Half of
address bits change every clock cy-
cle; Continuous data; Measurement
is taken during continuous READ
IDD2R (VDD) x18 2250 2250 2045 2045 1785 1785 1785 mA
IDD2R (VDD) x36 2395 2395 2180 2180 1895 1895 1895
IDD2R (VEXT) 80807575707070
Operating
burst read cur-
rent
example
BL = 4; Cyclic bank access; Half of
address bits change every two clock
cycles; Continuous data; Measure-
ment is taken during continuous
READ
IDD4R (VDD) x18 1740 1740 1595 1595 1400 1400 1400 mA
IDD4R (VDD) x36 1835 1835 1685 1685 1475 1475 1475
IDD4R (VEXT) 55555555505050
Operating
burst read cur-
rent
example
BL = 8; Cyclic bank access; Half of
address bits change every four clock
cycles; Continuous data; Measure-
ment is taken during continuous
READ
IDD8R (VDD) x18 1450 1450 1315 1315 1175 1175 1175 mA
IDD8R (VDD) x36 NA NA NA NA NA NA NA
IDD8R (VEXT) 45454040404040
576Mb: x18, x36 RLDRAM 3
Electrical Characteristics – IDD Specifications
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Notes: 1. IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +95°C;
+1.28V ≤ VDD ≤ +1.42V,+1.14V ≤ VDDQ ≤ +1.26V,+2.38V ≤ VEXT ≤ +2.63V,VREF = VDDQ/2.
2. IDD mesurements use tCK (MIN), tRC (MIN), and minimum data latency (RL and WL).
3. Input slew rate is 1V/ns for single ended signals and 2V/ns for differential signals.
4. Definitions for IDD conditions:
• LOW is defined as VIN ≤ VIL(AC)MAX.
• HIGH is defined as VIN ≥ VIH(AC)MIN.
• Continuous data is defined as half the DQ signals changing between HIGH and LOW
every half clock cycle (twice per clock).
• Continuous address is defined as half the address signals changing between HIGH and
LOW every clock cycle (once per clock).
• Sequential bank access is defined as the bank address incrementing by one every tRC.
• Cyclic bank access is defined as the bank address incrementing by one for each com-
mand access. For BL = 2 this is every clock, for BL = 4 this is every other clock, and for
BL = 8 this is every fourth clock.
5. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never tran-
sitions more than once per clock cycle.
6. IDD parameters are specified with ODT disabled.
7. Upon exiting standby current conditions, at least one NOP command must be issued
with stable clock prior to issuing any other valid command.
576Mb: x18, x36 RLDRAM 3
Electrical Characteristics – IDD Specifications
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Electrical Specifications – Absolute Ratings and I/O Capacitance
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions outside those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may ad-
versely affect reliability.
Table 5: Absolute Maximum Ratings
Symbol Parameter Min Max Units
VDD VDD supply voltage relative to VSS –0.4 1.975 V
VDDQ Voltage on VDDQ supply relative to VSS –0.4 1.66 V
VIN,VOUT Voltage on any ball relative to VSS –0.4 1.66 V
VEXT Voltage on VEXT supply relative to VSS –0.4 2.8 V
Input/Output Capacitance
Table 6: Input/Output Capacitance
Notes 1 and 2 apply to entire table
Capacitance Parameters Symbol
RL3-2133 RL3-1866 RL3-1600
Units NotesMin Max Min Max Min Max
CK/CK# CCK 1.3 2.1 1.3 2.1 1.3 2.2 pF
ΔC: CK to CK# CDCK 0 0.15 0 0.15 0 0.15 pF
Single-ended I/O: DQ, DM CIO 1.9 2.9 1.9 3.0 2.0 3.1 pF 3
Input strobe: DK/DK# CIO 1.9 2.9 1.9 3.0 2.0 3.1 pF
Output strobe: QK/QK#, QVLD CIO 1.9 2.9 1.9 3.0 2.0 3.1 pF
ΔC: DK to DK# CDDK 0 0.15 0 0.15 0 0.15 pF
ΔC: QK to QK# CDQK 0 0.15 0 0.15 0 0.15 pF
ΔC: DQ to QK or DQ to DK CDIO –0.5 0.3 –0.5 0.3 –0.5 0.3 pF 4
Inputs (CMD, ADDR) CI1.25 2.25 1.25 2.25 1.25 2.25 pF 5
ΔC: CMD_ADDR to CK CDI_CMD_ADDR –0.5 0.3 –0.5 0.3 –0.4 0.4 pF 6
JTAG balls CJTAG 1.5 4.5 1.5 4.5 1.5 4.5 pF 7
RESET#, MF balls CI– 3.0 – 3.0 – 3.0 pF
Notes: 1. +1.28V ≤ VDD ≤ +1.42V, +1.14V ≤ VDDQ ≤ 1.26V, +2.38V ≤ VEXT ≤ +2.63V, VREF = VSS, f = 100
MHz, TC = 25°C, VOUT(DC) = 0.5 × VDDQ, VOUT (peak-to-peak) = 0.1V.
2. Capacitance is not tested on ZQ ball.
3. DM input is grouped with the I/O balls, because they are matched in loading.
4. CDIO = CIO(DQ) - 0.5 × (CIO [QK] + CIO [QK#]).
5. Includes CS#, REF#, WE#, A[19:0], and BA[3:0].
6. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 × (CCK [CK] + CCK [CK#]).
7. JTAG balls are tested at 50 MHz.
576Mb: x18, x36 RLDRAM 3
Electrical Specifications – Absolute Ratings and I/O Capaci-
tance
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AC and DC Operating Conditions
Table 7: DC Electrical Characteristics and Operating Conditions
Note 1 applies to the entire table; Unless otherwise noted: 0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V
Description Symbol Min Max Units Notes
Supply voltage VEXT 2.38 2.63 V
Supply voltage VDD 1.28 1.42 V
Isolated output buffer supply VDDQ 1.14 1.26 V
Reference voltage VREF 0.49 × VDDQ 0.51 × VDDQ V 2, 3
Input HIGH (logic 1) voltage VIH(DC) VREF + 0.10 VDDQ V
Input LOW (logic 0) voltage VIL(DC) VSS VREF - 0.10 V
Input leakage current: Any input 0V ≤ VIN ≤ VDD, VREF ball
0V ≤ VIN ≤ 1.1V (All other balls not under test = 0V)
ILI –2 2 μA
Reference voltage current (All other balls not under test =
0V)
IREF –5 5 μA
Notes: 1. All voltages referenced to VSS (GND).
2. The nominal value of VREF is expected to be 0.5 × VDDQ of the transmitting device. VREF is
expected to track variations in VDDQ.
3. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2% of the DC value.
DC values are determined to be less than 20 MHz. Peak-to-peak AC noise on VREF should
not exceed ±2% of VREF(DC). Thus, from VDDQ/2, VREF is allowed ±2% VDDQ/2 for DC error
and an additional ±2% VDDQ/2 for AC noise. The measurement is to be taken at the
nearest VREF bypass capacitor.
Table 8: Input AC Logic Levels
Notes 1-3 apply to entire table; Unless otherwise noted: 0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V
Description Symbol Min Max Units
Input HIGH (logic 1) voltage VIH(AC) VREF + 0.15 – V
Input LOW (logic 0) voltage VIL(AC) –V
REF - 0.15 V
Notes: 1. All voltages referenced to VSS (GND).
2. The receiver will effectively switch as a result of the signal crossing the AC input level,
and will remain in that state as long as the signal does not ring back above/below the
DC input LOW/HIGH level.
3. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is
900mV (peak-to-peak).
576Mb: x18, x36 RLDRAM 3
AC and DC Operating Conditions
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Figure 6: Single-Ended Input Signal
0.450V
0.0V
0.50V
0.576V
0.588V
0.60V
0.612V
0.624V
0.70V
0.750V
VIL(AC)
VIL(DC)
VREF - AC noise
VREF - DC error
VREF + DC error
VREF + AC noise
VIH(DC)
VIH(AC)
1.20V
1.60V
–0.40V
VDDQ
VDDQ + 0.4V narrow
pulse width
VSS - 0.4V narrow
pulse width
VSS
0.45V
0.50V
0.576V
0.588V
0.60V
0.612V
0.624V
0.70V
0.750V
Minimum VIL and VIH levels
VIH(DC)
VIH(AC)
VIL(AC)
VIL(DC)
VIL and VIH levels with ringback
576Mb: x18, x36 RLDRAM 3
AC and DC Operating Conditions
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AC Overshoot/Undershoot Specifications
Table 9: Control and Address Balls
Parameter RL3-2133 RL3-1866 RL3-1600
Maximum peak amplitude allowed for overshoot area 0.4V 0.4V 0.4V
Maximum peak amplitude allowed for undershoot area 0.4V 0.4V 0.4V
Maximum overshoot area above VDDQ 0.25 Vns 0.28 Vns 0.33 Vns
Maximum undershoot area below VSS/VSSQ 0.25 Vns 0.28 Vns 0.33 Vns
Table 10: Clock, Data, Strobe, and Mask Balls
Parameter RL3-2133 RL3-1866 RL3-1600
Maximum peak amplitude allowed for overshoot area 0.4V 0.4V 0.4V
Maximum peak amplitude allowed for undershoot area 0.4V 0.4V 0.4V
Maximum overshoot area above VDDQ 0.10 Vns 0.11 Vns 0.13 Vns
Maximum undershoot area below VSS/VSSQ 0.10 Vns 0.11 Vns 0.13 Vns
Figure 7: Overshoot
Maximum amplitude
Overshoot area
VDDQ
Time (ns)
Volts (V)
Figure 8: Undershoot
Maximum amplitude
Undershoot area
VSS/VSSQ
Time (ns)
Volts (V)
576Mb: x18, x36 RLDRAM 3
AC and DC Operating Conditions
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Table 11: Differential Input Operating Conditions (CK, CK# and DKx, DKx#)
Notes 1 and 2 apply to entire table
Parameter/Condition Symbol Min Max Units Notes
Differential input voltage logic HIGH – slew VIH,diff_slew +200 n/a mV 3
Differential input voltage logic LOW – slew VIL,diff_slew n/a -200 mV 3
Differential input voltage logic HIGH VIH,diff(AC) 2 × (VIH(AC) - VREF)V
DDQ mV 4
Differential input voltage logic LOW VIL,diff(AC) VSSQ 2 × (VIL(AC) - VREF )mV 5
Differential input crossing voltage relative to VDD/2 VIX VREF(DC) - 150 VREF(DC) + 150 mV 6
Single-ended HIGH level VSEH VIH(AC) VDDQ mV 4
Single-ended LOW level VSEL VSSQ VIL(AC) mV 5
Notes: 1. CK/CK# and DKx/DKx# are referenced to VDDQ and VSSQ.
2. Differential input slew rate = 2 V/ns.
3. Defines slew rate reference points, relative to input crossing voltages.
4. Maximum limit is relative to single-ended signals; overshoot specifications are applica-
ble.
5. Minimum limit is relative to single-ended signals; undershoot specifications are applica-
ble.
6. The typical value of VIX is expected to be about 0.5 × VDDQ of the transmitting device
and VIX is expected to track variations in VDDQ. VIX indicates the voltage at which differ-
ential input signals must cross.
Figure 9: VIX for Differential Signals
CK, DKx
VDDQ/2
VDDQ/2
VIX
VIX
CK#, DKx#
VDDQ
CK, DKx
VDDQ
VSSQ
CK#, DKx#
VSSQ
X
X
X
X
VIX
VIX
576Mb: x18, x36 RLDRAM 3
AC and DC Operating Conditions
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Figure 10: Single-Ended Requirements for Differential Signals
VSS
VDDQ
VSEL,max
VSEH,min
VSEH
VSEL
VDDQ/2
CK or DKx
Figure 11: Definition of Differential AC Swing and tDVAC
VIH,diff(AC)min
VIH,diff_slew,min
0.0
VIL,diff_slew,max
tDVAC
half cycle tDVAC
CK - CK#
DKx - DKx#
VIL,diff(AC)max
576Mb: x18, x36 RLDRAM 3
AC and DC Operating Conditions
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Table 12: Allowed Time Before Ringback (tDVAC) for CK, CK#, DKx, and DKx#
Slew Rate (V/ns) MIN tDVAC (ps) at |VIH/VIL,diff(AC)|
>4.0 175
4.0 170
3.0 167
2.0 163
1.9 162
1.6 161
1.4 159
1.2 155
1.0 150
<1.0 150
Slew Rate Definitions for Single-Ended Input Signals
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate be-
tween the last crossing of VREF and the first crossing of VIH(AC)min. Setup (tIS and tDS)
nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VREF and the first crossing of VIL(AC)max.
Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate be-
tween the last crossing of VIL(DC)max and the first crossing of VREF. Hold (tIH and tDH)
nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VIH(DC)min and the first crossing of VREF (see Figure 12 (page 28)).
Table 13: Single-Ended Input Slew Rate Definition
Input Slew Rates
(Linear Signals) Measured
CalculationInput Edge From To
Setup Rising VREF VIH(AC)min [VIH(AC)min - VREF@ΔTRS
Falling VREF VIL(AC)max [VREF - VIL(AC)max@ΔTFS
Hold Rising VIL(DC)max VREF [VREF - VIL(DC)max@ΔTRH
Falling VIH(DC)min VREF [VIH(DC)min - VREF@ΔTFH
576Mb: x18, x36 RLDRAM 3
AC and DC Operating Conditions
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Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals
ǻTRS
ǻTFS
ǻTRH
ǻTFH
VREF
VREF
VIH(AC)min
VIL(AC)max
VIL(AC)max
VIH(AC)min
VIH(DC)min
VIL(DC)max
VIL(DC)max
VIH(DC)min
Setup
Hold
Single-ended input voltage (DQ, CMD, ADDR)
Single-ended input voltage (DQ, CMD, ADDR)
576Mb: x18, x36 RLDRAM 3
AC and DC Operating Conditions
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Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DKx, DKx#) are defined and meas-
ured as shown in the following two tables. The nominal slew rate for a rising signal is
defined as the slew rate between VIL,diff,max and VIH,diff,min. The nominal slew rate for a
falling signal is defined as the slew rate between VIH,diff,min and VIL,diff,max.
Table 14: Differential Input Slew Rate Definition
Differential Input
Slew Rates
(Linear Signals) Measured
CalculationInput Edge From To
CK and DK
reference
Rising VIL,diff_slew,max VIH,diff_slew,min [VIH,diff_slew,min - VIL,diff_slew,max@ΔTRdiff
Falling VIH,diff_slew,min VIL,diff_slew,max [VIH,diff_slew,min - VIL,diff_slew,max@ΔTFdiff
Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx#
ǻTRdiff
ǻTFdiff
VIH,diff_slew,min
VIL,diff_slew,max
0
Differential input voltage (CK, CK#; DKx, DKx#)
576Mb: x18, x36 RLDRAM 3
AC and DC Operating Conditions
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ODT Characteristics
ODT effective resistance, RTT, is defined by MR1[4:2]. ODT is applied to the DQ, DM,
and DKx, DKx# balls. The individual pull-up and pull-down resistors (RTTPU and RTTPD)
are defined as follows:
RTTPU =(VDDQ - VOUT) / |IOUT|, under the condition that RTTPD is turned off
RTTPD = (VOUT) / |IOUT|, under the condition that RTTPU is turned off
Figure 14: ODT Levels and I-V Characteristics
RTTPU
RTTPD
ODT
Chip in termination mode
VDDQ
DQ
VSSQ
IOUT = IPD - IPU
IPU
IPD
IOUT
VOUT
To
other
circuitry
such as
RCV, . . .
Table 15: ODT DC Electrical Characteristics
Parameter/Condition Symbol Min Nom Max Units Notes
RTT effective impedance from VIL(AC) to VIH(AC) RTT_EFF See Table 16 (page 31). 1, 2
Deviation of VM with respect to VDDQ/2 ΔVm -5 - +5 % 3
Notes: 1. Tolerance limits are applicable after proper ZQ calibration has been performed at a sta-
ble temperature and voltage. Refer to ODT Sensitivity (page 32) if either the tempera-
ture or voltage changes after calibration.
2. Measurement definition for RTT: Apply VIH(AC) to ball under test and measure current
I[VIH(AC)], then apply VIL(AC) to ball under test and measure current I[VIL(AC)]:
VIH(AC) - VIL(AC)
|I[VIH(AC)] - I[VIL(AC)]|
RTT
3. Measure voltage (VM) at the tested ball with no load:
2 × VM
VDDQ
ǻVM - 1 × 100
ODT Resistors
The on-die termination resistance is selected by MR1[4:2]. The following table provides
an overview of the ODT DC electrical characteristics. The values provided are not speci-
576Mb: x18, x36 RLDRAM 3
ODT Characteristics
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fication requirements; however, they can be used as design guidelines to indicate what
RTT is targeted to provide:
•R
TT Ω is made up of RTT120(PD240) and RTT120(PU240).
•R
TT Ω is made up of RTT60(PD120) and RTT60(PU120).
•R
TT Ω is made up of RTT40(PD80) and RTT40(PU80).
Table 16: RTT Effective Impedances
RTT Resistor VOUT Min Nom Max Units
ΩRTT120(PD240) 0.2 x VDDQ 0.6 1.0 1.1 RZQ/1
0.5 x VDDQ 0.9 1.0 1.1 RZQ/1
0.8 x VDDQ 0.9 1.0 1.4 RZQ/1
RTT120(PU240) 0.2 x VDDQ 0.9 1.0 1.4 RZQ/1
0.5 x VDDQ 0.9 1.0 1.1 RZQ/1
0.8 x VDDQ 0.6 1.0 1.1 RZQ/1
ΩVIL(AC) to
VIH(AC)
0.9 1.0 1.6 RZQ/2
ΩRTT60(PD120) 0.2 x VDDQ 0.6 1.0 1.1 RZQ/2
0.5 x VDDQ 0.9 1.0 1.1 RZQ/2
0.8 x VDDQ 0.9 1.0 1.4 RZQ/2
RTT60(PU120) 0.2 x VDDQ 0.9 1.0 1.4 RZQ/2
0.5 x VDDQ 0.9 1.0 1.1 RZQ/2
0.8 x VDDQ 0.6 1.0 1.1 RZQ/2
ΩVIL(AC) to
VIH(AC)
0.9 1.0 1.6 RZQ/4
ΩRTT40(PD80) 0.2 x VDDQ 0.6 1.0 1.1 RZQ/3
0.5 x VDDQ 0.9 1.0 1.1 RZQ/3
0.8 x VDDQ 0.9 1.0 1.4 RZQ/3
RTT40(PU80) 0.2 x VDDQ 0.9 1.0 1.4 RZQ/3
0.5 x VDDQ 0.9 1.0 1.1 RZQ/3
0.8 x VDDQ 0.6 1.0 1.1 RZQ/3
ΩVIL(AC) to
VIH(AC)
0.9 1.0 1.6 RZQ/6
576Mb: x18, x36 RLDRAM 3
ODT Characteristics
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ODT Sensitivity
If either temperature or voltage changes after I/O calibration, then the tolerance limits
listed in Table 15 (page 30) and Table 16 (page 31) can be expected to widen according
to Table 17 (page 32) and Table 18 (page 32).
Table 17: ODT Sensitivity Definition
Symbol Min Max Units
RTT 0.9 - dRTTdT × |DT| - dRTTdV × |DV| 1.6 + dRTTdT × |DT| + dRTTdV × |
DV|
RZQ/(2,4,6)
Note: 1. DT = T - T(@ calibration), DV = VDDQ - VDDQ(@ calibration) or VDD - VDD(@ calibration).
Table 18: ODT Temperature and Voltage Sensitivity
Change Min Max Units
dRTTdT 0 1.5 %/°C
dRTTdV 0 0.15 %/mV
576Mb: x18, x36 RLDRAM 3
ODT Characteristics
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Output Driver Impedance
The output driver impedance is selected by MR1[1:0] during initialization. The selected
value is able to maintain the tight tolerances specified if proper ZQ calibration is per-
formed.
Output specifications refer to the default output driver unless specifically stated other-
wise. A functional representation of the output buffer is shown below. The output driver
impedance RON is defined by the value of the external reference resistor RZQ as follows:
•R
ON,x = RZQ/y (with RZQ = 240Ω rx Ω or 60Ω with y = 6 or 4, respectively)
The individual pull-up and pull-down resistors (RON(PU) and RON(PD)) are defined as fol-
lows:
•R
ON(PU) = (VDDQ - VOUT)/|IOUT|, when RON(PD) is turned off
•R
ON(PD) = (VOUT)/|IOUT|, when RON(PU) is turned off
Figure 15: Output Driver
RON(PU)
RON(PD)
Chip in drive mode
Output Driver
VDDQ
DQ
VSSQ
IPU
IPD
IOUT
VOUT
To
other
circuitry
such as
RCV, . . .
576Mb: x18, x36 RLDRAM 3
Output Driver Impedance
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Table 19: Driver Pull-Up and Pull-Down Impedance Calculations
RON Min Nom Max Units
RZQ/6 = (240Ω r 39.6 40 40.4 Ω
RZQ/4 = (240Ω r 59.4 60 60.6 Ω
Driver VOUT Min Nom Max Units
Ω pull-down 0.2 × VDDQ 24 40 44 Ω
0.5 × VDDQ 36 40 44 Ω
0.8 × VDDQ 36 40 56 Ω
Ω pull-up 0.2 × VDDQ 36 40 56 Ω
0.5 × VDDQ 36 40 44 Ω
0.8 × VDDQ 24 40 44 Ω
Ω pull-down 0.2 × VDDQ 36 60 66 Ω
0.5 × VDDQ 54 60 66 Ω
0.8 × VDDQ 54 60 84 Ω
Ω pull-up 0.2 × VDDQ 54 60 84 Ω
0.5 × VDDQ 54 60 66 Ω
0.8 × VDDQ 36 60 66 Ω
576Mb: x18, x36 RLDRAM 3
Output Driver Impedance
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Output Driver Sensitivity
If either the temperature or the voltage changes after ZQ calibration, then the tolerance
limits listed in Table 19 (page 34) can be expected to widen according to Table 20
(page 35) and Table 21 (page 35).
Table 20: Output Driver Sensitivity Definition
Symbol Min Max Units
RON(PD) @ 0.2 × VDDQ 0.6 - dRONdTH × DT - dRONdVH × DV 1.1 + dRONdTH × DT + dRONdVH × DV RZQ/(6, 4)
RON(PD) @ 0.5 × VDDQ 0.9 - dRONdTM × DT - dRONdVM × DV 1.1 + dRONdTM × DT + dRONdVM × DV RZQ/(6, 4)
RON(PD) @ 0.8 × VDDQ 0.9 - dRONdTL × DT - dRONdVL × DV 1.4 + dRONdTL × DT + dRONdVL × D RZQ/(6, 4)
RON(PU) @ 0.2 × VDDQ 0.9 - dRONdTH × DT - dRONdVH × DV 1.4 + dRONdTH × DT + dRONdVH × DV RZQ/(6, 4)
RON(PU) @ 0.5 × VDDQ 0.9 - dRONdTM × DT - dRONdVM × DV 1.1 + dRONdTM × DT + dRONdVM × DV RZQ/(6, 4)
RON(PU) @ 0.8 × VDDQ 0.6 - dRONdTL × DT - dRONdVL × DV 1.1 + dRONdTL × DT + dRONdVL × DV RZQ/(6, 4)
Note: 1. DT = T - T(@ calibration), DV = VDDQ - VDDQ(@ calibration) or VDD - VDD(@ calibration).
Table 21: Output Driver Voltage and Temperature Sensitivity
Change Min Max Unit
dRONdTM 0 1.5 %/°C
dRONdVM 0 0.15 %/mV
dRONdTL 0 1.5 %/°C
dRONdVL 0 0.15 %/mV
dRONdTH 0 1.5 %/°C
dRONdVH 0 0.15 %/mV
576Mb: x18, x36 RLDRAM 3
Output Driver Impedance
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Output Characteristics and Operating Conditions
Table 22: Single-Ended Output Driver Characteristics
Note 1 and 2 apply to entire table
Parameter/Condition Symbol Min Max Units Notes
Output leakage current; DQ are disabled; Any output ball
0V ≤ VOUT ≤ VDDQ; ODT is disabled; All other balls not under
test = 0V
IOZ –5 5 μA
Output slew rate: Single-ended; For rising and falling edges,
measures between VOL(AC) = VREF - 0.1 × VDDQ and VOH(AC) =
VREF + 0.1 × VDDQ
SRQSE 2.5 6 V/ns 4, 5
Single-ended DC high-level output voltage VOH(DC) 0.8 × VDDQ V6
Single-ended DC mid-point level output voltage VOM(DC) 0.5 × VDDQ V6
Single-ended DC low-level output voltage VOL(DC) 0.2 × VDDQ V6
Single-ended AC high-level output voltage VOH(AC) VTT + 0.1 × VDDQ V 7, 8, 9
Single-ended AC low-level output voltage VOL(AC) VTT - 0.1 × VDDQ V 7, 8, 9
Impedance delta between pull-up and pull-down for DQ
and QVLD
MMPUPD –10 10 % 3
Test load for AC timing and output slew rates Output to VTT (VDDQ/2) via 25Ω resistor 9
Notes: 1. All voltages are referenced to VSS.
2. RZQ is 240Ω (±1%) and is applicable after proper ZQ calibration has been performed at
a stable temperature and voltage.
3. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Meas-
ure both RON(PU) and RON(PD) at 0.5 × VDDQ:
RonPU - RonPD
RonNOM
MMPUPD x 100
4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from
HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are
either all static or switching the opposite direction. For all other DQ signal switching
combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns.
5. See Table 24 (page 40) for output slew rate.
6. See the Driver Pull-Up and Pull-Down Impedance Calculations table for IV curve linearity.
Do not use AC test load.
7. VTT = VDDQ/2
8. See Figure 16 (page 38) for an example of a single-ended output signal.
9. See Figure 18 (page 39) for the test load configuration.
576Mb: x18, x36 RLDRAM 3
Output Characteristics and Operating Conditions
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Table 23: Differential Output Driver Characteristics
Notes 1 and 2 apply to entire table
Parameter/Condition Symbol Min Max Units Notes
Output leakage current; DQ are disabled; Any output
ball 0V ≤ VOUT ≤ VDDQ; ODT is disabled; All other balls not
under test = 0V
IOZ –5 5 μA
Output slew rate: Differential; For rising and falling
edges, measures between VOL,diff(AC) = –0.2 × VDDQ and
VOH,diff(AC) = +0.2 × VDDQ
SRQdiff 5 12 V/ns 5
Output differential cross-point voltage VOX(AC) VREF - 150 VREF + 150 mV 6
Differential high-level output voltage VOH,diff(AC) +0.2 × VDDQ V6
Differential low-level output voltage VOL,diff(AC) –0.2 × VDDQ V6
Delta resistance between pull-up and pull-down for
QK/QK#
MMPUPD –10 10 % 3
Test load for AC timing and output slew rates Output to VTT (VDDQ/2) via 25Ω resistor 4
Notes: 1. All voltages are referenced to VSS.
2. RZQ is 240Ω (±1%) and is applicable after proper ZQ calibration has been performed at
a stable temperature and voltage.
3. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Meas-
ure both RON(PU) and RON(PD) at 0.5 x VDDQ:
RonPU - RonPD
RonNOM
MMPUPD x 100
4. See Figure 18 (page 39) for the test load configuration.
5. See Table 25 (page 41) for the output slew rate.
6. See Figure 17 (page 39) for an example of a differential output signal.
576Mb: x18, x36 RLDRAM 3
Output Characteristics and Operating Conditions
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Figure 16: DQ Output Signal
VOH(AC)
MIN output
MAX output
VOL(AC)
576Mb: x18, x36 RLDRAM 3
Output Characteristics and Operating Conditions
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Figure 17: Differential Output Signal
VOH,diff
MIN output
MAX output
VOL,diff
VOX(AC)max
VOX(AC)min
X
X
X
X
Reference Output Load
The following figure represents the effective reference load of 25Ω used in defining the
relevant device AC timing parameters as well as the output slew rate measurements. It is
not intended to be a precise representation of a particular system environment or a de-
piction of the actual load presented by a production tester. System designers should use
IBIS or other simulation tools to correlate the timing reference load to a system envi-
ronment.
Figure 18: Reference Output Load for AC Timing and Output Slew Rate
Timing reference point
DQ
QKx
QKx#
QVLD
DUT
V
REF
V
TT
= V
DDQ
/2
V
DDQ
/2
ZQ
RZQ = 240ȍ
V
SS
R
TT
= 25ȍ
576Mb: x18, x36 RLDRAM 3
Output Characteristics and Operating Conditions
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Slew Rate Definitions for Single-Ended Output Signals
The single-ended output driver is summarized in the following table. With the reference
load for timing measurements, the output slew rate for falling and rising edges is de-
fined and measured between VOL(AC) and VOH(AC) for single-ended signals.
Table 24: Single-Ended Output Slew Rate Definition
Single-Ended Output Slew Rates (Linear Signals) Measured
CalculationOutput Edge From To
DQ and QVLD Rising VOL(AC) VOH(AC) VOH(AC) - VOL(AC)
ǻTRSE
Falling VOH(AC) VOL(AC) VOH(AC) - VOL(AC)
ǻTFSE
Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals
ǻTRSE
ǻTFSE
VOH(AC)
VOL(AC)
VTT
576Mb: x18, x36 RLDRAM 3
Slew Rate Definitions for Single-Ended Output Signals
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Slew Rate Definitions for Differential Output Signals
The differential output driver is summarized in the following table. With the reference
load for timing measurements, the output slew rate for falling and rising edges is de-
fined and measured between VOL(AC) and VOH(AC) for differential signals.
Table 25: Differential Output Slew Rate Definition
Differential Output Slew Rates (Linear Sig-
nals) Measured
CalculationOutput Edge From To
QKx, QKx# Rising VOL,diff(AC) VOH,diff(AC) VOH,diff(AC)max - VOL,diff(AC)
ǻTRdiff
Falling VOH,diff(AC) VOL,diff(AC) VOH,diff(AC) - VOL,diff(AC)
ǻTFdiff
Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx#
ǻTRdiff
ǻTFdiff
VOH,diff(AC)
VOL,diff(AC)
0
576Mb: x18, x36 RLDRAM 3
Slew Rate Definitions for Differential Output Signals
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Speed Bin Tables
Table 26: RL3 2133/1866 Speed Bins
The MIN tCK value for a given RL/WL parameter must be used to determine the tRC mode register setting.
Parameter Symbol
-093E -093 -107E -107
UnitsMin Max Min Max Min Max Min Max
Clock Timing
RL = 3 ; WL = 4 tCK (avg) 5 5 5 5 Reserved Reserved ns
RL = 4 ; WL = 5 tCK (avg) 4 5 4 5 4 5 4 5 ns
RL = 5 ; WL = 6 tCK (avg) 3 4.3 3 4.3 3.5 4.3 4 4.3 ns
RL = 6 ; WL = 7 tCK (avg) 2.5 3.5 2.5 4 3 3.5 3 4.3 ns
RL = 7 ; WL = 8 tCK (avg) 2.5 3 2.5 3 2.5 3 2.5 3 ns
RL = 8 ; WL = 9 tCK (avg) 1.875 2.5 1.875 3 2 2.5 2 3 ns
RL = 9 ; WL = 10 tCK (avg) 1.875 2 1.875 2 1.875 2 1.875 2 ns
RL = 10 ; WL = 11 tCK (avg) 1.5 2 1.5 2 1.875 2 1.875 2 ns
RL = 11 ; WL = 12 tCK (avg) 1.5 1.875 1.5 2 1.5 1.875 1.5 2 ns
RL = 12 ; WL = 13 tCK (avg) 1.25 1.5 1.25 1.875 1.5 1.66 1.5 1.875 ns
RL = 13 ; WL = 14 tCK (avg) 1.25 1.5 1.25 1.5 1.25 1.5 1.25 1.5 ns
RL = 14 ; WL = 15 tCK (avg) 1.07 1.25 1.07 1.5 1.25 1.33 1.25 1.5 ns
RL = 15 ; WL = 16 tCK (avg) 1.0 1.25 1.0 1.25 1.07 1.33 1.07 1.25 ns
RL = 16 ; WL = 17 tCK (avg) 0.9375 1.25 0.9375 1.25 Reserved Reserved ns
Row Cycle Timing
Row cycle time tRC 8 – 10 – 8 – 10 – ns
576Mb: x18, x36 RLDRAM 3
Speed Bin Tables
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Table 27: RL3 1600 Speed Bins
The MIN tCK value for a given RL/WL parameter must be used to determine the tRC mode register setting.
Parameter Symbol
-125F 125E -125
UnitsMin Max Min Max Min Max
Clock Timing
RL = 3 ; WL = 4 tCK (avg) Reserved Reserved Reserved ns
RL = 4 ; WL = 5 tCK (avg) Reserved 4555ns
RL = 5 ; WL = 6 tCK (avg) Reserved 4 4.3 4 5 ns
RL = 6 ; WL = 7 tCK (avg) Reserved 3 4.3 3.5 4.3 ns
RL = 7 ; WL = 8 tCK (avg) Reserved 2.5 3 3 3.5 ns
RL = 8 ; WL = 9 tCK (avg) Reserved 2 3 2.5 3 ns
RL = 9 ; WL = 10 tCK (avg) Reserved 1.875 2 2.33 2.66 ns
RL = 10 ; WL = 11 tCK (avg) Reserved 1.875 2 2 2.33 ns
RL = 11 ; WL = 12 tCK (avg) Reserved 1.5 2 1.875 2.33 ns
RL = 12 ; WL = 13 tCK (avg) 1.33 1.66 1.5 1.875 1.875 2 ns
RL = 13 ; WL = 14 tCK (avg) 1.25 1.5 1.25 1.5 1.5 1.875 ns
RL = 14 ; WL = 15 tCK (avg) Reserved Reserved 1.4 1.66 ns
RL = 15 ; WL = 16 tCK (avg) Reserved Reserved 1.33 1.66 ns
RL = 16 ; WL = 17 tCK (avg) Reserved Reserved 1.25 1.33 ns
Row Cycle Timing
Row cycle time tRC 8 –10–12–ns
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AC Electrical Characteristics
Table 28: AC Electrical Characteristics
Notes 1–7 apply to entire table
Parameter Symbol
RL3–2133 RL3–1866 RL3–1600
Units NotesMin Max Min Max Min Max
Clock Timing
Clock period average:
DLL disable mode
tCK(DLL_DIS
) 8 488 8 488 8 488 ns 8
Clock period average: DLL en-
able mode
tCK(avg) See tCK values in the RL3 Speed Bins table. ns 9, 10
High pulse width average tCH(avg) 0.47 0.53 0.47 0.53 0.47 0.53 CK 11
Low pulse width average tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 CK 11
Clock
period
jitter
DLL locked tJIT(per) –50 50 –60 60 –70 70 ps 12
DLL locking tJIT(per),lck –40 40 –50 50 –60 60 ps 12
Clock absolute period tCK(abs) MIN = tCK(avg),min + tJIT(per),min; MAX =
tCK(avg),max + tJIT(per),max
ps
Clock absolute high pulse
width
tCH(abs) 0.43 – 0.43 – 0.43 – tCK(avg) 13
Clock absolute low pulse
width
tCL(abs) 0.43 – 0.43 – 0.43 – tCK(avg) 14
Cycle-to-
cycle
jitter
DLL locked tJIT(cc) 100 120 140 ps 15
DLL locking tJIT(cc),lck 80 100 120 ps 15
Cumulative
error across
2 cycles tERR(2per) –74 74 –88 88 –103 103 ps 16
3 cycles tERR(3per) –87 87 –105 105 –122 122 ps 16
4 cycles tERR(4per) –97 97 –117 117 –136 136 ps 16
5 cycles tERR(5per) –105 105 –126 126 –147 147 ps 16
6 cycles tERR(6per) –111 111 –133 133 –155 155 ps 16
7 cycles tERR(7per) –116 116 –139 139 –163 163 ps 16
8 cycles tERR(8per) –121 121 –145 145 –169 169 ps 16
9 cycles tERR(9per) –125 125 –150 150 –175 175 ps 16
10 cycles tERR(10per) –128 128 –154 154 –180 180 ps 16
11 cycles tERR(11per) –132 132 –158 158 –184 184 ps 16
12 cycles tERR(12per) –134 134 –161 161 –188 188 ps 16
n = 13, 14 ... 49,
50 cycles
tERR(nper) tERR(nper),min = [1 + 0.68LN(n)] × tJIT(per),min
tERR(nper),max = [1 + 0.68LN(n)] × tJIT(per),max
ps 16
DQ Input Timing
Data setup
time to DK,
DK#
Base
(specification)
tDS(AC150) –30 – –15 – 10 – ps 17, 18
VREF
@ 1 V/ns
120 – 135 – 160 – ps 18, 19
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Table 28: AC Electrical Characteristics (Continued)
Notes 1–7 apply to entire table
Parameter Symbol
RL3–2133 RL3–1866 RL3–1600
Units NotesMin Max Min Max Min Max
Data hold
time from
DK, DK#
Base
(specification)
tDH(DC100) 5 – 20 – 45 – ps 17, 18
VREF
@ 1 V/ns
105 – 120 – 145 – ps
Minimum data pulse width tDIPW 280 – 320 – 360 – ps 20
DQ Output Timing
QK, QK# edge to output data
edge within byte group
tQKQx– 75 – 85 – 100 ps
QK, QK# edge to any output
data edge within specific data
word grouping (only for x36)
tQKQ02,
tQKQ13
– 125 – 135 – 150 ps 22
DQ output hold time from
QK, QK#
tQH 0.38 – 0.38 – 0.38 – tCK(avg) 23
DQ Low-Z time from CK, CK# tLZ –360 180 –390 195 –450 225 ps 24, 26
DQ High-Z time from CK, CK# tHZ – 180 – 195 – 225 ps 24, 26
Input and Output Strobe Timing
DK (rising), DK# (falling) edge
to/from CK (rising), CK# (fall-
ing) edge
tCKDK –0.27 0.27 –0.27 0.27 –0.27 0.27 CK 29
DK, DK# differential input
HIGH width
tDKH 0.45 0.55 0.45 0.55 0.45 0.55 CK
DK, DK# differential input
LOW width
tDKL 0.45 0.55 0.45 0.55 0.45 0.55 CK
QK (rising), QK# (falling) edge
to CK (rising), CK# (falling)
edge
tCKQK –135
- 5%
tCK
135
+ 5%
tCK
–140
- 5%
tCK
140
+ 5%
tCK
–160
- 5%
tCK
160
+ 5%
tCK
ps 26
QK (rising), QK# (falling) edge
to CK (rising), CK# (falling)
edge with DLL disabled
tCKQK
DLL_DIS
1 10 1 10 1 10 ns 27
QK, QK# differential output
HIGH time
tQKH 0.4 – 0.4 – 0.4 – CK 23
QK, QK# differential output
LOW time
tQKL 0.4 – 0.4 – 0.4 – CK 23
QK (falling), QK# (rising) edge
to QVLD edge
tQKVLD – 125 – 135 – 150 ps 25
Command and Address Timing
CTRL, CMD,
ADDR, set-
up to
CK,CK#
Base
(specification)
tIS(AC150) 85 – 120 – 170 – ps 28, 30
VREF
@ 1 V/ns
235 – 270 – 320 – ps 19, 30
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Table 28: AC Electrical Characteristics (Continued)
Notes 1–7 apply to entire table
Parameter Symbol
RL3–2133 RL3–1866 RL3–1600
Units NotesMin Max Min Max Min Max
CTRL, CMD,
ADDR,
hold from
CK,CK#
Base
(specification)
tIH(DC100) 65 – 100 – 120 – ps 28, 30
VREF
@ 1 V/ns
165 – 200 – 220 – ps 19, 30
Minimum CTRL, CMD, ADDR
pulse width
tIPW 470 – 535 – 560 – ps 20
Row cycle time tRC See minimum tRC values in the RL3 Speed Bins table. ns 21
Refresh rate tREF 64 – 64 – 64 – ms
Sixteen-bank access window tSAW 8 – 8 – 8 – ns
Multibank access delay tMMD 2 – 2 – 2 – CK 33
WRITE-to-READ to same ad-
dress
tWTR WL +
BL/2
– WL +
BL/2
– WL +
BL/2
–CK 32
Mode register set cycle time
to any command
tMRSC 12 – 12 – 12 – CK
READ training register mini-
mum READ time
tRTRS 2 – 2 – 2 – CK
READ training register burst
end to mode register set for
training register exit
tRTRE 1 – 1 – 1 – CK
Calibration Timing
ZQCL: Long
calibration
time
POWER-UP and
RESET operation
tZQinit 512 – 512 – 512 – CK
Normal operation tZQoper 256 – 256 – 256 – CK
ZQCS: Short calibration time tZQcs 64 – 64 – 64 – CK
Initialization and Reset Timing
Begin power-supply ramp to
power supplies stable
tVDDPR – 200 – 200 – 200 ms
RESET# LOW to power sup-
plies stable
tRPS – 200 – 200 – 200 ms
RESET# LOW to I/O and RTT
High-Z
tIOz – 20 – 20 – 20 ns 31
Notes: 1. Parameters are applicable with 0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V, +2.38V ≤ VEXT ≤
+2.63V, +1.14V ≤ VDDQ ≤ 1.26V.
2. All voltages are referenced to VSS.
3. The unit tCK(avg) represents the actual tCK(avg) of the input clock under operation. The
unit CK represents one clock cycle of the input clock, counting the actual clock edges.
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environ-
ment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the
AC/DC trip points and CK,CK# and DKx, DKx# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
and 2 V/ns for differential inputs in the range between VIL(AC) and VIH(AC).
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5. All timings that use time-based values (ns, μs, ms) should use tCK(avg) to determine the
correct number of clocks. In the case of noninteger results, all minimum limits should be
rounded up to the nearest whole integer, and all maximum limits should be rounded
down to the nearest whole integer.
6. The term “strobe” refers to the DK and DK# or QK and QK# differential crossing point
when DK and QK, respectively, is the rising edge. Clock, or CK, refers to the CK and CK#
differential crossing point when CK is the rising edge.
7. The output load defined in Figure 18 (page 39) is used for all AC timing and slew rates.
The actual test load may be different. The output signal voltage reference point is
VDDQ/2 for single-ended signals and the crossing point for differential signals.
8. When operating in DLL disable mode, Micron does not warrant compliance with normal
mode timings or functionality.
9. The clock’s tCK(avg) is the average clock over any 200 consecutive clocks and
tCK(avg),min is the smallest clock rate allowed, with the exception of a deviation due to
clock jitter. Input clock jitter is allowed provided it does not exceed values specified and
must be of a random Gaussian distribution in nature.
10. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of tCK(avg) as a long-term jitter component; however, the spread spec-
trum may not use a clock rate below tCK(avg),min.
11. The clock’s tCH(avg) and tCL(avg) are the average half-clock period over any 200 consec-
utive clocks and is the smallest clock half-period allowed, with the exception of a devia-
tion due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.
12. The period jitter, tJIT(per), is the maximum deviation in the clock period from the aver-
age or nominal clock. It is allowed in either the positive or negative direction.
13. tCH(abs) is the absolute instantaneous clock high pulse width as measured from one ris-
ing edge to the following falling edge.
14. tCL(abs) is the absolute instantaneous clock low pulse width as measured from one fall-
ing edge to the following rising edge.
15. The cycle-to-cyle jitter, tJIT(cc), is the amount the clock period can deviate from one cycle
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
16. The cumulative jitter error, tERR(nper), where n is the number of clocks between 2 and
50, is the amount of clock time allowed to accumulate consecutively away from the
average clock over n number of clock cycles.
17. tDS(base) and tDH(base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns dif-
ferential DK, DK# slew rate.
18. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-
tion edge to its respective data strobe signal (DK, DK#) crossing.
19. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate
of 1 V/ns, are for reference only.
20. Pulse width of an input signal is defined as the width between the first crossing of
VREF(DC) and the consecutive crossing of VREF(DC).
21. Bits MR0[3:0] select the number of clock cycles required to satisfy the minimum tRC val-
ue. Minimum tRC value must be divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge that the subsequent command can
be issued to the bank.
22. tQKQ02 defines the skew between QK0 and DQ[26:18] and between QK2 and DQ[8:0].
tQKQ13 defines the skew between QK1 and DQ[35:27] and between QK3 and DQ[17:9].
23. When the device is operated with input clock jitter, this parameter needs to be derated
by the actual tJIT(per) (the larger of tJIT(per),min or tJIT(per),max of the input clock; out-
put deratings are relative to the SDRAM input clock).
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24. Single-ended signal parameter.
25. For x36 device this specification references the skew between the falling edge of QK0
and QK1 to QVLD0 and the falling edge of QK2 and QK3 to QVLD1.
26. The DRAM output timing is aligned to the nominal or average clock. The following out-
put parameters must be derated by the actual jitter error when input clock jitter is
present, even when within specification. This results in each parameter becoming larger.
The following parameters are required to be derated by subtracting tERR(10per),max:
tCKQK (MIN), and tLZ (MIN). The following parameters are required to be derated by
subtracting tERR(10per),min: tCKQK (MAX), tHZ (MAX), and tLZ (MAX).
27. The tDQSCKdll_dis parameter begins RL - 1 cycles after the READ command.
28. tIS(base) and tIH(base) values are for a single-ended 1 V/ns control/command/address
slew rate and 2 V/ns CK, CK# differential slew rate.
29. These parameters are measured from the input data strobe signal (DK/DK#) crossing to
its respective clock signal crossing (CK/CK#). The specification values are not affected by
the amount of clock jitter applied as they are relative to the clock signal crossing. These
parameters should be met whether or not clock jitter is present.
30. These parameters are measured from a command/address signal transition edge to its
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether or not clock jitter is present.
31. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-
sive current, depending on bus activity.
32. If tWTR is violated, the data just written will not be read out when a READ command is
issued to the same address. Whatever data was previously written to the address will be
output with the READ command.
33. This specification is defined as any bank command (READ, WRITE, AREF) to a multi-bank
command or a multi-bank command to any bank command. This specification only ap-
plies to quad bank WRITE, 3-bank AREF and 4-bank AREF commands. Dual bank WRITE,
2-bank AREF, and all single bank access commands are not bound by this specification.
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Temperature and Thermal Impedance Characteristics
It is imperative that the device’s temperature specifications be maintained in order to
ensure that the junction temperature is in the proper operating range to meet data
sheet specifications. An important way to maintain the proper junction temperature is
to use the device’s thermal impedances correctly. Thermal impedances are listed for the
available packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications” prior to using thermal impedances
listed below.
The device’s safe junction temperature range can be maintained when the TC specifica-
tion is not exceeded. In applications where the device’s ambient temperature is too
high, use of forced air and/or heat sinks may be required in order to meet the case tem-
perature specifications.
Table 29: Temperature Limits
Parameter Symbol Min Max Units Notes
Storage temperature TSTG -55 150 °C 1
Reliability junction temperature Commercial TJ(REL) - 110 °C 2
Industrial - 110 °C 2
Operating junction temperature Commercial TJ(OP) 0 100 °C 3
Industrial -40 100 °C 3
Operating case temperature Commercial TC0 95 °C 4, 5
Industrial -40 95 °C 4, 5
Notes: 1. MAX storage case temperature; TSTG is measured in the center of the package (see Fig-
ure 21 (page 50)). This case temperature limit is allowed to be exceeded briefly during
package reflow, as noted in Micron technical note TN-00-15.
2. Temperatures greater than 110°C may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at or above this is not implied.
Exposure to absolute maximum rating conditions for extended periods may adversely
affect the reliability of the part.
3. Junction temperature depends upon package type, cycle time, loading, ambient temper-
ature, and airflow.
4. MAX operating case temperature; TC is measured in the center of the package (see Fig-
ure 21 (page 50)).
5. Device functionality is not guaranteed if the device exceeds maximum TC during opera-
tion.
Table 30: Thermal Impedance
Package Substrate
θ
θ
JA (°C/W)
Airflow = 0m/s
θ
JA (°C/W)
Airflow = 1m/s
θ
JA (°C/W)
Airflow = 2m/s
θ
JB (°C/W)
θ
JC (°C/W)
FBGA 2-layer 39.3 28.8 25.2 16.3 2.0
4-layer 22.0 17.2 15.9 10.3
Note: 1. Thermal impedance data is based on a number of samples from multiple lots, and
should be viewed as a typical number.
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Figure 21: Example Temperature Test Point Location
13.5mm
6.75mm
Test point
13.5mm
6.75mm
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Command and Address Setup, Hold, and Derating
The total tIS (setup time) and tIH (hold time) required is calculated by adding the data
sheet tIS (base) and tIH (base) values (see Table 31 (page 51); values come from Ta-
ble 28 (page 44)) to the ΔtIS and ΔtIH derating values (see Table 32 (page 52)), respec-
tively. Example: tIS (total setup time) = tIS (base) + ΔtIS. For a valid transition, the input
signal must remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 33
(page 52)).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transi-
tion), a valid input signal is still required to complete the transition and to reach VIH(AC)/
VIL(AC). For slew rates which fall between the values listed in Table 32 (page 52) and
Table 33 (page 52) for Valid Transition, the derating values may be obtained by linear
interpolation.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate
for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and
the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew
rate line between the shaded VREF(DC)-to-AC region, use the nominal slew rate for derat-
ing value (see Figure 22 (page 53)). If the actual signal is later than the nominal slew
rate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a tangent
line to the actual signal from the AC level to the DC level is used for derating value (see
Figure 24 (page 55)).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew rate
for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and
the first crossing of VREF(DC). If the actual signal is always later than the nominal slew
rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derat-
ing value (see Figure 23 (page 54)). If the actual signal is earlier than the nominal slew
rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a tangent
line to the actual signal from the DC level to the VREF(DC) level is used for derating value
(see Figure 25 (page 56)).
Table 31: Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based
Symbol RL3-2133 RL3-1866 RL3-1600 Units Reference
tIS(base),AC150 85 120 170 ps VIH(AC)/VIL(AC)
tIH(base),DC100 65 100 120 ps VIH(DC)/VIL(DC)
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Table 32: Derating Values for tIS/tIH – AC150/DC100-Based
Δ
Δ
tIS,
Δ
tIH Derating (ps) - AC/DC-Based AC 150 Threshold: VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV
CMD/ADDR
Slew Rate
(V/ns)
CK, CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100
1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84
1.0 000000881616242432344050
0.9 0 –4 0 –4 0 –4 8 4 16 12 24 20 32 30 40 46
0.8 0 –10 0 –10 0 –10 8 –2 16 6 24 14 32 24 40 40
0.7 0 –16 0 –16 0 –16 8 –8 16 0 24 8 32 18 40 34
0.6 –1 –26 –1 –26 –1 –26 7 –18 15 –10 23 –2 31 8 39 24
0.5 –10 –40 –10 –40 –10 –40 –2 –32 6 –24 14 –16 22 –6 30 10
0.4 –25 –60 –25 –60 –25 –60 –17 –52 –9 –44 –1 –36 7 –26 15 –10
Table 33: Minimum Required Time tVAC Above VIH(AC) (or Below VIL(AC)) for Valid Transition
Slew Rate (V/ns) tVAC (ps)
>2.0 175
2.0 170
1.5 167
1.0 163
0.9 162
0.8 161
0.7 159
0.6 155
0.5 150
<0.5 150
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Figure 22: Nominal Slew Rate and tVAC for tIS (Command and Address - Clock)
VSS
Setup slew rate
rising signal
Setup slew rate
falling signal
'TF 'TR
==
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
Nominal
slew rate
VREF to AC
region
tVAC
tVAC
DK
DK#
CK#
CK
tIS tIH tIS tIH
Nominal
slew rate
VREF to AC
region
VREF(DC) - VIL(AC)max
'TF
VIH(AC)min - VREF(DC)
'TR
Note: 1. Both the clock and the data strobe are drawn on different time scales.
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Figure 23: Nominal Slew Rate for tIH (Command and Address - Clock)
VSS
Hold slew rate
falling signal
Hold slew rate
rising signal
'TR 'TF
==
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
Nominal
slew rate
DC to VREF
region
DK
DK#
CK#
CK
tIS tIH tIS tIH
DC to VREF
region
Nominal
slew rate
VREF(DC) - VIL(DC)max
'TR
VIH(DC)min - VREF(DC)
'TF
Note: 1. Both the clock and the data strobe are drawn on different time scales.
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Figure 24: Tangent Line for tIS (Command and Address - Clock)
VSS
Setup slew rate
rising signal
Setup slew rate
falling signal
'TF
'TR
=
=
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
Tangent
line
VREF to AC
region
Nominal
line
tVAC
tVAC
DK
DK#
CK#
CK
tIS tIH tIS tIH
VREF to AC
region
Tangent
line
Nominal
line
Tangent line VIH(DC)min - VREF(DC)
'TR
][
Tangent line VREF(DC) - VIL(AC)max
'TF
][
Note: 1. Both the clock and the data strobe are drawn on different time scales.
576Mb: x18, x36 RLDRAM 3
Command and Address Setup, Hold, and Derating
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Figure 25: Tangent Line for tIH (Command and Address - Clock)
VSS
'TR
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
Tangen t
line
DC to VREF
region
DK
DK#
CK#
CK
tIS tIH tIS tIH
DC to VREF
region
Tangen t
line
Nominal
line
Nominal
line
'TF
Hold slew rate
rising signal =
Tangent line VREF(DC) - VIL(DC)max
'TR
][
Hold slew rate
falling signal =
Tangent line VIH(DC)min - VREF(DC)
'TF
][
Note: 1. Both the clock and the data strobe are drawn on different time scales.
576Mb: x18, x36 RLDRAM 3
Command and Address Setup, Hold, and Derating
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Data Setup, Hold, and Derating
The total tDS (setup time) and tDH (hold time) required is calculated by adding the data
sheet tDS (base) and tDH (base) values (see the table below; values come from Table 28
(page 44)) to the ΔtDS and ΔtDH derating values (see Table 35 (page 58)), respectively.
Example: tDS (total setup time) = tDS (base) + ΔtDS. For a valid transition, the input sig-
nal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 36
(page 58)).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached VIH(AC)/VIL(AC)) at the time of the rising clock transi-
tion), a valid input signal is still required to complete the transition and to reach VIH/
VIL(AC). For slew rates which fall between the values listed in Table 35 (page 58) and
Table 36 (page 58), the derating values may obtained by linear interpolation.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tDS) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC)
and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal
slew rate line between the shaded VREF(DC)-to-AC region, use the nominal slew rate for
derating value (see Figure 26 (page 59)). If the actual signal is later than the nominal
slew rate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a
tangent line to the actual signal from the AC level to the DC level is used for derating
value (see Figure 28 (page 61)).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tDH) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min
and the first crossing of VREF(DC). If the actual signal is always later than the nominal
slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for
derating value (see Figure 27 (page 60)). If the actual signal is earlier than the nominal
slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a
tangent line to the actual signal from the DC-to-VREF(DC) region is used for derating val-
ue (see Figure 29 (page 62)).
Table 34: Data Setup and Hold Values at 1 V/ns (DKx, DKx# at 2V/ns) – AC/DC-Based
Symbol RL3-2133 RL3-1866 RL3-1600 Units Reference
tDS(base),AC150 –30 -15 10 ps VIH(AC)/VIL(AC)
tDH(base),DC100 5 20 45 ps VIH(DC)/VIL(DC)
576Mb: x18, x36 RLDRAM 3
Data Setup, Hold, and Derating
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Table 35: Derating Values for tDS/tDH – AC150/DC100-Based
Empty cells indicate slew rate combinations not supported
Δ
Δ
tDS,
Δ
tDH Derating (ps) - AC/DC-Based
DQ Slew
Rate (V/ns)
DKx, DKx# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
2.0 75 50 75 50 75 50
1.5 50 34 50 34 50 34 58 42
1.0 000000881616
0.9 0 –4 0 –4 8 4 16 12 24 20
0.8 0 –10 8 –2 16 6 24 14 32 24
0.7 8 –8 16 0 24 8 32 18 40 34
0.6 15 –10 23 –2 31 8 39 24
0.5 14 –16 22 –6 30 10
0.4 7 –26 15 –10
Table 36: Minimum Required Time tVAC Above VIH(AC) (or Below VIL(AC)) for Valid Transition
Slew Rate (V/ns) tVAC (ps)
>2.0 175
2.0 170
1.5 167
1.0 163
0.9 162
0.8 161
0.7 159
0.6 155
0.5 150
<0.5 150
576Mb: x18, x36 RLDRAM 3
Data Setup, Hold, and Derating
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Figure 26: Nominal Slew Rate and tVAC for tDS (DQ - Strobe)
VSS
Setup slew rate
rising signal
Setup slew rate
falling signal
'TF 'TR
==
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
Nominal
slew rate
VREF to AC
region
tVAC
tVAC
tDH
tDS
DK
DK#
tDH
tDS
CK#
CK
VREF to AC
region
Nominal
slew rate
VIH(AC)min - VREF(DC)
'TR
VREF(DC) - VIL(AC)max
'TF
Note: 1. Both the clock and the strobe are drawn on different time scales.
576Mb: x18, x36 RLDRAM 3
Data Setup, Hold, and Derating
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Figure 27: Nominal Slew Rate for tDH (DQ - Strobe)
VSS
Hold slew rate
rising signal
'TR 'TF
=
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
Nominal
slew rate
DC to VREF
region
tDH
tDS
DK
DK#
tDH
tDS
CK#
CK
DC to VREF
region
Nominal
slew rate
VREF(DC) - VIL(DC)max
'TR
Hold slew rate
falling signal =
VIH(DC)min - VREF(DC)
'TF
Note: 1. Both the clock and the strobe are drawn on different time scales.
576Mb: x18, x36 RLDRAM 3
Data Setup, Hold, and Derating
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Figure 28: Tangent Line for tDS (DQ - Strobe)
VSS
Setup slew rate
rising signal
'TF
'TR
=
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
Tangent
line
VREF to AC
region
Nominal
line
tVAC
tVAC
tDH
tDS
DK
DK#
tDH
tDS
CK#
CK
VREF to AC
region
Tangent
line
Nominal
line
'TR
Tangent line VIH(AC)min - VREF(DC)][
Setup slew rate
falling signal =
'TF
Tangent line VREF(DC) - VIL(AC)max][
Note: 1. Both the clock and the strobe are drawn on different time scales.
576Mb: x18, x36 RLDRAM 3
Data Setup, Hold, and Derating
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Figure 29: Tangent Line for tDH (DQ - Strobe)
VSS
'TF'TR
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
Tangent
line
DC to VREF
region
DK
DK#
CK#
CK
DC to VREF
region
Tangent
line
Nominal
line
Nominal
line
tDS tDH tDS tDH
Hold slew rate
rising signal =
'TR
Tangent line VREF(DC) - VIL(DC)max][
Hold slew rate
falling signal =
'TF
Tangent line VIH(DC)min - VREF(DC)
][
Note: 1. Both the clock and the strobe are drawn on different time scales.
576Mb: x18, x36 RLDRAM 3
Data Setup, Hold, and Derating
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Commands
The following table provides descriptions of the valid commands of the RLDRAM 3 de-
vice. All command and address inputs must meet setup and hold times with respect to
the rising edge of CK.
Table 37: Command Descriptions
Command Description
NOP The NOP command prevents new commands from being executed by the DRAM.
Operations already in progress are not affected by NOP commands. Output values depend on com-
mand history.
MRS Mode registers MR0, MR1, and MR2 are used to define various modes of programmable operations of
the DRAM. A mode register is programmed via the MODE REGISTER SET (MRS) command during initi-
alization and retains the stored information until it is reprogrammed, RESET# goes LOW, or until the
device loses power. The MRS command can be issued only when all banks are idle, and no bursts are
in progress.
READ The READ command is used to initiate a burst read access to a bank. The BA[3:0] inputs select a bank,
and the address provided on inputs A[19:0] select a specific location within a bank.
WRITE The WRITE command is used to initiate a burst write access to a bank (or banks). MRS bits MR2[4:3]
select single, dual, or quad bank WRITE protocol. The BA[x:0] inputs select the bank(s) (x = 3, 2, or 1
for single, dual, or quad bank WRITE, respectively). The address provided on inputs A[19:0] select a
specific location within the bank. Input data appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coincident with the data. If the DM signal is registered
LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the cor-
responding data inputs will be ignored (that is, this part of the data word will not be written).
AREF The AREF command is used during normal operation of the RLDRAM 3 to refresh the memory con-
tent of a bank. There are two methods by which the RLDRAM 3 can be refreshed, both of which are
selected within the mode register. The first method, bank address-controlled AREF, is identical to the
method used in RLDRAM2. The second method, multibank AREF, enables refreshing of up to four
banks simultaneously. More info is available in the Auto Refresh section. For both methods, the com-
mand is nonpersistent, so it must be issued each time a refresh is required.
Table 38: Command Table
Note 1 applies to the entire table
Operation Code CS# WE# REF# A[19:0] BA[3:0] Notes
NOP NOP H H H X X
MRS MRS L L L OPCODE OPCODE
READ READ L H H A BA 2
WRITE WRITE L L H A BA 2
AUTO REFRESH AREF LHLABA3
Notes: 1. X = “Don’t Care;” H = logic HIGH; L = logic LOW; A = valid address; BA = valid bank ad-
dress; OPCODE = mode register bits
2. Address width varies with burst length and configuration; see the Address Widths of
Different Burst Lengths table for more information.
3. Bank address signals (BA) are used only during bank address-controlled AREF; Address
signals (A) are used only during multibank AREF.
576Mb: x18, x36 RLDRAM 3
Commands
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MODE REGISTER SET (MRS) Command
The mode registers, MR0, MR1, and MR2, store the data for controlling the operating
modes of the memory. The MODE REGISTER SET (MRS) command programs the
RLDRAM 3 operating modes and I/O options. During an MRS command, the address
inputs are sampled and stored in the mode registers. The BA[1:0] signals select between
mode registers 0–2 (MR0–MR2). After the MRS command is issued, each mode register
retains the stored information until it is reprogrammed, until RESET# goes LOW, or un-
til the device loses power.
After issuing a valid MRS command, tMRSC must be met before any command can be
issued to the RLDRAM 3. The MRS command can be issued only when all banks are
idle, and no bursts are in progress.
Figure 30: MRS Command Protocol
Don’t Care
CK
CK#
CS#
WE#
REF#
OPCODE
OPCODE
Address
Bank
Address
576Mb: x18, x36 RLDRAM 3
MODE REGISTER SET (MRS) Command
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Mode Register 0 (MR0)
Figure 31: MR0 Definition for Non-Multiplexed Address Mode
A6A7 A4A8A9A10 A3 A2 A1 A0A5 Address Bus
...A17BA0BA1BA2BA3
t
RC_MRS
DLLAM
0
1
0
1
Reserved
MRS Data Latency
Mode Register (Mx)
678
943210518192021 17-10
M19
0
0
1
1
M18
0
1
0
1
Mode Register Definition
Mode Register 0 (MR0)
Mode Register 1 (MR1)
Mode Register 2 (MR2)
Reserved
M8
0
1
DLL Enable
Enable
Disable
M9
0
1
Address MUX
Non-multiplexed
Multiplexed
M4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
M7
0
0
0
0
0
0
0
0
Data Latency (RL & WL)
RL = 3 ; WL = 4
RL = 4 ; WL = 5
RL = 5 ; WL = 6
RL = 6 ; WL = 7
RL = 7 ; WL = 8
RL = 8 ; WL = 9
RL = 9 ; WL = 10
RL = 10 ; WL = 11
RL = 11 ; WL = 12
RL = 12 ; WL = 13
RL = 13 ; WL = 14
RL = 14 ; WL = 15
RL = 15 ; WL = 16
RL = 16 ; WL = 17
Reserved
Reserved
M0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
M3
0
0
0
0
0
0
0
0
t
RC_MRS
2
2,3
3
2
4
2
5
6
7
8
9
10
11
12
Reserved
Reserved
Reserved
Reserved
Reserved
Notes: 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
2. BL8 not allowed.
3. BL4 not allowed.
576Mb: x18, x36 RLDRAM 3
Mode Register 0 (MR0)
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tRC
Bits MR0[3:0] select the number of clock cycles required to satisfy the tRC specifications.
After a READ, WRITE, or AREF command is issued to a bank, a subsequent READ,
WRITE, or AREF cannot be issued to the same bank until tRC has been satisfied. The
correct value (tRC_MRS) to program into MR0[3:0] is shown in the table below.
Table 39: tRC_MRS MR0[3:0] values
Parameter -093E -093 -107E -107 -125F -125E -125
RL = 3; WL = 4 2 2 Reserved Reserved Reserved Reserved Reserved
RL = 4; WL = 5 2 3 2 3 Reserved 3 3
RL = 5; WL = 6 3 4 3 3 Reserved 3 3
RL = 6; WL = 7 4 4 3 4 Reserved 4 4
RL = 7; WL = 8 4 4 4 4 Reserved 4 4
RL = 8; WL = 9 5 6 4 5 Reserved 5 5
RL = 9; WL = 10 5 6 5 6 Reserved 6 6
RL = 10; WL = 11 6 7 5 6 Reserved 6 6
RL = 11; WL = 12 6 7 6 7 Reserved 7 7
RL = 12; WL = 13 7 8 67677
RL = 13; WL = 14 7 8 78788
RL = 14; WL = 15 8 10 7 8 Reserved Reserved 9
RL = 15; WL = 16 8 10 8 10 Reserved Reserved 10
RL = 16; WL = 17 9 11 Reserved Reserved Reserved Reserved 10
Data Latency
The data latency register uses MR0[7:4] to set both the READ and WRITE latency (RL
and WL). The valid operating frequencies for each data latency register setting can be
found in Table 28 (page 44).
DLL Enable/Disable
Through the programming of MR0[8], the DLL can be enabled or disabled.
The DLL must be enabled for normal operation. The DLL must be enabled during the
initialization routine and upon returning to normal operation after having been disa-
bled for the purpose of debugging or evaluation. To operate the RLDRAM with the DLL
disabled, the tRC MRS setting must equal the read latency (RL) setting. Enabling the
DLL should always be followed by resetting the DLL using the appropriate MR1 com-
mand.
Address Multiplexing
Although the RLDRAM has the ability to operate similar to an SRAM interface by ac-
cepting the entire address in one clock (non-multiplexed, or broadside addressing),
MR0[9] can be set to 1 so that it functions with multiplexed addressing, similar to a tra-
ditional DRAM. In multiplexed address mode, the address is provided to the RLDRAM
in two parts that are latched into the memory with two consecutive rising edges of CK.
576Mb: x18, x36 RLDRAM 3
Mode Register 0 (MR0)
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When in multiplexed address mode, only 11 address balls are required to control the
RLDRAM, as opposed to 20 address balls when in non-multiplexed address mode. The
data bus efficiency in continuous burst mode is only affected when using the BL = 2 set-
ting because the device requires two clocks to read and write data. During multiplexed
mode, the bank addresses as well as WRITE and READ commands are issued during the
first address part, Ax. The Address Mapping in Multiplexed Address Mode table shows
the addresses needed for both the first and second rising clock edges (Ax and Ay, re-
spectively).
After MR0[9] is set HIGH, READ, WRITE, and MRS commands follow the format descri-
bed in the Command Description in Multiplexed Address Mode figure. Refer to Multi-
plexed Address Mode for further information on operation with multiplexed address-
ing.
576Mb: x18, x36 RLDRAM 3
Mode Register 0 (MR0)
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Mode Register 1 (MR1)
Figure 32: MR1 Definition for Non-Multiplexed Address Mode
A0A1A2A3A4A5A6A7A8 A17 ... A11 A9A10BA0BA1BA2BA3 Address Bus
ODT
Reserved
MRS Drive
Mode Register (Mx)
DLLRefBL ZQZQe
18
01
01
19
20
21 45678910
17-11 3210
M0
0
1
0
1
M1
0
0
1
1
Output Drive
RZQ/6 (40:
RZQ/4 (60:
Reserved
Reserved
M9
0
1
0
1
M10
0
0
1
1
Burst Length
2
Reserved ZQ Calibration Selection
Short ZQ Calibration
Long ZQ Calibration
M2
0
1
0
1
0
1
0
1
ODT
Off
RZQ/6 (40:
RZQ/4 (60:
RZQ/2 (120:
Reserved
Reserved
Reserved
Reserved
M3
0
0
1
1
0
0
1
1
1
1
1
1
M4
0
0
0
0
M19
0
0
1
1
M18
0
1
0
1
Mode Register Definition
Mode Register 0 (MR0)
Mode Register 1 (MR1)
Mode Register 2 (MR2)
Reserved
DLL Reset
No
Yes
M8
0
1
AREF P rotocol
Bank Address Control
Multibank
M7
0
1
M6
0
1
M5
0
1
ZQ Calibration Enable
Disabled - Default
Enable
Notes: 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
2. BL8 not available in x36.
Output Drive Impedance
The RLDRAM 3 uses programmable impedance output buffers, which enable the user
to match the driver impedance to the system. MR1[0] and MR1[1] are used to select 40Ω
or 60Ω output impedance, but the device powers up with an output impedance of 40Ω.
The drivers have symmetrical output impedance. To calibrate the impedance a 240Ω
±1% external precision resistor (RZQ) is connected between the ZQ ball and VSSQ.
The output impedance is calibrated during initialization through the ZQCL mode regis-
ter setting. Subsequent periodic calibrations (ZQCS) may be performed to compensate
for shifts in output impedance due to changes in temperature and voltage. More de-
tailed information on calibration can be found in the ZQ Calibration section.
DQ On-Die Termination (ODT)
MR1[4:2] are used to select the value of the on-die termination (ODT) for the DQ, DKx
and DM balls. When enabled, ODT terminates these balls to V DDQ/2. The RLDRAM 3
device supports 40ΩΩ, or 120Ω ODT. The ODT function is dynamically switched off
when a DQ begins to drive after a READ command has been issued. Similarly, ODT is
designed to switch on at the DQs after the RLDRAM has issued the last piece of data.
The DM and DKx balls are always terminated after ODT is enabled.
DLL Reset
Programming MR1[5] to 1 activates the DLL RESET function. MR1[5] is self-clearing,
meaning it returns to a value of 0 after the DLL RESET function has been initiated.
576Mb: x18, x36 RLDRAM 3
Mode Register 1 (MR1)
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Whenever the DLL RESET function is initiated, CK/CK# must be held stable for 512
clock cycles before a READ command can be issued. This is to allow time for the inter-
nal clock to be synchronized with the external clock. Failing to wait for synchronization
to occur may cause output timing specifications, such as tCKQK, to be invalid .
ZQ Calibration
The ZQ CALIBRATION mode register command is used to calibrate the DRAM output
drivers (RON) and ODT values (RTT) over process, voltage, and temperature, provided a
dedicated 240Ω (±1%) external resistor is connected from the DRAM’s RZQ ball to VSSQ.
Bit MR1[6] selects between ZQ calibration long (ZQCL) and ZQ calibration short
(ZQCS), each of which are described in detail below. When bit MR1[7] is set HIGH, it
enables the calibration sequence. Upon completion of the ZQ calibration sequence,
MR1[7] automatically resets LOW.
The RLDRAM 3 needs a longer time to calibrate RON and ODT at power-up initialization
and a relatively shorter time to perform periodic calibrations. An example of ZQ calibra-
tion timing is shown below.
All banks must have tRC met before ZQCL or ZQCS mode register settings can be issued
to the DRAM. No other activities (other than loading another ZQCL or ZQCS mode reg-
ister setting may be issued to another DRAM) can be performed on the DRAM channel
by the controller for the duration of tZQinit or tZQoper. The quiet time on the DRAM
channel helps accurately calibrate RON and ODT. After DRAM calibration is achieved,
the DRAM will disable the ZQ ball’s current consumption path to reduce power.
ZQ CALIBRATION mode register settings can be loaded in parallel to DLL reset and
locking time.
In systems that share the ZQ resistor between devices, the controller must not allow
overlap of tZQinit, tZQoper, or tZQcs between devices.
576Mb: x18, x36 RLDRAM 3
Mode Register 1 (MR1)
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Figure 33: ZQ Calibration Timing (ZQCL and ZQCS)
NOPMRS NOP NOP Valid Valid MRS NOP NOP NOP ValidCommand
Indicates a break in
time scale
T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2
Address Valid ValidValid
CK
CK#
Don’t Care
or Unknown
DQ
QVLD
Activities Activ-
ities
QK#
QK
tZQCS
tZQinit or tZQoper
Activities Activ-
ities
ZQCL ZQCS
Notes: 1. All devices connected to the DQ bus should be held High-Z during calibration.
2. The state of QK and QK# are unknown during ZQ calibration.
3. tMRSC after loading the MR1 settings, QVLD output drive strength will be at the value
selected or higher (lower resistance) until ZQ calibration is complete.
ZQ Calibration Long
The ZQ calibration long (ZQCL) mode register setting is used to perform the initial cali-
bration during a power-up initialization and reset sequence. It may be loaded at any
time by the controller depending on the system environment. ZQCL triggers the cali-
bration engine inside the DRAM. After calibration is achieved, the calibrated values are
transferred from the calibration engine to the DRAM I/O, which are reflected as upda-
ted RON and ODT values.
The DRAM is allowed a timing window defined by either tZQinit or tZQoper to perform
the full calibration and transfer of values. When ZQCL is issued during the initialization
sequence, the timing parameter tZQinit must be satisfied. When initialization is com-
plete, subsequent loading of the ZQCL mode register setting requires the timing param-
eter tZQoper to be satisfied.
ZQ Calibration Short
The ZQ calibration short (ZQCS) mode register setting is used to perform periodic cali-
brations to account for small voltage and temperature variations. The shorter timing
window is provided to perform the reduced calibration and transfer of values as defined
by timing parameter tZQCS. ZQCS can effectively correct a minimum of 0.5% RON and
RTT impedance error within 64 clock cycles, assuming the maximum sensitivities speci-
fied in the ODT Temperature and Voltage Sensitivity and the Output Driver Voltage and
Temperature Sensitivity tables.
576Mb: x18, x36 RLDRAM 3
Mode Register 1 (MR1)
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AUTO REFRESH Protocol
The AUTO REFRESH (AREF) protocol is selected with bit MR1[8]. There are two ways in
which AREF commands can be issued to the RLDRAM. Depending upon how bit
MR1[8] is programmed, the memory controller can issue either bank address-control-
led or multibank AREF commands. Bank address-controlled AREF uses the BA[3:0] in-
puts to refresh a single bank per command. Multibank AREF is enabled by setting bit
MR1[8] HIGH during an MRS command. This refresh protocol enables the simultane-
ous refreshing of a row in up to four banks. In this method, the address pins A[15:0] rep-
resent banks 0–15, respectively. More information on both AREF protocols can be found
in AUTO REFRESH Command (page 78).
Burst Length (BL)
Burst length is defined by MR1[9] and MR1[10]. Read and write accesses to the
RLDRAM are burst-oriented, with the burst length being programmable to 2, 4, or 8.
Figure 34 (page 72) shows the different burst lengths with respect to a READ com-
mand. Changes in the burst length affect the width of the address bus (see the following
table for details).
The data written by the prior burst length is not guaranteed to be accurate when the
burst length of the device is changed.
Table 40: Address Widths of Different Burst Lengths
Burst Length
Configuration
x18 x36
2 A[19:0] A[18:0]
4 A[18:0] A[17:0]
8 A[17:0] NA
576Mb: x18, x36 RLDRAM 3
Mode Register 1 (MR1)
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Figure 34: Read Burst Lengths
Command
Address
DQ
QVLD
DO
an
QK
QK#
QK
QK#
QK
QK#
RL = 4
CK
CK#
DQ DO
an
Don’t CareTransitioning Data
DQ DO
an
READ NOP NOP NOP NOP NOP NOP NOP
Bank a,
Col n
T0 T1 T2 T3 T4n T5nT4 T5 T6n T7nT6 T7
QVLD
QVLD
BL = 2BL = 4BL = 8
NOP
Note: 1. DO an = data-out from bank a and address an.
576Mb: x18, x36 RLDRAM 3
Mode Register 1 (MR1)
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Mode Register 2 (MR2)
Figure 35: MR2 Definition for Non-Multiplexed Address Mode
A0A1A2A3A4...A17BA0BA1BA2BA3 Address Bus
RTREnWRITEReservedMRS
Mode Register (Mx)
17-51819
0
1
0
1
2021 23410
M4
0
0
1
1
M3
0
1
0
1
WRITE Protocol
Single Bank
Dual Bank
Quad Bank
Reserved
READ Training Register Enable
Normal RLDRAM Operation
READ Training Enabled
M19
0
0
1
1
M18
0
1
0
1
Mode Register Definition
Mode Register 0 (MR0)
Mode Register 1 (MR1)
Mode Register 2 (MR2)
Reserved
M2
0
1
M1
0
0
1
1
M0
0
1
0
1
READ Training Register
0-1-0-1 on all DQs
Even DQs: 0-1-0-1 ; Odd DQs: 1-0-1-0
Reserved
Reserved
Note: 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
READ Training Register (RTR)
The READ training register (RTR) is controlled through MR2[2:0]. It is used to output a
predefined bit sequence on the output balls to aid in system timing calibration. MR2[2]
is the master bit that enables or disables access to the READ training register, and
MR2[1:0] determine which predefined pattern for system calibration is selected. If
MR2[2] is set to 0, the RTR is disabled, and the DRAM operates in normal mode. When
MR2[2] is set to 1, the DRAM no longer outputs normal read data, but a predefined pat-
tern that is defined by MR2[1:0].
Prior to enabling the RTR, all banks must be in the idle state (tRC met). When the RTR is
enabled, all subsequent READ commands will output four bits of a predefined se-
quence from the RTR on all DQs. The READ latency during RTR is defined with the Data
Latency bits in MR0. To loop on the predefined pattern when the RTR is enabled, suc-
cessive READ commands must be issued and satisfy tRTRS. Address balls A[19:0] are
considered "Don't Care" during RTR READ commands. Bank address bits BA[3:0] must
access Bank 0 with each RTR READ command. tRC does not need to be met in between
RTR READ commands to Bank 0. When the RTR is enabled, only READ commands are
allowed. When the last RTR READ burst has completed and tRTRE has been satisfied, an
MRS command can be issued to exit the RTR. Standard RLDRAM 3 operation may then
start after tMRSC has been met. The RESET function is supported when the RTR is ena-
bled.
If MR2[1:0] is set to 00 a 0-1-0-1 pattern will be output on all DQs with each RTR READ
command. If MR2[1:0] is set to 01, a 0-1-0-1 pattern will output on all even DQs and the
opposite pattern, a 1-0-1-0, will output on all odd DQs with each RTR READ command.
Note: Enabling RTR may corrupt previously written data.
576Mb: x18, x36 RLDRAM 3
Mode Register 2 (MR2)
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Figure 36: READ Training Function - Back-to-Back Readout
CK
CK#
Command
Bank
QVLD
DQ
READ
MRS
MR2[21:18]
T0 T1 T2
Don’t Care Indicates a break
in time scale
Transitioning Data
NOP NOPREAD
T3 T4 T5
BANK 0 BANK 0 BANK 0 BANK 0 BANK 0
T6
READ
T7 T8 T9 T10 T11 T12 T13
NOP NOP
DK
DK#
QK
DM
QK#
RL
NOPREAD
tMRSC tRTRS tRTRS tRTRS tRTRS
READ NOP NOP MRS
MR2[21:18]
MR2[17:0]
VALID
(
)(
)
(
)(
)
(
)(
)
(
)(
)
Address MR2[17:0]
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
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)
(
)(
)
(
)(
)
(
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)
(
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)
(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
tRTRE tMRSC
Note: 1. RL = READ latency defined with data latency MR0 setting.
576Mb: x18, x36 RLDRAM 3
Mode Register 2 (MR2)
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WRITE Protocol
Single or multibank WRITE operation is programmed with bits MR2[4:3]. The purpose
of multibank WRITE operation is to reduce the effective tRC during READ commands.
When dual- or quad-bank WRITE protocol is selected, identical data is written to two or
four banks, respectively. With the same data stored in multiple banks on the RLDRAM,
the memory controller can select the appropriate bank to READ the data from and min-
imize tRC delay. Detailed information on the multibank WRITE protocol can be found
in Multibank WRITE (page 76).
WRITE Command
Write accesses are initiated with a WRITE command. The address needs to be provided
concurrent with the WRITE command.
During WRITE commands, data will be registered at both edges of DK, according to the
programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) de-
termined by the data latency bits within MR0. The first valid data is registered at the first
rising DK edge WL cycles after the WRITE command.
Any WRITE burst may be followed by a subsequent READ command (assuming tRC is
met). Depending on the amount of input timing skew, an additional NOP command
might be necessary between WRITE and READ commands to avoid external data bus
contention (see Figure 44 (page 84)).
Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and
tDH. The input data is masked if the corresponding DM signal is HIGH.
Figure 37: WRITE Command
CK#
CK
WE#
REF#
CS#
A
Address
Bank
Address BA
Don’t Care
576Mb: x18, x36 RLDRAM 3
WRITE Command
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Multibank WRITE
All the information provided above in the WRITE section is applicable to a multibank
WRITE operation as well. Either two or four banks can be simultaneously written to
when the appropriate MR2[4:3] mode register bits are selected.
If a dual-bank WRITE has been selected through the mode register, both banks x and x
+8 will be written to simultaneously with identical data provided during the WRITE
command. For example, when a dual-bank WRITE has been loaded and the bank ad-
dress for Bank 1 has been provided during the WRITE command, Bank 9 will also be
written to at the same time. When a dual-bank WRITE command is issued, only bank
address bits BA[2:0] are valid and BA3 is considered a “Don’t Care.”
The same methodology is used if the quad-bank WRITE has been selected through the
mode register. Under these conditions, when a WRITE command is issued to Bank x,
the data provided on the DQs will be issued to banks x, x+4, x+8, and x+12. When a
quad-bank WRITE command is issued, only bank address bits BA[1:0] are valid and
BA[3:2] are considered “Don’t Care.”
The timing parameter tSAW must be adhered to when operating with multibank WRITE
commands. This parameter limits the number of active banks at 16 within an 8ns win-
dow. The tMMD specification must also be followed if the quad-bank WRITE is being
used. This specification requires two clock cycles between any bank command (READ,
WRITE, or AREF) to a quad-bank WRITE or a quad-bank WRITE to any bank command.
The data bus efficiency is not compromised if BL4 or BL8 is being utilized.
READ Command
Read accesses are initiated with a READ command (see the figure below). Addresses are
provided with the READ command.
During READ bursts, the memory device drives the read data so it is edge-aligned with
the QK signals. After a programmable READ latency, data is available at the outputs.
One half clock cycle prior to valid data on the read bus, the data valid signal(s), QVLD,
transitions from LOW to HIGH. QVLD is also edge-aligned with the QK signals.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQx is the
skew between a QK pair and the last valid data edge generated at the DQ signals in the
associated byte group, such as DQ[7:0] and QK0. tQKQx is derived at each QK clock edge
and is not cumulative over time. For the x36 device, the tQKQ02 and tQKQ13 specifica-
tions define the relationship between the DQs and QK signals within specific data word
groupings. tQKQ02 defines the skew between QK0 and DQ[26:18] and between QK2 and
DQ[8:0]. tQKQ13 defines the skew between QK1 and DQ[35:17] and between QK3 and
DQ[17:9].
After completion of a burst, assuming no other commands have been initiated, output
data (DQ) will go High-Z. The QVLD signal transitions LOW on the last bit of the READ
burst. The QK clocks are free-running and will continue to cycle after the read burst is
complete. Back-to-back READ commands are possible, producing a continuous flow of
output data.
Any READ burst may be followed by a subsequent WRITE command. Some systems
having long line lengths or severe skews may need an additional idle cycle inserted be-
tween READ and WRITE commands to prevent data bus contention.
576Mb: x18, x36 RLDRAM 3
READ Command
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Figure 38: READ Command
Don’t Care
CK
CK#
CS#
WE#
REF#
A
BA
Address
Bank
Address
576Mb: x18, x36 RLDRAM 3
READ Command
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AUTO REFRESH Command
The RLDRAM 3 device uses two unique AUTO REFRESH (AREF) command protocols,
bank address-controlled AREF and multibank AREF. The desired protocol is selected by
setting MR1[8] LOW (for bank address-controlled AREF) or HIGH (for multibank AREF)
during an MRS command. Bank address-controlled AREF is identical to the method
used in RLDRAM2 devices, whereby banks are refreshed independently. The value on
bank addresses BA[3:0], issued concurrently with the AREF command, define which
bank is to be refreshed. The array address is generated by an internal refresh counter,
effectively making each address bit a "Don't Care" during the AREF command. The de-
lay between the AREF command and a subsequent command to the same bank must be
at least tRC.
Figure 39: Bank Address-Controlled AUTO REFRESH Command
CK#
CK
WE#
REF#
CS#
Address
Bank
Address
BA[3:0]
Don’t Care
The multibank AREF protocol, enabled by setting bit MR1[8] HIGH during an MRS
command, enables the simultaneous refresh of a row in up to four banks. In this meth-
od, address balls A[15:0] represent banks [15:0], respectively. The row addresses are gen-
erated by an internal refresh counter for each bank; therefore, the purpose of the ad-
dress balls during an AREF command is only to identify the banks to be refreshed. The
bank address balls BA[3:0] are considered "Don't Care" during a multibank AREF com-
mand.
A multibank AUTO REFRESH is performed for a given bank when its corresponding ad-
dress ball is asserted HIGH during an AREF command. Any combination of up to four
address balls can be asserted HIGH during the rising clock edge of an AREF command
to simultaneously refresh a row in each corresponding bank. The delay between an
AREF command and subsequent commands to the banks refreshed must be at least
tRC. Adherence to tSAW must be followed when simultaneously refreshing multiple
banks. If refreshing three or four banks with the multibank AREF command, tMMD
must be followed. This specification requires two clock cycles between any bank com-
mand (READ, WRITE, AREF) to the multibank AREF or the multibank AREF to any bank
576Mb: x18, x36 RLDRAM 3
AUTO REFRESH Command
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command. Note that refreshing one or two banks with the multibank AREF command is
not subject to the tMMD specification.
The entire device must be refreshed every 64ms (tREF). The RLDRAM device requires
128K cycles at an average periodic interval of 0.489μs MAX (64ms/[8K rows x 16 banks]).
Figure 40: Multibank AUTO REFRESH Command
CK#
CK
WE#
REF#
CS#
Address
Bank
Address
A[15:0]
Don’t Care
576Mb: x18, x36 RLDRAM 3
AUTO REFRESH Command
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INITIALIZATION Operation
The RLDRAM 3 device must be powered up and initialized in a predefined manner. Op-
erational procedures other than those specified may result in undefined operations or
permanent damage to the device.
The following sequence is used for power-up:
1. Apply power (VEXT, VDD, VDDQ). Apply VDD and VEXT before, or at the same time as,
VDDQ. VDD must not exceed VEXT during power supply ramp. VEXT, VDD, VDDQ must
all ramp to their respective minimum DC levels within 200ms.
2. Ensure that RESET# is below 0.2 × VDDQ during power ramp to ensure the outputs
remain disabled (High-Z) and ODT is off (RTT is also High-Z). DQs, and QK signals
will remain High-Z until MR0 command. All other inputs may be undefined dur-
ing the power ramp.
3. After the power is stable, RESET# must be LOW for at least 200μs to begin the initi-
alization process.
4. After 100 or more stable input clock cycles with NOP commands, bring RESET#
HIGH.
5. After RESET# goes HIGH, a stable clock must be applied in conjunction with NOP
commands and all Address pins (A[19:0] & BA[3:0]) to be held low for 10,000 cy-
cles.
6. Load desired settings into MR0.
7. tMRSC after loading the MR0 settings, load operating parameters in MR1, includ-
ing DLL Reset and Long ZQ Calibration.
8. After the DLL is reset and Long ZQ Calibration is enabled, the input clock must be
stable for 512 clock cycles while NOPs are issued.
9. Load desired settings into MR2. If using the RTR, follow the procedure outlined in
the READ Training Function – Back-to-Back Readout figure prior to entering nor-
mal operation.
10. The RLDRAM 3 is ready for normal operation.
576Mb: x18, x36 RLDRAM 3
INITIALIZATION Operation
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Figure 41: Power-Up/Initialization Sequence
DM
Address
CK
CK#
DK
DK#
tCL
Command
tCH
tCK
tDKL
tDKH
tDK
100 cycles
DQ
QVLD1
VEXT
VREF
VDDQ
VDD
RESET#
Stable and
valid clock
Power-up
ramp
T (MAX) = 200ms
QK
QK#
See power-up
conditions
in the
initialization
sequence text
= 20ns
tIOZ
R
TT
T = 200μs (MIN)
READ Training
register specs
apply
tMRSC 512 clock cycles
for DLL Reset &
ZQ Calibration
10,000 CK cycles (MIN)
MR1 MR2
MR0 Valid
All voltage
supplies valid
and stable
NOP NOP NOP ValidMRS
MRSMRS
Don’t Care
or Unknown
Normal
operation
Indicates a break in
time scale
Notes: 1. QVLD output drive status during power-up and initialization:
a. QVLD remains High-Z until 20ns after power supplies are stable and TCK or CK
have cycled 4 times.
b. QVLD will then drive LOW with 40Ω or lower until the output drive value selected
in MR1 is enabled.
576Mb: x18, x36 RLDRAM 3
INITIALIZATION Operation
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c. tMRSC after loading the MR1 settings, QVLD output drive strength will be at the
value selected or lower until ZQ calibration is complete.
d. QVLD will meet the output drive strength specifications upon completion of the
ZQ calibration timing.
2. After MR2 has been issued, Rtt is either High-Z or enabled to the ODT value selected in
MR1.
576Mb: x18, x36 RLDRAM 3
INITIALIZATION Operation
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WRITE Operation
Figure 42: WRITE Burst
tCKDKnom
Command WRITE NOP NOP NOP NOPNOP
Address Bank a,
Add n
NOP
CK
CK#
T0 T1 T2 T3 T4 T5 T5n T6 T6n T7
DK
DK#
DQ
DM
DI
an
tCKDKmin
DQ
DM
DI
an
tCKDKmax
DQ
DM
DI
an
Don’t CareTransitioning Data
WL = 5
DK
DK#
DK
DK#
NOP
WL - tCKDK
WL + tCKDK
Note: 1. DI an = data-in for bank a and address n.
576Mb: x18, x36 RLDRAM 3
WRITE Operation
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Figure 43: Consecutive WRITE Bursts
CK
CK#
Command
WRITE NOP WRITE WRITE NOP NOP NOP NOP NOP
Bank a,
Add n Bank b,
Add n Bank a,
Add n
NOP
Address
T0 T1
T2
T3 T4 T5 T6 T6nT5n T7 T8 T9T8nT7n
DQ
DM
DI
bn DI
an
DI
an
Don’t CareTransitioning Data
WL
tRC
WL
DK
DK#
Indicates a break
in time scale
Note: 1. DI an (or bn or cn) = data-in for bank a (or b or c) and address n.
Figure 44: WRITE-to-READ
Command
NOP READ NOP NOPNOP
Address
Bank a,
Add n
NOP
CK
CK#
T0 T1 T2 T3 T4 T5 T5n T6 T6n T7
DQ
DM
DI
an DO
bn
Don’t Care Transitioning Data
WL = 5
QVLD
DK#
DK
QK#
QK
NOP
Bank b,
Add n
WRITE
RL = 4
Notes: 1. DI an = data-in for bank a and address n.
2. DO bn = data-out from bank b and address n.
576Mb: x18, x36 RLDRAM 3
WRITE Operation
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Figure 45: WRITE - DM Operation
CK
CK#
DK
DK#
tCK tCH tCL
T0 T1 T2 T3 T4 T5 T7nT6 T7 T8T6n
NOPNOP
Command WRITE
Bank a,
Add n
NOPNOP NOP NOP NOP
tDKL tDKH
DQ
DM
DI
an
tDS tDH
Don’t Care
Transitioning Data
Address
WL = 5
NOP
Note: 1. DI an = data-in for bank a and address n.
576Mb: x18, x36 RLDRAM 3
WRITE Operation
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Figure 46: Consecutive Quad Bank WRITE Bursts
Don’t CareTransitioning Data
Command Quad-Bank
WRITE
Quad-Bank
WRITE
NOP NOP NOPNOP
Address
Bank a,
Add n Bank b,
Add n
NOP
CK
CK#
T0 T1 T2 T3 T4 T5 T5n T6 T6n T7nT7
DQ
DM
DI
an DI
bn
WL = 5
tMMD = 2
DK
DK#
NOP
Notes: 1. DI an = data-in for bank a, a+4, a+8, and a+12 and address n.
2. DI bn = data-in for bank b, b+4, b+8, and b+12 and address n.
Figure 47: Interleaved READ and Quad Bank WRITE Bursts
Don’t CareTransitioning Data
Command
READ Quad-Bank
WRITE
NOP READ Quad-Bank
WRITE
NOP
Address
Bank a,
Add n Bank b,
Add n Bank c,
Add n Bank d,
Add n
NOP
CK
CK#
T0 T1 T2 T3 T4 T5 T5n T6 T6n T7 T8 T8n T9 T9n
DQ
DM
DO
an DI
bn
RL = 5
tMMD = 2
DK
QVLD
DK#
QK
QK#
NOP NOP NOP
WL = 6
tMMD = 2 tMMD = 2
Notes: 1. DO an = data-out for bank a and address n.
2. DI bn = data-in for bank b, b+4, b+8, and b+12 and address n.
576Mb: x18, x36 RLDRAM 3
WRITE Operation
PDF: 09005aef84003617
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READ Operation
Figure 48: Basic READ Burst
CK
CK#
tCK tCH tCL
t
QK
t
QKH
t
QKL
tRC = 4
RL = 4
DM
T0 T1 T2 T3 T4 T5 T5n T6nT6 T7
QK
QVLD
QK#
DQ
t
CKQKmin
t
CKQKmin
DO
an
DO
an
NOPNOP
Command READ
Bank a
Add n Bank a
Add n
NOPNOP READ NOP NOP
t
QK
t
QKH
t
QKL
Don’t CareTransitioning Data
Address
QK#
QVLD
QK
DQ
t
CKQKmax
t
CKQKmax
t
QKVLD
t
QKVLD
Note: 1. DO an = data-out from bank a and address an.
576Mb: x18, x36 RLDRAM 3
READ Operation
PDF: 09005aef84003617
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Figure 49: Consecutive READ Bursts (BL = 2)
Command
READ READ READ READ READ READ
Address
CK
CK#
QK
QK#
QVLD
DQ
RL = 4
DO
an DO
bn DO
cn
T0 T1 T2 T3
Bank a
Add n Bank b
Add n Bank c
Add n Bank d
Add n Bank e
Add n Bank f
Add n Bank g
Add n
READ
T4nT4 T5 T6
T5n T6n
Don’t CareTransitioning Data
Note: 1. DO an (or bn, cn) = data-out from bank a (or bank b, c) and address n.
Figure 50: Consecutive READ Bursts (BL = 4)
Command
READ NOP READ NOP READ NOP
Address
Bank a
Add n Bank b
Add n Bank c
Add n Bank d
Add n
CK
CK#
QK
QK#
QVLD
DQ
RL = 4
DO
an DO
bn
T0 T1 T2 T3
READ
T4nT4 T5 T6
T5n T6n
Don’t CareTransitioning Data
Note: 1. DO an (or bn) = data-out from bank a (or bank b) and address n.
576Mb: x18, x36 RLDRAM 3
READ Operation
PDF: 09005aef84003617
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Figure 51: READ-to-WRITE (BL = 2)
CK
CK#
Command
Address
QVLD
DQ
READ WRITE
T0 T1 T2
Don’t CareTransitioning Data
NOP
T3 T4 T5
NOP NOP
T6
NOP
WL = 5
T7 T8
NOP NOP
DK
DK#
QK
DM
QK#
DO
an DI
bn
RL = 4
Bank a,
Add n Bank b,
Add n
NOP NOP
Notes: 1. DO an = data-out from bank a and address n.
2. DI bn = data-in for bank b and address n.
Figure 52: Read Data Valid Window
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Bank,
Addr n
NOPREAD NOPNOP NOP NOP NOP NOP NOP NOP NOP
CK
CK#
Command
Address
QVLD
tQKQx,max
QKx, QKx#
DQ (last data valid)
2
DQ (first data no longer valid)
2
All DQ collectively
2
DO
nDO
n + 3
DO
n + 2
DO
n + 1 DO
n + 7
DO
n + 6
DO
n + 5
DO
n + 4
DO
n + 2
DO
n + 1 DO
n + 7
DO
n + 6
DO
n + 5
DO
n + 4
DO
n + 3
DO
n + 2
DO
n + 1
DO
n DO
n + 7
DO
n + 6
DO
n + 5
DO
n DO
n + 3
Don’t CareTransitioning Data
Data valid Data valid
tQH
tQH
tHZmax
DO
n + 4
RL = 5
tQKQx,max
tLZmin
Notes: 1. DO n = data-out from bank a and address n.
2. Represents DQs associated with a specific QK, QK# pair.
3. Output timings are referenced to VDDQ/2 and DLL on and locked.
4. tQKQx defines the skew between the QK0, QK0# pair to its respective DQs. tQKQx does
not define the skew between QK and CK.
5. Early data transitions may not always happen at the same DQ. Data transitions of a DQ
can vary (either early or late) within a burst.
576Mb: x18, x36 RLDRAM 3
READ Operation
PDF: 09005aef84003617
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AUTO REFRESH Operation
Figure 53: Bank Address-Controlled AUTO REFRESH Cycle
T0 T1 T2 T3
CK#
CK
Command
Address
Bank
DQ
DM
DK, DK#
Don’t Care’
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
tRC
tCK tCH tCL
ACyACx
BAyBAx
AREFx AREFy
Indicates a break
in time scale
Notes: 1. AREFx (or AREFy)= AUTO REFRESH command to bank x (or bank y).
2. ACx = any command to bank x; ACy = any command to bank y.
3. BAx = bank address to bank x; BAy = bank address to bank y.
Figure 54: Multibank AUTO REFRESH Cycle
CK
CK#
Command
AREF AREF
Address
Bank
Bank
0,4,8,12 Bank
1,5,9,13
AREF
DQ
DM
DK, DK#
tRC
tMMD
T0 T1 T2 T3 T4 T5 T6 T7
Don’t Care
Indicates a break
in time scale
tMMD
Bank
2, 3
AC
Bank
0
576Mb: x18, x36 RLDRAM 3
AUTO REFRESH Operation
PDF: 09005aef84003617
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Figure 55: READ Burst with ODT
Command
Address
DQ
ODT
QVLD
DO
an
ODT off
QK
QK#
QK
QK#
QK
QK#
RL = 4
CK
CK#
DQ
ODT
ODT
DO
an
Don’t CareTransitioning Data
DQ
DO
an
READ NOP NOP NOP NOP NOP NOP NOP
Bank a,
Col n
T0 T1 T2 T3 T4n T5nT4 T5 T6n T7nT6 T7
QVLD
QVLD
%/ %/ %/
NOP
ODT on ODT on
ODT off
ODT on on
ODT off
ODT on ODT on
Note: 1. DO an = data out from bank a and address n.
576Mb: x18, x36 RLDRAM 3
AUTO REFRESH Operation
PDF: 09005aef84003617
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Figure 56: READ-NOP-READ with ODT
Command
Address
DQ
ODT
QVLD
DO
an DO
bn
ODT off ODT off
QK
QK#
RL = 4
CK
CK#
Don’t CareTransitioning Data
READ NOP READ NOP NOP NOP NOP NOP
Bank a,
Col n Bank b,
Col n
T0 T1 T2 T3 T4nT4 T5 T6nT6 T7
NOP
ODT on ODT on ODT on
Note: 1. DO an (or bn) = data-out from bank a (or bank b) and address n.
576Mb: x18, x36 RLDRAM 3
AUTO REFRESH Operation
PDF: 09005aef84003617
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2011 Micron Technology, Inc. All rights reserved.
Multiplexed Address Mode
Figure 57: Command Description in Multiplexed Address Mode
Address
Bank
Address
Ax Ay Ax Ay Ax Ay Ay1
Ax1
MRS AREFWRITEREAD
Don’t Care
CK#
CK
CS#
WE#
REF#
BA BA BA BA2
Notes: 1. Addresses valid only during a multibank AUTO REFRESH command.
2. Bank addresses valid only during a bank address-controlled AUTO REFRESH command.
3. The minimum setup and hold times of the two address parts are defined as tIS and tIH.
576Mb: x18, x36 RLDRAM 3
Multiplexed Address Mode
PDF: 09005aef84003617
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Figure 58: Power-Up/Initialization Sequence in Multiplexed Address Mode
DM
Address
CK
CK#
DK
tIOZ = 20ns
DK#
tCL
Command
tCH
tCK
tDKL
tDKH
tDK
100 cycles
DQ
QVLD5
VEXT
VREF
VDDQ
VDD
RESET#
Stable and
valid clock
Power-up
ramp
T (MAX) = 200ms
QK
QK#
See power-up
conditions
in the
initialization
sequence text
R
TT
High-Z
T = 200μs (MIN) tMRSC tMRSC
10,000 CK cycles (MIN)
MR02 (Ax) MR0 (Ay)
MR01MR1 (Ax)
All voltage
supplies valid
and stable
NOP MRS
NOP
MRS
MRS
MR2 (Ax) MR2 (Ay)
MR1 (Ay) V
Va
NOP
MRS
NOP
Don’t Care
or Unknown
Indicates a break
in time scale
512 clock cycles
for DLL Reset &
ZQ Calibration
READ Training
register specs
apply
NOP NOP
Notes: 1. Set address bit MR0[9] HIGH. This enables the device to enter multiplexed address mode
when in non-multiplexed mode operation. Multiplexed address mode can also be en-
tered at a later time by issuing an MRS command with MR0[9] HIGH. After address bit
MR0[9] is set HIGH, tMRSC must be satisfied before the two-cycle multiplexed mode MRS
command is issued.
2. Address MR0[9] must be set HIGH. This and the following step set the desired MR0 set-
ting after the RLDRAM device is in multiplexed address mode.
3. MR1 (Ax), MR1 (Ay), MR2 (Ax), and MR2 (Ay) represent MR1 and MR2 settings in multi-
plexed address mode.
4. The above sequence must be followed in order to power up the RLDRAM device in the
multiplexed address mode.
5. See QVLD output drive strength status during power up and initialization in non-multi-
plexed initialization operation section.
6. After MR2 has been issued, RTT is either High-Z or enabled to the ODT value selected in
MR1.
576Mb: x18, x36 RLDRAM 3
Multiplexed Address Mode
PDF: 09005aef84003617
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Figure 59: MR0 Definition for Multiplexed Address Mode
t
RC_MRS
DLLAM
0
1
0
1
Reserved
MRS Data Latency
Address Bus
Mode Register (Mx)
678
9432105
BA0BA1BA2BA3
18192021 17-10
M19
0
0
1
1
M18
0
1
0
1
Mode Register Definition
Mode Register 0 (MR0)
Mode Register 1 (MR1)
Mode Register 2 (MR2)
Reserved
M8
0
1
DLL Enable
Enable
Disable
M9
0
1
Address MUX
Non-multiplexed
Multiplexed
M4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
M7
0
0
0
0
0
0
0
0
Data Latency (RL & WL)
RL = 3 ; WL = 4
RL = 4 ; WL = 5
RL = 5 ; WL = 6
RL = 6 ; WL = 7
RL = 7 ; WL = 8
RL = 8 ; WL = 9
RL = 9 ; WL = 10
RL = 10 ; WL = 11
RL = 11 ; WL = 12
RL = 12 ; WL = 13
RL = 13 ; WL = 14
RL = 14 ; WL = 15
RL = 15 ; WL = 16
RL = 16 ; WL = 17
Reserved
Reserved
A3
A4A8A9Ay A18.......A10
A18.......A10 A8A9 A0
A4 A3
A5
Ax
M0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
M3
0
0
0
0
0
0
0
0
t
RC_MRS
2
2,3
3
2
4
2
5
6
7
8
9
10
11
12
Reserved
Reserved
Reserved
Reserved
Reserved
Notes: 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
2. BL8 not allowed.
3. BL4 not allowed.
576Mb: x18, x36 RLDRAM 3
Multiplexed Address Mode
PDF: 09005aef84003617
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Figure 60: MR1 Definition for Multiplexed Address Mode
ODT
Reserved
MRS Drive
Mode Register (Mx)
DLLRefBL
2
ZQZQe
18
0
1
0
1
19
20
21 45678910
17-11 3210
M0
0
1
0
1
M1
0
0
1
1
Output Drive
RZQ/6 (40:
RZQ/4 (60:
Reserved
Reserved
M9
0
1
0
1
M10
0
0
1
1
Burst Length
2
Reserved ZQ Calibration Selection
Short ZQ Calibration
Long ZQ Calibration
M2
0
1
0
1
0
1
0
1
ODT
Off
RZQ/6 (40:
RZQ/4 (60:
RZQ/2 (120:
Reserved
Reserved
Reserved
Reserved
M3
0
0
1
1
0
0
1
1
1
1
1
1
M4
0
0
0
0
M19
0
0
1
1
M18
0
1
0
1
Mode Register Definition
Mode Register 0 (MR0)
Mode Register 1 (MR1)
Mode Register 2 (MR2)
Reserved
BA0BA1BA2BA3
DLL Reset
No
Yes
M8
0
1
AREF Protocol
Bank Address Control
Multibank
M7
0
1
M6
0
1
M5
0
1
ZQ Calibration Enable
Disabled - Default
Enable
Address Bus
A3A4
A9
A18.......A13
A18.......A13 A0A3A4A5
A8
Ay
Ax A9 A8A10
Notes: 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
2. BL8 not available in x36.
576Mb: x18, x36 RLDRAM 3
Multiplexed Address Mode
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Figure 61: MR2 Definition for Multiplexed Address Mode
RTREnWRITEReservedMRS
Mode Register (Mx)
17-51819
0
1
0
1
2021 23410
M1
0
0
1
1
M0
0
1
0
1
READ Training Register
0-1-0-1 on all DQs
Even DQs: 0-1-0-1 ; Odd DQs: 1-0-1-0
Reserved
Reserved
M4
0
0
1
1
M3
0
1
0
1
WRITE Protocol
Single Bank
Dual Bank
Quad Bank
Reserved
READ Training Register Enable
Normal RLDRAM Operation
READ Training Enabled
M19
0
0
1
1
M18
0
1
0
1
Mode Register Definition
Mode Register 0 (MR0)
Mode Register 1 (MR1)
Mode Register 2 (MR2)
Reserved
BA0BA1BA2BA3
M2
0
1
Address Bus
A3A4
Ay A18.......A5
A18.......A5 A0
Ax A4 A3
Note: 1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
Table 41: Address Mapping in Multiplexed Address Mode
Data
Width
Burst
Length Ball
Address
A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18
x36 2 AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18
AyX A1 A2 X A6 A7 X A11 A12 A16 A15
4AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 X
AyX A1 A2 X A6 A7 X A11 A12 A16 A15
x18 2 AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18
AyX A1 A2 X A6 A7 A19 A11 A12 A16 A15
4AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18
AyX A1 A2 X A6 A7 X A11 A12 A16 A15
8AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 X
AyX A1 A2 X A6 A7 X A11 A12 A16 A15
Note: 1. X = “Don’t Care”
576Mb: x18, x36 RLDRAM 3
Multiplexed Address Mode
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Data Latency in Multiplexed Address Mode
When in multiplexed address mode, data latency (READ and WRITE) begins when the
Ay part of the address is issued with any READ or WRITE command. tRC is measured
from the clock edge in which the command and Ax part of the address is issued in both
multiplexed and non-multiplexed address mode.
REFRESH Command in Multiplexed Address Mode
Similar to other commands when in multiplexed address mode, both modes of AREF
(single and multibank) are executed on the rising clock edge, following the one on
which the command is issued. However, when in bank address-controlled AREF, as only
the bank address is required, the next command can be applied on the following clock.
When using multibank AREF, the bank addresses are mapped across Ax and Ay so a sub-
sequent command cannot be issued until two clock cycles later.
Figure 62: Bank Address-Controlled AUTO REFRESH Operation with Multiplexed Addressing
CK
CK#
Command
AC1NOP
Ay
AREF AREF AREF AREFAREF AREF AREF AREF AC1
Bank
Bank 0Bank n Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank n
Address
Ax Ay
Ax
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
Don’t Care
Note: 1. Any command subject to tRC specification.
Figure 63: Multibank AUTO REFRESH Operation with Multiplexed Addressing
CK
CK#
Command
AREF
1
NOP
Ay
AREF
1
AREF
1
NOP NOPAC
2
NOP
Bank
Address
Ax Ay
Ax Ay
Ax Ay
Ax
Bank n
T0 T1 T2 T3 T4 T5 T6 T7
Don’t Care
Notes: 1. Usage of multibank AREF subject to tSAW and tMMD specifications.
2. Any command subject to tRC specification.
576Mb: x18, x36 RLDRAM 3
Multiplexed Address Mode
PDF: 09005aef84003617
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Figure 64: Consecutive WRITE Bursts with Multiplexed Addressing
CK
CK#
Command
WRITE NOP
Ay
WRITE WRITE NOP NOP NOP NOP NOP
Bank
Bank a
Ay
NOP
Bank b Bank a
Address
Ax Ax Ax Ay
T0 T1 T2 T3 T4 T5 T6 T6n T7 T8 T9T8nT7n
DQ
DM
DI
b
DI
a
Don’t CareTransitioning Data
WL
tRC
DK
DK#
Indicates a break
in time scale
Note: 1. DI a = data-in for bank a; DI b = data-in for bank b.
576Mb: x18, x36 RLDRAM 3
Multiplexed Address Mode
PDF: 09005aef84003617
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Figure 65: WRITE-to-READ with Multiplexed Addressing
Command
NOP READ NOP NOPNOP
Address
Ax
NOP
CK
CK#
T0 T1 T2 T3 T4 T5 T6 T6n T7nT7 T8nT8
DM
Don’t CareTransitioning Data
WL
QVLD
DK#
DK
QK#
QK
NOP NOP
Bank
Bank a Bank b
WRITE
RL
DQ
DI
aDO
b
Ax AyAy
Indicates a break
in time scale
Note: 1. DI a = data-in for bank a; DI b = data-in for bank b.
Figure 66: Consecutive READ Bursts with Multiplexed Addressing
Command READ NOP READ NOP READ NOP
Address Ax Ay
Bank a
CK
CK#
QK
QK#
Bank
QVLD
DQ
RL
DO
a
T0 T1 T2 T3
READ
T4 T5 T6T5n T6n
Don’t CareTransitioning Data
Bank b Bank c Bank d
Ax Ax Ax
Ay Ay
Indicates a break
in time scale
Note: 1. DO a = data-out for bank a.
576Mb: x18, x36 RLDRAM 3
Multiplexed Address Mode
PDF: 09005aef84003617
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Figure 67: READ-to-WRITE with Multiplexed Addressing
CK
CK#
Command
Address
Bank
QVLD
DQ
READ
T0 T1 T2
Don’t CareTransitioning Data
WRITE NOP
T3 T4 T5 T7n
NOP NOP
T6 T6n
NOP
WL
T7 T8 T9 T9n
NOP NOP
DK
DK#
QK
DM
QK#
DO
an DI
bn
Ax Ay Ay
Bank a
Ax
Bank b
NOP NOP
Indicates a break
in time scale
RL
NOP
Note: 1. DO a = data-out for bank a; DI b = data-in for bank b.
576Mb: x18, x36 RLDRAM 3
Multiplexed Address Mode
PDF: 09005aef84003617
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Mirror Function
The mirror function ball (MF) is a DC input used to create mirrored ballouts for simple
dual-loaded clamshell mounting. If the MF ball is tied LOW, the address and command
balls are in their true layout. If the MF ball is tied HIGH, the address and command balls
are mirrored around the central y-axis (column 7). The following table shows the ball
assignments when the MF ball is tied HIGH for a x18 device. Compare that table to Ta-
ble 1 (page 12) to see how the address and command balls are mirrored. The same balls
are mirrored on the x36 device.
Table 42: 32 Meg x 18 Ball Assignments with MF Ball Tied HIGH
1 2 3 4 5 6 7 8 9 10 11 12 13
A V
SS VDD NF VDDQ NF VREF DQ7 VDDQ DQ8 VDD VSS RESET#
BVEXT VSS NF VSSQ NF VDDQ DM0 VDDQ DQ5 VSSQ DQ6 VSS VEXT
CVDD NF VDDQ NF VSSQ NF DK0# DQ2 VSSQ DQ3 VDDQ DQ4 VDD
DA13 VSSQ NF VDDQ NF VSSQ DK0 VSSQ QK0 VDDQ DQ0 VSSQ A11
EVSS CS# VSSQ NF VDDQ NF MF QK0# VDDQ DQ1 VSSQ A0 VSS
FA9 A5 VDD A4 A3 REF# ZQ WE# A1 A2 VDD NC1A7
GVSS A18 A8 VSS BA0 VSS CK# VSS BA1 VSS A6 A15 VSS
HA10 VDD A12 A17 VDD BA2 CK BA3 VDD A16 A14 VDD A19
JVDDQ NF VSSQ NF VDDQ NF VSS QK1# VDDQ DQ9 VSSQ QVLD VDDQ
KNF VSSQ NF VDDQ NF VSSQ DK1 VSSQ QK1 VDDQ DQ10 VSSQ DQ11
LVDD NF VDDQ NF VSSQ NF DK1# DQ12 VSSQ DQ13 VDDQ DQ14 VDD
MVEXT VSS NF VSSQ NF VDDQ DM1 VDDQ DQ15 VSSQ DQ16 VSS VEXT
NVSS TCK VDD TDO VDDQ NF VREF DQ17 VDDQ TDI VDD TMS VSS
RESET Operation
The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops
LOW. There are no restrictions for when it can go LOW. After RESET# goes LOW, it must
remain LOW for 100ns. During this time, the outputs are disabled, ODT (RTT) turns off
(High-Z), and the DRAM resets itself. Prior to RESET# going HIGH, at least 100 stable CK
cycles with NOP commands must be given to the RLDRAM. After RESET# goes HIGH,
the DRAM must be reinitialized as though a normal power-up was executed. All refresh
counters on the DRAM are reset, and data stored in the DRAM is assumed unknown af-
ter RESET# has gone LOW.
576Mb: x18, x36 RLDRAM 3
Mirror Function
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IEEE 1149.1 Serial Boundary Scan (JTAG)
The RLDRAM 3 device incorporates a serial boundary-scan test access port (TAP) for
the purpose of testing the connectivity of the device after it has been mounted on a
printed circuit board (PCB). As the complexity of PCB high-density surface mounting
techniques increases, the boundary-scan architecture is a valuable resource for inter-
connectivity debug. This port operates in accordance with IEEE Standard 1149.1-2001
(JTAG) with the exception of the ZQ pin. To ensure proper boundary-scan testing of the
ZQ pin, MR1[7] needs to be set to 0 until the JTAG testing of the pin is complete. Note
that upon power up, the default state of the MRS bit M1[7] is low.
The JTAG test access port utilizes the TAP controller on the device, from which the in-
struction register, boundary-scan register, bypass register, and ID register can be selec-
ted. Each of these functions of the TAP controller is described in detail below.
Disabling the JTAG Feature
It is possible to operate an RLDRAM 3 device without using the JTAG feature. To disable
the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI
and TMS are internally pulled up and may be unconnected. They may alternately be
connected to VDDQ through a pull-up resistor. TDO should be left unconnected. Upon
power-up, the device will come up in a reset state, which will not interfere with the op-
eration of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising
edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the
rising edge of TCK.
All the states in Figure 68 (page 105) are entered through the serial input of the TMS
ball. A 0 in the diagram represents a LOW on the TMS ball during the rising edge of TCK,
while a 1 represents a HIGH on TMS.
Test Data-In (TDI)
The TDI ball is used to serially input test instructions and data into the registers and can
be connected to the input of any of the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. For informa-
tion on loading the instruction register, see Figure 68 (page 105). TDI is connected to
the most significant bit (MSB) of any register (see Figure 69 (page 105)).
Test Data-Out (TDO)
The TDO output ball is used to serially clock test instructions and data out from the reg-
isters. The TDO output driver is only active during the Shift-IR and Shift-DR TAP con-
troller states. In all other states, the TDO ball is in a High-Z state. The output changes on
the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any regis-
ter (see Figure 69 (page 105)).
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
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TAP Controller
The TAP controller is a finite state machine that uses the state of the TMS ball at the
rising edge of TCK to navigate through its various modes of operation (see Figure 68
(page 105)). Each state is described in detail below.
Test-Logic-Reset
The test-logic-reset controller state is entered when TMS is held HIGH for at least five
consecutive rising edges of TCK. As long as TMS remains HIGH, the TAP controller will
remain in the test-logic-reset state. The test logic is inactive during this state.
Run-Test/Idle
The run-test/idle is a controller state in between scan operations. This state can be
maintained by holding TMS LOW. From there, either the data register scan, or subse-
quently, the instruction register scan, can be selected.
Select-DR-Scan
Select-DR-scan is a temporary controller state. All test data registers retain their previ-
ous state while here.
Capture-DR
The capture-DR state is where the data is parallel-loaded into the test data registers. If
the boundary-scan register is the currently selected register, then the data currently on
the balls is latched into the test data registers.
Shift-DR
Data is shifted serially through the data register while in this state. As new data is input
through the TDI ball, data is shifted out of the TDO ball.
Exit1-DR, Pause-DR, and Exit2-DR
The purpose of exit1-DR is used to provide a path to return back to the run-test/idle
state (through the update-DR state). The pause-DR state is entered when the shifting of
data through the test registers needs to be suspended. When shifting is to reconvene,
the controller enters the exit2-DR state and then can re-enter the shift-DR state.
Update-DR
When the EXTEST instruction is selected, there are latched parallel outputs of the boun-
dary-scan shift register that only change state during the update-DR controller state.
Instruction Register States
The instruction register states of the TAP controller are similar to the data register
states. The desired instruction is serially shifted into the instruction register during the
shift-IR state and is loaded during the update-IR state.
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
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Figure 68: TAP Controller State Diagram
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
1
1
1
0
1 1
0 0
1 1
1
0
0
0
0 0
0
0
0 0
1
0
1
1
0
1
0
1
1
1
1 0
Test-logic
reset
Run-test/
Idle
Select
IR-scan
Select
DR-scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Figure 69: TAP Controller Functional Block Diagram
0
01234567
012293031 ...
012.. ...
TCK
TMS
Selection
circuitry
Selection
circuitry TDO
TDI
Boundry scan register
Identification register
Instruction register
TAP controller
Bypass register
x1
Note: 1. x = 121 for all configurations.
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
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Performing a TAP RESET
A reset is performed by forcing TMS HIGH (VDDQ) for five rising edges of tCK. This RE-
SET does not affect the operation of the device and may be performed while the device
is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
If JTAG inputs cannot be guaranteed to be stable during power-up it is recommended
that TMS be held HIGH for at least 5 consecutive TCK cycles prior to boundary scan
testing.
TAP Registers
Registers are connected between the TDI and TDO balls and allow data to be scanned
into and out of the RLDRAM 3 device test circuitry. Only one register can be selected at
a time through the instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is
loaded during the update-IR state of the TAP controller. Upon power-up, the instruction
register is loaded with the IDCODE instruction. It is also loaded with the IDCODE in-
struction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the capture-IR state, the two LSBs are loaded with a bina-
ry 01 pattern to allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous
to skip certain chips. The bypass register is a single-bit register that can be placed be-
tween the TDI and TDO balls. This enables data to be shifted through the device with
minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is exe-
cuted.
Boundary-Scan Register
The boundary-scan register is connected to all the input and bidirectional balls on the
device. Several balls are also included in the scan register to reserved balls. The device
has a 121-bit register.
The boundary-scan register is loaded with the contents of the RAM I/O ring when the
TAP controller is in the capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the shift-DR state.
The order in which the bits are connected is shown in Table 49 (page 111). Each bit cor-
responds to one of the balls on the RLDRAM package. The MSB of the register is con-
nected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR
state when the IDCODE command is loaded in the instruction register. The IDCODE is
hardwired into the RLDRAM 3 and can be shifted out when the TAP controller is in the
shift-DR state. The ID register has a vendor code and other information described in
Table 46 (page 110).
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
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TAP Instruction Set
Overview
There are 28 different instructions possible with the 8-bit instruction register. All combi-
nations used are listed in Table 48 (page 111). These six instructions are described in
detail below. The remaining instructions are reserved and should not be used.
The TAP controller used in this RLDRAM 3 device is fully compliant to the IEEE 1149.1
convention.
Instructions are loaded into the TAP controller during the shift-IR state when the in-
struction register is placed between TDI and TDO. During this state, instructions are
shifted through the instruction register through the TDI and TDO balls. To execute the
instruction after it is shifted in, the TAP controller needs to be moved into the update-IR
state.
EXTEST
The EXTEST instruction enables circuitry external to the component package to be tes-
ted. Boundary-scan register cells at output balls are used to apply a test vector, while
those at input balls capture test results. Typically, the first test vector to be applied using
the EXTEST instruction will be shifted into the boundary-scan register using the PRE-
LOAD instruction. Thus, during the update-IR state of EXTEST, the output driver is
turned on, and the PRELOAD data is driven onto the output balls.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the in-
struction register. It also places the instruction register between the TDI and TDO balls
and enables the IDCODE to be shifted out of the device when the TAP controller enters
the shift-DR state. The IDCODE instruction is loaded into the instruction register upon
power-up or whenever the TAP controller is given a test logic reset state.
High-Z
The High-Z instruction causes the bypass register to be connected between the TDI and
TDO. This places all RLDRAM outputs into a High-Z state.
CLAMP
When the CLAMP instruction is loaded into the instruction register, the data driven by
the output balls are determined from the values held in the boundary-scan register.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the
TAP controller is in the capture-DR state, a snapshot can be taken of the states of the
component's input and output signals without interfering with the normal operation of
the assembled board. The snapshot is taken on the rising edge of TCK and is captured in
the boundry-scan register. The data can then be viewed by shifting through the compo-
nent's TDO output.
The user must be aware that the TAP controller clock can only operate at a frequency up
to 50 MHz, while the RLDRAM 3 clock operates significantly faster. Because there is a
large difference between the clock frequencies, it is possible that during the capture-DR
state, an input or output will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm the device, but there is
576Mb: x18, x36 RLDRAM 3
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no guarantee as to the value that will be captured. Repeatable results may not be possi-
ble.
To ensure that the boundary-scan register will capture the correct value of a signal, the
RLDRAM signal must be stabilized long enough to meet the TAP controller’s capture
setup plus hold time (tCS plus tCH). The RLDRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/
PRELOAD instruction. If this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the boundary-scan register.
After the data is captured, it is possible to shift out the data by putting the TAP into the
shift-DR state. This places the boundary-scan register between the TDI and TDO balls.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed
in a shift-DR state, the bypass register is placed between TDI and TDO. The advantage
of the BYPASS instruction is that it shortens the boundary-scan path when multiple de-
vices are connected together on a board.
Reserved for Future Use
The remaining instructions are not implemented but are reserved for future use. Do not
use these instructions.
Figure 70: JTAG Operation - Loading Instruction Code and Shifting Out Data
TMS
TDI
TCK
TDO
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
TAP
Controller
State
Test-Logic-
Reset Run-Test
Idle Capture-IR Shift-IR
Select-DR-
SCAN Select-IR-
SCAN Pause-IR Pause-IRShift IR Exit 1-IR
8-bit instruction
code
Don’t CareTransitioning Data
TMS
TDI
TCK
TDO
TAP
Controller
State
T10 T11 T12 T13 T14 T15 T16 T17 T18
Exit 2-IR Select-DR-
Scan Capture-DR Shift-DR Shift DR Exit1-DR Update-DR Run-Test
Idle
Update-IR
n-bit register
between
TDI and TDO
T19
Run-Test
Idle
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
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Figure 71: TAP Timing
Test clock
(TCK)
Test mode select
(TMS)
Test data-in
(TDI)
Test data-out
(TDO)
T1 T2 T3 T4 T5 T6
Don’t CareUndefined
tTHTL
tMVTH
tDVTH tTHDX
tTLOX
tTHMX
tTLTH tTHTH
tTLOV
Table 43: TAP Input AC Logic Levels
0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V, unless otherwise noted
Description Symbol Min Max Units
Input HIGH (logic 1) voltage VIH VREF + 0.225 - V
Input LOW (logic 0) voltage VIL -V
REF - 0.225 V
Note: 1. All voltages referenced to VSS (GND).
Table 44: TAP AC Electrical Characteristics
0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V
Description Symbol Min Max Units
Clock
Clock cycle time tTHTH 20 ns
Clock frequency fTF 50 MHz
Clock HIGH time tTHTL 10 ns
Clock LOW time tTLTH 10 ns
TDI/TDO times
TCK LOW to TDO unknown tTLOX 0 ns
TCK LOW to TDO valid tTLOV 10 ns
TDI valid to TCK HIGH tDVTH 5 ns
TCK HIGH to TDI invalid tTHDX 5 ns
Setup times
TMS setup tMVTH 5 ns
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
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Table 44: TAP AC Electrical Characteristics (Continued)
0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V
Description Symbol Min Max Units
Capture setup tCS 5 ns
Hold times
TMS hold tTHMX 5 ns
Capture hold tCH 5 ns
Note: 1. tCS and tCH refer to the setup and hold time requirements of latching data from the
boundary-scan register.
Table 45: TAP DC Electrical Characteristics and Operating Conditions
0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V, unless otherwise noted
Description Condition Symbol Min Max Units Notes
Input HIGH (logic 1) volt-
age
V
IH VREF + 0.15 VDDQ V 1, 2
Input LOW (logic 0) voltage VIL VSSQ VREF - 0.15 V 1, 2
Input leakage current 0V ≤ VIN ≤ VDD ILI -5.0 5.0 μA
Output leakage current Output disabled, 0V ≤
VIN ≤ VDDQ
ILO -5.0 5.0 μA
Output low voltage IOLC = 100μA VOL1 0.2 V 1
Output low voltage IOLT = 2mA VOL2 0.4 V 1
Output high voltage |IOHC| = 100μA VOH1 VDDQ - 0.2 V 1
OUTPUT HIGH VOLTAGE |IOHT| = 2mA VOH2 VDDQ - 0.4 V 1
Notes: 1. All voltages referenced to VSS (GND).
2. See AC Overshoot/Undershoot Specifications section for overshoot and undershoot lim-
its.
Table 46: Identification Register Definitions
Instruction Field All Devices Description
Revision number (31:28) abcd ab = 00 for Die Revision A
cd = 00 for x18, 01 for x36
Device ID (27:12) 00jkidef10100111 def = 000 for 576Mb, 001 for 1Gb Double Die Package, 010 for
1Gb Monolithic
i = 0 for common I/O
jk = 10 for RLDRAM 3
Micron JEDEC ID code (11:1) 00000101100 Enables unique identification of RLDRAM vendor
ID register presence indicator (0) 1 Indicates the presence of an ID register
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
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Table 47: Scan Register Sizes
Register Name Bit Size
Instruction 8
Bypass 1
ID 32
Boundary scan 121
Table 48: Instruction Codes
Instruction Code Description
Extest 0000 0000 Captures I/O ring contents; Places the boundary-scan register between TDI and TDO;
This operation does not affect RLDRAM 3 operations.
ID code 0010 0001 Loads the ID register with the vendor ID code and places the register between TDI
and TDO; This operation does not affect RLDRAM 3 operations.
Sample/preload 0000 0101 Captures I/O ring contents; Places the boundary-scan register between TDI and TDO.
Clamp 0000 0111 Selects the bypass register to be connected between TDI and TDO; Data driven by
output balls are determined from values held in the boundary-scan register.
High-Z 0000 0011 Selects the bypass register to be connected between TDI and TDO; All outputs are
forced into High-Z.
Bypass 1111 1111 Places the bypass register between TDI and TDO; This operation does not affect
RLDRAM operations.
Table 49: Boundary Scan (Exit)
Bit# Ball Bit# Ball Bit# Ball
1 N842L783M3
2N843K784M3
3 M11 44 H1 85 M5
4 M11 45 H4 86 M5
5 M946G287L2
6 M947G388L2
7 L12 48 F1 89 L4
8 L12 49 F5 90 L4
9 L10 50 F4 91 L6
10 L10 51 F2 92 L6
11 L8 52 D1 93 K1
12 L8 53 F7 94 K1
13 K13 54 D7 95 K3
14 K13 55 C7 96 K3
15 K11 56 A13 97 J4
16 K11 57 B7 98 J4
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
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Table 49: Boundary Scan (Exit) (Continued)
Bit# Ball Bit# Ball Bit# Ball
17 J10 58 E7 99 J6
18 J10 59 D13 100 K5
19 J8 60 F12 101 J2
20 K9 61 F10 102 A4
21 J12 62 F9 103 A4
22 A10 63 E2 104 A6
23 A10 64 E12 105 A6
24 A8 65 F6 106 B3
25 A8 66 F8 107 B3
26 B11 67 G7 108 B5
27 B11 68 H7 109 B5
28 B9 69 G5 110 C2
29 B9 70 G9 111 C2
30 C12 71 H6 112 C4
31 C12 72 H8 113 C4
32 C10 73 F13 114 C6
33 C10 74 G11 115 C6
34 C8 75 G12 116 E4
35 C8 76 H10 117 E4
36 E10 77 H3 118 D3
37 E10 78 H11 119 D3
38 D11 79 H13 120 E6
39 D11 80 M7 121 D5
40 E8 81 N6 - -
41 D9 82 N6 - -
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
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Revision History
Rev. C, Production – 12/12
• Changed the units from nS to CK for tWTR specification
• Corrected values from 0.935 to 0.9375 in the speed bin table
• Added reference to -125F on front page, part number guide, speed bin table, and
tRC_MRS table
• Added a -125F column into the IDD table
• Updated the Imbref4 IDD values for most fields. This increase is necessary because a
mistake in the char test used to set these limits caused the values to be incorrect
• Corrected typo in the tIS/tIH derating table. (tIH - 0.4 CMD/ADDR slew rate, CK/CK#
4.0 V/ns)
• Changed definition of NOP command to specify the states of WE# & REF#
• Added note on the leaded (PA) package to "Consult factory"
• Updated READ-to-WRITE timing diagram from BL = 4 to BL = 2. The WRITE-to-READ
timing diagram is BL = 2 (I did not want customers to think that a NOP was required
when transitioning from a READ to a WRITE )
• Changed wording in Note 3 of ZQ calibration description
• Added note to general description, which explains using a X36 devices with only 2
QK/QK# sets instead of all 4.
• Modified ball out to reflect the ballout required to support the X18 DDP and the 2Gb
monolithic devices
• Added note to Iref that states: "all other balls not under test = 0V"
• Added updates to -125F speed bin table and tRC_MRS table to meet customer request
to support CL=12, tRC_MRS = 6 for tCK=1.334ns
Rev. B, Advance – 1/12
• Changed tQKQx,min to tQKQx,max in figure 52 read data valid window
• Added Vext information to Note 1 of Input/Output Capacitance table
• Added Table 38 tRC_MRS values
• Updated tIS/tIH(base) values on page 50 to 85,120,170 & 65,100, 120
• Corrected error in High-Z description. replaced "boundry-scan" with "bypass"
• Added verbage in SAMPLE/PRELOAD description, specifying which edge of TCK is
used to capture the states of the pins.
• Changed JTAG boundary scan order. Now L7=bit 42, K7=bit 43, J6=bit 99, K5=bit 100
• Updated Figure 70 "JTAG Operation" to match actual operation of the device.
• Changed QKx, QKx# to DKx, DKx# in table 33 & 34 Derating values for tDS/tDH.
• Changed Cjtag min from 2.0 to 1.5.
• Corrected typo in X36 functional block diagram. Changed DQ1/DK1# to DK1/DK1#.
• Added RESET# and MF pin Ci Max spec into Input/Output Capacitance table 6.
• Listed QVLD with the QK/QK# signals in Table 6.
• Changed tDS Base value from 15 to -15 in Table 33.
• Corrected errors in VSEH min, VSEL max and VILdiff(AC) max definitions.
• Updated Speed bin table 26 to fill in tCK gaps by adjusting tCKmin values for -107E,
RL=5, -125, RL=6,9,14,15.
576Mb: x18, x36 RLDRAM 3
Revision History
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• Updated table 38 tRC_MRS values to reflect the speed bin table changes
• Changed the Cimax (CMD, ADDR) spec from 2.1 to 2.25
• Changed the Cjtag max from 5.3 to 4.5
• Added X18 & X36 IDD values.
• updated tCKQK AC timing specifications.
• Added in the thermal impedance values
Rev. A, Advance – 6/11
• Initial release
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
576Mb: x18, x36 RLDRAM 3
Revision History
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