Comlinear WwW} Corporation CLC522 APPLICATIONS: variable attenuators * pulse amplitude equalizers e RF modulators * automatic gain control & leveling loops video production switching e differential line receivers * voltage controlled filters DESCRIPTION The CLC522 variable gain amplifier (VGA) is a dc-coupled, two- Wideband Variable- Gain Amplifier FEATURES: 330MHz signal bandwidth: Avmax= 2 165MHz gain-control bandwidth * 0.3 to 6OMHz linear phase deviation * 0.04% (-68dB) signal-channel non-linearity e >40dB gain-adjustment range differential or single-end voltage inputs single-ended voltage output Gain vs. Gain Control Voltage (Vg) quadrant multiplier with differential voltage inputs and a single- 0 ended voltage output. Two input buffers and an output operational A] amplifer are integrated with the multiplier core to make the CLC522 4 a complete VGA system that does not require external buffering. > = a The CLC522 provides the flexibility of externally setting the maximum 5 Pa a gain with only two external resistors. Greater than 40dB gain control Z| is easily achieved through a single high impedance voltage input. LT The CLC522 provides a linear (in Volts per Volt) relationship o}< between the amplifiers gain and the gain-control input voltage. 14 Gain Control Voltage, V, (Valts) i The CLC522's maximum gain may be set anywhere over a nominal range of 2V/V to 100V/V. The gain control input then provides PINOUT attenuation from the maximum setting. For example, set for a = maximum gain of 100V/V, the CLC522 will provide a 100V/V to 1V/V Voc Li} @ [14] +Voc gain control range by sweeping the gain control input voltage from Vo [21 M3] #Voc +1 to -0.98V. vel SN fe wo Set at a maximum gain of 10V/V, the CLC522 provides a 165MHz +R, [4] Oo [17] GND signal channel bandwidth and a 165MHz gain control bandwidth. Ay [5] Lidl Vou Gain nonlinearity over a400B gain range is 0.5% and gain accuracy Vn [6] [9] Ver at Avnax = 10V/V is typically +0.3%. Vee [7 3] Vee Va Ry c TYPICAL APPLICATION a 2nd Order Tuneable Bandpass Filter Rp 1 R Mo _ (- 1 CR, 7 1 k c Vin Ms? +5 + 45 T CR, CR, Kee cates Q_vK _ vk + t 5? _ cm R, Ry CR, Comlinear Corporation 4800 Wheaton Drive e Fort Collins, CO 80525 (800) 776-0500 FAX (303) 226-0564 DS522.03 me 2279101 0001578 175 | June 1994CLC522 Electrical Characteristics (v.. = +5V; Avo = +10; R,=1kQ; Ry =1820; R, = 1000; V,=+1.1V) PARAMETERS CONDITIONS TYP GUARANTEED MIN/MAX UNITS _||NOTES Ambient Temperature AJE,AJP +25 +25 Oto+70 | -40to+85 || C 1 FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vou < 0.5V op 165 120 115 110 MHz 3 Vout < 5.0Vo, 150 100 95 90 MHz gain control bandwidth Vou < 0.5V>, 165 120 115 110 MHz 4 gain flatness Vou < 0.5V 50 peaking DC to 30MHz 0 0.1 0.1 0.1 dB 3 rolloff DC to 30MHz 0.05 0.25 0.25 1.3 dB 3 linear phase deviation DC to 6OMHz 0.3 1.0 1.1 1.2 feedthrough 30MHz - 62 - 57 - 57 -57 dB 3,5 TIME DOMAIN RESPONSE rise and fall time 0.5V step 2.2 2.9 3.0 3.2 ns 5.0V step 3.0 5.0 5.0 5.0 ns settling time 2.0V step to 0.1% 12 18 18 18 ns overshoot 0.5V step 2 15 15 15 % slew rate 4.0V step 2000 1400 1400 1400 Vius DISTORTION AND NOISE RESPONSE 2 harmonic distortion 2Vp 2OMHz - 50 - 44 -44 -44 dBc 3 37 harmonic distortion 2V pp, 20MHz - 65 -58 - 56 -54 dBc 3 equivalent input noise 1 to 200MHz 5.8 6.2 6.5 6.8 nV/VHz noise floor 1 to 200MHz - 152 - 150 - 149 - 149 dBmun, GAIN ACCURACY signal channel nonlinearity (SGNL) Vou= +2Vpp 0.04 0.1 0.1 0.1 % 2 gain control nonlinearity (GcnL) full range 0.5 2.0 2.2 3.0 % 2 gain error (Gaccu) AVinax=+10 + 0.0 +0.5 + 0.5 +1.0 dB 2 Vg high + 990 +990+60 | +990+60 | +990260 || mV low - 975 - 975280 {| -975+80 | -975+80 || mV STATIC DC PERFORMANCE Vin voltage range common mode 2.2 1.2 +1.2 +14 Vv bias current 9 21 26 45 HA 2 average drift 65 --- 175 275 nAvrc offset current 0.2 2.0 3.0 4.0 pA average drift 5 --- 30 40 nA/PC resistance 1500 650 450 175 kQ capacitance 1.0 2.0 2.0 2.0 pF Vg bias current 15 38 47 82 LA average drift 125 _ 300 600 nA/rC resistance 100 38 30 15 kQ capacitance 1.0 2.0 2.0 2.0 pF output voltage range R,= +4.0 +3.7 + 3.6 +3.5 Vv current +70 +47 + 40 +25 mA offset voltage AVmax=t+10 25 85 95 120 mV 2 average drift 100 --- 350 400 pVv/eC resistance 0.1 0.2 0.3 0.6 Q IRgmax 1.8 1.37 1.26 1.15 mA power supply sensitivity output referred 10 40 40 40 mv/V 3 common-mode rejection ratio input referred 70 59 59 59 dB supply current R= ce 46 61 62 63 mA 2 Absolute Maximum Ratings Ordering Information supply voltage +7V Model Temperature Range Description short circuit current 96mA CLC522AJP -40C to +85C 14-pin PDIP common-mode input voltage +V.. CLOS522AJE -40C to +85C 14-pin SOIC maximum junction temperature +200C CLC522ALC -40C to +85C dice Storage temperature 65C to+150C CLC522A8B* -55C to +125C 14-pin CerDIP, MiL-STD-883 lead temperature (soldering 10 sec) +300C CLC522AMC* 55C to +125C dice, MIL-STD-883 CLC522A8L-2* -55C to +125C 20pin LCC, MIL-STD-883 1) AJE (SOIC) is tested/guaranteed with R=866Q andRy=1650. See CLC522 MIL-883 Data Sheet for Specifications 2) J-level, spec is 100% tested at +25C, sample tested at +85C. L-level, spec is 100% wafer probed at 25C. 3) J-level, spec is sample tested at 25C. 4) Tested with Vin = 0.2V and Vg < 0.5Vpp. 5) Feedtrough is tested at maximum attenuation (i.e Vg =-1.1V) Comlinear reserves the right to change specifications without notice. @ 2279101 0001579 031 QoFull Scale Non-linearity (%) PSRR/CMAR (dB) Settling Error (%) CLC522 Typical Performance Frequency Response (Ay,,ax=2) PSRR and CMRR (Input Referred) RR =~ Be woFt om n oo oOo 09CO Oo 8 & o 6 ney (Hz) 104 j05 0 SGNLvs. 10 10 Freque! , Gain Vg (Volts) Time & Aymax = +10 Vig = 0.25V DC Gain Control 5Vidiv. Vg=-1 Time (5ns/div) Long Term Settling Time AVmax = + 10 2V output step Vg=1.0V oe 10 10 107 10 40 104 10 10 10' 4 Time (sec) > Vout = 2Vpp 8 2 |] Gain 2 iN a on s <= x= = @ = uu 2 0 8 = -45 a 8 -90 & 135 2 -180 -270 1 Frequency (MHz) 500 (A/a) ureD Qo Gain(dB) Settling Time, TS, (ns), to 0.1% (Ta=+25C, Vec=t5V, Av=+10, Vg=1.1V, RL=100Q; unless noted) Magnitude (1dB/div) 100mV/div 50 40 w i=J 20 10 Normalized Magnitude (1dB/div) Frequency Response (Aymax=10) Frequency Response (Av a,=100) 70 wy Vour = 500m a Vin = 25m p Gain @ =|] Gain @ > am f ao ao ao 2 3 +o = = = = 2 Zz ao = 0 s 0 iJ 44 #2 -45 ca -90 S -90 R,=182Q 1 ER 10.20 Vv 8 o= 2 g= IU. R= 1kQ 1800 = FR 27150 180 -270 -270 1 Frequency (MHz) 200 1 Frequency (MHz) 400 Feed-through Isolation Gain Flatness & Linear Phase Deviation < Avmax + 10 e Y Gain Rie 1k & oe > Vget.1 US < = = S 3 = = Ss 5 3 & 2 x4 2 2 > wn 0 ; Frequency (MHz) Frequency (3MHz/div) 30MHz Large Signal Frequency Response Large & Small Signal Pulse Response Vy = xz Avmay = +10 A =42 0 max Rk Va=ttV 18 3iF wy=t.ov Vout = 5Vpp +75 BS _oll Rr=1ka 50 10 & 3 ot =+ 1 25 3 Ri= 1kO o = Vout = 0.5Vpp = 45 0 s 2 2 0 St Bs 135 = 480 2 50 & Avmax = +100 y= B06 25 7 0 Frequency (25MHz/div) 250 Time (Sns/div) Gain Control Channel Feedthrough Short Term Settling Time 2 Vin = 0 AVmax= + 10 Vp Input 1S 2V output step 04 Vg= 1.0V se Tr 05 S wo 2 =-05 Output 3 1 -15 2 Time (5ns/div) 0 Time (10ns/div) 100 Settling Time vs. Capacitive Load 100 Settling Time vs. Gain 30 = 110 Hoo as 80 40 70 50 35 60 S 30 50 2 25) 408 FE 20 > 30 15 20 10 10 5 0 Ql 10 100 0 2 4 6 8 10 12 14 Load Capacitance, C, (pF) Attenuation From Maximum Gain (dB) Mm 2279101 00015480 453 f 5_ Differential Gain (%) Distortion Level (dBc) Differential Gain and Phase CLC522 Typical Performance (Ta=+25C, Vec=45V, Av=+10, Vg=1.1V, Ri=10002; unless noted Differential Gain and Phase ) Input Referred Voltage Noise vs Avmax 100 25 a43MHz || ' aa3MHz | Gain Avmax = +10 Phase, Vg = 0.0V Positive Sync || 20|+ Negative Sync | Vg=1.0V - 208 08 4 Avmax = +2 08 & || 2a \ gz Phase wep ss 151 15 & 3.06 06 & Negative Syne Phase eo 7 3 Sod Positive Sync 23 Phase, Vg i B 3" 10 10% 5.04|b Gain, Vg = 1.0V oe in a 5 , Be Positive Sync 3 Oo ; ss 05 a = 052 .02)/- v 028 7 Ln Gain, Vg=0.0V 0 0 0 0 1 1 2 3 i 2 3 4 0 10 20 40 40 50 60 70 80 90 100 Numberof 1502 Loads Number of 150Q Loads Maximum Gain Setting, AVmax (VV) 2nd Harmonic Distortion vs. Pout 3rd Harmonic Distortion vs. Pout 0 -1dB Compression at Maximum Gain 35 VR Output 40 500 SOMHz 19 Limited t- 522 ~~ 18 ZA=1.4kQ {| 45 z a Y g -50 317 = ss 20MHz 5 46 a @ - 2 & 8 45 Input ~~ = 60 2 Limited = -65 14 Rr = 9002 & -70 S iy a a 2 son 500 Py 75 = 12 > -B0 1 500 200 -85 10 4 0 2 4 6 10 0 Frequency (MHz) 100 Output Power (Pout, dBm) Application Discussion Theory of Operation Vin The CLC522 is a linear wideband variable-gain amplifier since In = R. as illustrated in Fig 1. A voltage input signal may be g applied differentially between the two inputs (+Vin, -Vin), R. (V,+1 or single-endedly by grounding one of the unused inputs. A., =185*-+} 2 V Eq. 2 Vg Rg 2 q. The CLC522 input buffers convert the input voltage to a current (lpg) that is a function of the differential input voltage (Vin=+Vin - -Vin) and the value of the gain-setting resistor (Rg). This current (Ipg) is then mirrored to a gain stage with a current gain of 1.85. The voltage-controlled two-quadrant multiplier attenuates this current which is then converted to a voltage via the output amplifier. This output amplifier is a current-feedback op amp configured as a transimpedance amplifier. It's ttansimpedance gain is the feedback resistor (R;). The input signal, output, and gain control are all voltages. The output voltage can easily be calculated and is expressed in Eq. 1. V, Vout =le #1.85+| 2 Eq. 1 out R 9 ( 2 q +1 jr me 2279101 00015461 777 The gain of the CLC522 is therefore a function of three external variables; Rg, Ry and Vg as expressed in Eq. 2. The gain-control voltage (Vg) has a ideal input range of -1V<Vg<+1V. At Vg=+1V, the gain of the CLC522 is at its maximum as expressed in Eq. 3. = 195 81 Rg Notice also that Eq. 3 holds for both differential and single-ended operation. AV ax Eq. 3 Choosing R; and Rg Rg is calculated using Eq.4. Vi,,,., is the maximum peak V; Rg= Eq. 4 Ip Gmax input voltage (Vpx) determined by the application. TRomax is the maximum allowable current through Rg and is typically 1.8mA. Once Avy,,,, is determined from the minimum input and desired output voltages, Ry is then determined using Eq. 5. These values of Ry and Rg are 1 R; =*R,g#A 185 9 Ym the minimum possible vaules that meet the input voltage and maximum gain constraints. Scaling the resistor values will decrease bandwidth and improve stability. U Eq. 5Bandwidth vs. Vinmax VS. AVmax tw o = oQ Maximum Input Voltage, Vin (Voltspp) Vou=1Vpp 0.05 10 100 Maximum Gain Setting, Avmax (V/V) Fig. 2 Fig. 2 illustrates the resulting CLC522 bandwidths as a function of the maximum and minimum input voltages when Vout is held constant at 1Vpp. Adjusting Offsets Treating the offsets introduced by the input and output stages of the CLC522 is easily accomplished with a two Step process. The offset voltage of the output stage is treated by first applying -1.1Volts on Vg, which effectively +5V T C7 0.1nF 5SVvOO= Fig. 3 isolates the input stage and multiplier core from the output stage. As illustrated in Fig. 3, the trim pot located at R14 on the CLC522 Evaluation Board should then be adjusted in order to null the offset voltage seen at the CLC522's output (pin 10). Once this is accomplished, the offset errors introduced by the input stage and multiplier core can then be treated. The second step requires the absence of an input signal and matched source imped- ances on the two input pins in order to cancel the bias current errors. This done then +1.1Volts should be applied to Vg and the trim pot located at R10 adjusted in order to null the offset voltage seen at the CLC522's output. If a more limited gain range is anticipated, the above adjustments should be made at these operating points. Gain Errors The CLC522's gain equation as theoretically expressed in Eq. 2 must include the device's error terms in order to yield the actual gain equation. Each of the gain error M@ 2279101 0001542 bch terms are specified in the Electrical Characteristics table and are defined below and illustrated in Fig. 4. Gaccu : error of Ay,.,, expressed as +dB. GCNL : deviation from theoretical expressed as +%. Vonigh : voltage on Vy producing Ay... - Vo.ow : Voltage on Vg producing Av nin = OWN. AV, AV, :errorofV iVq_ expresedas+mvV. Shigh Stow Sigh? Slow pres Av 4 } Avinax +GaCCU 4 Leok, ' T - Avmin . ~ I ie tAVg *AV guigh | a V T T 9 Vow Vorugh Fig. 4 Combining these error terms with Eq. 2 gives the "gain envelope" equation and is expressed in Eq. 7. From the Electrical Characteristics table, the nominal endpoint values of Vg are: Vonig, =+990MV and Vg, = -975mV. (Ay,,, tGaccu)(V, - Vow # Ay = (Man + AV. oh ~ VOen + Woy ) tAy | (1-Vg? }@cnt Eq.7 Signal-Channel Nonlinearity Signal-channel nonlinearity, sant, also known as integral endpoint linearity, measures the non-linearity of an amplifiers voltage transfer function. The CLC522's SGNL, as it is specified in the Electrical Characteristics table, is measured while the gain is set at its maximum (i.e. Vg=+1.1V). The Typical Performance Characteristics plot labled "SGNL & Gain vs V," illustrates the CLC522's SGNL as Vg is swept through its full range. As can be seen in this plot, when the gain as reduced from Avmax , SGNL improves to < 0.02%(-74dB) at Vg=0 and then degrades somewhat at the lowest gains. Noise Fig. 5 describes the CLC522's input-refered Spot noise density as a function of Aya, . The plot includes all the noise contributing terms. At Avmax = 10V/V, the CLC522 has a typical input-referred spot noise density (ni) of 5.8nV/VHz. The input rms voltage noise can be deter- mined from the following single-pole model: Vams = @ni*y1.57*(-3dB bandwidth) Eq. 8 Further discussion and plots of noise and the noise model is provided in Application Note OA-23. Comlinear also provides SPICE models that model internal noise and other parameters for a typical part. S Input Referred Voltage Noise vs Aymax Voltage Noise (nV/VHz) 0 10 20 30 40 50 60 70 80 90 100 Maximum Gain Setting, Avmax (V/V) Fig. 5 Circuit Layout Considerations Good high-frequency operation requires all of the de- coupling capcitors shown in Fig. 6 to be placed as close as possible to the power supply pins in order to insure a proper high-frequency low-impedance bypass. Adequate oul Soar fos pF o-mrl Pave ome Fig. 6 ground plane and low-inductive power returns are also required of the layout. Minimizing the parasitic capaci- tances at pins 3, 4, 5, 6, 9, 10 and 12 as shown in Fig. 7 will assure best high frequency performance. Vref (pin 9) +Vin Fig. 7 to ground should include a small resistor value of 25 ohms or greater to buffer the internal voltage follower. The parasitic inductance of component leads or traces to pins 4, 5 and 9 should also be kept to a minimum. Parasitic or load capacitance, C., on the output (pin 10) degrades phase margin and can lead to frequency re- sponse peaking or circuit oscillation. This should be treated with a small series resistor between output (pin 10) and C, (see the plot Settling Time vs. Capacitive Load" for a recommended series resistance). Component parasitics also influence high frequency results, therefore it is recommended to use metal film Me 2279101 0001583 5be mm resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not recommended. If socketing is necessary, it is recom- mended to use low impedance flush mount connector jacks such as Cambion (P/N 450-2598). For additional layout information refer to the CLC522's Evaluation Board literature. Application Circuits Four-Quadrant Multiplier Applications requiring multiplication, squaring or other non-linear functions can be implemented with four-quad- rant multipliers. The CLC522 implements a four-quad- rant multiplier as illustrated in figure 8. aR = 2Ry Rim = 735 We Vearrier Rs Vbaseband of Rr Vout Rg R;=Rril Rom Il As Fig. 8 Frequency Shaping Frequency shaping and bandwidth extension of the CLC522 can be accomplished using parallel networks connected across the Rg ports. The network shown in the Fig. 9 schematic will effectively extend the CLC522s bandwidth. +Vin Ri Fig. 9 2nd Order Tuneable Bandpass Filter The CLC522 Variable-Gain Amplifier placed into feed- back loops provide signal processing functions such as 2nd order tuneable bandpass filters. The center fre- quency of the 2nd order bandpass illustrated on the front page is adjusted through the use of the CLC522's gain- control voltage, Vg. The integrators implemented with two CLC420s, provide the coefficients for the transfer function. (