1. General description
The 74LVC244A; 74LVCH244A is an octal non-inverting buffer/line driver with 3-state
outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE.
A HIGH on nOE causes the outputs to assume a high-impedance OFF-st ate.
Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise
and fall times.
Inputs can be driven from either 3.3 V or 5.0 V devices. In 3-state operation, outputs can
handle 5 V. These features allow the use of these devices as translators in a mixed
3.3 Vand 5 V environment.
The 74LVCH244A bus hold on data inputs eliminates the need for external pu ll-up
resistors to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance when VCC = 0 V
Bus hold on all data inputs (74LVCH244A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
Rev. 7 — 22 November 2011 Product data sheet
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 2 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
3. Ordering information
4. Functional diagram
Tabl e 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC244AD 40 C to +125 C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74LVCH244AD
74LVC244ADB 40 C to +125 C SSOP20 plastic shrink small ou tline package; 20 leads;
body width 5.3 mm SOT339-1
74LVCH244ADB
74LVC244APW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74LVCH244APW
74LVC244ABQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
SOT764-1
74LVCH244ABQ
74LVC244ABX 40 C to +125 C DHXQFN20U plastic dual in-line compatible thermal enhanced
extremely thin quad flat package; no leads; 20
terminals; UTLP based; body 2.5 4.5 0.5 mm
SOT1045-1
74LVCH244ABX
Fig 1. Logic symbol
mna874
8
6
4
2
1A0
1A1
1A2
1A3
1OE
18
16
1Y0
1Y1
1Y2
1Y3
14
12
1
11
13
15
17
2A0
2A1
2A2
2A3
2OE
3
5
2Y0
2Y1
2Y2
2Y3
7
9
19
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 3 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
Fig 2. IEC logic diagram Fig 3. Functional diagram
12
14
2
4
6
8
18
16
1EN
mna873
3
5
11
13
15
17
9
7
19 EN
mna875
1A3
1A2
1A1
1A0
2
4
6
8
1
1Y0
1Y1
18
16
14
12
1Y2
1Y3
1OE
2A3
2A2
2A1
2A0
17
15
13
11
19
2Y0
2Y1
3
5
7
9
2Y2
2Y3
2OE
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 4 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration for SO20 and (T)SSOP20 Fig 5. Pin configu ration for DHVQFN20 and
DHXQFN20U
74LVC244A
74LVCH244A
1OE VCC
1A0 2OE
2Y0 1Y0
1A1 2A0
2Y1 1Y1
1A2 2A1
2Y2 1Y2
1A3 2A2
2Y3 1Y3
GND 2A3
001aad113
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
001aad114
74LVC244A
74LVCH244A
Transparent top view
GND(1)
GND
2A3
1OE
VCC
912
8 13
7 14
6 15
5 16
4 17
3 18
2 19
10
11
1
20
terminal 1
index area
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
2OE
1Y0
2A0
1Y1
2A1
1Y2
2A2
1Y3
Table 2. Pin description
Symbol Pin Description
1OE, 2OE 1, 19 output enable input (active low)
1A0, 1A1, 1A2, 1A3 2, 4, 6, 8 data input
2Y0, 2Y1, 2Y2, 2Y3 3, 5, 7, 9 data output
GND 10 ground (0 V)
2A0, 2A1, 2A2, 2A3 17, 15, 13, 11 data input
1Y0, 1Y1, 1Y2, 1Y3, 18, 16, 14, 12 data output
VCC 20 supply voltage
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 5 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C derate linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN20 and DHXQFN20U packages: above 60 C derate linearly with 4.5 mW/K.
Table 3. Function table [1]
Control Input Output
nOE nAn nYn
LLL
LHH
HXZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clam pi n g cu rre nt VI<0V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO>V
CC or VO<0V - 50 mA
VOoutput voltage output HIGH or LOW [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.5 V
IOoutput current VO=0V toV
CC -50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C[3] -500mW
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 6 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - 3.6 V
VIinput voltage 0 - 5.5 V
VOoutput voltage output HIGH or LOW 0 - VCC V
output 3-state 0 - 5.5 V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC = 1.2 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65
VCC
-V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage
VI=V
IH or VIL
IO=100 A;
VCC =1.65Vto3.6V VCC 0.2 - - VCC 0.3 - V
IO=4mA; V
CC = 1.65 V 1.2 - - 1.05 - V
IO=8mA; V
CC = 2.3 V 1.8 - - 1.65 - V
IO=12 mA; VCC = 2.7 V 2.2 - - 2 . 0 5 - V
IO=18 mA; VCC = 3.0 V 2.4 - - 2 . 2 5 - V
IO=24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage
VI=V
IH or VIL
IO=100A;
VCC = 1.65 V to 3.6 V --0.2 - 0.3V
IO=4mA; V
CC = 1.65 V - - 0.45 - 0.65 V
IO=8mA; V
CC = 2.3 V - - 0.6 - 0.8 V
IO=12mA; V
CC = 2.7 V - - 0.4 - 0.6 V
IO=24mA; V
CC = 3.0 V - - 0.55 - 0.8 V
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 7 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25C.
[2] The bus hold circuit is switched off when VI>V
CC allowing 5.5 V on the input terminal.
[3] Valid for data inputs of bus hold parts only (74LVCH244A). Note that control inputs do not have a bus hold circuit.
[4] The specified sustaining current at the data input holds the input below the specified VI level.
[5] The specified overdrive current at the data input forces the data input to the opposite input state.
IIinput
leakage
current
VI= 5.5 Vor GND;
VCC =3.6V [2] -0.1 5-20 A
IOZ OFF-state
output
current
VI=V
IH or VIL;
VO= 5.5 V or GND;
VCC =3.6V
[2] -0.1 5-20 A
IOFF power-off
leakage
current
VIor VO=5.5V; V
CC = 0.0 V - 0.1 10 - 20 A
ICC supply
current VI=V
CC or GND; IO=0A;
VCC =3.6V -0.110 - 40A
ICC additional
supply
current
per input pin;
VI=V
CC 0.6 V; IO=0A;
VCC = 2.7 V to 3.6 V
- 5 500 - 5000 A
CIinput
capacitance -4.0- - -pF
IBHL bus hold
LOW current VCC = 1.65 V; VI = 0.58 V [3][4] 10 - - 10 - A
VCC = 2.3 V; VI = 0.7 V 30 - - 25 - A
VCC = 3.0 V; VI = 0.8 V 75 - - 60 - A
IBHH bus hold
HIGH
current
VCC = 1.65 V; VI = 1.07 V [3][4] 10 - - 10 - A
VCC = 2.3 V; VI = 1.7 V 30 - - 25 - A
VCC = 3.0 V; VI = 2.0 V 75 - - 60 - A
IBHLO bus hold
LOW
overdrive
current
VCC = 1.95 V [3][5] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
IBHHO bus hold
HIGH
overdrive
current
VCC = 1.95 V [3][5] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 8 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
10. Dynamic characteristics
[1] Typical values are measured at Tamb =25C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CLVCC2fo) = sum of the outputs.
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation
delay nAntonYn; see Figure 6 [2]
VCC = 1.2 V - 17.0 - - - ns
VCC = 1.65 V to 1.9 5 V 1.5 6.4 13.7 1.5 15.8 ns
VCC = 2.3 V to 2.7 V 1.0 3.4 7.1 1.0 8.2 ns
VCC = 2.7 V 1.5 3.4 6.9 1.5 9.0 ns
VCC = 3.0 V to 3.6 V 1.5 2.9 5.9 1.5 7.5 ns
ten enable time nOE to nYn; see Figure 7 [2]
VCC = 1.2 V - 24.0 - - - ns
VCC = 1.65 V to 1.9 5 V 1.5 7.0 17.3 1.5 20.0 ns
VCC = 2.3 V to 2.7 V 1.5 3.9 9.5 1.5 11.0 ns
VCC = 2.7 V 1.5 4.1 8.6 1.5 11.0 ns
VCC = 3.0 V to 3.6 V 1.0 3.2 7.6 1.0 9.5 ns
tdis disable time nOE to nYn; see Figure 7 [2]
VCC = 1.2 V - 9.0 - - - ns
VCC = 1.65 V to 1.9 5 V 2.2 4.5 9.8 2.2 11.3 ns
VCC = 2.3 V to 2.7 V 0.5 3.6 5.5 0.5 6.4 ns
VCC = 2.7 V 1.5 3.3 6.8 1.5 8.5 ns
VCC = 3.0 V to 3.6 V 1.5 3.1 5.8 1.5 7.5 ns
tsk(o) output skew
time [3] --1.0- 1.5ns
CPD power
dissipation
capacitance
per input; VI=GNDtoV
CC [4]
VCC = 1.65 V to 1.95 V - 6.4 - - - pF
VCC = 2.3 V to 2.7 V - 9.6 - - - pF
VCC = 3.0 V to 3.6 V - 12.5 - - - pF
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 9 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
11. AC waveforms
Measurement points are given in Table 8.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. The input (nAn) to output (nYn) propagation delays
mna171
nAn input
nYn output
tPLH tPHL
GND
VI
VM
VM
VM
VM
VOH
VOL
Measurement points are given in Table 8.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. 3-state enable and dis a b l e times.
mna362
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Table 8. Measurement points
Supply voltage Input Output
VCC VIVMVMVXVY
1.2 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
1.65 V to 1.95 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.3 V to 2.7 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 10 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
CL
RT
RL
RL
G
Table 9. Test data
Supply voltage Input Load VEXT
VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
1.2 V VCC 2ns 30pF 1 kopen 2 VCC GND
1.65 V to 1.95 V VCC 2ns 30pF 1 kopen 2 VCC GND
2.3 V to 2.7 V VCC 2ns 30pF 500open 2 VCC GND
2.7V 2.7V 2.5 ns 50 p F 500 open 2 VCC GND
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 11 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
12. Package outline
Fig 9. Package outline SOT163-1 (SO20)
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 12 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
Fig 10. Package outline SOT339-1 (SSOP20)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 13 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
Fig 11. Package outline SOT360-1 (TSSOP20)
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 14 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
Fig 12. Package outline SOT764-1 (DHVQFN20)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.6
4.4
Dh
3.15
2.85
y1
2.6
2.4 1.15
0.85
e1
3.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT764-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT764-1
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
29
19 12
11
10
1
20
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 15 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
Fig 13. Package outline SOT1045-1 (DHXQFN20U)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT1045-1 - - -- - -
SOT1045-1
07-12-01
09-08-04
UNIT A
max
mm 0.5 0.05
0.00 0.30
0.18 3.35
3.05 2.6
2.4 1.35
1.05 0.5 0.45
0.25 0.13
0.05 0.05
A1
DIMENSIONS (mm are the original dimensions)
DHXQFN20U: plastic dual in-line compatible thermal enhanced extremely thin quad flat package;
no leads; 20 terminals; UTLP based; body 2.5 x 4.5 x 0.5 mm
b D
4.6
4.4
DhE Ehe e1
3.5
L L1v
0.1
w y
0.05
y1
0.1
C
y
C
y1
X
b
terminal 1
index area e1
e
e
AC B
vMCw M
Dh
Eh
L1
L
29
10
1
20
19 12
11
terminal 1
index area
B A
D
E
detail X
A1
A
0 2.5 5 mm
scale
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 16 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charged Device Mo del
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC_LVCH244A v.7 20111122 Product data sheet - 74LVC_LVCH244A v.6
Modifications: •The format of this document has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage
ranges.
74LVC_ LVCH244A v.6 20090813 Product data sheet - 74LVC_LVCH244A v.5
74LVC_ LVCH244A v.5 20090709 Product data sheet - 74LVC_LVCH244A v.4
74LVC_ LVCH244A v.4 20031030 Product specification - 74LVC_LVCH244A v.3
74LVC_LVCH244A v.3 20030520 Product specification - 74LVC_H2 44A v.2
74LVC_H244A v.2 19980520 Product specification - 74LVC244A_74LVCH244A v.1
74LVC244A_7 4LVCH244A v.1 19960906 Product specification - -
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 17 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short dat a sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole re sponsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with their
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Not hing in this document may be interpret ed or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyri ghts, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document cont ains data from the pre liminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVC_LVCH244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 22 November 2011 18 of 19
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors prod uct is automotive qualified,
the product is not suitable for automotive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever cust omer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 November 2011
Document identifier: 74LVC_LVCH244A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16 Contact information. . . . . . . . . . . . . . . . . . . . . 18
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19