K7B401825M 256Kx18 Synchronous SRAM
- 1 - Rev. 2.0
December 1998
Document Title
256Kx18-Bit Synchronous Burst SRAM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
0.3
1.0
2.0
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
History
Initial draft
Modify power down cycle timing & Interleaved read timing,
Insert Note 4 at AC timing characteristics.
Change ISB1 value from 10mA to 30mA.
Change ISB2 value from 10mA to 20mA.
Change Undershoot spec
from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2)
Add Overshoot spec 4.6V((pulse width≤tCYC/2)
Change VIH max from 5.5V to VDD+0.5V
Change ISB2 value from 20mA to 30mA.
Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V.
Final spec Release
Add VDDQ Supply voltage( 2.5V )
Draft Date
May. 15. 1997
February. 11. 1998
April. 14. 1998
May 13. 1998
May 15. 1998
Dec. 02. 1998
K7B401825M 256Kx18 Synchronous SRAM
- 2 - Rev. 2.0
December 1998
FAST ACCESS TIMES
PARAMETER Symbol -75 -80 -90 Unit
Cycle Time tCYC 8.5 10 12 ns
Clock Access Time tCD 7.5 8 9 ns
Output Enable Access Time tOE 3.5 3.5 3.5 ns
256Kx18-Bit Synchronous Burst SRAM
The K7B401825M is a 4,718,592 bit Synchronous Static Ran-
dom Access Memory designed for support zero wait state per-
formance for advanced Pentium/Power PC address pipelining.
And with CS1 high, ADSP is blocked to control signal.
It is organized as 256K words of 18 bits and integrates address
and control registers, a 2-bit burst address counter and high
output drive circuitry onto a single integrated circuit for reduced
components count implementation of high performance cache
RAM applications.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input. ZZ pin controls Power Down
State and reduces Stand-by current regardless of CLK.
The K7B401825M is implemented in SAMSUNG′s high perfor-
mance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
GENERAL DESCRIPTIONFEATURES
LOGIC BLOCK DIAGRAM
• Synchronous Operation.
• On-Chip Address Counter.
• Write Self-Timed Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a
linear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
WEa
WEb
OE
ZZ
DQa
0
~ DQb
7
DQPa, DQPb
BURST CONTROL
LOGIC BURST 256Kx18
ADDRESS
CONTROL OUTPUT
DATA-IN
ADDRESS
COUNTER
MEMORY
ARRAY
REGISTER
REGISTER
BUFFER
LOGIC
CONTROL
REGISTER
CONTROL
REGISTER
A
′
0
~A
′
1
A
0
~ A
1
A
2
~A
17
A
0
~A
17
K7B401825M 256Kx18 Synchronous SRAM
- 3 - Rev. 2.0
December 1998
PIN CONFIGURATION(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
N.C.
N.C.
WEb
WEa
CS2
VDD
VSS
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
81 A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A17
A16
A15
A14
A13
A12
A11
N.C.
N.C.
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31
LBO
PIN NAME
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A17
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37,
44,45,46,47,48,49,
50,80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31
VDD
VSS
N.C.
DQa0~a7
DQb0~b7
DQPa, Pb
VDDQ
VSSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,
29,30,38,39,42,43,51
52,53,56,57,66,75
78,79,95,96
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
K7B401825M 256Kx18 Synchronous SRAM
- 4 - Rev. 2.0
December 1998
FUNCTION DESCRIPTION
The K7B401825M is a synchronous SRAM designed to support the burst address accessing sequence of the Pentium and Power PC
based microprocessor. All inputs(with the exception of OE, LBO and ZZ) are sampled on rising clock edges.
The start and duration of the burst access is controlled by ADSP, ADSC, ADV and Chip Select pins.
When ZZ is pulled HIGH, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both
GW and BW are high or when BW is low and both WEa and WEb are high, When ADSP is sampled low, the chip selects are sampled
active, and the output buffer is enabled with OE, the data of cell array accessed by the current address are projected to the output
pins.
Write cycles are also initiated with ADSP(or ADSC)and are differentiated into two kinds of operations; All byte write operation and
individual byte write operation. All byte write occurs by enabling GW(in dependent of BW and WEx.), and individual byte write is per-
formed only when GW is High and BW is Low. WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb.
CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded.
ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when ADV is sampled low.
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE (Interleaved Burst)
LBO PIN HIGH Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
SEQUENCE TABLE (Linear Burst)
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
LBO PIN LOW Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION ZZ OE I/O STATUS
Sleep Mode HXHigh-Z
Read L L DQ
LHHigh-Z
Write LXDin, High-Z
Deselected LXHigh-Z
Notes
1. X means "Don′t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
TRUTH TABLES
K7B401825M 256Kx18 Synchronous SRAM
- 5 - Rev. 2.0
December 1998
SYNCHRONOUS TRUTH TABLE
Notes : 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
CS1CS2CS2ADSP ADSC ADV WRITE CLK ADDRESS ACCESSED OPERATION
HXXXLX X ↑None Not Selected
L L XLX X X ↑None Not Selected
LXHLX X X ↑None Not Selected
L L X X LX X ↑None Not Selected
LXHXLX X ↑None Not Selected
LHL L X X X ↑External Address Begin Burst Read Cycle
LHLHLXL↑External Address Begin Burst Write Cycle
LHLHLXH↑External Address Begin Burst Read Cycle
XXXH H LH↑Next Address Continue Burst Read Cycle
HXXXHLH↑Next Address Continue Burst Read Cycle
XXXH H L L ↑Next Address Continue Burst Write Cycle
HXXXHL L ↑Next Address Continue Burst Write Cycle
XXXH H H H ↑Current Address Suspend Burst Read Cycle
HXXXH H H ↑Current Address Suspend Burst Read Cycle
XXXHHH L↑Current Address Suspend Burst Write Cycle
HXXXH H L↑Current Address Suspend Burst Write Cycle
WRITE TRUTH TABLE
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
GW BW WEaWEbOPERATION
H H X X READ
HLH H READ
HL L HWRITE BYTE a
HLHLWRITE BYTE b
HL L L WRITE ALL BYTEs
LX X X WRITE ALL BYTEs
K7B401825M 256Kx18 Synchronous SRAM
- 6 - Rev. 2.0
December 1998
CAPACITANCE*(TA=25°C, f=1MHz)
*Note : Sampled not 100% tested.
PARAMETER SYMBOL TEST CONDI- MIN MAX UNIT
Input Capacitance CIN VIN=0V -5pF
Output Capacitance COUT VOUT=0V -8pF
ABSOLUTE MAXIMUM RATINGS*
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER SYMBOL RATING UNIT
Voltage on VDD Supply Relative to VSS VDD -0.3 to 4.6 V
Voltage on VDDQ Supply Relative to VSS VDDQ VDD V
Voltage on Input Pin Relative to VSS VIN -0.3 to 6.0 V
Voltage on I/O Pin Relative to VSS VIO -0.3 to VDDQ+0.5 V
Power Dissipation PD1.2 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature TOPR 0 to 70 °C
Storage Temperature Range Under Bias TBIAS -10 to 85 °C
OPERATING CONDITIONS at 3.3V I/O (0°C≤ TA≤70°C)
PARAMETER SYMBOL MIN Typ. MAX UNIT
Supply Voltage VDD 3.135 3.3 3.6 V
VDDQ 3.135 3.3 3.6 V
Ground VSS 0 0 0 V
OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)
PARAMETER SYMBOL MIN Typ. MAX UNIT
Supply Voltage VDD 3.135 3.3 3.6 V
VDDQ 2.375 2.5 2.9 V
Ground VSS 000V
K7B401825M 256Kx18 Synchronous SRAM
- 7 - Rev. 2.0
December 1998
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
* VIL(Min)=-2.0(Pulse Width ≤ tCYC/2)
** VIH(Max)=4.6(Pulse Width ≤ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT
Input Leakage Current(except ZZ) IIL VDD=Max ; VIN=VSS to VDD -2 2µA
Output Leakage Current IOL Output Disabled, VOUT=VSS to VDDQ -2 2µA
Operating Current ICC Device Selected, IOUT=0mA,
ZZ≤VIL, All Inputs=VIL or VIH
Cycle Time ≥ tCYC Min
-75 -350
mA-80 -325
-90 -300
Standby Current
ISB Device deselected, IOUT=0mA,
ZZ≤VIL, f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V
-75 -100
mA-80 -90
-90 -80
ISB1 Device deselected, IOUT=0mA, ZZ≤0.2V,
f=0, All Inputs=fixed (VDD-0.2V or 0.2V) -30 mA
ISB2 Device deselected, IOUT=0mA,
ZZ≥VDD-0.2V, f=Max,
All Inputs≤VIL or ≥VIH
-30 mA
Output Low Voltage(3.3V I/O) VOL IOL = 8.0mA -0.4 V
Output High Voltage(3.3V I/O) VOH IOH = -4.0mA 2.4 -V
Output Low Voltage(2.5V I/O) VOL IOL = 1.0mA -0.4 V
Output High Voltage(2.5V I/O) VOH IOH = -1.0mA 2.0 -V
Input Low Voltage(3.3V I/O) VIL -0.5* 0.8 V
Input High Voltage(3.3V I/O) VIH 2.0 VDD+0.5** V
Input Low Voltage(2.5V I/O) VIL -0.3* 0.7 V
Input High Voltage(2.5V I/O) VIH 1.7 VDD+0.5** V
TEST CONDITIONS
PARAMETER VALUE
Input Pulse Level(for 3.3V I/O) 0 to 3V
Input Pulse Level(for 2.5V I/O) 0 to 2.5V
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O) 2ns
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O) 2ns
Input and Output Timing Reference Levels for 3.3V I/O 1.5V
Input and Output Timing Reference Levels for 2.5V I/O VDDQ/2
Output Load See Fig. 1
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)
K7B401825M 256Kx18 Synchronous SRAM
- 8 - Rev. 2.0
December 1998
AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
4. At any given voltage and temperature, tHZC is less than tLZC.
PARAMETER SYMBOL -75 -80 -90 UNIT
MIN MAX MIN MAX MIN MAX
Cycle Time tCYC 8.5 -10 -12 -ns
Clock Access Time tCD -7.5 -8-9ns
Output Enable to Data Valid tOE -3.5 -3.5 -3.5 ns
Clock High to Output Low-Z tLZC 0-0-0-ns
Output Hold from Clock High tOH 2-2-2-ns
Output Enable Low to Output Low-Z tLZOE 0-0-0-ns
Output Enable High to Output High-Z tHZOE -3.5 -3.5 -3.5 ns
Clock High to Output High-Z tHZC 23.5 23.5 23.5 ns
Clock High Pulse Width tCH 3-4-4.5 -ns
Clock Low Pulse Width tCL 3-4-4.5 -ns
Address Setup to Clock High tAS 2.0 -2.0 -2.0 -ns
Address Status Setup to Clock High tSS 2.0 -2.0 -2.0 -ns
Data Setup to Clock High tDS 2.0 -2.0 -2.0 -ns
Write Setup to Clock High(GW, BW, WEx) tWS 2.0 -2.0 -2.0 -ns
Address Advance Setup to Clock High tADVS 2.0 -2.0 -2.0 -ns
Chip Select Setup to Clock High tCSS 2.0 -2.0 -2.0 -ns
Address Hold from Clock High tAH 0.5 -0.5 -0.5 -ns
Address Status Hold from Clock High tSH 0.5 -0.5 -0.5 -ns
Data Hold from Clock High tDH 0.5 -0.5 -0.5 -ns
Write Hold from Clock High(GW, BW, WEx) tWH 0.5 -0.5 -0.5 -ns
Address Advance Hold from Clock High tADVH 0.5 -0.5 -0.5 -ns
Chip Select Hold from Clock High tCSH 0.5 -0.5 -0.5 -ns
ZZ High to Power Down tPDS 2-2-2-cycle
ZZ Low to Power Up tPUS 2-2-2-cycle
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
5pF*
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Z0=50Ω
* Capacitive Load consists of all components of
30pF*
the test environment.
RL=50Ω
353Ω / 1538Ω
+3.3V for 3.3V I/O
319Ω / 1667Ω
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
/+2.5V for 2.5V I/O
K7B401825M 256Kx18 Synchronous SRAM
- 9 - Rev. 2.0
December 1998
CLOCK
ADSP
ADSC
ADDRESS
WRITE
CS
ADV
OE
Data Out
TIMING WAVEFORM OF READ CYCLE
NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx.= L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tCH tCL
tSS tSH
tSS tSH
tAS tAH
A1 A2 A3
BURST CONTINUED WITH
NEW BASE ADDRESS
tWS tWH
tCSS tCSH
tADVS tADVH
tOE tHZOE
tLZOE tCD
tOH
(ADV INSERTS WAIT STATE)
tHZC
Q3-4Q3-3Q3-2Q3-1Q2-4Q2-3Q2-2Q2-1
Q1-1
Don′t Care
Undefined
tCYC
K7B401825M 256Kx18 Synchronous SRAM
- 10 Rev. 2.0
December 1998
CLOCK
ADSP
ADSC
ADDRESS
WRITE
CS
ADV
Data In
OE
Data Out
tCH tCL
tSS tSH
tAS tAH
A1 A2 A3
(ADSC EXTENDED BURST)
tLZOE
D2-1D1-1
tCSS tCSH
(ADV SUSPENDS BURST)
D2-2 D2-3 D2-4 D3-1 D3-2 D3-3D2-2 D3-4
Q0-3 Q0-4
tSS tSH
tWS tWH
tADVS tADVH
tDS tDH
TIMING WAVEFORM OF WRTE CYCLE
Don′t Care
Undefined
tCYC
K7B401825M 256Kx18 Synchronous SRAM
- 11 Rev. 2.0
December 1998
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
CLOCK
ADSP
ADDRESS
WRITE
CS
ADV
OE
Data Out
tCH tCL
tDS tDH
Q3-3
Data In tOE tOH
A1 A2 A3
D2-1
Q3-1 Q3-2 Q3-4
tSS tSH
tAS tAH
tWS tWH
tADVS tADVH
tLZOE
tHZOE
tCD
tHZC tLZC
Don′t Care
Undefined
tCYC
Q1-1
K7B401825M 256Kx18 Synchronous SRAM
- 12 Rev. 2.0
December 1998
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED, ADSP=HIGH)
CLOCK
ADSC
ADDRESS
WRITE
CS
ADV
OE
Data In
tCH tCL
tHZOE
D6-1
Data Out
tWS tWH
tCD tOH
tOE
D5-1 D7-1
tWS tWH
tLZOE
tDH
tDS
A1 A2 A3 A4 A5 A6 A7 A8 A9
Q3-1Q1-1 Q2-1 Q4-1 Q8-1 Q9-1
tCSS tCSH
tSS tSH
Don′t Care
Undefined
tCYC
K7B401825M 256Kx18 Synchronous SRAM
- 13 Rev. 2.0
December 1998
D7-1
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
CLOCK
ADSP
ADDRESS
WRITE
CS
ADV
OE
Data In
tCH tCL
tHZOE
Data Out
tAS tAH
tCD tOH
tOE
D5-1
tLZOE
tDHtDS
A1 A2 A3 A4 A5 A6 A9
Q3-1Q1-1 Q2-1 Q4-1 Q8-1 Q9-1
tCSS tCSH
tSS tSH
A7 A8
D6-1
Don′t Care
Undefined
tCYC
K7B401825M 256Kx18 Synchronous SRAM
- 14 Rev. 2.0
December 1998
TIMING WAVEFORM OF POWER DOWN CYCLE
CLOCK
ADSP
ADDRESS
WRITE
CS
ADV
Data In
tCH tCL
D2-2
OE
tWH
tHZOE
tLZOE D2-1
A1
tSS tSH
Data Out
tPUS
A2
ADSC
Q1-1
ZZ
tAS tAH
tCSS tCSH
tOE
tHZC
tPDS
Sleep State
ZZ Setup Cycle
Normal Operation Mode
ZZ Recovery Cycle
tWS
Don′t Care
Undefined
tCYC
K7B401825M 256Kx18 Synchronous SRAM
- 15 Rev. 2.0
December 1998
APPLICATION INFORMATION
The Samsung 256Kx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
DEPTH EXPANSION
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
Data
Address
CLK
ADS
Microprocessor
CS2
CS2
CLK
ADSC
WEx
OE
CS1
Address Data
ADV ADSP
256Kx18
SB
SRAM
(Bank 0)
CS2
CS2
CLK
ADSC
WEx
OE
CS1
Address Data
ADV ADSP
256Kx18
SB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A[0:18] A[18] A[0:17] A[18] A[0:17]
I/O[0:71]
CLOCK
ADSP
ADDRESS
Data Out
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
Q1-1 Q1-2 Q1-4Q1-3
OE
Data Out
tSS tSH
A1 A2
WRITE
CS1
An+1
ADV
(Bank 0)
(Bank 1) Q2-1 Q2-2 Q2-4Q2-3
tAS tAH
tCSS tCSH
tWS tWH
tADVS tADVH
tOE
tLZOE tHZC
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
[0:n]
Don′t Care Undefined
tCD
tLZC
*Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
(ADSP CONTROLLED , ADSC=HIGH)
K7B401825M 256Kx18 Synchronous SRAM
- 16 Rev. 2.0
December 1998
0.10 MAX
0~8°
22.00 ±0.30
20.00 ±0.20
16.00 ±0.30
14.00 ±0.20
1.40 ±0.10 1.60 MAX
0.05 MIN
(0.58)
0.50 ±0.10
#1
(0.83) 0.50 ±0.10
100-TQFP-1420A
0.65 0.30 ±0.10
0.10 MAX
+ 0.10
- 0.05
0.127
PACKAGE DIMENSIONS
Units:millimeters/inches
