DATA SH EET
Product specification
Supersedes data of October 1990
File under Integrated Circuits, IC06
September 1993
INTEGRATED CIRCUITS
74HC/HCT7404
5-Bit x 64-word FIFO register;
3-state
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
September 1993 2
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
FEATURES
•Synchronous or asynchronous operation
•3-state outputs
•30 MHz (typical) shift-in and shift-out rates
•Readily expandable in word and bit dimensions
•Pinning arranged for easy board layout: input pins
directly opposite output pins
•Output capability: driver (8 mA)
•ICC category: LSI.
APPLICATIONS
•High-speed disc or tape controller
•Communications buffer.
GENERAL DESCRIPTION
The 74HC/HCT7404 are high-speed Si-gate CMOS
devices specified in compliance with JEDEC standard
no.7A.
The “7404” is an expandable, First-In First-Out (FIFO)
memory organized as 64 words by 5 bits. A guaranteed
15 MHz data-rate makes it ideal for high-speed
applications. A higher data-rate can be obtained in
applications where the status flags are not used
(burst-mode).
With separate controls for shift-in (SI) and shift-out (SO),
reading and writing operations are completely
independent, allowing synchronous and asynchronous
data transfers. Additional controls include a master-reset
input (MR), an output enable input (OE) and flags. The
data-in-ready (DIR) and data-out-ready (DOR) flags
indicate the status of the device.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Note
1. For HC the condition is VI = GND to VCC.
For HCT the condition is VI = GND to VCC −1.5 V.
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS TYP. UNIT
HC HCT
tPHL/tPLH propagation delay SO, SI to DIR and DOR CL = 15 pF; VCC = 5 V 15 17 ns
fmax maximum clock frequency 30 30 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package note 1 475 490 pF
EXTENDED
TYPE NUMBER PACKAGE
PINS PIN POSITION MATERIAL CODE
74HC/HCT7404N 18 DIL plastic SOT102
74HC/HCT7404D 20 SO20 plastic SOT163A
September 1993 3
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
PINNING (SOT102)
SYMBOL PIN DESCRIPTION
OE 1 output enable input (active
LOW)
DIR 2 data-in-ready output
SI 3 shift-in input (active HIGH)
DO to D44, 5, 6, 7, 8 parallel data inputs
GND 9 ground
MR 10 asynchronous master-reset
input (active LOW)
Q4 to Q011, 12, 13,
14, 15 data outputs
DOR 16 data-out-ready output
SO 17 shift-out input (active LOW)
VCC 18 positive supply voltage
PINNING (SOT163A)
SYMBOL PIN DESCRIPTION
OE 1 output enable input (active
LOW)
DIR 2 data-in-ready output
SI 3 shift-in input (active HIGH)
n.c. 4 not connected
D0 to D45, 6, 7, 8, 9 parallel data inputs
GND 10 ground
MR 11 asynchronous master-reset
input (active LOW)
Q4 to Q012, 13, 14,
15, 16 data outputs
n.c. 17 not connected
DOR 18 data-out ready output
n.c. 19 not connected
VCC 20 positive supply voltage
Fig.1 Pin configuration (SOT102).
handbook, halfpage
DIR
GND
V
CC
D0
D1
D2
D3
D4Q4
Q3
Q2
Q1
Q0
OE
7404
MGA670
SI DOR
SO
MR
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
Fig.2 Pin configuration (SOT163).
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
GND
V
CC
D0
D1
D2
D3
D4Q4
Q3
Q2
Q1
Q0
OE
7404
MGA671
SI
n.c.
DOR
SO
n.c.
MR
September 1993 4
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Fig.3 Logic symbol.
Pin numbers between parentheses refer to the SO package.
handbook, halfpage
MGA673
16 (18)
2 (2)
15 (16)
14 (15)
13 (14)
12 (13)
11 (12)
1 (1)
(3) 3
10 (11)
(19) 17
(5) 4
(6) 5
(7) 6
(8) 7
(9) 8
DIR
D0
D1
D2
D3
D4Q4
Q3
Q2
Q1
Q0
OE
SI DOR
SO MR
Fig.4 IEC logic symbol.
Pin numbers between parentheses refer to the SO package.
handbook, halfpage
MGA675
1 ( /C2)
CT = 0
5
<
CT 64
>
CT 0
CTR
5Z6
1Z3
EN4
G1
G5
[IR] 3
[OR] 6
FIFO 64 x 5
2D 4
16 (18)
2 (2)
15 (16)
14 (15)
13 (14)
12 (13)
11 (12)
(1) 1
(3) 3
(11) 10
(19) 17
(5) 4
(6) 5
(7) 6
(8) 7
(9) 8
Fig.5 Functional diagram.
Pin numbers between parentheses refer to the SO package.
handbook, full pagewidth
MGA680
16 (18)2 (2) 1 (1) 3 (3)
(11) 10
17 (19)
DIR OE
SI DOR SO
MR
(5) 4
(6) 5
(7) 6
(8) 7
(9) 8
D0
D1
D2
D3
D4
15 (16)
14 (15)
13 (14)
12 (13)
11 (12)
Q4
Q3
Q2
Q1
Q0
INPUT
STAGE
1 x 5 BITS
MAIN FIFO
REGISTER
62 x 5 BITS
CONTROL LOGIC
OUTPUT
STAGE
1 x 5 BITS OE
September 1993 5
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
f
ull pagewidth
MSB117
(1)
R
SQ
FS
5
LATCHES
CL CL
D0
D1
D3
D4
DIR
SI
MR
(2)
R
SQ
FF1
(2)
R
SQ
FF2
RQ RQ
R
SQ
FF3
to
FF63
RQ
61 x
R
SQ
FF64
RQ
(2)
R
SQ
FB
(1)
R
SQ
FP
(1)
R
DOR
SO
OE
position 1
5
LATCHES
CL CL
position 2
5
LATCHES
CL CL
position 3 to 63
5
LATCHES
CL CL
position 64
3-STATE
OUTPUT
BUFFER
Q0
Q1
Q3
Q4
Fig.6 Logic diagram.
(See control flip-flops)
LOW on S input of flip-flops FS, FB and FP will set Q output to HIGH independent of state on R input.
LOW on R input of FF1 to FF64 will set Q output to LOW independent of state on S input.
September 1993 6
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
FUNCTIONAL DESCRIPTION
The DIR flag indicates the input stage
status, either empty and ready to
receive data (DIR = HIGH) or full and
busy (DIR = LOW). When DIR and SI
are HIGH, data present at D0 to D4 is
shifted into the input stage; once
complete DIR goes LOW. When SI is
set LOW, data is automatically shifted
to the output stage or to the last
empty location. A FIFO which can
receive data is indicated by DIR set
HIGH.
A DOR flag indicates the output stage
status, either data available
(DOR = HIGH) or busy
(DOR = LOW). When SO and DOR
are HIGH, data is available at the
outputs (Q0 to Q4). When SO is LOW
new data may be shifted into the
output stage, once complete DOR is
set LOW.
Expanded Format (see Fig.18)
The DOR and DIR signals are used to
allow the ‘7404’ to be cascaded. Both
parallel and serial expansion is
possible. Serial expansion is only
possible with typical devices.
Parallel Expansion
Parallel expansion is accomplished
by logically ANDing the DOR and DIR
signals to form a composite signal.
Serial Expansion
Serial expansion is accomplished by:
•tying the data outputs of the first
device to the data inputs of the
second device
•connecting the DOR pin of the first
device to the SI pin of the second
device
•connecting the SO pin of the first
device to the DIR pin of the second
device.
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI
Output capability: driver 8 mA
ICC category: LSI
Voltages are referenced to GND (ground = 0 V).
DC CHARACTERISTICS FOR 74HC
SYMBOL PARAMETER
Tamb °C
UNIT
TEST CONDITION
+25 −40 to +85 −40 to +125 VCC
(V) VIOTHER
MIN TYP MAX MIN MAX MIN MAX
VOH HIGH level
output voltage 3.98
5.48 4.32
5.81 −
−3.84
5.34 −
−3.70
5.20 −
−V
V4.5
6VIH
or
VIL
IO = −8 mA
IO = −10 mA
VOL LOW level
output voltage −
−0.15
0.15 0.26
0.26 −
−0.33
0.33 −
−0.4
0.4 V
V
4.5
6VIH
or
VIL
IO = 8 mA
IO = 10 mA
September 1993 7
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
SYMBOL PARAMETER
Tamb °C
UNIT
TEST CONDITION
+25 −40 to +85 −40 to +125 VCC
(V) WAVEFORMS
MIN TYP MAX MIN MAX MIN MAX
tPHL/tPLH propagation
delay
MR to DIR,
DOR
−
−
−
69
25
20
210
42
36
−
−
−
265
53
45
−
−
−
315
63
54
ns
ns
ns
2.0
4.5
6.0
Fig.9
tPHL propagation
delay
MR to Qn
−
−
−
52
19
15
160
32
27
−
−
−
200
40
34
−
−
−
240
48
41
ns
ns
ns
2.0
4.5
6.0
Fig.9
tPHL/tPLH propagation
delay
SI to DIR
−
−
−
66
24
19
205
41
35
−
−
−
255
51
43
−
−
−
310
62
53
ns
ns
ns
2.0
4.5
6.0
Fig.7
tPHL/tPLH propagation
delay
SO to DOR
−
−
−
94
34
27
290
58
49
−
−
−
365
73
62
−
−
−
435
87
74
ns
ns
ns
2.0
4.5
6.0
Fig.10
tPHL/tPLH propagation
delay
DOR to Qn
−
−
−
11
4
3
35
7
6.0
−
−
−
45
9
8
−
−
−
55
11
9
ns
ns
ns
2.0
4.5
6.0
Fig.11
tPHL/tPLH propagation
delay
SO to Qn
−
−
−
105
38
30
325
65
55
−
−
−
406
81
69
−
−
−
488
98
83
ns
ns
ns
2.0
4.5
6.0
Fig.15
tPLH propagation
delay/ripple
through delay
SI to DOR
−
−
−
2.2
0.8
0.6
7.0
1.4
1.2
−
−
−
8.8
1.8
1.5
−
−
−
10.5
2.1
1.8
µs
µs
µs
2.0
4.5
6.0
Fig.16
tPLH propagation
delay/bubble-up
delay SO to
DIR
−
−
−
2.8
1.0
0.8
9.0
1.8
1.5
−
−
−
11.2
2.2
1.9
−
−
−
13.5
2.7
2.3
µs
µs
µs
2.0
4.5
6.0
Fig.8
tPZH/tPZL 3-state output
enable
OE to Qn
−
−
−
44
16
13
150
30
26
−
−
−
190
38
32
−
−
−
225
45
38
ns
ns
ns
2.0
4.5
6.0
Fig.17
tPHZ/tPLZ 3-state output
disable
OE to Qn
−
−
−
50
18
14
150
30
26
−
−
−
190
38
33
−
−
−
225
45
38
ns
ns
ns
2.0
4.5
6.0
Fig.17
tTHL/tTLH output transition
time −
−
−
14
5
4
60
12
10
−
−
−
75
15
13
−
−
−
90
18
15
ns
ns
ns
2.0
4.5
6.0
Fig.17
tWSI pulse width
HIGH or LOW 35
7
6
11
4
3
−
−
−
45
9
8
−
−
−
55
11
9
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.7
tWSO pulse width
HIGH or LOW 70
14
12
22
8
6
−
−
−
90
18
15
−
−
−
105
21
18
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.10
September 1993 8
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
tWDIR pulse width
HIGH 10
5
4
41
15
12
130
26
22
8
4
3
165
33
28
8
4
3
195
39
33
ns
ns
ns
2.0
4.5
6.0
Fig.8
tWDOR pulse
width HIGH 14
7
6
52
19
15
160
32
27
12
6
5
200
40
34
12
6
5
240
48
41
ns
ns
ns
2.0
4.5
6.0
Fig.11
tWMR pulse
width LOW 120
24
20
39
14
11
−
−
−
150
30
26
−
−
−
180
36
31
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.9
trem removal time
MR to SI 80
16
14
24
8
7
−
−
−
100
20
17
−
−
−
120
24
20
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.16
tsu set-up time
Dn to SI −8
−4
−3
−36
−13
−10
−
−
−
−6
−3
−3
−
−
−
−6
−3
−3
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.14
thhold time
Dn to SI 135
27
23
44
16
13
−
−
−
170
34
29
−
−
−
205
41
35
−
−
−
ns
ns
ns
2.0
4.5
6.0
Fig.14
fmax maximum clock
pulse frequency
SI, SO burst
mode
3.6
18
21
9.9
30
36
−
−
−
2.8
14
16
−
−
−
2.4
12
14
−
−
−
MHz
MHz
MHz
2.0
4.5
6.0
Fig.12 and
Fig.13
fmax maximum clock
pulse frequency
SI, SO using
flags
3.6
18
21
9.9
30
36
−
−
−
2.8
14
16
−
−
−
2.4
12
14
−
−
−
MHz
MHz
MHz
2.0
4.5
6.0
Fig.7 and
Fig.10
fmax maximum clock
pulse frequency
SI, SO
cascaded
−
−
−
7.6
23
27
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
MHz
MHz
MHz
2.0
4.5
6.0
Fig.7 and
Fig.10
SYMBOL PARAMETER
Tamb °C
UNIT
TEST CONDITION
+25 −40 to +85 −40 to +125 VCC
(V) WAVEFORMS
MIN TYP MAX MIN MAX MIN MAX
September 1993 9
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
, except that VOH and VOL are not
valid for driver output. They are replaced by the values given below.
Output capability: driver 8 mA
ICC category: LSI.
Voltages are referenced to GND (ground = 0 V).
DC CHARACTERISTICS FOR 74HCT
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
UNIT LOAD COEFFICIENT
SYMBOL PARAMETER
Tamb °C
UNIT
TEST CONDITION
+25 −40 to +85 −40 to +125 VCC
(V) VIOTHER
MIN TYP MAX MIN MAX MIN MAX
VOH HIGH level
output voltage 3.98 4.32 −3.84 −3.7 −V 4.5 VIH
or
VIL
IO = −8 mA
VOL LOW level
output voltage −0.15 0.26 −0.33 −0.40 V 4.5 VIH
or
VIL
IO = 8 mA
INPUT UNIT LOAD COEFFICIENT
OE 1
SI 1.5
Dn0.75
MR 1.5
SO 1.5
September 1993 10
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
SYMBOL PARAMETER
Tamb °C
UNIT
TEST CONDITION
+25 −40 to +85 −40 to +125 VCC
(V) WAVEFORMS
MIN TYP MAX MIN MAX MIN MAX
tPHL/tPLH propagation
delay
MR to DIR,
DOR
−30 51 −53 −63 ns 4.5 Fig.9
tPHL propagation
delay
MR to Qn
−22 38 −48 −57 ns 4.5 Fig.9
tPHL/tPLH propagation
delay
SI to DIR
−25 43 −54 −65 ns 4.5 Fig.7
tPHL/tPLH propagation
delay
SO to DOR
−36 61 −76 −92 ns 4.5 Fig.10
tPHL/tPLH propagation
delay
SO to Qn
−42 72 −90 −108 ns 4.5 Fig.15
tPHL/tPLH propagation
delay
DOR to Qn
−712−15 −18 ns 4.5 Fig.11
tPLH propagation
delay/ripple
through delay
SI to DOR
−0.8 1.4 −1.75 −2.1 µs 4.5 Fig.11
tPLH propagation
delay/bubble-
up delay
SO to DIR
−1 1.8 −2.25 −2.7 µs 4.5 Fig.8
tPZH/tPZL 3-state output
enable
OE to Qn
−16 30 −38 −45 ns 4.5 Fig.17
tPHZ/tPLZ 3-state output
disable
OE to Qn
−19 30 −38 −45 ns 4.5 Fig.17
tTHL/tTLH output
transition time −512−15 −18 ns 4.5 Fig.17
tWSI pulse width
HIGH or LOW 95−6−8−ns 4.5 Fig.7
tWSO pulse width
HIGH or LOW 14 8 −18 −21 −ns 4.5 Fig.10
tWDIR pulse width
HIGH 5 17 29 4 36 4 44 ns 4.5 Fig.8
September 1993 11
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
tWDOR pulse
width HIGH 7 21 36 6 45 6 54 ns 4.5 Fig.11
tWMR pulse
width LOW 26 15 −33 −39 −ns 4.5 Fig.9
trem removal time
MR to SI 18 10 −23 −27 −ns 4.5 Fig.16
tsu set-up time
Dn to SI −5−16 −−4−−4−ns 4.5 Fig.14
thhold time
Dn to SI 30 18 −38 −45 −ns 45 Fig.14
fmax maximum
clock pulse
frequency
SI, SO burst
mode
18 30 −14 −12 −MHz 4.5 Fig.12 and Fig.13
fmax maximum
clock pulse
frequency
SI, SO using
flags
18 30 −14 −12 −MHz 4.5 Fig.7 and Fig.10
fmax maximum
clock pulse
frequency
SI, SO
cascaded
−23 −−−−−MHz 4.5 Fig.7 and Fig.10
SYMBOL PARAMETER
Tamb °C
UNIT
TEST CONDITION
+25 −40 to +85 −40 to +125 VCC
(V) WAVEFORMS
MIN TYP MAX MIN MAX MIN MAX
September 1993 12
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
AC WAVEFORMS
Shifting in sequence FIFO empty to FIFO full
Notes to Fig.7
1. DIR initially HIGH; FIFO is prepared for valid data
2. SI set HIGH; data loaded into input stage
3. DIR goes LOW, input stage “busy”
4. SI set LOW; data from first location “ripple through”
5. DIR goes HIGH, status flag indicates FIFO prepared for additional data
6. Repeat process to load 2nd word through to 64th word into FIFO
DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.
Fig.7 Waveforms showing the SI input to DIR output propagation delay, the SI pulse width and SI maximum
pulse frequency.
handbook, full pagewidth
MGA659
VM(1)
1/ f max
W
t
tPHL tPLH
VM(1)
1st word 2nd word 64th word
73
15
64
2
SI INPUT
Dn INPUT
DIR OUTPUT
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
September 1993 13
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
With FIFO full; SI held HIGH in anticipation of empty location
Notes to Fig.8
1. FIFO is initially full, shift-in is held HIGH
2. SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins
3. DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input
4. DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again
5. SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.
Fig.8 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.
handbook, full pagewidth
SI INPUT
MGA660
34
DIR OUTPUT
VM(1)
2
bubble - up
delay
VM(1)
5
SO INPUT
tPLH
VM(1)
1
tW
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
September 1993 14
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Master reset applied with FIFO full
Notes to Fig.9
1. DIR LOW, output ready HIGH; assume FIFO is full
2. MR pulse LOW; clears FIFO
3. DIR goes HIGH; flag indicates input prepared for valid data
4. DOR goes LOW; flag indicates FIFO empty
5. Qn outputs go LOW (only last bit will be reset).
Fig.9 Waveforms showing the MR input to DIR, DOR and Qn output propagation delays and the MR pulse width.
handbook, halfpage
tPHL
VM(1)
tW
tPLH
DIR OUTPUT
VM(1)
MR INPUT VM(1)
MGA668
Qn OUTPUT
tPHL
4
5
1
3
2
DOR OUTPUT
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
September 1993 15
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Notes to Fig.10
1. DOR HIGH; no data transfer in progress, valid data is present at output stage
2. SO set HIGH; results in DOR going LOW
3. DOR goes LOW; output stage “busy”
4. SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location “bubbles-up” to input
stage
5. DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay
6. Repeat process to unload the 3rd through to the 64th word from FIFO.
7. DOR remains LOW; FIFO is empty.
Fig.10 Waveforms showing the SO input to DOR output propagation delay, the SO pulse widths and maximum
pulse frequency.
handbook, full pagewidth
MGA661
VM(1)
SO INPUT
Qn OUTPUT
1/ fmax
W
t
DOR OUTPUT
tPHL tPLH
VM(1)
VM(1)
1st SO pulse 2nd SO pulse 64th SO pulse
1st word 2nd word 64th word
73
15
64
2
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
September 1993 16
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
With FIFO empty; SO is held HIGH in anticipation
Notes to Fig.11
1. FIFO is initially empty, SO is held HIGH
2. SI pulse; loads data into FIFO and initiates ripple through process
3. DOR flag signals the arrival of valid data at the output stage
4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the
DOR pulse to the Qn output
5. DOR goes LOW; data shift-out is complete, FIFO is empty again
6. SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty.
Fig.11 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation
delay from the DOR pulse to the Qn output.
handbook, full pagewidth
SI INPUT
MGA669
35
Q
n
OUTPUT
DOR OUTPUT
VM(1)
2
ripple through
delay
VM(1)
6
4
SO INPUT
tPLH
tPLH
tPHL
VM(1)
1
tW
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
September 1993 17
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Shift-in operation; high-speed burst mode
Note to Fig.12
In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications.
The DIR status flag is a don't care condition, and a shift-in pulse can be applied regardless of the flag. A SI pulse which
would overflow the storage capacity of the FIFO is ignored.
Fig.12 Waveforms showing SI minimum pulse width and maximum pulse frequency, in high-speed shift-in burst
mode.
handbook, full pagewidth
MGA662
VM(1)
SI INPUT
Dn INPUT
1/ fmax
tW
DIR OUTPUT
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
September 1993 18
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Shift-out operation; high-speed burst mode
Note to Fig.13
In the high-speed mode, the burst-out rate is determined by the minimum shift-out HIGH and shift-out LOW
specifications. The DOR flag is a don't care condition and an SO pulse can be applied without regard to the flag.
Fig.13 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out
burst mode.
handbook, full pagewidth
MGA663
VM(1)
SO INPUT
Qn OUTPUT
1/ fmax
tW
DOR OUTPUT
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
September 1993 19
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Fig.14 Waveforms showing hold and set-up times for Dn input to SI input.
The shaded areas indicate when the input is permitted to change for predictable output performance.
handbook, full pagewidth
SI INPUT
MGA657
VM(1)
Dn INPUT
tsu th
VM(1)
tsu th
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.15 Waveforms showing SO input to Qn output propagation delays and output transition time.
handbook, full pagewidth
tTHL
tTLH
tPLH
MGA664
VM(1)
SO INPUT
Qn OUTPUT VM(1)
tPHL
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.16 Waveform showing the MR input to SI input removal time.
handbook, halfpage
MGA665
trem
SI INPUT
MR INPUT
VM(1)
VM(1)
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
September 1993 20
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Fig.17 Waveforms showing the 3-state enable and disable times for input OE.
handbook, full pagewidth
MGA656
tPLZ tPZL
VM(1)
outputs
disabled outputs
enabled
tPZH
90 %
tPHZ
10 %
90 %
tf
tr
outputs
enabled
OE INPUT
10 %
VM(1)
VM(1)
Q OUTPUT
LOW - to - OFF
OFF - to - LOW
n
Q OUTPUT
HIGH - to - OFF
OFF - to - HIGH
n
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
September 1993 21
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
APPLICATION INFORMATION
Fig.18 Expanded FIFO (parallel and serial) for increased word length; 10 bits wide ×64 n-bits.
handbook, full pagewidth
MGA686
DIR
SI DOR
SO
MR
OE
OE
DIR
SI DOR
SOMR
7404
D0
D1
D2
D3
D4Q4
Q3
Q2
Q1
Q0
OE
DIR
SI DOR
SOMR
7404
D0
D1
D2
D3
D4Q4
Q3
Q2
Q1
Q0
OE
DIR
SI DOR
SOMR
7404
D0
D1
D2
D3
D4Q4
Q3
Q2
Q1
Q0
OE
DIR
SI DOR
SOMR
7404
D0
D1
D2
D3
D4Q4
Q3
Q2
Q1
Q0
10-bit
data 10-bit
data
September 1993 22
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Note to Fig.19
The ”7404” is easily expanded to increase word length. Composite DIR and DOR flags are formed with the addition of
an AND gate. The basic operation and timing are identical to a single FIFO, with the exception of an added gate delay
on the flags.
Fig.19 Expanded FIFO for increased word length; 64 words ×10 bits.
handbook, full pagewidth
MGA681
DIR
OE
SI
DOR
SO
MR
DnQn
5 5
7404
DIR
OE
SI
DOR
SO
MR
7404
DnQn
5 5
DATA INPUT
COMPOSITE
DIR
FLAG SI
MR OE
SO
DATA OUTPUT
COMPOSITE
DOR
FLAG
DATA INPUT DATA OUTPUT
September 1993 23
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Note to Fig.20
This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in
cycles are started or if SO output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are
started (see Fig.8 and Fig.10).
Expanded format
Figure 21 shows two cascaded FIFOs providing a capacity of 128 words x 5 bits. Figure 22 shows the signals on the
nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially empty. After a ripple through delay,
data arrives at the output of FIFOA. Due to SOA being HIGH, a DORA pulse is generated. The requirements of SIB and
DnB are satisfied by the DORA pulse width and the timing between the rising edge of DORA and QnA. After a second ripple
through delay, data arrives at the output of FIFOB.
Figure 23 shows the signals on the nodes of both FIFOs after the application of aSOB pulse, when both FIFOs are initially
full. After a bubble-up delay a DIRB pulse is generated, which acts as a SOA pulse for FIFOA. One word is transferred
from the output of FIFOA to the input of FIFOB. The requirements of the SOA pulse for FIFOA is satisfied by the pulse
width of DORB. After a second bubble-up delay an empty space arrives at DnA, at which time DIRA goes HIGH.
Figure 24 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
Fig.20 Expanded FIFO for increased word length.
handbook, full pagewidth
MGA685
DIR
OE
SI
DOR
SO
MR
DnQn
5
7404
DIR
OE
SI
DOR
SO
MR
7404
DnQn
SI
MR OE
SO
composite
DOR
composite
DIR
5
5 5
DQ
CP
R
74
Q
DQ
CP
Q
DQ
CP
74
Q
DQ
CP
QR
September 1993 24
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Note to Fig.21
The “7404” is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figures 22 and 23 demonstrate the intercommunication timing between
FIFOA and FIFOB. Figure 24 provides an overview of pulses and timing of two cascaded FIFOs, when shifted full and
shifted empty again.
Fig.21 Cascading for increased word capacity; 128 word × 5 bits.
handbook, full pagewidth
MGA682
DIR
OE
SI
MR
DnA
5
DIR
SI
DOR
SO
DATA INPUT
A
A5
SOA
DORA
QnA
7404
FIFO A
DIR
OE
SI
MR
DnB
B
B
5
SOB
DORB
QnB
7404
FIFO B DATA OUTPUT
OE
MR
September 1993 25
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Notes to Fig.22
1. FIFOA and FIFOB initially empty, SOA held HIGH in anticipation of data
2. Load one word into FIFOA; SI pulse applied, results in DIR pulse
3. Data-out A/data-in B transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag,
meeting data input set-up requirements of FIFOB
4. DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data
output ready pulse, data is shifted into FIFOB
5. DIRB and SOA go LOW; flag indicates input stage of FIFOB is busy, shift-out of FIFOA is complete
6. DIRB and SOA go HIGH automatically; the input stage of FIFOB is again able to receive data, SO is held HIGH in
anticipation of additional data
7. DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFOB
output stage.
Fig.22 FIFO to FIFO communication; input timing under empty condition.
handbook, full pagewidth
VM(1)
DORB
SIA
VM(1)
MGA666
56
DIR
A
QnA nB
D
SOA
DIR B
DORASI B
VM(1) 2
ripple through
delay
VM(1)
VM(1)
1
4
ripple through
delay
3
nB
Q
7
September 1993 26
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Notes to Fig.23
1. FIFOA and FIFOB initially full, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up
2. Unload one word from FIFOB; SO pulse applied, results in DOR pulse
3. DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse,
data is shifted out of FIFOA
4. DORA and SIB go LOW; flag indicates the output stage of FIFOA is busy, shift-in to FIFOB is complete
5. DORA and SIB go HIGH; flag indicates valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting
bubble-up of empty location
6. DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFOA.
Fig.23 FIFO to FIFO communication; output timing under full condition.
handbook, full pagewidth
VM(1)
DORB
SOB
VM(1)
MGA667
45
6
DIR
A
QnA nB
D
SOA
DIR B
DORASI B
VM(1) 2
bubble - up
delay
VM(1)
VM(1)
bubble - up
delay
1
3
September 1993 27
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Note to Fig.24
Sequence 1 (both FIFOS empty, starting SHIFT-IN process)
After a MR pulse has been applied FIFOA and FIFOB are empty. The DOR flags of FIFOA and FIFOB go LOW due to no
valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SOB
is held HIGH and two SIA pulses are applied (1). These pulses allow two data words to ripple through to the output stage
of FIFOA and to the input stage of FIFOB (2). When data arrives at the output of FIFOB, a DORB pulse is generated (3).
When SOB goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DORB goes
HIGH (4).
Fig.24 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.19).
handbook, full pagewidth
DORB OUTPUT
DIRB OUTPUT
DORA OUTPUT
DIRA OUTPUT
Q OUTPUT
nB
QnA OUTPUT
SI INPUT
A
D INPUT
nA
MR INPUT
SO INPUT
B
sequence 1 sequence 2 sequence 3 sequence 4 sequence 5 sequence 6
(1)
(2)
(3) (4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
MGA687
September 1993 28
Philips Semiconductors Product specification
5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404
Sequence 2 (FIFOB runs full)
After the MR pulse, a series of 64 SI
pulses are applied. When 64 words
are shifted in, DIRB remains LOW due
to FIFOB being full (5). DORA goes
LOW due to FIFOA being empty.
Sequence 3 (FIFOA runs full)
When 65 words are shifted in, DORA
remains HIGH due to valid data
remaining at the output of FIFOA. QnA
remains HIGH, being the polarity of
the 65th data word (6). After the 128th
SI pulse, DIR remains LOW and both
FIFOs are full (7). Additional pulses
have no effect.
Sequence 4 (both FIFOs full,
starting SHIFT-OUT process)
SIA is held HIGH and two SOB pulses
are applied (8). These pulses shift out
two words and thus allow two empty
locations to bubble-up to the input
stage of FIFOB, and proceed to FIFOA
(9). When the first empty location
arrives at the input of FIFOA, a DIRA
pulse is generated (10) and a new
word is shifted into FIFOA. SIA is
made LOW and now the second
empty location reaches the input
stage of FIFOA, after which DIRA
remains HIGH (11).
Sequence 5 (FIFOA runs empty)
At the start of sequence 5 FIFOA
contains 63 valid words due to two
words being shifted out and one word
being shifted in, in sequence 4. An
additional series of SOB pulses are
applied. After 63 SOB pulses, all
words from FIFOA are shifted into
FIFOB. DORA remains LOW (12).
Sequence 6 (FIFOB runs empty)
After the next SOB pulse, DIRB
remains HIGH due to the input stage
of FIFOB being empty. After another
63 SOB pulses, DORB remains LOW
due to both FIFOs being empty (14).
AdditionalSOB pulses have no effect.
The last word remains available at the
output Qn.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic
Package Outlines”
.
