Semiconductor Components Industries, LLC, 2004
January, 2004 − Rev. 0 1Publication Order Number:
NCP5425DEMO1/D
NCP5425DEMO1/D
NCP5425 Demonstration
Board Note
Single Input to Single Output Two−Phase
Buck Regulator 5.0 V to 0.8 V/30 A
The NCP5425 demonstration board contains all the
circuitry required for a two−phase Buck regulator. The IC
provides undervoltage lockout, soft start, built−in adaptive
FET non−overlap, a mode to interrupt switching to provide
low noise, and cycle−by−cycle overcurrent protection.
All of these features are provided on a 4.0″ by 4.0″
two−layer circuit board with an actual circuit area of 2.5″ by
2.3″.
Features
•Dual Synchronous Buck Topology
•Programmable Input Current Ratio between Phases
allows Separate Input Power Rationing
•Out−of−Phase Synchronization between Channels
•Cycle−by−Cycle Overcurrent Protection
•Undervoltage Lockout
•Low Noise Disable Mode
Figure 1.
DEMONSTRATION NOTE
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Figure 2. NCP5425 Demo Board
MAXIMUM RATINGS
Pin Name VMAX VMIN ISOURCE ISINK
5.0 VIN 6.3 V −0.3 V N/A N/A
5.0 V RTN 0.3 V −0.3 V N/A N/A
VOUT 2.0 V −0.3 V 40 A N/A
VOUT RTN 0.3 V −0.3 V N/A 40 A
TERMINAL DESCRIPTION
Terminal Name Description
5.0 V Input Power Source
5.0 V RTN 5.0 V Input Power Source Return
VOUT 0.8 V/30 A Output
VOUT RTN 0.8 V Output Return
LNDM Low Noise Disable Mode
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Figure 3. NCP5425 Single Output Demonstration Board
GATE H1
GATE L1
IS+1
IS−1
COMP1
Vfb1
GATE H2
GATE L2
IS−2
IS+2
COMP2
Vfb2
VREF2
Rosc
GND
MODE
NC
NC
Vcc
BST
U1
NCP5425
16
3
5
6
10
9
8
7
2
1
Q4
NTD110N02RT4
C30
R26
n/a
R3
523
R5
0
R4
10 K R6
Open
R22
7.5 K C8
0.22 F
C29
Open
C3 C4 C12
n/a
1800 F/6.3 V (2X)
C26
10 F/16 V
C27
n/a
10 F/16 V
SWN1
C5
n/a C2 C1
1500 F/16 V (2X) Q3
NTD60N02R
C19
10 F/
16 V
5 Vin
Vin RTN
5 V
R11
0
C10
1.0 F
18
4
C11
1.0 F
0.22 F
C16 R23
0
D1
BAV99LT1
n/a D4
20
Q1
NTD60N02R
C22
10 F/
16 V
C17 C18
n/a C6
1500 F/16 V (2X)
Q2
NTD110N02RT4
19
15
14
13
11
12
17
SWN2
R27
n/a C14
0.1 F
R15
523
R16
10 K
R12
30.1 K
JP1
1
2
Normally
Shorted
Q5
MMBF2201NT1
C13
0.047 F
LN Disable
Mode (0 V)
R1
10 K
10 F/16 V
C28
10 F/16 V
C32
n/a C7 C9 C20
n/a
0.8 V Sense
0.8 V Return
1800 F/6.3 V (2X)
L2
1.0 H/
1 m
D3
MBRM120ET3
R20
11 K
C23
0.1 F
R19
Open
0.8 V @ 30 A
VOUT RTN
C31
n/a
D2
MBRM120ET3
Open
R8
R17
11 K L1
1.0 H/1 m
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OPERATION GUIDELINES
•To power the demo board, an adjustable high current
DC power supply is required. To fully examine the
capabilities of this board, select a 5.0 V supply capable
of 10 A continuous output current.
•The VIN and LGND terminals are located on the top of
the board. The positive and negative terminals of the
5.0 V power supply should be connected to 5.0 VIN and
5.0 RTN respectively.
•The demo board will start up once the voltage applied
to the VIN pin reaches 4.2 V.
•The VOUT 0.8 V and VOUT RTN terminals are located
on the bottom of the board. If using mechanical
pressure connectors, keep in mind that the 0.8 V output
can source up to 30 A.
•The demo board will go into cycle−to−cycle
overcurrent protection when the current reaches
approximately 42 A at room temperature and
approximately 40 A when at maximum operating
temperature. To set different current limits levels, the
values of R3 and R15 must be changed. Please refer
to the data sheet for details.
•The NCP5425 has a Low Noise Disable Mode. This
feature allows the user to temporarily disable both
output drivers (<100 A) thereby reducing radiated and
conducted EMI in noise−sensitive applications. To
evaluate this feature, Jp1 must be removed, and 3.3 V
applied to the L.N. Mode pin to restore normal
operation. With those modifications, the user may
disable the clock by bringing the L.N. Mode pin to 0 V.
This disables both gate drivers, leaving the switch node
floating, and discharges the internal ramp. If this
feature is not required, leave Jp1 in place.
DESIGN GUIDELINES
Please see the NCP5425 data sheet for guidelines on using
and designing with the NCP5425.
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ELECTRICAL CHARACTERISTICS (0°C Tambient 50°C, 4.5 V Vin 5.5 V, fSW = 300 kHz, unless otherwise specified.)
Characteristic Test Condition Min Typ Max Unit
VOUT
Output Voltage 0.5 A < I(VOUT) < 30 A 0.788 0.8 0.812 V
Line Regulation
5.0 V 4.5 V ≤ VIN (5.0 V) ≤ 5.5 V − 0.05 − −
Load Regulation 0.5 A < I(VOUT1) < 30 A − 0.16 − %
Ripple and Noise 0.5 A < I(VOUT1) < 10 A, 20 MHz Scope Bandwidth − 25 − mV(p−p)
Transient Regulation 25 A Load Step, 20 MHz Scope Bandwidth − 60 − mV
Transient Recovery Time 30 A Load Step, 20 MHz Scope Bandwidth.
Measure the time when output exceeds DC limit. − 15 − s
Efficiency I(VOUT) = 15 A, see graph on page 8 for efficiency
overload current. − 86 − %
Over−Current Threshold − 39 42 44 A
VIN
Start Threshold − 3.8 4.2 4.6 V
Stop Threshold − 3.6 4.0 4.4 V
GENERAL
Efficiency Load = 25 A − 80 − %
Switching Frequency Free Running 224 300 376 kHz
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Figure 4. Normal Operation with No Load
TYPICAL OPERATING CHARACTERISTICS
Figure 5. Normal Operation with 30 A Load
Figure 6. GATEL1−GATEH1 Transition Showing
Rise, Fall and Non−Overlap Times with No Load Figure 7. GATEL1−GATEH1 Transition Showing
Rise, Fall and Non−Overlap with 30 A Load
Figure 8. GATEH1−GATEL1 Transition Showing
Rise, Fall and Non−Overlap Times with No Load Figure 9. GATEH1−GATEL1 Transition Showing
Rise, Fall and Non−Overlap Times with 30 A Load
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Figure 10. GATEL2−GATEH2 Transition Showing
Rise, Fall and Non−Overlap Times with No Load
TYPICAL OPERATING CHARACTERISTICS
Figure 11. GATEL2−GATEH2 Transition Showing
Rise, Fall and Non−Overlap Times with 30 A Load
Figure 12. GATEH2−GATEL2 Transition Showing
Rise, Fall and Non−Overlap Times with No Load Figure 13. GATEH2−GATEL2 Transition Showing
Rise, Fall and Non−Overlap Times with 30 A Load
Figure 14. Dynamic Load Step from 0 to 25 A,
Showing IOUT and VOUT
Figure 15. Turn−on of Dynamic Load Step from
0 to 25 A
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Figure 16. Turn−off of Dynamic Load Step from
25 to 0 A
Efficiency NCP5425 Single In to Single
Output
60
65
70
75
80
85
90
0.00 5.00 10.00 15.00 20.00 25.00 30.00
Load Currents (A)
Figure 17. Graph Shows the Efficiency of the
Total Application
Efficiency (%)
Ch. 1 Ch. 2 Ch. 1 Ch. 2
Load 0 35 A
Top FET 27 27 81 85 °C
Bottom FET 28 28 74 78 °C
Inductor 27 27 55 55 °C
Input Cap. 26 26 52 52 °C
Output Cap. 26 27 43 43 °C
IC 34 N/A 65 N/A °C
Figure 18. Component Temperatures Measured in Still
Air, and Ambient Temperature at 23C
Current Sharing
0
5
10
15
20
0 10203040
Load(A)
Phase Current(A)
Ph1(A) Ph2(A)
Figure 19. Master (Ph1) and Slave (Ph2) Phase
Current Over Output Load
−5
Figure 20. The NCP5425 in Low Noise Disable Mode
for 100 s. Showing SWN1, SWN2, VOUT ripple and
disable signal (both Controllers are disabled).
Figure 21. Startup showing VOUT, Comp1 and 2.
VOUT and Comp2 start to rise when Comp1
reaches approximately 0.3 V (internal offset).
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Figure 22. PCB Layout
Top Layer Bottom Layer
Silk Layer
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Table 1. Bill of Material
Part Type Designator Footprint Description MFG Part Number Manufacturer
0.01 F/25 V (Not Used) C30,31 805 Ceramic Capacitor VJ0805Y103KXXAT00 Vishay
0.047 F C13 805 Ceramic Capacitor VJ0805Y473KXXAT00 Vishay
0.1 F C14,23 805 Ceramic Capacitor VJ0805Y104KXXAT00 Vishay
0.22 F C16 1206 Ceramic Capacitor VJ1206Y224KXXAT00 Vishay
0.22 F C8 805 Ceramic Capacitor VJ0805Y224KXXAT00 Vishay
1.0 F C10,11 805 Ceramic Capacitor C2012X5RIC105 TDK
10 F/16 V C19,22,26,28 1206 Ceramic Capacitor C3225X7R1C106MT TDK
10 F/16 V (Not Used) C,27,32 1206 Ceramic Capacitor C3225X7R1C106MT TDK
1800 F/6.3 V (2X)
(Both Outputs) C3,4,7,9 TH−F Through Hole Cap 6.3MBZ1800M
(10X16) Rubycon
1800 F/6.3 V (Not Used) C12,20 TH−F Through Hole Cap 6.3MBZ1800M
(10X16) Rubycon
1500 F/16 V (2X) 12 V
(Both Inputs) C1,2,6,17 TH−F Through Hole Cap 16MBZ1500M
(10X20) Rubycon
1500 F/16 V (Not Used) C5,18 TH−F Through Hole Cap 16MBZ1500M
(10X20) Rubycon
Open (Not Used) C29 805 Ceramic Capacitor − Vishay
0 R5,11,23 805 Resistor CRCW080500R0 Vishay
10 (Not Used) R26,27 805 Resistor CRCW080510R0F Vishay
523 R3,15 805 Resistor CRCW0805523RF Vishay
7.5 K R22 805 Resistor CRCW08057K50F Vishay
10 K R1,4,16 805 Resistor CRCW080510K0F Vishay
11 K R17,20 805 Resistor CRCW080511K0F Vishay
20 K (Not Used) R6 805 Resistor CRCW080520K0F Vishay
30.1 K R12 805 Resistor CRCW080530K1F Vishay
Open (Not Used) R8,19 805 Resistor − Vishay
1.0 H/1.0 m L1 & 2 Inductor SER−1590 SER1590−102MX Coilcraft
BAV99LT1 D1 SOT−23 Dual Diode BAV99LT1 ON
Semiconductor
MMBZ5240BLT1 (Not Used) D4 SOT−23 Zener Diode MMBZ5240BLT1 ON
Semiconductor
MBRM120ET3 D2,3 PowerMite Schottky Diode MBRM120ET3 ON
Semiconductor
NCP5425 U1 TSSOP−20 Dual Synchronous
PWM NCP5425 ON
Semiconductor
NTD60N02R Q1,Q3 D−Pak N Ch MOSFET NTD60N02R ON
Semiconductor
NTD110N02R Q2,Q4 D−Pak N Ch MOSFET NTD110N02R ON
Semiconductor
MMBF2201NT1 Q5 SOT−323 N Ch MOSFET MMBF2201NT1 ON
Semiconductor
NCP5425DEMO1/D
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Notes
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81−3−5773−3850
NCP5425DEMO1/D
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