FEATURES MCS-48 and MCS-80/85 bus compatible-no inter. facing logic required ADCO0801-ADC0804 8-Bit Microprocessor Compatible A/D Converters GENERAL DESCRIPTION The ADC0801 family are CMOS 8-bit successive approxi- mation A/D converters which use a modified potentiometric ladder, and are designed. to operate with the 8080A control * Conversion time < 100 us b ia three-stat tputs. These converters appear to the Easy interface to all microprocessors us via three-state outpuls. ers appear i processor as memory locations or 1/0 ports, hence no inter- Will operate stand alone facing is required Differential analog voltage inputs , * Bandgap voltage references A differential analog voltage input allows increasing the TTL compatible inputs and outputs common-mode-rejection and offsetting the analog zero input * ON-chip clock generator voltage value. In addition, the voltage reference input can be . adjusted to allow encoding any smatier analog voltage span e supply) analog voltage input range (single + 5V to the full 8 bits of resolution. * No zero adjust required The ADC0801 family is available in the industry standard 20 pin CERDIP packages. TYPICAL APPLICATION PIN CONFIGURATION C V+ OR Vace 6s Veo +22 D [1] CLKR } 0} AD CLK RHA me | wR [18] DBO (LSB) +---BO! WR So NTR oxk in}A I 50 pF ctk [4] Bt a DET ap iNTR p82 a ANY + DBs 6 8-BIT RESOLUTION PROCESSOR a - hogs WING) 7 3 DIFF JoveR ANY DESIRED +n [6] 15] 083 Ce 14 - INPUTS ) ANALOG INPUT -IN B4 | 75 | 084 vin(-) a VOLTAGE RANGE Ha) 0 16 pas AGND - ANALOG GND [a | DBS yi 7 oes Vaeri2 }2~O Vacel2 Vagri2 [12] pee 18 10 = <. DBO DGND Ay - DIGITAL GND [10] DB7 (MSB) TOP VIEW ORDERING INFORMATION TEMPERATURE ORDER PART ERR OR RANGE PACKAGE NUMBER ADC0801 + 1/4 bit adjusted full scale 0C to + 70C 20 pin CERDIP ADC0801LCN 40C to + 85C 20 pin CERDIP ADCO0801LCD 55C to +128C 20 pin CERDIP ADCOS801LD ADC0802 + 1/2 bit no adjust 0C to + 70C 20 pin CERDIP ADC0802LCN 40C to +85C 20 pin CERDIP ADC0802LCD 55C to +125C 20 pin CERDIP ADC0802i-_D ADC0803 + 1/2 bit adjusted full scale 0C to + 70C 20 pin CERDIP ADCO0803LCN - 40C to +85C 20 pin CERDIP ADCO803LCD 85C to +125C 20 pin CERDIP ADCO08031-D ADC0804 + 1 bit no adjust QC to +70C 20 pin CERDIP ADCO804LCN - 40C to +.85C 20 pin CERDIP ADCO804LCD 4-9 ADC0801ADC0804 DNMNERSIL ABSOLUTE MAXIMUM RATINGS OPERATING RATINGS Supply Voltage . Wenner eee ete tenet een ene > 6.5V Temperature Range Voltage atAnyinput..............-. -0.3Vto(V+t +0.3V) ADCO801/02/03LD ...............005 ~55C to +125C Storage Temperature Range ........... - 65C to + 150C ADCO801/02/03/04LCD ...........008. 40C to + 85C Package Dissipation at Ty = 25C ..........6..005. 875 mW ADCO801/O2/03/04LON... 0... cee eee eee OCto + 70C Lead Temperature (Soldering, 10seconds) .........- 300C Supply Voltage Range .......... bette eens 4.5V to6.5V ELECTRICAL CHARACTERISTICS . - Converter Specifications: V+ =5V, Vace/2 = 2.500V, Twn S Ta S Tmax and f, = 640 kHz unless otherwise stated. PARAMETER MIN TYP MAX UNIT TEST CONDITIONS ADC0801: Total Adjusted Error 14 LSB With Full Scale Adjust ADC0802: . Total Unadjusted Error + 1/2 LSB Completely Unadjusted ADC0803: Total Adjusted Error + 1/2 LSB With Full Scale Adjust ADCO0804: Total Unadjusted Error +1 LSB Completely Unadjusted Vrer/2 Input Resistance 1.0 1.3 kQ Input Resistance at Pin9 Analog Input Voltage Range GND - 0.05 V++0.05 v DC Common-Mode Rejection + 1/16 +8 LSB Over Analog Input Voltage Range Power Supply Sensitivity + 1/16 + 18 LSB V+ =5V + 10% Over Allowed Input Voltage Range Timing Specifications: V + =5V and T, = 25C unless otherwise stated. PARAMETER MIN TYP MAX UNIT TEST CONDITIONS fe Clock Frequency 100 640 1280 kHz vt =6V, 100 640 800 kHz V+ =5V teony Conversion Time : 66 73 ns CR Conversion Rate In Free-Running Mode 8770 ConviS INTR tied to WR with CS = OV, f, = 640 kHz twovay. Width of WR Input (Start Pulse Width) 100 ns CS =0V tacc Access Time (Delay from Falting Edge of 135 200 ns C, = 100 pF (Use Bus Driver IC RD to Output Data Valid) tor Larger ,) tiy, toy 3-State Control (Delay from Rising Edge 125 250 ns C, = 10 pF, R, = 10k of RD to Hi-Z State) tw Delay from Falling Edge of WR to 300 450 ns Reset of INTR Cin Input Capacitance of Logic - 5 75 pF Control Inputs Cour 3-State Output Capacitance (Data Buffers) 5 75 pF 4-10