Am29F040B-90ECB - Advanced Micro Devices

PRELIMINARY

Publicati on# 21445 Rev: BAmendment/+2

Issue Date: April 1998

Am29F040B

4 Megabit (512 K x 8-Bit)

CMOS 5.0 Volt-only, Uniform Sector Flash Memory

Distinctive Characteristics

■5.0 V ± 10% for read and write operations

— Minimizes system level power requirements

■Manufactured on 0.35 µm process technology

— Compatible with 0.5 µm Am29F040 device

■High performan c e

— Access times as fast as 55 ns

■Low power consumptio n

— 20 mA typical active read current

— 30 mA typical program/erase current

— 1 µA typical standby current (standard access

time to active mode)

■Flexible sector architecture

— 8 unifor m sectors of 64 Kbytes each

— Any combination of sectors can be erased

— Supports full chip erase

— Sector protection:

A hardware method of lo cking sectors to pre vent

any program or erase operations within that

sector

■Embe dded Algorithms

— Embedded Erase algorithm automatically

preprogr ams and erases the ent ire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

■Minimum 1,000,000 program/erase c ycles per

sector guaranteed

■Package options

— 32-pin PLCC, TSOP, or PDIP

■Compatible with JEDEC standar ds

— Pinout and software compatible with

single-power-supply Flash standard

— Superior inadvertent write protection

■Data# Polling and toggle bits

— Provides a software method of detecting

program or erase cycle completion

■Erase Suspend/Erase Resume

— Suspends a sector erase operation to read data

from, or progr am data to, a non-erasing sector,

then resumes the erase operation

2 Am29F040B

PRELIMINARY

GENERAL DESCRIPTION

The Am29F040B is a 4 M bit, 5.0 volt-only Flash mem-

ory organized as 524,288 Kbytes of 8 bits each. The

512 Kbyt es of data are divided into eight sectors of 64

Kbytes each for flexible erase capability. The 8 bits of

data appear on DQ0–DQ7. The Am29F040B is off ered

in 32-pin PLCC, TSOP, and PDIP packages. This de-

vice is designed to be programm ed in-system with the

standard system 5.0 v olt V CC supply. A 12.0 volt VPP is

not required for write or erase operations. The device

can also be programmed in standard EPROM pro-

grammers.

This device is manufactured using AMD’s 0.35 µm

process technolog y, and off ers all the f eatures an d ben-

efits of the Am29F040, whic h was manufactured using

0.5 µm process technology. In addtion, the

Am29F040B has a second toggle bit, DQ2, and also

offers the ability to program in the Erase Suspend

mode.

The standard Am29F040B offers access times of 55,

70, 90, 120, and 150 ns, allowing high-speed micropro-

cessors to oper ate without w ait states . To eliminate b us

contention the device has separat e chip enable (CE#),

write enable (WE#) and output enable (OE#) controls.

The de vice requires only a single 5.0 volt power sup-

ply for both read and write functions. Inter nally gener-

ated and regulated voltages are provided for the

program and erase operations.

The de vice is entirely command set compatib le with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-

dard microprocessor write timings. Register contents

serve as input to an internal state-machine that con-

trols the er ase and programming circuitry. Write cycles

also internally latch addresses and data neede d f or the

programming and erase operations. Reading data out

of the device is similar to reading from other Flash or

EPROM de vices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprogr ams the arra y (i f it is not already prog rammed)

bef ore ex ecuting the er ase operation. During er ase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by reading the DQ7 (Data#

Polling) and DQ6 (toggle) status bits. After a program

or erase cycle has been completed, the de vice is ready

to read array data or accept another command.

The sector erase ar chitecture a llo ws memory se ctors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achie v ed via prog ramming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure . True background er ase can thus be achieved.

The system can place the device into the standby

mode. Power consumption is greatly reduced in

this mode.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases al l b it s wi th i n a

sector simultaneously via Fowler-Nordheim tunnel-

ing. The data is programmed using hot electron injec-

tion.

Am29F040B 3

PRELIMINARY

PRODUCT SELECTOR GUIDE

Note: See the “AC Characteristics” section for more information.

BLOCK DIAGRAM

Family Part Number Am29F040B

Speed Option VCC = 5.0 V ± 5% -55

VCC = 5.0 V ± 10% -70 -90 -120 -150

Max access time, ns (tACC) 55 70 90 120 150

Max CE# access time, ns (tCE) 55 70 90 120 150

Max OE# access time, ns (tOE) 2530355055

Erase Voltage

Generator

Y-Gating

Cell MatrixX-Decoder

Y-Decoder

Address Latch

Chip Enable

Output Ena ble

Logic

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

WE#

CE#

OE#

A0–A18

STB

DQ0–DQ7

VCC

VSS

21445B-1

Data Latch

Input/Output

Buffers

4 Am29F040B

PRELIMINARY

CONNECTION DIAGRAMS

21445B-2

VCC

WE#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

A18

A16

A15

A12

DQ0

DQ1

DQ2

VSS

PDIP

13 17 18 19 20161514

1313023432

DQ0

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

A14

A13

A11

OE#

A10

CE#

DQ7

A12

A15

A16

A18

VCC

WE#

A17

21445B-3

PLCC

A11

A13

A14

A17

WE#

VCC

A18

A16

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

A11

A13

A14

A17

WE#

VCC

A18

A16

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

21445B-4

32-Pin Standard TSOP

32-Pin Reverse TSOP

Am29F040B 5

PRELIMINARY

PIN CONFIGURATION

A0–A18 = Address Inputs

DQ0–DQ7 = Data Input/Output

CE# = Chip Enable

WE# = Write Enable

OE# = Output Enable

VSS = De vice Ground

VCC = +5.0 V single power supply

(see Product Selec tor Guide for

device speed ratings and voltage

supply tolerances)

LOGIC SYMBOL

ORDERING INFORMATION

Standard Prod ucts

AMD standard products are a vailable in se veral packages and operating ranges. The order number (V alid Combination) is formed

by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in v olume for this device. Consult the local AMD sales

office to confirm a vailability of specific valid combinations and

to check on newly released combinations.

DQ0–DQ7

A0–A18

CE#

OE#

WE#

21445B-5

DEVICE NUM BE R/ DES CR IPT IO N

Am29F040B

4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory

5.0 V Read, Program, and Erase

Am29F040B -55 E C B

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I=Industrial (–40°C to +85°C)

E = Extend ed (–5 5°C to +125°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)

J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

Am29F040B-55 JC, JI, JE, EC, EI, EE, FC, FI, FE

Am29F040B-70

Am29F040B-90 PC, PI, PE,

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

Am29F040B-120

Am29F040B-150

6 Am29F040B

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory loca-

tion. The regi st er is composed of latc hes that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. The appropriate device bus operations

table lists the inputs and control le vels required, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29F040B Device Bus Operations

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0

0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In

Note: See the section on Sector Protection for more information.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device . OE# is the output control

and gates arra y dat a to the output pins . WE# should re-

main at VIH.

The internal state machine is set for reading array

data upon device power-up , or after a hardware reset.

This ensures that no spur ious alteration of the mem-

ory content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs

produce valid data on the device data outputs. The

device remains enabled for read access until the

command reg ister contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to the Read Operations Timings diagram for

the timing waveforms. ICC1 in the DC Characteristics

table represents the active current specification for

reading array data.

Writing Commands/Command Sequences

To wr ite a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

An erase oper at ion can er ase one sect or, multiple sec-

tors, or the entire de vice. The Sector Address Tables in-

dicate the address space that each sector occupies. A

“sector address” consists of the address bits required

to uniquely select a sector. See the “Command Defini-

tions” section for details on erasing a sector or the en-

tire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autos elect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections f or more information.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tabl es and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or prog ram opera tion, the system ma y

check the status of the operation by reading the status

bits on DQ7–DQ0. Sta ndard read cycle timings and I CC

read specifications apply. Refer to “Write Operation

Status” for more information, and to each AC Charac -

teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the de vice,

it can place the device in the standby mode. In this

mode, current con sumption is g reat ly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

Operation CE# OE# WE# A0–A20 DQ0–DQ7

Read L L H AIN DOUT

Write L H L AIN DIN

CMOS Sta ndby VCC ± 0.5 V X X X High-Z

TTL Standby H X X X High-Z

Output Disable L H H X High-Z

Am29F040B 7

PRELIMINARY

The device enters the CMOS standby mode when the

CE# pin is held at VCC ± 0.5 V. (Note that this is a more

restricted voltage range than VIH.) The device enters

the TTL standby mode when CE# is held at VIH. The

dev ice requires the st andard access time (t CE) b efore it

is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

ICC3 in the DC Characteristics tables represents the

standby current specification.

Output Disable Mode

When the OE# input is at VIH, output from the de vice is

disabled. The output pins are plac ed in the h igh imped-

ance state.

Table 2. Sector Addresses Table

Note: All sectors are 64 Kbytes in size.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended f or programming equipment

to automatically match a de vice to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the c ommand register.

When using programming equipment, the autoselect

mode requires VID (11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Aut oselect Codes (High Voltage Method) tab le. In addi-

tion, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order

address bits. Refer to the corresponding Sector Ad-

dress Tables. The Command Definitions table shows

the remaining address bits that are don’t care . When all

necessary b its hav e been set as required, the progr am-

ming equipment may then read the corresponding

identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in the Command Defini-

tions table. This method does not require VID. See

“Command Definitions” for details on using the autose-

lect mode.

Sector A18 A17 A16 Address Range

SA0 0 0 0 00000h–0FFFFh

SA1 0 0 1 10000h–1FFFFh

SA2 0 1 0 20000h–2FFFFh

SA3 0 1 1 30000h–3FFFFh

SA4 1 0 0 40000h–4FFFFh

SA5 1 0 1 50000h–5FFFFh

SA6 1 1 0 60000h–6FFFFh

SA7 1 1 1 70000h–7FFFFh

8 Am29F040B

PRELIMINARY

Table 3. Am29F040B Autoselect Co des (High Voltage Method)

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The

hardware sector unprotection feature re-enables both

program and erase operations in previously pro-

tected sectors.

Sector protection/unprotection must be implemented

using programming equipment. The procedure re-

quires a high voltage (VID) on address pin A9 and the

control pins. Details on this method are provided in a

supplement, publication number 19957. Contact an

AMD representativ e to obtain a copy of the appropriate

document.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possib le to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to the Command Defi-

nitions table). In addition, the following hardware data

protection measures pre vent accidental eras ure or pro-

gramming, which might otherwise be caused by spuri-

ous system level signals during VCC power-up and

power-down transitions, or from system noise.

Low V CC Write Inhibit

When VCC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-do wn. The command register and

all internal program/er ase circuits are disabled, and the

dev ice resets . Subsequent writes are ignored until VCC

is greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical In hibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up , the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates de vice op-

erations. The Command Definitions table defines the

valid register command sequences. Writing incorrect

address and data values or writing them in the im-

proper sequence resets the device to reading array

data.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Charac teristics” section.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within eras e-

suspended sectors, the device outputs status data.

After completi ng a prog ramming ope ration in t he Er ase

Suspend mode, the system may once again read arra y

Description A18–A16 A15–A10 A9 A8–A7 A6 A5–A2 A1 A0 Identifier Co de on

DQ7-DQ0

Manufacturer ID: AMD X X VID XV

IL XV

IL VIL 01h

Device ID: Am29F040B X X VID XV

IL XV

IL VIH A4h

Sector Protec tion

Verification Se cto r

Address XV

ID XV

IL XV

IH VIL 01h (protec ted )

00h (unprotected)

Am29F040B 9

PRELIMINARY

data with the same exception. See “Erase Suspend/

Erase Resume Commands” for more infor mation on

this mode.

The system

must

issue the reset command to re-en-

abl e the de vice f or reading arr ay data if DQ5 goes high,

or while in the autoselect mode. See the “Res et Com-

mand” se ctio n , next.

See also “Requirements for Reading Arr a y Data” in the

“Device Bus Operations” section for more infor mation.

The Read Operations table provides the read param e-

ters, and Read Operation Timings diagram shows the

timing diagram.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Addres s bits are don’t c are

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the au toselect mode , the r eset command

must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operat ion,

writing the reset command retur ns the device to read-

ing array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the man uf acture r and devices c odes,

and determine whether or not a sector is protected.

The Command Definitions table shows the address

and data requirements . This method is an alternativ e to

that shown in the Autoselect Codes (High Voltage

Method) table, which is intended for PROM program-

mers and requires VID on address bit A9.

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

A read cycle at address XX00h or retrie v es the manu-

facturer cod e. A read cycle a t ad dress X X 01h returns

the device code. A read cycle containin g a sector ad-

dress (SA) and the address 02h in returns 01h if that

sector i s pr ot ected, o r 0 0h if it i s unp rotect e d. Refer to

the Sect or Address tables for valid sector addresses.

The system must write the reset command to exit the

autoselect mode and return to reading arra y data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated b y writing two un-

lock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is

not

required to provide fur ther

controls or timings. The device autom atically provides

internally generated progr am pulses and v erify the pro-

grammed cell margin. The Command Definitions take

shows the address and data requirements for the byte

progr am command sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the stat us of the p rogra m operation by using DQ7

or DQ6. See “Write Operation Status” for information

on these status bits.

Any commands written to the device during the Em-

bedded Progr am Algorithm are ignored.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempti ng to do so ma y halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. Howe ver , a succeeding read will show that the

data is still “0”. Only erase operations can conv ert a “0”

to a “1”.

10 Am29F040B

PRELIMINARY

Note: See the appropriate Command Definitions table for

program comma nd seq ue nce.

Figure 1. Program Operation

Chip Erase Command Sequence

Chip erase is a six-b us-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, fo llowed by a set-up command. Two additional

unlock write cycles ar e then followed by the c hip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does

not

require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprogr ams a nd v e rifies the entire

memor y for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during thes e operations. The Command

Definitions table shows the address and data require-

ments f or the chip erase command sequence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored.

The system can determine the status of the erase

operation by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status

bits. When the Embedded Erase algorithm is com-

plete, the device returns to reading array data and

addresses ar e no long er latched.

Figure 2 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to the Chip/Sector

Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated b y writing two un-

lock cycles, fo llowed by a set-up com mand. Two addi-

tional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. The Command Definitions table

shows the address and data requirements for the sec-

tor erase command sequence.

The device does

not

require the system to preprogram

the memory prior to er ase. The Embedded Erase algo-

rithm automatically progr ams and verifies the s ector f or

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

ma y be done in any sequence , and the number of sec-

tors ma y be from one sector to al l sectors. The time be-

tween these additional cycles mus t be less than 50 µs,

otherwise the last address and command might not be

accepted, and erasure may begin. It is recommended

that processor interrupts be disab led during this time to

ensure all commands are accepted. The inte rrupts can

be re-enabled after the last Sector Erase command is

written. If the time between additional sector erase

commands can be assumed to be les s than 50 µs, the

system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the

time-out period resets the device to reading array

data. The system must rewrite the command sequence

and any additional sector addresses and commands.

The system can monitor DQ3 t o determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, only the

Erase Suspend command is v alid. All othe r commands

are ignored.

When the Embedded Erase algorithm is complete, the

dev ice returns to reading arr a y dat a and addr esses are

no longer latched. T he sys tem can deter mine the sta-

tus of the e rase operat ion b y using DQ7, DQ6, or DQ2.

Refer to “Write Operation Status” for information on

these status bits.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

21445B-6

Am29F040B 11

PRELIMINARY

Figure 2 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “A C Char acteristics ” section f or par amet ers , and to

the Sector Er ase Oper ations Timing dia gr am for timing

waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend c ommand allo ws the s ystem to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and s uspends t he er ase oper at ion. Ad-

dresses are “don’t-cares” when writing the Erase Sus -

pend command.

When the Erase Suspend command is written during a

sector erase oper ation, the de vice requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected f or eras ure. (The de vice “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determ ine

if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” for information on these

status bits.

After an erase-suspended program operation is com-

plete, t he system can once again read arr ay data within

non-suspended sectors. The system can determine

the status of the program operation using the DQ7 or

DQ6 status bits, just as in the s tandard program oper-

ation. See “Write Operation Status” for more informa-

tion.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “ Autoselect Command Sequence”

for more information.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the s ector erase oper ati on. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be wr itten after the de-

vice has resumed erasing.

Notes:

1. See the appropriate Command Definitions table for erase

command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 2. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

21445B-7

12 Am29F040B

PRELIMINARY

Table 4. Am29F040B Command Definitions

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read op eration.

PA = Address of the memory locati on to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be v erified (in autoselect mode) or

erased. Address bits A18–A16 select a unique sector.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading arra y or autoselect data, all b us cycles

are write operations.

4. Address bits A18–A11 are don’t cares for unlock and

command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading a rray

data.

6. The Reset com mand is required to return to reading array

data when device is in the autoselect mode, or if DQ5 goes

high (while the device is providing status data).

7. The fourth cycle of the autoselect command sequence is a

read cycle.

8. The data is 00h for an unprotected sector and 01h for a

protected sector. See “Autoselect Command Sequence” for

more information.

9. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend

mode. The Erase Sus pend command is valid on ly during a

sector erase operation.

10. The Erase Resume command is valid only during the Erase

Suspend mode.

Command

Sequence

(Note 1)

Bus Cycles (Notes 2–4)

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 5) 1 RA RD

Reset (Note 6) 1 XXX F0

Autoselect

(Note 7)

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01

Device ID 4 555 AA 2AA 55 555 90 X01 A4

Sector Protect Verify

(Note 8) 4 555 AA 2AA 55 555 90 SA

X02 XX00

XX01

Program 4 555 AA 2AA 55 555 A0 PA PD

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

Erase Suspen d (Note 9) 1 XXX B0

Erase Resume (N ote 10) 1 XXX 30

Cycles

Am29F040B 13

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to deter mine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 5 and the following subsections describe

the functions of these bits. DQ7 and DQ6 each offer a

method for determining whether a program or erase

operation is complete or in progress. These three bits

are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in

progress or completed, or whether the device is in

Erase Suspend. Data# P olling is v alid after the rising

edge of the final WE# pulse in the program or erase

command sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is a ctive f or ap-

proximately 2 µs, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When t he Embedded Erase al-

gorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous t o the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status in-

formation on DQ7.

After an er ase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately 100 µs, then t he de-

vice returns to reading array data. If not all selected

sectors are protec ted, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ7–DQ0 on the

following

read cycles. This is be-

cause DQ7 may change asynchronously with

DQ0–DQ6 while Output Enable (OE#) is asserted low.

The Data# Polling Timings (During Embedded Algo-

rithms) figure in the “AC Characteristics” section illus-

trates this.

Table 5 shows the outputs for Data# Polling on DQ7.

Figure 3 shows the Data# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

21445B-8

Figure 3. Data# Polling Algorithm

14 Am29F040B
PRELIMINARY
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Er ase algorithm is in prog ress or complete ,
or whether the dev ice has entered the Erase Sus pend
mode. Toggle Bit I may be read at any address,  and is
valid  after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read c ycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles f or app roximately 100 µ s , t hen returns to read ing
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected. 
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the de vice is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then retur ns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The Write Operation Status tab le shows the out puts for
Toggle Bit I on DQ6. Ref er to Figure 4 f or the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on D Q2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is ,  the Embedded Er as e alg orithm is in pr og ress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence. 
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode info rmation. Ref er t o Tabl e 5 to compare output s
for DQ2 and DQ6. 
Figure 4 shows the toggle bit algorithm in flowchart
for m, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subse ction.
Refer  to the Toggle Bit Timings figure for the toggle  bit
timing diagr am. The DQ2 vs. DQ6 figure sho ws the dif-
ferences between DQ2 and DQ6 in gr aphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 4 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle  bi t is togg ling. Typica lly, a
system w ould note and  store the v alue  of the toggle  bit
after the first read. After t he second read, the syst em
would co mpare the ne w v alue of the  toggle bit  with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The sys-
tem can r ead arra y data on  DQ7–DQ0 on  the f ollowing
read cycle.
However, if after the initial two read cycles, the  system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as  DQ5 went high. If  the toggle bit is  no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
dev ice did not complete the operat ion successfully, and
the system must wr ite the reset command to retur n to
reading array data. 
The remaining scenario is that the system initially de-
termines that the toggle bit  is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and  DQ5 t hrough successive  read cycles, de-
termining the statu s as described in the previous  para-
graph. Alternatively, it may choose to perform other
syst em task s.  In thi s case ,  the syst em m ust st art at the
beginning of the algorithm when it ret urns to determine
the status of the operation (top of Figure 4).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exc eeded a specified inter nal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that  indicates the pro gram or er ase cycle w as
not successfully completed. 

Am29F040B 15

PRELIMINARY

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system ma y read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tiona l sector s are selected f or erasure, th e enti re time-

out also applies after each additional sector erase

command. When the time-out is complete, DQ3

switches from “0” to “1.” The system may ignore DQ3

if the s ystem can gua rant ee that t he ti me betw een ad-

ditional sector erase commands will always be less

than 50 µ s . See also the “ Secto r Era se Command Se-

quence” sect ion.

After the sector erase command sequence is written,

the system should re ad the s tatus on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence , and then read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has be-

gun; all further commands (other th an Er ase Su spend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the s ystem softw are should chec k the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 5 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it ma y stop toggling as DQ5

changes to “1”. See text.

21445B-9

Figure 4. Toggle Bit Algorithm

(Notes

1, 2)

Note 1

16 Am29F040B

PRELIMINARY

Table 5. Write Operation Status

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

Operation DQ7

(Note 1) DQ6 DQ5

(Note 2) DQ3 DQ2

(Note 1)

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle

Embedded Erase Algorithm 0 Toggle 0 1 Toggle

Erase

Suspend

Mode

Reading with in Erase

Suspend ed Sec tor 1 No toggle 0 N/A Toggle

Reading with in Non -Eras e

Suspend ed Sec tor Data Data Data Data Data

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A

Am29F040B 17

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . .–2.0 V to 7.0 V

A9, OE# (Note 2). . . . . . . . . . . . .–2.0 V to 12.5 V

All other pins (Note 1) . . . . . . . . . .–2.0 V to 7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transition s, inpu ts may unde rsh oot VSS to – 2.0 V

for periods of up to 20 ns. See Figure 5. Maximum DC

voltage on input and I/O pins is VCC + 0.5 V. During

voltage transitions, input and I/O pins may overshoot to

VCC + 2.0 V for periods up to 20 ns. See Figure 6.

2. Minimum DC input voltage on A9 pin is –0.5 V. During

voltage transitions, A9 and OE# may undershoot V SS to

–2.0 V for periods of up to 20 ns. See Figure 5. Maximum

DC input voltage on A9 and OE# is 12.5 V which may

overshoot to 13.5 V for periods up to 20 ns.

3. No more than one output shorted to ground at a time.

Duration of the short circuit should not be greater than

one second.

Stresses above those listed under “Absolute Maximum

Ratings ” may cau se permane nt damage to the d evice. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the op-

erational sections of this specification is not implied. Expo-

sure of the device to absolu te max imu m ratin g con ditio ns for

extended periods may affect device reliability.

Figure 5. Maximum Negative Overshoot

Waveform

Figure 6. Maximum Positive Overshoot

Waveform

OPERATING RANGES

Commer cial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125°C

VCC Supply Voltages

VCC for ± 5% devi ces. . . . . . . . . . .+4.75 V to +5.25 V

VCC for± 10% de vices . . . . . . . . . . . .+4.5 V to +5.5 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

21445B-10

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

21445B-11

18 Am29F040B

PRELIMINARY

DC CHARACTERISTICS

TTL/NMOS Compatible

CMOS Compatible

Notes for DC Characteristics (both tables):

1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).

The frequency component typically is less than 2 mA/MHz, with OE# at VIH.

2. ICC active while Embedded Algorithm (program or erase) is in progress.

3. Not 100% tested.

4. For CMOS mode only, ICC3 = 20 µA max at extended temperatures (> +85°C).

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Active Read Current (Note 1) CE# = VIL, OE# = VIH 20 30 mA

ICC2 VCC Act ive Write (Pro gram/E rase)

Current (Notes 2, 3) CE# = VIL, OE# = VIH 30 40 mA

ICC3 VCC Standby Current VCC = VCC Max, CE# = VIH 0.4 1.0 mA

VIL Input Low Level –0.5 0.8 V

VIH Input High Level 2.0 VCC + 0.5 V

VID Voltage for Autoselect

and Sector Protect VCC = 5.25 V 10.5 12.5 V

VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V

VOH Output High Level IOH = –2.5 mA, VCC = VCC Min 2.4 V

VLKO Low VCC Lock-Out Voltage 3.2 4.2 V

Parameter

Symbol Parame ter Des cri ptio n Test Descr ipt ion Mi n Ty p Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Active Read Current

(Note 1) CE# = VIL, OE# = VIH 20 30 mA

ICC2 VCC Active Program/Erase Current

(Notes 2, 3) CE# = VIL, OE# = VIH 30 40 mA

ICC3 VCC Standby Current (Note 4) VCC = VCC Max, CE# = VCC ± 0.5 V 1 5 µA

VIL Input Low Level –0.5 0.8 V

VIH Input High Level 0.7 x VCC VCC + 0.3 V

VID Voltage for Autoselect and Sector

Protect VCC = 5.25 V 10.5 12.5 V

VOL Output Low Voltage IOL = 12.0 mA, VCC = VCC Min 0.45 V

VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V

VOH2 IOH = –100 µA, VCC = VCC Min VCC –0.4 V

VLKO Low VCC Lock-out Voltage 3.2 4.2 V

Am29F040B 19

PRELIMINARY

TEST CONDITIONS

Table 6. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

5.0 V

Device

Under

Test

21445B-12

ure 7. Test Setu

Note: Diodes are IN3064 or equivalent

Test Condition -55 All others Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap aci tan ce) 30 100 pF

Input Rise and Fall Times 5 20 ns

Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement

reference levels 1.5 0.8 V

Output timing measurement

reference levels 1.5 2.0 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changi ng from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

20 Am29F040B
PRELIMINARY
AC CHARACTERISTICS
Read Only Operations
Notes:
1. See Figure 7 and Table 6 for test conditions.
2. Output driver disable time.
3. Not 100% tested.
Parameter Symbols
Description T est Setup
Speed Options (Note 1)
UnitJEDEC Standard -55 -70 -90 -120 -150
tAVAV tRC Read Cycle Time (Note 3) Min 55 70 90 120 150 ns
tAVQV tACC Address to Output Delay CE# = VIL, 
OE# = VIL Max 55 70 90 120 150 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 150 ns
tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 55 ns
tOEH Output Enable Hold 
Time (Note 3)
Read Min00000ns
Toggle and 
Data# Polling Min1010101010ns
t
EHQZ tDF Chip Enable to Output High Z
(Notes 2, 3) Max1820203035ns
t
GHQZ tDF Output Enable to Output High Z 
(Notes 2, 3) 18 20 20 30 35 ns
tAXQX tOH Output Hold Time from Addresses, CE# 
or OE#, Whichever Occurs First Min00000ns
t
CE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
tDF
tOH
21445B-13
 Figure 8. Read Operation Timings

Am29F040B 21

PRELIMINARY

AC CHARACTERISTICS

Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter Symbols

Description

Speed Options

UnitJEDEC Std. -55 -70 -90 -120 -150

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 150 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min 40 45 45 50 50 ns

tDVWH tDS Data Setup Time Min 25 30 45 50 50 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHWL tGHWL Read Recover Time Before Write

(OE# high to WE# low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 30 35 45 50 50 ns

tWHWL tWPH Write Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Byte Programming Operation

(Note 2) Typ 7 µs

tWHWH2 tWHWH2 Sector Erase Operation

(Note 2) Typ 1 sec

tVCS VCC Set Up Time (Note 1) Min 50 µs

22 Am29F040B

PRELIMINARY

OE#

WE#

CE#

VCC

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tGHWL

tCS

Status DOUT

Program Command Sequence (last two cycles)

tCH

Note: PA = program address, PD = program data, DOUT is the true data at the program address.

21445B-14

Figure 9. Program Operation Timings

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tGHWL

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

Note:

SA = Sector Address. VA = Valid Address for reading status data.

21445B-15

Figure 10. Chip/Sector Erase Operation Timings

Am29F040B 23

PRELIMINARY

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle .

21445B-16

Figure 11. Data# Polling Tim ings (During E m bedded Alg orithm s)

WE#

CE#

OE#

High Z

tOE

DQ6/DQ2

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

tACC

tRC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note:

V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,

and array data read cycle.

21445B-17

Figure 12. Toggle Bit Timings (During Embedded Algorithms)

24 Am29F040B

PRELIMINARY

AC CHARACTERISTICS

Erase and Program Operations

Alternate CE# Controlled Writes

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Note: Both DQ6 and DQ2 toggle with OE# or CE#. See the text on DQ6 and DQ2 in the “Write Operation Status” section for more

information.

21445B-18

Figure 13. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Pro gra m

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2 DQ2 and DQ6 toggle with OE# and CE#

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

Parameter Symbols

Description

Speed Options

UnitJEDEC Standard -55 -70 -90 -120 -150

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 150 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 40 45 45 50 50 ns

tDVEH tDS Data Setup Time Min 25 30 45 50 50 ns

tEHDX tDH Data Hold Time Min 0 ns

tGHEL tGHEL Read Recover Time Before Write Min 0 ns

tWLEL tWS CE# Setup Time Min 0 ns

tEHWH tWH CE# Hold Time Min 0 ns

tELEH tCP Write Pulse Width Min 30 35 45 50 50 ns

tEHEL tCPH Write Pulse Width High Min 20 20 20 20 20 ns

tWHWH1 tWHWH1 Byte Programming Operation

(Note 2) Typ 7 µs

tWHWH2 tWHWH2 Sector Erase Operation

(Note 2) Typ 1 sec

Am29F040B 25

PRELIMINARY

AC CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 5.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for -55), 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then

does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-lev el overhead is the time required to e xecute the four-bus-cycle command sequence for programming. See Table 4

for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 8 sec Excludes 00h programming prior to

erasure (Note 4)

Chip Erase Time 8 64 sec

Byte Programming Time 7 300 µs Excludes system-level overhead

(Note 5)

Chip Programming Time (Note 3) 3.6 10.8 sec

tGHEL

tWS

OE#

CE#

WE#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.

2. Figure indicates the last two bus cycles of the command sequence.

21445B-19

Figure 14. Alternate CE# Controlled Write Operation Timings

26 Am29F040B

PRELIMINARY

LATCHUP CHARACTERISTICS

Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

PLCC AND PDIP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Min Max

Input Voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capac itan ce VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capac itan ce VIN = 0 4 6 pF

COUT Output Capacitance VOUT = 0 8 12 pF

CIN2 Control Pin Capacitance VPP = 0 8 12 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C 10 Years

125°C 20 Years

Am29F040B 27

PRELIMINARY

PH YS ICAL DIMENSIONS

PD 032

32-Pin Plastic DIP (measured in inches)

PL 032

32-Pin Plastic Leaded Chip Carrier (measured in inches)

Pin 1 I.D.

1.640

1.670

.530

.580

.005 MIN

.045

.065

.090

.110

.140

.225

.120

.160 .016

.022

SEATING PLANE

.015

.060

16-038-S_AG

PD 032

EC75

5-28-97 lv

32 17

16 .630

.700

0°

10°

.600

.625

.009

.015

.050 REF.

.026

.032 TOP VIEW

Pin 1 I.D.

.485

.495

.447

.453

.585

.595

.547

.553

16-038FPO-5

PL 032

DA79

6-28-94 ae

SIDE VIEW

SEATING

PLANE

.125

.140

.009

.015

.080

.095

.042

.056

.013

.021

.400

REF. .490

.530

28 Am29F040B

PRELIMINARY

PH YSICAL DIMENSI ONS (continued)

TS 032

32-Pin Standard Thin Small Package (measured in millimeters)

Pin 1 I.D.

18.30

18.50

7.90

8.10

0.50 BSC

0.05

0.15

0.95

1.05

16-038-TSOP-2

TS 032

DA95

3-25-97 lv

19.80

20.20

1.20

MAX

0.50

0.70

0.10

0.21

0°

5°

0.08

0.20

Am29F040B 29

PRELIMINARY

PH YSICAL DIMENSI ONS (continued)

TSR032

32-Pin Reversed Thin Small Outline Package (measured in millimeters)

18.30

18.50

19.80

20.20

7.90

8.10

0.50 BSC

0.05

0.15

0.95

1.05

16-038-TSOP-2

TSR032

DA95

3-25-97 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0°

5°

0.08

0.20

30 Am29F040B

PRELIMINARY

REVISION SUMMARY FOR AM29F040B

Global

Formatted for consistency with other 5.0 volt-only data

data sheets .

Revision B+1

A C Characteristi cs, Erase and Pr ogram Opera tions

Added Note references to tWHWH1. Corrected the pa-

rameter symbol for VCC Set-up Time to tVCS; the spec-

ification is 50 µs minimum. Deleted the last row in tab le.

Revision B+2

Distinctive Characteri stics

Changed minimum 100K write/erase cycles guaran-

teed to 1,000,000.

Ordering Infomation

Added e xtended temper ature a v ailability to t he -55 and

-70 speed options.

AC Characteristics

Erase/Program Operations; Erase and Program Oper-

ations Alternate CE# Controlled Wr ites:

Corrected the

notes ref erence f or tWHWH1 and tWHWH2. These param-

eters are 100% tested. Corrected the note ref erence for

tVCS. This parameter is not 100% tested.

Erase and Programming Performance

Changed minimum 100K program and erase cycles

guaranteed to 1,000,000.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.