CSP-12 QFN-10
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FEATURES DESCRIPTION
APPLICATIONS
VOUT
AVIN
SW
CIN
SW
LED
PGND
PGND P
P
P
AGND
GPIO
SDA
SCL
I2CI/F
FLASH_SYNC
L
P
TPS61050
2.2 Hm
C
10 F
OUT
m
+BATTERY
LED ANODE
DIGITAL I/O
PGND
INPUT
CAP
OUTPUT
CAP
INDUCTOR
C1
L1
C2
LED
SENSE
AGND
4.7mm
4.7mm
PGND
TPS61050
TPS61052
SLUS525 MARCH 2007
1.2-A HIGH POWER WHITE LED DRIVER2-MHz SYNCHRONOUS BOOST CONVERTER WITH I
2
C COMPATIBLE INTERFACE
Four Operational Modes
The TPS6105x device is based on a high-frequencysynchronous-boost topology with constant current Torch and Flash up to I
LED
= 1200 mA
sink to drive single white LEDs. The device uses an Voltage-Regulated Boost Converter:
inductive fixed-frequency PWM control scheme using4.5/5.0/5.25 V
small external components, minimizing input ripple Shutdown: 0.3 µA (typ)
current.Total Solution Circuit Area < 25 mm
2
The 2-MHz switching frequency allows the use ofUp to 96% Efficiency
small and low profile 2.2- µH inductors. To optimizeoverall efficiency, the device operates with only aI
2
C-Compatible Interface up to 400 kbps
250 mV LED feedback voltage.Integrated LED Turn-On Safety Timer
The TPS6105x device not only operates as aZero Latency TX-Masking Input (TPS61050)
regulated current source, but also as a standardHardware Voltage Mode Selection Input
voltage-boost regulator. This additional operating(TPS61052)
mode can be useful to supply other high-powerIntegrated ADC for LED V
F
Monitoring
devices in the system, such as a hands-free audiopower amplifier, or any other component requiring aIntegrated Low Light Dimming Mode
supply voltage higher than the battery voltage (referLED Disconnect During Shutdown
to TPS61052).Open/Shorted LED Protection
For highest flexibility, the LED current or the desiredOver-Temperature Protection
output voltage can be programmed via an I
2
CAvailable in a 12-Pin NanoFree™ (CSP) and
compatible interface. To simplify flashsynchronization with the camera module, the device10-Pin QFN Packaging
offers a trigger pin (FLASH_SYNC) for fast LEDturn-on time.Camera White LED Torch/Flash for Cell
When the TPS6105x is not in use, it can be put intoPhones, Smart-Phones and PDAs
shutdown mode via the I
2
C-compatible interface,reducing the input current to 0.3 µA (typ). DuringAudio Amplifier Power Supply
shutdown, the LED pin is high impedance to avoidleakage current through the LED.
Figure 1. Typical Application Figure 2. Typical PC-Board Layout
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.NanoFree, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
TPS61050
TPS61052
SLUS525 MARCH 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
SAFETY TIMERT
A
PART NUMBER
(1)
PACKAGE MARKING PACKAGEMAXIMUM DURATION
TPS61050YZG 1.02 s 61050 CSP-12TPS61050DRC 1.02 s BRV QFN-10–40 °C to 85 °C
TPS61052YZG 1.02 s 61052 CSP-12TPS61052DRC 1.02 s BRW QFN-10
(1) The YZG package is available in tape and reel. Add R suffix (TPS6105xYZGR, TPS6105xDRCR) to order quantities of 3000 parts. AddT suffix (TPS6105xYZGT, TPS6105xDRCT) to order quantities of 250 parts.
over operating free-air temperature range (unless otherwise noted)
(1)
TPS6105X UNIT
Voltage range on AVIN, VOUT, SW, LED
(2)
–0.3 to 7 VVoltage range on SCL, SDA, FLASH_SYNC, GPIO, ENVM
(2)
–0.3 to 7 VInput current on GPIO 25 mAT
A
Operating ambient temperature range
(3)
–40 to 85 °CT
J (MAX)
Maximum operating junction temperature 150 °CT
stg
Storage temperature range –65 to 150 °CHuman body model 2 kVESD
Charge device model 1 kVrating
(4)
Machine model 200 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature mayhave to be derated. Maximum ambient temperature (T
A(max)
) is dependent on the maximum operating junction temperature (T
J(max)
), themaximum power dissipation of the device in the application (P
D(max)
), and the junction-to-ambient thermal resistance of the part/packagein the application ( θ
JA
), as given by the following equation: T
A(max)
= T
J(max)
–( θ
JA
X P
D(max)
).(4) The human body model is a 100-pF capacitor discharged through a 1.5-k resistor into each pin. The machine model is a 200-pFcapacitor discharged directly into each pin.
DERATING FACTORPOWER RATINGPACKAGE THERMAL RESISTANCE
(1) (2)
ABOVE
(1) (2)T
A
= 25 °C
T
A
= 25 °C
YZG θ
JA
= 89 °C/W θ
JB
= 35 °C/W 1.1 W 12 mW/ °CDRC θ
JA
= 49 °C/W θ
JC
= 3.2 °C/W 2.4 W 20 mW/ °C
(1) Measured with high-K board.(2) Maximum power dissipation is a function of T
J(max)
,θ
JA
and T
A
. The maximum allowable power dissipation at any allowable ambienttemperature is P
D
= (T
J(max)
–T
A
)/ θ
JA
.
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ELECTRICAL CHARACTERISTICS
TPS61050
TPS61052
SLUS525 MARCH 2007
Unless otherwise noted the specification applies for V
IN
= 3.6 V over an operating junction temp. of –40 °CT
J
125 °C.Typical values are for T
A
= 25 °C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
Input voltage range 2.5 6.0 VV
IN
Minimum input voltage for start-up MODE_CTRL[1:0] = 11, OV[1:0] = 01, R
L
= 10 2.5 V
I
Q
Operating quiescent current into AVIN MODE_CTRL[1:0] = 01, I
LED
= 0 mA 8.5 mA
MODE_CTRL[1:0] = 00, OV[1:0] 11
0.3 3.0 µA 40 °CT
J
85 °CI
SD
Shutdown current into AVIN
MODE_CTRL[1:0] = 00, OV[1:0] = 11
140 µA 40 °CT
J
85 °C
V
UVLO
Undervoltage lockout threshold V
IN
falling 2.3 2.4 V
OUTPUT
Current regulator mode V
IN
5.5V
OUT
Output voltage range VVoltage regulator mode 4.5 5.25
OVP Output overvoltage protection V
OUT
rising 5.7 6.0 6.25 VOVP
Output overvoltage protection hysterisis 0.15 V
D Minimum duty cycle 7.5%
0.25 V V
LED
2.0 V,
–15% 15%50 mA I
LED
250 mA, T
J
= 50 °CLED current accuracy
(1)
0.25 V V
LED
2.0 V,
–12% 12%200 mA I
LED
1200 mA, T
J
= 50 °C
LED current temperature coefficient 0.08 %/ °C
DC output voltage accuracy 2.5 V V
IN
0.9 V
OUT
, PWM operation –3% 3%
V
LED
LED sense voltage I
LED
= 1200 mA 250 mV
LED input leakage current V
LED
= V
OUT
= 5 V, –40 °CT
J
85 °C 0.1 1 µA
POWER SWITCH
Switch MOSFET on-resistance 80r
DS(on)
V
OUT
= V
GS
= 3.6 V m Rectifier MOSFET on-resistance 80
Switch MOSFET leakage 0.1 1I
lkg(SW)
V
DS
= 6.0 V, –40 °CT
J
85 °CµARectifier MOSFET leakage 0.1 1
2.5 V V
IN
6.0 V, ILIM bits = 00 850 1000 1150
1275 1500 1725I
lim
Switch current limit 2.5 V V
IN
6.0 V, ILIM bits = 01, 10
(1)
mA
1700 2000 23002.5 V V
IN
6.0 V, ILIM bits = 11
(1)
140 160 °CThermal shutdown
(1)
20 °CThermal shutdown hysteresis
(1)
OSCILLATOR
f
SW
Oscillator frequency 1.8 2.0 2.2 MHz
ADC
Resolution 3 Bits
V
LED
= 0.25 V, assured monotonic by design ±0.25 ±1 LSBTotal error
(1)
SDA, SCL, GPIO, ENVM, FLASH_SYNC
V
(IH)
High-level input voltage 1.2 V
V
(IL)
Low-level input voltage 0.4 V
Low-level output voltage (SDA) I
OL
= 8 mA 0.3V
(OL)
VLow-level output voltage (GPIO) DIR = 1, I
OL
= 8 mA 0.3
I
(LKG)
Logic input leakage current Input connected to V
IN
or GND, –40 °CT
J
85 °C 0.01 0.1 µA
GPIO pull-down resistance DIR = 0, GPIO 0.4 V (TPS61050) 400 k
ENVM pull-down resitance ENVM 0.4 V (TPS61052) 400 k
FLASH_SYNC pull-down resistance FLASH_SYNC 0.4 V 400 k
(1) Assured by design. Not tested in production.
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I
2
C INTERFACE TIMING CHARACTERISTICS
(1)
TPS61050
TPS61052
SLUS525 MARCH 2007
ELECTRICAL CHARACTERISTICS (continued)Unless otherwise noted the specification applies for V
IN
= 3.6 V over an operating junction temp. of –40 °CT
J
125 °C.Typical values are for T
A
= 25 °C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TIMING
From shutdown into torch mode I
LED
= 75 mA 1.2 msStart-up time
From shutdown into voltage mode via ENVM
650 µsI
OUT
= 0 mA
LED current settling time
(2)
triggered by MODE_CTRL[1:0] = 10,
400 µsrising edge on FLASH_SYNC I
LED
= from 0 mA to 900 mA
LED current settling time
(2)
triggered by MODE_CTRL[1:0] = 10,
20 µsTX mask I
LED
= 900 mA to 150 mA
(2) Settling time to ±15% of the target value
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Standard mode 100f
SCL
SCL clock frequency kHzFast mode 400Standard mode 4.7t
BUF
Bus free time between a STOP and START condition µsFast mode 1.3Standard mode 4.0 µst
HD
; t
STA
Hold time (repeated) START condition
Fast mode 600 nsStandard mode 4.7t
LOW
LOW period of the SCL clock µsFast mode 1.3Standard mode 4.0 µst
HIGH
HIGH period of the SCL clock
Fast mode 600 nsStandard mode 4.7 µst
SU
; t
STA
Setup time for a repeated START condition
Fast mode 600 nsStandard mode 250t
SU
; t
DAT
Data setup time nsFast mode 100Standard mode 0 3.45t
HD
; t
DAT
Data hold time µsFast mode 0 0.9Standard mode 20 + 0.1C
B
1000t
RCL
Rise time of SCL signal nsFast mode 20 + 0.1C
B
300Standard mode 20 + 0.1C
B
1000Rise time of SCL signal after a repeated START conditiont
RCL1
nsand after an acknowledge bit
Fast mode 20 + 0.1C
B
1000Standard mode 20 + 0.1C
B
300t
FCL
Fall time of SCL signal nsFast mode 20 + 0.1C
B
300Standard mode 20 + 0.1C
B
1000t
RDA
Rise time of SDA signal nsFast mode 20 + 0.1C
B
300Standard mode 20 + 0.1C
B
300t
FDA
Fall time of SDA signal nsFast mode 20 + 0.1C
B
300Standard mode 4.0 µst
SU
; t
STO
Setup time for STOP condition
Fast mode 600 nsC
B
Capacitive load for SDA and SCL 400 pF
(1) Assured by design. Not tested in production.
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DEVICE INFORMATION
I
2
C TIMING DIAGRAMS
tftLOW tr
thd;STA
thd;DAT
tsu;DAT tf
HIGH
tsu;STA
S Sr P S
thd;STA tr
tBUF
tsu;STO
SDA
SCL
PIN ASSIGMENTS
TPS61050
TPS61052
SLUS525 MARCH 2007
Figure 3. Serial Interface Timing for F/S-Mode
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNO. NO.NAME
(QFN) (CSP)
AVIN 5 D3 I This is the input voltage pin of the device. Connect directly to the input bypass capacitor.VOUT 9 A2 O Boost converter output.LED 6 D2 I LED return input. This feedback pin regulates the LED current through the internal senseresistor by regulating the voltage across it. The regulation operates with typically 250 mVdropout voltage. Connect to the cathode of the LED.FLASH_SYNC 10 A1 I Flash strobe pulse synchronization input.FLASH_SYNC = LOW (GND): The device is operating and regulating the LED current tothe torch current level (TC).FLASH_SYNC = HIGH (VIN): The device is operating and regulating the LED current tothe flash current level (FC).SCL 2 B3 I Serial interface clock line. This pin must not be left floating and must be terminated.SDA 1 A3 I/O Serial interface address/data line. This pin must not be left floating and must be terminated.GPIO 3 C3 I/O General purpose input/output (refer to REGISTER2). This pin can either be configured as alogic input or as an open-drain output (TPS61050).ENVM 3 C3 I Enable pin for voltage mode boost converter (TPS61052).SW 8 B1, B2 I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side ofthe inductor. SW is high impedance during shutdown.PGND 7 C1, C2 Power ground. Connect to AGND underneath IC.AGND 4 D1 Analog ground.PowerPAD™ N/A Internally connected to PGND.
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FUNCTIONAL BLOCK DIAGRAM
Undervoltage
Lockout
BiasSupply
AVIN
VOUT
SW
LED
REF
Bandgap
SCL
SDA
AGND PGND
FLASH_SYNC
CURRENT
CONTROL
LEDCurrentRegulator
P
P
P
SENSEFB
S
Ramp
Compensation
Control
Logic
COMPARATOR
ERROR
AMPLIFIER
OVP
COMPARATOR
GPIOorENVM
VOLTAGE
REGULATION
CURRENT
REGULATION
Control
Logic DAC
3-bit
ADC
+
-
V =1.22V
REF
VREF
2MHz
Oscillator
D=k*(VOUT-LED)
ON/OFF
Maxt Timer
ON
2
ICI/F
TPS61050
TPS61052
SLUS525 MARCH 2007
6
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TIMER BLOCK DIAGRAM (TPS61050)
16-bitPrescaler Safety Timer
FLASH_SYNC
LEDCURRENT CONTROL
GPIO
tSTIM
Safety Timer Trigger
(STT)
1
FlashBlanking
(Tx-MASK)
0
1
0
0
1
0:Input
1:Output
PortDirection
(DIR)
(GPIOBit)
2MHzCLOCK
EdgeDetect
Start
MODE0
MODE1
0: TORCHCURRENT LEVEL
1:FLASHCURRENT LEVEL
122Hz
400kW
400kW
LEDCURRENT CONTROL -OFF ILED
0 0 TorchCurrent
0 1 TorchCurrent
1 0 FlashCurrent
1 1 Torch Current
CURRENT REGULATORMODE- TORCH/FLASH ACTIVE
MODE0=LOW
MODE1=HIGH
Start
Flash/Timer
(SFT)
30.5Hz
Time-Out(TO)
Dimming
(DIM)
Timer
Value
(STIM)
Timer
Value
(DCTIM
Duty-CycleGenerator(0.8%...8.6%)
LEDON/OFFCONTROL
0:LEDOFF
1: TORCHCURRENT LEVEL
(GPIOBit)
TX
-OFFTX
TPS61050
TPS61052
SLUS525 MARCH 2007
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TIMER BLOCK DIAGRAM (TPS61052)
PARAMETER MEASUREMENT INFORMATION
VOUT
AVIN
SW
CIN
VIN
SW
LED
COUT
PGND
PGND P
P
P
AGND
GPIO
SDA
SCL
I2CI/F
FLASH_SYNC
L
2.2µH
10µF
P
TPS6105X
ListOfComponents:
-L =WuerthElektronikWE-PDSSeries
-C =C =TDKC1605X5R0J106MT
IN OUT
TPS61050
TPS61052
SLUS525 MARCH 2007
8
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TYPICAL CHARACTERISTICS
0
10
20
30
40
50
60
70
80
90
100
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 5.5
V -InputVoltage-V
I
LEDPowerEfficiency(PLED/PIN)-%
I =50mA
LED
I =250mA
LED
I =100mA
LED
I =2000mA
LIM
I =150mA
LED
0
10
20
30
40
50
60
70
80
90
100
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 5.5
V -InputVoltage-V
I
LEDPowerEfficiency(PLED/PIN)-%
I =300mA
LED
I =500mA
LED
I =700mA
LED
I =900mA
LED
I =1200mA
LED
ILIM=2000mA
TPS61050
TPS61052
SLUS525 MARCH 2007
Table 1. Table of Graphs
FIGURE
LED Power Efficiency vs. Input Voltage Figure 4 ,Figure 5DC Input Current vs. Input Voltage Figure 6LED Current vs. LED Pin Headroom Voltage Figure 7LED Current vs. LED Current Digital Code Figure 8 ,Figure 9 ,Figure 10Voltage Mode Efficiency vs. Output Current Figure 11DC Output Voltage vs. Load Current Figure 12DC Output Voltage vs. Input Voltage Figure 13Quiescent Current vs. Input Voltage Figure 14Shutdown Current vs. Input Voltage Figure 15Junction Temperature vs. GPIO Voltage Figure 16PWM Operation Figure 17Down-Mode Operation Figure 18Voltage Mode Load Transient Response Figure 19Down-Mode Line Transient Response Figure 20Duty Cycle Jitter Figure 21Input Ripple Voltage Figure 22Low-Light Dimming Mode Operation Figure 23Torch/Flash Sequence Figure 24TX-Masking Operation Figure 25 ,Figure 26 ,Figure 27Junction Temperature Monitoring Figure 28Start-up Into Torch Operation Figure 29 ,Figure 30
LED POWER EFFICIENCY LED POWER EFFICIENCYvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 4. Figure 5.
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0
200
400
600
800
1000
1200
1400
250 350 450 550 650 750 850 950 1050
LEDPinHeadroomVoltage-mV
LEDCurrent-mA
I =75mA
LED
I =1200mA
LED
I =2000mA
LIM
I =150mA
LED
I =900mA
LED
I =700mA
LED
I =500mA
LED
0
250
500
750
1000
1250
1500
1750
2000
2250
2500
DCInputCurrent-mA
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 5.5
V -InputVoltage-V
I
I =300mA
LED
I =1200mA
LED
I =2000mA
LIM
I =900mA
LED
I =500mA
LED
I =700mA
LED
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
040 80 120 160 200 240 280 300
LEDCurrentDigitalCode-mA
LEDCurrent-mA
V =3.6V
IN
V =2.5V
IN
I =2000mA
LIM
V =4.5V
IN
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
0 200 400 600 800 1000 1200 1300
LEDCurrentDigitalCode-mA
LEDCurrent-mA
V =4.5V
IN
V =3.6V
IN
V =2.5V
IN
I =2000mA
LIM
TPS61050
TPS61052
SLUS525 MARCH 2007
DC INPUT CURRENT LED CURRENTvs vsINPUT VOLTAGE LED PIN HEADROOM VOLTAGE
Figure 6. Figure 7.
LED CURRENT LED CURRENTvs vsLED CURRENT DIGITAL CODE LED CURRENT DIGITAL CODE
Figure 8. Figure 9.
10
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0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
0 200 400 600 800 1000 1200 1300
LEDCurrentDigitalCode-mA
LEDCurrent-mA
T =85°C
A
T =-40°C
A
T =25°C
A
I =2000mA
LIM
0
10
20
30
40
50
60
70
80
90
100
0 1 10 100 1000 10000
I -OutputCurrent-mA
O
Efficiency-%
V =5V,
I =2000mA
OUT
LIM
V =4.2V
IN
V =3V
IN
V =2.5V
IN
V =3.6V
IN
4.85
4.90
4.95
5
5.05
5.10
5.15
0.1 1 10 100 1000 10000
I -OutputCurrent-mA
O
DCOutputVoltage-V
V =5V,
I =2000mA
OUT
LIM
V =3.6V
IN
V =2.5V
IN
V =4.2V
IN
V =3V
IN
4.80
4.90
5
5.10
5.20
5.30
5.40
5.50
5.60
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 5.5
V -InputVoltage-V
I
DCOutputVoltage-V
I =0mA
OUT
I =100mA
OUT
I =1000mA
OUT
V =5V,
I =2000mA
OUT
LIM
TPS61050
TPS61052
SLUS525 MARCH 2007
LED CURRENT VOLTAGE MODE EFFICIENCYvs vsLED CURRENT DIGITAL CODE LOAD CURRENT
Figure 10. Figure 11.
DC OUTPUT VOLTAGE DC OUTPUT VOLTAGEvs vsOUTPUT CURRENT INPUT VOLTAGE
Figure 12. Figure 13.
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 5.5
V -InputVoltage-V
I
QuiescentCurrent-mA
VoltageModeRegulation,
V =5V
O
0
0.20
0.40
0.60
0.80
1
1.20
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 5.5
V -InputVoltage-V
I
ShutdownCurrent- Am
1.40
T =85°C
A
T =25°C
A
T =-40°C
A
V =3.6V,V =5V,
I =500mA,I =2000mA
I O
O LIM
t-Time=125ns/div
I
(200mA/div-0.6 A Offset)
L
V
(50mV/div-5VOffset)
OUT
SW
(2V/div)
-50
-25
0
25
50
75
100
125
150
175
200
-0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20
GPIOVoltage-V
T-JunctionTemperature-°C
J
GPIO
InputBuffer
100 Am
VGPIO
GPIO=Input,
I =-100 A
GPIO m
TPS61050
TPS61052
SLUS525 MARCH 2007
QUIESCENT CURRENT SHUTDOWN CURRENTvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 14. Figure 15.
JUNCTION TEMPERATURE
vsGPIO VOLTAGE PWM OPERATION
Figure 16. Figure 17.
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V =4.2V,
I =75mA
I
LED
(500mV/div-3.5VOffset)
VOUT
LEDHeadroomVoltage
t-Time=250ns/div
(1V/div)
(50mA/div)
ILED
I
(50mA/div)
L
V =3.6V,V =5V,
I =2000mA
I O
LIM
t-Time=50 s/divm
V
(500mV/div-5VOffset)
OUT
I
(500mA/div)
L
I
(500mA/div)
OUT
I
(200mA/div-0.3 A Offset)
L
V =3.6Vto3.9V,
I =500mA,I =2000mA
I
LED LIM
V
(200mV/div-4VOffset)
OUT
BatteryVoltage
(200mV/div-4VOffset) I
(100mA/div-0.3 A Offset)
LED
t-Time=20 s/divm
TRIGGEREDONRISINGEDGE
V =3.6V,
V =5V,
I =500mA,
I =2000mA
I
O
O
LIM
t-Time=50ns/div
SW
(1V/div)
TPS61050
TPS61052
SLUS525 MARCH 2007
DOWN-MODE OPERATION VOLTAGE MODE LOAD TRANSIENT RESPONSE
Figure 18. Figure 19.
DOWN-MODE LINE TRANSIENT RESPONSE DUTY CYCLE JITTER
Figure 20. Figure 21.
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I
(200mA/div-0.7 A Offset)
LED
Li-PolymerBatteryat3.7V,
I =1200mA,I =2000mA
LED LIM
BatteryVoltage
(20mV/div-3.7VOffset) V
(100mV/div-5VOffset)
OUT
I
(500mA/div-0.5 A Offset)
L
t-Time=500ns/div
Frequency=121Hz
DutyCycle=6.25%
V =3.6V,I =75mA,
DCTIM[2:0]=110
IN TORCH
V
(200mV/div-3.5VOffset)
OUT
I
(20mA/div)
LED
t-Time=2ms/div
SAFETY TIMERLIMITATION
V =3.2V,I =2000mA,I =75mA (Torch)to700mA (Flash),
STIM[5:0]=10001(558ms)
I LIM LED
V
(500mV/div-3.35VOffset)
OUT
LEDPinHeadroomVoltage
(200mV/div)
I
(500mA/div)
LED
FLASH_SYNC
(2V/div)
t-Time=100ms/div
V =3.6V,I =2000mA,DIRbit=0,Tx-MASKbit=1,
TC[2:0]=111,FC[2:0]=111
I LIM
I
(500mA/div)
L
I
(500mA/div)
LED
GPIO (Tx-MASK)
(2 V/div)
FLASH_SYNC
(2V/div)
t-Time=200 s/divm
TPS61050
TPS61052
SLUS525 MARCH 2007
INPUT RIPPLE VOLTAGE LOW-LIGHT DIMMING MODE OPERATION
Figure 22. Figure 23.
TORCH/FLASH SEQUENCE TX-MASKING OPERATION
Figure 24. Figure 25.
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GPIO(Tx-MASK)
(2V/div)
I
(500mA/div)
LED
I
(500mA/div)
L
V =3.6V,I =2000mA,DIRbit=0,Tx-MASKbit=1,
Torch=150mA /Flash=900mA
I LIM
t-Time=50 s/divm
I
(500mA/div)
LED
I
(500mA/div)
L
V =3.6V,I =2000mA,DIRbit=0,Tx-MASKbit=1,
Torch=150mA /Flash=900mA
I LIM
GPIO(Tx-MASK)
(2V/div)
t-Time=10 s/divm
I
(1 A/div)
LED
FLASH_SYNC
(2V/div)
V
(500mV/div-4.5VOffset)
OUT
T =65°C
J
T =25°C
J
V =3.3Vat900mA,
I =0mA (Torch)to900mA (Flash)
F(LED)
LED
V =4.2V,I =2000mA,
I =-100 A,T =25°C
I LIM
GPIO mA
GPIOVoltage
(20mV/div--0.41VOffset)
t-Time=100ms/div
SCL
(2V/div)
I
(50mA/div)
L
I
(50mA/div)
LED
ACK
V =3.6V,I =2000mA,
Torch=75mA
I LIM
t-Time=200 s/divm
TPS61050
TPS61052
SLUS525 MARCH 2007
TX-MASKING OPERATION TX-MASKING OPERATION
Figure 26. Figure 27.
JUNCTION TEMPERATURE MONITORING START-UP IN TORCH OPERATION
Figure 28. Figure 29.
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V =3.60V,I =2000mA,TC[2:0]=000
I LIM
V
(2V/div)
OUT
I
(50mA/div)
LED
I
(50mA/div
L
)
t-Time=100 s/divm
SCL
(2V/div)
ACK
TPS61050
TPS61052
SLUS525 MARCH 2007
START-UP IN TORCH OPERATION
Figure 30.
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DETAILED DESCRIPTION
OPERATION
EFFICIENCY
SOFT-START
TPS61050
TPS61052
SLUS525 MARCH 2007
The TPS6105x family employs a 2-MHz constant-frequency, current-mode PWM converter to generate theoutput voltage required to drive high-power LEDs. The device integrates a power stage based on an NMOSswitch and a synchronous NMOS rectifier. The device also implements a linear low-side current regulator tocontrol the LED current when the battery voltage is higher than the diode forward voltage.
In boost mode, the duty cycle of the converter is set by the error amplifier and the saw-tooth ramp applied to thecomparator. Because the control architecture is based on a current-mode control, a compensation ramp isadded to allow stable operation at duty cycles larger than 50%. The converter is a fully-integratedsynchronous-boost converter, always operating in continuous-conduction mode. This allows low-noise operation,and avoids ringing on the switch pin, which would be seen on a converter when enteringdiscontinuous-conduction mode.
The TPS6105x device not only operates as a regulated current source but also as a standard voltage-boostregulator. In the TPS61052 device, the voltage-mode operation can be activated either by a software commandor by means of a hardware signal (ENVM). This additional operating mode can be useful to properly synchronizethe converter when supplying other high-power devices in the system, such as a hands-free audio poweramplifier, or any other component requiring a supply voltage higher than the battery voltage.
The TPS6105x integrates an I
2
C-compatible interface, allowing transfers up to 400 kbps. This communicationinterface can be used toset the operating mode (shutdown, constant output current mode vs. constant output voltage mode),control the brightness of the external LED (torch and flash modes),adjust the output voltage (4.5/5/5.25 V) or to program the safety timer.For more details, refer to the I
2
CRegister Description section.
The torch and flash functions can be controlled by the I
2
C interface. To simplify flash synchronization with thecamera module, the device offers a FLASH_SYNC strobe input pin to switch (with zero latency) the LED currentfrom flash to torch light. The maximum duration of the flash pulse can be limited by means of an internaluser-programmable safety timer (STIM).
The sense voltage has a direct effect on the converter’s efficiency. Because the voltage across the low-sidecurrent regulator does not contribute to the output power (LED brightness), the lower the sense voltage, thehigher the efficiency will be.
When running in boost mode (V
F(LED)
> V
IN
), the voltage present at the LED pin of the low-side current regulatoris typically 250 mV, which contributes to high power-conversion efficiency.
When running in the linear down-ocnverter mode (V
F(LED)
< V
IN
), the low-side current regulator drops the voltagedifference between the input voltage and the LED forward voltage. Depending on the input voltage and the LEDforward voltage characteristic, the converter displays efficiency of approximately 80% to 90%.
Since the output capacitor always remains biased to the input voltage, the TPS6105x can immediately startswitching once it has been enabled via the I
2
C-compatible interface (refer to MODE_CTRL[1:0] bits). The devicestarts-up by smoothly ramping up it’s internal reference voltage, thus limiting the inrush current.
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SHUTDOWN
LED FAILURE MODES
UNDERVOLTAGE LOCKOUT
THERMAL SHUTDOWN
TPS61050
TPS61052
SLUS525 MARCH 2007
DETAILED DESCRIPTION (continued)
The MODE_CTRL[1:0] bits are low, the device is forced into shutdown. Depending on the setting of OV[1:0] thedevice can enter different shutdown modes. In shutdown mode, the regulator stops switching and the LED pin ishigh impedance thus eliminating any DC conduction path.
If OV[1:0] 11, the internal switch and rectifier MOSFET are turned off. VOUT is one body-diode drop below theinput voltage and the device consumes only a shutdown current of 0.3 µA (typ). The output capacitor remainsbiased to the input voltage.
If OV[1:0] = 11, the internal switch MOSFET is turned off and the rectifier MOSFET is turned on. In thisshutdown mode there is almost no dropout voltage between the converter’s input and output. The shutdowncurrent is 150 µA (typ).
If the LED fails as a short circuit, the low-side current regulator limits the maximum output current and the LEDFAILURE (LF) flag will be set.
If the LED fails as an open circuit, the control loop initially attempts to regulate off of its low-side currentregulator feedback signal. This drives VOUT higher. Because the open-circuited LED will never accept itsprogrammed current, VOUT must be voltage-limited by means of a secondary control loop. In this failure mode,the TPS6105x limits VOUT to 6.0 V (typ.) and sets the LED FAILURE (LF) flag.
The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents theconverter from turning on the switch or rectifier MOSFET under undefined conditions.
As soon as the junction temperature, T
J
, exceeds 160 °C typical, the device goes into thermal shutdown. In thismode, the boost power stage and the low-side current regulator are turned off, the MODE_CTRL[1:0] bits arereset, the OVERTEMP bit is set and can only be reset by a readout.
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OPERATING MODES: TORCH AND FLASH
IFLASH
FLASH_SYNC
Free Free
I2CBus
LEDCurrent
DC/DC Turn-OnCommand
TC[2:0]=000
MODE_CTRL[1:0]=10
DC/DC Turn-OffCommand
MODE_CTRL[1:0]=00
FLASH_SYNCor(SFT)
LEDCONTROL
TIMER STIM
IFLASH
TORCH
TIME-OUT
RESET (SF)
FLASH_SYNCor(SFT)
LEDCONTROL
TIMER
STIM
FLASH
TORCH
TIME-OUT
RESET (SF)
TPS61050
TPS61052
SLUS525 MARCH 2007
DETAILED DESCRIPTION (continued)
The device operation is more easily understood by referring to the timer block diagram. Depending on thesettings of MODE_CTRL[1:0] bits the device can enter 4 different operating modes:MODE_CTRL[1:0] = 00: The device is in shutdown mode.MODE_CTRL[1:0] = 01: The device is regulating the LED current to the torch current level (TC bits)regardless of the FLASH_SYNC input and START_FLASH/TIMER (SFT) bit. The safety timer is disabled inthis operating mode.MODE_CTRL[1:0] = 11: The device is regulating a constant output voltage according to OV[1:0] bits settings.The low-side LED current regulator is disabled and the LED is disconnected from the output. In this operatingmode, the safety timer is disabled and the general purpose timer (DCTIM) can be used to generate asoftware timeout (TO) flag. DCTIM start is triggered on the rising edge of START_FLASH/TIMER (SFT).MODE_CTRL[1:0] = 10: The flash pulse can be either trigger by a hardware signal (FLASH_SYNC) or by asoftware bit (SFT).
Flash strobe is level sensitive (STT = 0): LED strobe pulse follows FLASH_SYNCFLASH_SYNC and (SFT) = 0: LED operation is set to the torch current level and the safety timer is disabled.FLASH_SYNC or (SFT) = 1: The LED is driven at the flash current level and the safety timer is running.
The maximum duration of the flash pulse is defined in the STIM register.
Figure 31. Torch Mode Operation Figure 32. Synchronized Flash Strobe
Figure 33. Level Sensitive Safety Timer (Timeout) Figure 34. Level Sensitive Safety Timer (NormalOperation + Timeout)
The safety timer is started by:a rising edge of FLASH_SYNC signal.a rising edge of START_FLASH/TIMER (SFT) bit.
The safety timer is stopped by:a low level of FLASH_SYNC signal or START_FLASH/TIMER (SFT) bit.a timeout signal (TO).
The START-FLASH/TIMER (SFT) bit is reset by the timeout (TO) signal.
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FLASH_SYNCor(SFT)
LEDCONTROL
TIMER STIM
IFLASH
ITORCH
RESET (SF)
FLASH_SYNCor(SFT)
LEDCONTROL
TIMER STIM
IFLASH
ITORCH
RESET (SFT)
FLASH_SYNCor(SFT)
LEDCONTROL
TIMER STIM
IFLASH
ITORCH
RESET (SFT)
MODE OF OPERATION: FLASH BLANKING (TPS61050)
IFLASH
ITORCH
LEDCurrent
Free Free
LED Turn-On
Command
I2
CBus
FLASH_SYNC
GPIO(Tx-MASK)
Free
LED Turn-Off
Command
TPS61050
TPS61052
SLUS525 MARCH 2007
DETAILED DESCRIPTION (continued)The Flash strobe is edge sensitive (STT = 1): The LED strobe pulse is triggered by a rising edge
When FLASH_SYNC and START_FLASH/TIMER (SFT) are both low, the LED operation is set to the torchcurrent level without timeout.
The duration of the flash pulse is defined in the STIM register. The flash strobe is started by:a rising edge of FLASH_SYNC signal.a rising edge of START_FLASH/TIMER (SFT) bit.
Once running, the timer ignores any triggering signal, and only stops after a timeout (TO). TheSTART-FLASH/TIMER (SFT) bit is reset by the timeout (TO) signal.
Figure 35. Edge Sensitive Timer (Single Trigger Event) Figure 36. Edge Sensitive Timer (Single Trigger Event)
Figure 37. Edge Sensitive Timer (Multiple TriggerEvents)
The TPS61050 device also integrates a general purpose I/O pin (GPIO) that can be configured either as astandard logic input/output or as a flash masking input (Tx-MASK). This blanking function turns the LED fromflash to torch light, thereby reducing almost instantaneously the peak current loading from the battery. TheTx-MASK function has no influence on the safety timer duration.
Figure 38. Synchronized Flash With Blanking Periods
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HARDWARE VOLTAGE MODE SELECTION (TPS61052)
LOW LIGHT DIMMING MODE
PWMDimmingSteps (DCTIM)
0.8%, 1.6%, 2.3%, 3.1%, 3.9%, 4.7%, 6.3%, 8.6%
ITORCH
0
ILED(DC) = ITORCH xDCTIM
TorchCurrentSteps (TC)
50mA, 75mA, 100mA, 150mA, 200mA, 250mA
TPS61050
TPS61052
SLUS525 MARCH 2007
DETAILED DESCRIPTION (continued)
The TPS61052 device integrates a logic input (ENVM) that can be used to force the converter to run in voltagemode regulation. This additional operating mode can be useful to supply other high power consumption devicesin the system (e.g. hands-free audio power amplifier...) or any other component requiring a supply voltage higherthan the battery voltage.
Table 2 gives an overview of the different mode of operation of TPS61052.
Table 2. TPS61052 Operating Modes
INTERNAL REGISTER
ENVM OPERATING MODESSETTINGS MODE_CTRL[1:0]
Power stage is in shutdown. The output is either connected directly to the battery00 0 (OV[1:0]=11, rectifier is bypassed) or via the rectifer’s body diode (OV[1:0]=01). In both casethe power stage LC filter is connected in series between the battery and the output.LED is turned-on for DC light operation. The converter is operating in the current regulation01 0
mode (CM). The output voltage is controlled by the forward voltage characteristic of the LED.LED is turned-on for flash operation. The converter is operating in the current regulation10 0
mode (CM). The output voltage is controlled by the forward voltage characteristic of the LED.LED is turned-off and the converter is operating in the voltage regulation mode (VM). The11 0
output voltage is set via the register OV[1:0].LED is turned-off and the converter is operating in the voltage regulation mode (VM). The00 1
output voltage is set via the register OV[1:0].The converter is operating in the voltage regulation mode (VM) and it’s output voltage is set01 1 via the register OV[1:0]. The LED is turned-on for torch operation according to the registerTC[2:0]. The LED current is regulated by the means of the low-side current sink.The converter is operating in the voltage regulation mode (VM) and it’s output voltage is set10 1 via the register OV[1:0]. The LED is turned-on for flash operation according to the registerFC[2:0]. The LED current is regulated by the means of the low-side current sink.LED is turned-off and the converter is operating in the voltage regulation mode (VM). The11 1
output voltage is set via the register OV[1:0].
The TPS6105x device features white LED drive capability at very low light intensity. To generate a reduced LEDaverage current, the device employs a 122 Hz fixed frequency PWM modulation scheme. Operation isunderstood best by referring to the timer block diagram.
The torch current is modulated with a duty cycle defined by the DCTIM[2:0] bits. The low light dimming modecan only be activated in the torch only mode, MODE_CTRL[1:0] = 01.
Figure 39. PWM Dimming Principle
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LEDONwithReducedCurrent
PWMDimmingSteps = 0.8%, 1.6%, 2.3%, 3.1%, 3.9%, 4.7%, 6.3%, 8.6%
ITORCH
FREEFREE FREE
I2CBus
TC[2:0]=I
DIM=1
TORCH
FREEFREE FREE
LEDOFF
ITORCH
TC[2:0]=000
DIM=0
TC[2:0]=I
DIM=1
TORCH TC[2:0]=000
DIM=0
3-BIT ADC
CIN
VBAT
COUT
P
P
L
IREF
Low-SideCurrentRegulator
PP
LED
VOUT
+
-
ADC
S/H
3-Bit ADC
ADC[2:0]
START FLASH 10ms
Delay
LEDFAILURE
VOUT-LED<1.5V
WRITEREGISTER2[5:3]=111
ADCDigitalOutputCoding, ADC[2:0]
000:(VOUT-LED)<3.20V
001:3.20V (VOUT-LED)<3.35V
010:3.35V (VOUT-LED)<3.50V
011:3.50V (VOUT-LED)<3.65V
100:3.65V (VOUT-LED)<3.80V
101:3.80V (VOUT-LED)<3.95V
110:3.95V (VOUT-LED)<4.10V
111:(VOUT-LED) 4.10V
TPS61050
TPS61052
SLUS525 MARCH 2007
White LED blinking can be achieved by turning on/off periodically the LED dimmer via the (DIM) bit, seeFigure 40 .
Figure 40. White LED Blinking Control
The TPS6105x device integrates a 3 bit A/D converter to measure the differential voltage across the output andthe low-side current regulator. In order to get a proper settling of the LED forward voltage, the data acquisition isdone approximately 10 ms after the start of the flash sequence.
When running in the linear down-mode (V
F(LED)
< V
IN
), the low-side current regulator drops the voltage differencebetween the input voltage and the LED forward voltage. This may result in thermal limitations (especially forCSP-12 packaging) when running high LED current under high battery conditions (V
IN
4.5 V) with low forwardvoltage LEDs and/or high ambient temperature.
The LED forward voltage measurement can be started either by a START FLASH event (FLASH_SYNC or SFTbit) or by setting ADC[2:0] bits (whilst MODE_CTRL[1:0]=01 or 10).
Figure 41. LED VF Measurement Principle
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SERIAL INTERFACE DESCRIPTION
F/S-MODE PROTOCOL
STARTCondition
DATA
CLK
STOP Condition
SP
DataLine
Stable;
DataValid
DATA
CLK
Change
ofData
Allowed
TPS61050
TPS61052
SLUS525 MARCH 2007
I
2
C is a 2-wire serial interface developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1,January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When thebus is idle, both SDA and SCL lines are pulled high. All the I
2
C compatible devices connect to the I
2
C busthrough open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signalprocessor, controls the bus. The master is responsible for generating the SCL signal and device addresses. Themaster also generates specific conditions that indicate the START and STOP of data transfer. A slave devicereceives and/or transmits data on the bus under control of the master device.
The TPS6105x device works as a slave and supports the following data transfer modes, as defined in theI
2
C-Bus Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to thepower supply solution, enabling most functions to be programmed to new values depending on theinstantaneous application requirements. Register contents remain intact as long as the supply voltage remainsabove approximately 2 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to asF/S-mode in this document. The TPS6105x device supports 7-bit addressing; 10-bit addressing and general calladdress are not supported. The device 7-bit address is defined as 011 0011.
The master initiates data transfer by generating a start condition. The start condition is when a high-to-lowtransition occurs on the SDA line while SCL is high, as shown in Figure 42 All I
2
C-compatible devices shouldrecognize a start condition.
Figure 42. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/Won the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requiresthe SDA line to be stable during the entire high period of the clock pulse (see Figure 43 ). All devices recognizethe address sent by the master and compare it to their internal fixed addresses. Only the slave device with amatching address generates an acknowledge (see Figure 44 ) by pulling the SDA line low during the entire highperiod of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link witha slave has been established.
Figure 43. Bit Transfer on the Serial Interface
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TPS61050
TPS61052
SLUS525 MARCH 2007
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from theslave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So anacknowledge signal can either be generated by the master or by the slave, depending on which one is thereceiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long asnecessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low tohigh while the SCL line is high (see Figure 42 ). This releases the bus and stops the communication link with theaddressed slave. All I
2
C compatible devices must recognize the stop condition. Upon the receipt of a stopcondition, all devices know that the bus is released, and they wait for a start condition followed by a matchingaddress.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
Figure 44. Acknowledge on the I
2
C Bus
Figure 45. Bus Protocol
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TPS6105X I2C UPDATE SEQUENCE
Slave Address R/W ACK Register Address ACK Data ACK PS
171 1 1 1 1
8 8
ACK = Acknowledge
S = START condition
P = STOP condition
FromMasterto TPS6105x
From TPS6105xtoMaster
“0” Write
TPS61050
TPS61052
SLUS525 MARCH 2007
The TPS6105x requires a start condition, a valid I
2
C address, a register address byte, and a data byte for asingle update. After the receipt of each byte, TPS6105x device acknowledges by pulling the SDA line low duringthe high period of a single clock pulse. A valid I
2
C address selects the TPS6105x. TPS6105x performs anupdate on the rising edge of the SCL clock that follows the ACK bit transmission.
Figure 46. Write Data Transfer Format in F/S-Mode
Figure 47. Read Data Transfer Format in F/S-ModeSLAVE ADDRESS BYTE
MSB LSB
X0110011
The slave address byte is the first byte received following the START condition from the master device.REGISTER ADDRESS BYTE
MSB LSB
0 0 0 0 0 0 D1 D0
Following the successful acknowledgement of the slave address, the bus master will send a byte to theTPS6105x, which will contain the address of the register to be accessed. The TPS6105x contains four 8-bitregisters accessible via a bidirectional I2C-bus interface. All internal registers have read and write access.
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REGISTER DESCRIPTION
REGISTER0 (READ/WRITE) (TPS6105X)
7 6 5 4 3 2 1 0 Memorylocation:00
Resetstate:00010010
000:0mA
(dc/dcswitching,LEDOff,VOUT setaccordingtoOV[1:0]
001:50mA
010:75mA (default)
011:100mA
100:150mA
101:200mA
110:250mA /400mA
TORCHCURRENT,TC[2:0]
(1)
111:250mA /500mA
ThisbitisonlyvalidforMODE_CTRL[1:0]=01
0:LEDcurrentisunchanged(default)
1:LEDcurrentisPWMdimmed(seeDCTIMbits)
ThisbitisonlyvalidforMODE_CTRL[1:0]=11
00:4.5Vconstantoutputvoltage
01:5.0Vconstantoutputvoltage
10:5.25Vconstantoutputvoltage
11:5.0Vconstantoutputvoltage
LEDDIMMING,DIM
OUTPUTVOLTAGE,OV[1:0]
(1)
(2)
(2)
(2)
(3)
(default)
00:Deviceinshutdownmode(default)
01:Deviceoperatesintorchonlymode
10:Deviceoperatesintorchandflashmodes
11:Deviceoperatesasconstantvoltagesource
WritingtoREGISTERS[7:6]automaticallyupdates
REGISTER[7:6].
MODECONTROL,MODE_CTRL[1:0]
MSB LSB
TPS61050
TPS61052
SLUS525 MARCH 2007
(1) 400 mA/500 mA current level can only be activated when DIR = 0, Tx-MASK = 1 and GPIO input is set high. Thisoperating mode only applies to TPS61050.(2) MODE_CTRL[1:0] = 00, VOUT is one body diode below the input voltage, I
Q
= 0.3 µA (typ).(3) MODE_CTRL[1:0] = 00, rectifier MOSFET is turned on shorting VOUT and SW, I
Q
= 150 µA (typ).
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REGISTER1 (READ/WRITE) (TPS6105X)
7 6 5 4 3 2 1 0 Memorylocation:01
Resetstate:00000100
000:150mA
001:200mA
010:300mA
011:400mA
100:500mA
101:700mA
110:900mA
FLASHCURRENT,FC[2:0]
(default)
111:1200mA
Thisbitisresetbythetime-outofthesafetytimer
0:NochangeinLEDcurrent(default)
1:LEDcurrentrampstotheflashcurrentlevel
ThisbitisonlyvalidforMODE_CTRL[1:0]=10
0:LEDsafetytimerislevelsensitive(default)
1:LEDsafetytimerisrisingedgesensitive
Time-outflagisresetatre-startofthesafetytimer.
0:Notime-outevent(default)
1: Time-outoccurred
00:Deviceinshutdownmode(default)
01:Deviceoperatesintorchonlymode
10:Deviceoperatesintorchandflashmodes
11:Deviceoperatesasconstantvoltagesource
WritingtoREGISTER1[7:6]automaticallyupdates
REGISTER0[7:6]
STARTFLASH/TIMER,SFT
SAFETY TIMERTRIGGER,STT
TIME-OUTFLAG,TO(READONLY)
MODECONTROL,MODE_CTRL[1:0]
MSB LSB
TPS61050
TPS61052
SLUS525 MARCH 2007
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REGISTER2 (READ/WRITE) (TPS61050)
7 6 5 4 3 2 1 0 Memorylocation:02
Resetstate:000XX000
0:GPIOconfiguredasinput(default)
1:GPIOconfiguredasopen-drainoutput
GPIODIRECTION,DIR
GPIOPORTBIT,GPIO
FLASHBLANKING,Tx-MASK
ThisbitcontainstheGPIOportvalue
ThisbitisonlyvalidforDIR=0
Inwritemode,thisbitenables/disablestheflash
blankingfunction.
0:Flashblankingisdisabled(default)
1:LEDcurrentisreducedtotorchcurrentlevel
whenGPIO=1
Inreadmode,thisflagindicateswhetherornotthe
flashlightmaskinginputhasbeenactivated.
Tx-MASKflagisresetafterreadoutoftheflag.
0:Noflashblankingeventoccured
1:Flashblankingtriggered
Referto3-Bit ADCsectionformoredetails.
ILIM[1:0]canonlybewrittenoncewhilstthedevice
isinshutdown.
00:1000mA (typ)(default)
01:1500mA (typ)
10:1500mA (typ)
11:2000mA (typ)
LEDfailureflagisresetafterreadoutoftheflag.
0:ProperLEDoperation
1:LEDfailed(openorshorted)
ADCOUTPUT , ADC[2:0](READONLY)
CURRENTLIMIT ,ILIM[1:0](WRITEONLY)
,LF(READONLY)
(1)
(2) (3)
(3)
LEDFAILURE
OVERTEMP (READONLY)
Time-outflagisresetafterreadoutoftheflag.
0:Normaloperation(default)
1: Thermalshutdowntripped
MSB LSB
TPS61050
TPS61052
SLUS525 MARCH 2007
(1) Setting bits 3, 4 and 5 (whilst MODE_CTRL[1:0]=01 or 10) starts an LED forward voltage measurement.(2) A write operation on bit 5 and 6 points to the ILIM[1:0] bits.(3) A read operation on bit 5 and 6 points to the LF and ADC[2] bits.
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REGISTER2 (READ/WRITE) (TPS61052)
7 6 5 4 3 2 1 0 Memorylocation:02
Resetstate:011XX000
RESERVED,DONOTCARE
ADCOUTPUT , ADC[2:0](READONLY)
CURRENTLIMIT ,ILIM[1:0](WRITEONLY)
(1)
(2) (3)
Referto3-Bit ADCsectionformoredetails.
ILIM[1:0]canonlybewritenoncewhilstthedevice
isinshutdown.
00:1000mA (typ)
01:1500mA (typ)
10:1500mA (typ)
11:2000mA (typ)(default)
LEDfailureflagisresetafterreadoutoftheflag.
0:ProperLEDoperation
1:LEDfailed(openorshorted)
0:Normaloperation(default)
1: Thermalshutdowntripped
LEDFAILURE ,LF(READONLY)
OVERTEMP (READONLY)
(3)
Time-outflagisresetafterreadoutoftheflag.
MSB LSB
REGISTER3 (READ/WRITE) (TPS6105X)
7 6 5 4 3 2 1 0
MSB LSB
Memorylocation:03
Resetstate:11010001
5-bitunsignedbinarycoding.STIMcanonlybe
Writtenoncebeforethedevicehasenteredthe
flashlightmode.
Timer=STIMx32.8ms,defaultis557.6ms
SAFETY TIMER,STIM[4:0]
GENERAL PURPOSETIMER,DCTIM[2:0]
000:0.8%xITORCH
001:1.6%xITORCH
010:2.3%xITORCH
011:3.1%xITORCH
100:3.9%xITORCH
101:4.7%xITORCH
110:6.3%xITORCH(default)
111:8.6%xITORCH
IfMODE_CTRL =01andDIM=1,DCTIMsetstheaverageLEDcurrent
3-bitunsignedbinarycoding
Timer=DCTIMx1.02s
IfMODE_CTRL =11,DCTIMsetsthedurationofthetimertill TObitisset
TPS61050
TPS61052
SLUS525 MARCH 2007
(1) Setting bits 3, 4 and 5 (whilst MODE_CTRL[1:0]=01 or 10) starts an LED forward voltage measurement.(2) A write operation on bit 5 and 6 points to the ILIM[1:0] bits.(3) A read operation on bit 5 and 6 points to the LF and ADC[2] bits.
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APPLICATION INFORMATION
INDUCTOR SELECTON
IL[IOUT +VOUT
h VIN
(1)
IL(PEAK) +VIN D
2 f L)IOUT
(1 *D) hwith D +VOUT *VIN
VOUT
(2)
TPS61050
TPS61052
SLUS525 MARCH 2007
A boost converter requires two main passive components for storing energy during the conversion. A boostinductor and a storage capacitor at the output are required. The TPS6105x device integrates a current limitprotection circuitry. The peak current of the NMOS switch is sensed to limit the maximum current flowing throughthe switch and the inductor. The typical peak current limit (1000 mA / 1500 mA / 2000 mA) is user selectable viathe I
2
C interface.
In order to optimize solution size the TPS6105x device has been designed to operate with inductance valuesbetween a minimum of 1.3 µH and maximum of 2.9 µH. In typical high-current white LED applications a 2.2 µHinductance is recommended.
To select the boost inductor, it is recommended to keep the possible peak inductor current below the currentlimit threshold of the power switch in the chosen configuration. The highest peak current through the inductorand the power switch depends on the output load, the input and output voltages. Estimation of the maximumaverage inductor current and the maximum inductor peak current can be done using Equation 1 and Equation 2 :
with:
f = switching frequency (2 MHz)L = inductance value (2.2 µH)η= estimated efficiency (85%)
For example, for an output current of 500 mA at 5 V, the TPS6105x device needs to be set for a 1000 mAcurrent limit operation together with an inductor supporting this peak current.
The losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter fortotal circuit efficiency.
Table 3. List of Inductors
MANUFACTURER SERIES DIMENSIONS ILIM SETTINGS
TDK VLF3010AT 2,6 mm ×2,8 mm ×1,0 mm max. height
1000 mA (typ.)TAIYO YUDEN NR3010 3,0 mm ×3,0 mm ×1,0 mm max. heightTDK VLF3014AT 2,6 mm ×2,8 mm ×1,4 mm max. heightCOILCRAFT LPS3015 3,0 mm ×3,0 mm ×1,5 mm max. height 1500 mA (typ.)MURATA LQH3NP 3,0 mm ×3,0 mm ×1,5 mm max. heightTOKO FDSE0312 3,0 mm ×3,0 mm ×1,2 mm max. height 2000 mA (typ.)
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CAPACITOR SELECTION
Input Capacitor
Output Capacitor
Cmin [IOUT ǒVOUT *VINǓ
f DV VOUT
(3)
CHECKING LOOP STABILITY
TPS61050
TPS61052
SLUS525 MARCH 2007
For good input voltage filtering low ESR ceramic capacitors are recommended. A 10- µF input capacitor isrecommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit.The input capacitor should be placed as close as possible to the input pin of the converter.
The primary parameter necessary to define the output capacitor is the maximum allowed output voltage ripple ofthe converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It ispossible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, byusing Equation 3 :
Parameter f is the switching frequency and V is the maximum allowed ripple.
With a chosen ripple voltage of 10mV, a minimum capacitance of 10 µF is needed. The total ripple is larger dueto the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 4 :V
ESR
= I
OUT
×R
ESR
The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of thecapacitor. Additional ripple is caused by load transients. This means that the output capacitor has to completelysupply the load during the charging phase of the inductor. A reasonable value of the output capacitancedepends on the speed of the load transients and the load current during the load change.
For the high current white LED application, a minimum of 3 µF effective output capacitance is usually requiredwhen operating with 2.2 µH (typ) inductors. For solution size reasons, this is usually one or more X5R/X7Rceramic capacitors. For stable operation of the internally compensated control loop, a maximum of 50 µFeffective output capacitance is tolerable.
Depending on the material, size and margin to the rated voltage of the used output capacitor, degradation on theeffective capacitance can be observed. This loss of capacitance is related to the DC bias voltage applied. It istherefore always recommended to check that the selected capacitors are showing enough effective capacitanceunder real operating conditions.
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:Switching node, SWInductor current, I
LOutput ripple voltage, V
OUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When theswitching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations theregulation loop may be unstable. This is often a result of board layout and/or L-C combination.
The next step in regulation loop evaluation is to perform a load transient test. Output voltage settling time afterthe load transient event is a good estimate of the control loop bandwidth. The amount of overshoot andsubsequent oscillations (ringing) indicates the stability of the control loop. Without any ringing, the loop hasusually more than 45 °of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFETr
DS(on)
) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,output current range, and temperature range.
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LAYOUT CONSIDERATIONS
THERMAL INFORMATION
ThetaJB:35 CW°
No Airflow
4
3.5
3
2.5
2
1.5
1
0.5
00 100 200 300 400 500 600 700 800 900 1000
PulseWidth-ms
SinglePulsePowerDisipation-W
t =85 C
PCB °
TPS61050
TPS61052
SLUS525 MARCH 2007
As for all switching power supplies, the layout is an important step in the design, especially at high peak currentsand high switching frequencies. If the layout is not carefully done, the regulator could show stability problems aswell as EMI problems. Therefore, use wide and short traces for the main current path and for the power groundtracks.
The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use acommon ground node for power ground and a different one for control ground to minimize the effects of groundnoise. Connect these ground nodes at any place close to one of the ground pins of the IC.
To lay out the control ground, it is recommended to use short traces as well, separated from the power groundtraces. This avoids ground shift problems, which can occur due to superimposition of power ground current andcontrol ground current.
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requiresspecial attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, addedheat sinks and convection surfaces, and the presence of other heat-generating components affect thepower-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:Improving the power dissipation capability of the PCB designImproving the thermal coupling of the component to the PCBIntroducing airflow in the system
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications wherehigh maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.The maximum junction temperature (T
J
) of the TPS6105x is 150 °C.
The maximum power dissipation gets especially critical when the device operates in the linear down mode athigh LED current. For single pulse power thermal analysis (e.g., flash strobe), the allowable power dissipationfor the device is given by Figure 48 .
Figure 48. Single Pulse Power Capability (CSP Package)
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TYPICAL APPLICATIONS
VOUT
AVIN
SW
CIN
SW
LED
COUT
10 Fm
PGND
PGND P
P
AGND
L
2.2 Hm
GPIO
SDA
SCL
I2CI/F
FLASH_SYNC
WHITELED
FLASH-LIGHT
TPS61050
CAMERA ENGINE
Li-Ion
VBAT
R
+2.8 V
REDLED
INDICATOR
VOUT
AVIN
SW
CIN
SW
LED
COUT
10 Fm
PGND
PGND P
P
P
AGND
L
2.2 mH
GPIO
SDA
SCL
I2C I/F
FLASH_SYNC
WHITELED
FLASH-LIGHT
TPS61050
CAMERA ENGINE
P
Li-Ion
VBAT
RFPA TX ACTIVE
VOUT
AVIN
SW
CIN
SW
COUT
10 Fm
PGND
PGND P
P
P
AGND
L
2.2 Hm
ENVM
SDA
SCL
I2CI/F
FLASH_SYNC
TPS61052
FlashSynchronization
CameraEngine
AF/ZoomMotorDriveEnable
CameraEngineEngine
VBAT
P
Li-Ior
5VDCPowerRail
for AF/ZoomMotorDrive
LED
TPS61050
TPS61052
SLUS525 MARCH 2007
Figure 49. High Power White LED Solution Featuring Privacy Indicator
Figure 50. High Power White LED Solution Featuring No-Latency Turn-Down via PA TX Signal
Figure 51. High Power White LED Flash Driver and AF/Zoom Motor Drive Supply
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VOUT
AVIN
SW
CIN
SW
LED
COUT
10 Fm
PGND
PGND P
P
P
AGND
L
2.2 Hm
ENVM
SDA
SCL
I2CI/F
FLASH_SYNC
TPS61052
FlashSynchronization
CameraEngine
APA Enable
Base-BandEngine
AudioInput
AudioInput
CLASS-D APA
EN_APA
1G97
VBAT
P
Li-Ion
VOUT
AVIN
SW
CIN
SW
LED
COUT
10 Fm
PGND
PGND P
P
P
AGND
L
2.2 Hm
ENVM
SDA
SCL
I2CI/F
FLASH_SYNC
TPS61052
FlashSynchronization
CameraEngine
APA Enable
Base-BandEngine
AudioInput
AudioInput
CLASS-D APA
EN _APA
VBAT
P
Li-Ion
GAIN_SEL
0:NormalGain
1:-6dB
VOUT
AVIN
SW
CIN
SW
LED
COUT
10 Fm
PGND
PGND P
P
P
AGND
L
2.2 Hm
ENVM
SDA
SCL
I2CI/F
FLASH_SYNC
TPS61052
FlashSynchronization
CameraEngine
VoltageModeEnable
-Base BandEngine
VBAT
P
Li-Ion
Dx Dy Dz
P0
P1
P2
SDA
SCL
EN
TCA6507
GND
VCC
+1.8V
I2CI/F
TPS61050
TPS61052
SLUS525 MARCH 2007
TYPICAL APPLICATIONS (continued)
Figure 52. White LED Flash Driver and Audio Amplifier Power Supply Exclusive Operation
Figure 53. White LED Flash Driver and Audio Amplifier Power Supply Operating Simultaneously
Figure 54. White LED Flash Driver and Auxiliary Lighting Zone Power Supply
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VOUT
AVIN
SW
CIN
SW
LED
COUT
PGND
PGND P
P
P
AGND
GPIO
SDA
SCL
I2CI /F
FLASH _SYNC
L
TPS61050
1 .5 R 1 .5 R
VBAT
P
Li-Ion LED 1 LED 2
2.2 Hm
10 Fm
LED1,LED2VFvariation
shouldbewith100mVfromeachother
TPS61050
TPS61052
SLUS525 MARCH 2007
TYPICAL APPLICATIONS (continued)
Figure 55. 2 ×300 mA Dual LED Camera Flash
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PACKAGE SUMMARY
YMLLLLS
6105x
A1
A1
B1
C1
D1
A2
B2
D
E
C2
D2
A3
B3
C3
D3
PACKAGE DIMENSIONS
TPS61050
TPS61052
SLUS525 MARCH 2007
CHIP SCALE PACKAGE
CHIP SCALE PACKAGE(BOTTOM VIEW)
(TOP VIEW)
Code:
Y 2 digit date codeLLLL - lot trace codeS - assembly site code
The dimensions for the YZG package are shown in Table 4 . See the package drawing at the end of this datasheet.
Table 4. YZG Package Dimensions
Packaged Devices D E
TPS6105xYZG 1.96 ±0.05 mm 1.46 ±0.05 mm
36
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS61050DRCR ACTIVE SON DRC 10 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS61050DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS61050DRCT ACTIVE SON DRC 10 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS61050DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS61050YZGR ACTIVE DSBGA YZG 12 3000 Green (RoHS &
no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPS61050YZGT ACTIVE DSBGA YZG 12 250 Green (RoHS &
no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPS61052DRCR ACTIVE SON DRC 10 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS61052DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS61052DRCT ACTIVE SON DRC 10 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS61052DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS61052YZGR ACTIVE DSBGA YZG 12 3000 Green (RoHS &
no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPS61052YZGT ACTIVE DSBGA YZG 12 250 Green (RoHS &
no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Dec-2009
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Dec-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS61050DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS61050DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS61050YZGR DSBGA YZG 12 3000 180.0 8.4 1.75 2.25 0.81 4.0 8.0 Q1
TPS61050YZGR DSBGA YZG 12 3000 180.0 8.4 1.75 2.25 0.81 4.0 8.0 Q1
TPS61050YZGT DSBGA YZG 12 250 180.0 8.4 1.75 2.25 0.81 4.0 8.0 Q1
TPS61050YZGT DSBGA YZG 12 250 180.0 8.4 1.75 2.25 0.81 4.0 8.0 Q1
TPS61052DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS61052DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS61052YZGT DSBGA YZG 12 250 180.0 8.4 1.75 2.25 0.81 4.0 8.0 Q1
TPS61052YZGT DSBGA YZG 12 250 180.0 8.4 1.75 2.25 0.81 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS61050DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS61050DRCT SON DRC 10 250 210.0 185.0 35.0
TPS61050YZGR DSBGA YZG 12 3000 220.0 220.0 34.0
TPS61050YZGR DSBGA YZG 12 3000 210.0 185.0 35.0
TPS61050YZGT DSBGA YZG 12 250 210.0 185.0 35.0
TPS61050YZGT DSBGA YZG 12 250 220.0 220.0 34.0
TPS61052DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS61052DRCT SON DRC 10 250 210.0 185.0 35.0
TPS61052YZGT DSBGA YZG 12 250 210.0 185.0 35.0
TPS61052YZGT DSBGA YZG 12 250 220.0 220.0 34.0
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Aug-2012
Pack Materials-Page 2
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