VNI8200XP Octal high-side smart power solid state relay with serial/parallel selectable interface on chip Datasheet - production data * Adjustable regulator output * Switching regulator disable * 5 V and 3.3 V compatible I/Os * Channel outputs status LED driving 4 x 2 multiplexed array * Fast demagnetization of inductive loads * ESD protection PowerSSO-36 * Designed to meet IEC 61131-2, IEC61000-4-4, and IEC61000-4-5 Features Type Vdemag(1) RDS(on)(1) VNI8200XP VCC-45 V Iout(1) VCC Applications 0.7 A 45 V * Programmable logic control 0.11 * Industrial PC peripheral input/output 1. Per channel * Numerical control machines * Output current: 0.7 A per channel Table 1. Device summary * Serial/parallel selectable interface Part number * Short-circuit protection * 8-bit and 16-bit SPI Interface for IC command and control diagnostic Package VNI8200XP Packing Tube PowerSSO-36 VNI8200XPTR Tape and reel * Channel overtemperature detection and protection * Thermal independence of separate channels * Drives all type of loads (resistive, capacitive, inductive load) * Loss of GND protection * Power Good diagnostic * Undervoltage shutdown with hysteresis * Overvoltage protection (VCC clamping) * Very low supply current * Common fault open drain output * IC warning temperature detection * Channel output enable * 100 mA high efficiency step-down switching regulator with integrated boot diode March 2013 This is information on a product in full production. DocID15234 Rev 5 1/37 www.st.com 37 Contents VNI8200XP Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.6 Step-down switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 LED driving array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 Functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/37 8.1 SPI/parallel selection mode (SEL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.2 Serial data in (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.3 Serial data out (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.4 Serial data clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.5 Slave select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.6 8/16-bit selection (SEL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.7 Output enable (OUT_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.8 IC warning case temperature detection (TWARN) . . . . . . . . . . . . . . . . . . 18 8.9 Fault indication (FAULT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.10 Power Good (PG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DocID15234 Rev 5 VNI8200XP Contents 8.11 9 Programmable watchdog counter reset (WD) . . . . . . . . . . . . . . . . . . . . . 20 SPI operation (SEL2 = H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1 8-bit SPI mode (SEL1 = L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.2 16-bit SPI mode (SEL1 = H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10 LED driving array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11 Step-down switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 12 Typical circuits and conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13.1 Thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14 Interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 15 Switching parameter test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 30 16 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DocID15234 Rev 5 3/37 Description 1 VNI8200XP Description The VNI8200XP is a monolithic 8-channel driver featuring a very low supply current, with integrated SPI interface and high efficiency 100 mA micropower step-down switching regulator peak current control loop mode. The IC, realized in STMicroelectronicsTM VIPowerTM technology, is intended for driving any kind of load with one side connected to ground. Active channel current limitation combined with thermal shutdown, independent for each channel, and automatic restart, protect the device against overload. Additional embedded functions are: loss of GND protection that automatically turns off the device outputs in case of ground disconnection, undervoltage shutdown with hysteresis, Power Good diagnostic for valid supply voltage range recognition, output enable function for immediate power outputs ON/OFF, and programmable watchdog function for microcontroller safe operation; case overtemperature protection to control the IC case temperature. The device embeds a four-wire SPI serial peripheral with selectable 8 or 16-bit operations; through a select pin the device can also operate with a parallel interface. Both the 8-bit and 16-bit SPI operations are compatible with daisy chain connection. The SPI interface allows command of the output driver by enabling or disabling each channel featuring, in 16-bit format, a parity check control for communication robustness. It also allows the monitoring of the status of the IC signaling Power Good, overtemperature condition for each channel, IC pre-warning temperature detection. Built-in thermal shutdown protects the chip from overtemperature and short-circuit. In overload condition, the channel turns OFF and ON again automatically after the IC temperature decreases below a threshold fixed by a temperature hysteresis so that junction temperature is controlled. If this condition makes case temperature reaching case temperature limit, TCSD, overloaded channels are turned OFF and restart, nonsimultaneously, when case and junction temperature decrease below their own reset threshold. If the case of thermal reset, the channels loaded are not switched on until the junction temperature reset event. Non-overloaded channels continue to operate normally. Case temperature above TCSD is reported through the TWARN open drain pin. An internal circuit provides a not latched common FAULT indicator reporting if one of the following events occurs: channel OVT (overtemperature), parity check fail. The Power Good diagnostic warns the controller that the supply voltage is below a fixed threshold. The watchdog function is used to detect the occurrence of a software fault of the host controller. The watchdog circuitry generates an internal reset on expiry of the internal watchdog timer. The watchdog timer reset can be achieved by applying a negative pulse on the WD pin. The watchdog function can be disabled by the WD_EN dedicated pin. This pin also allows the programming of a wide range of watchdog timings. An internal LED matrix driver circuitry (4 rows, 2 columns) allows the detection of the status of the single outputs. An integrated step-down voltage regulator provides supply voltage to the internal LED matrix driver and logic output buffers and can be used to supply the external optocouplers if the application requires isolation. The regulator is protected against short-circuit or overload conditions by means of pulse-by-pulse current limit with a peak current control loop. 4/37 DocID15234 Rev 5 VNI8200XP Block diagram '&'& &RQYHUWHU 8QGHUYROWDJHDQG 3RZHU*RRG 6(/,1 :'B(1,1 287B(1,1 :',1 6',,1 9FF &ODPS &ODPS3RZHU 63, /RJLF &/.,1 66,1 6'2,1 &XUUHQW/LPLWHU -XQFWLRQ7HP S 'HWHFWLRQ 6(/ 95(* 52: 52: 52: 9&& 3* '&9'' 95() 3+$6( )% %227 Figure 1. Block diagram &DVH7HP S 'HWHFWLRQ /(' 'ULYQJ 3XOO GRZQ UHVLVWRU 287 287 287 287 287 287 287 287 7:$51 *1' )$8/7 &2/ 52: &2/ 2 Block diagram $0Y DocID15234 Rev 5 5/37 Pin connection 3 VNI8200XP Pin connection Figure 2. Pin connection (top view) 6(/ 1& 6(/,1 1& :'B(1,1 287 287B(1,1 287 :',1 287 6',,1 287 &/.,1 287 66,1 7$% 9FF 287 6'2,1 287 95(* 287 &2/ 1& &2/ %227 '& 9'' 3+$6( *1' 95() 52: )% 52: 7:$51 52: )$8/7 52: 3* $0Y Table 2. Pin description 6/37 Pin Name Type Description 1 SEL2 Logic input SPI/parallel selection mode 2 SEL1/IN1 Logic input 8/16-bit SPI selection mode/channel 1 input 3 WD_EN/ IN2 Logic/analog input 4 OUT_EN /IN3 Logic input Output enable/channel 3 input 5 WD/IN4 Logic input Watchdog input. The internal watchdog counter is cleared on the falling edges/channel 4 input. 6 SDI/IN5 Logic input Serial data input/channel 5 input 7 CLK/IN6 Logic input Serial clock/channel 6 input 8 SS/IN7 Logic input Slave select/channel 7 input 9 SDO/IN8 Logic input/output 10 VREG Power supply 11 COL0 Open source output LED source output 12 COL1 Open source output LED source output 13 DCVDD Analog output Watchdog enable_setting/channel 2 input Serial data output/channel 8 input SPI/inputs/LED supply voltage Internally generated DC-DC low voltage supply. (To be connected to external 10 nF capacitor). DocID15234 Rev 5 VNI8200XP Pin connection Table 2. Pin description (continued) Pin Name Type Description 14 VREF Analog output Internally generated DC-DC voltage reference (To be connected to external 10 nF capacitor). 15 ROW0 Open drain output Status channel 1-2 16 ROW1 Open drain output Status channel 3-4 17 ROW2 Open drain output Status channel 5-6 18 ROW3 Open drain output Status channel 7-8 19 PG Open drain output Power Good diagnostic - active low 20 FAULT Open drain output Fault indication - active low 21 TWARN Open drain output IC case warning temperature detection - active low Analog input Step-down feedback input. Connecting the output voltage directly to this pin results in an output voltage of 3.3 V. An external resistor divider is required for higher output voltages. 22 FB 23 GND 24 PHASE Power output Step-down output 25 BOOT Power output Step-down bootstrap voltage. Used to provide a drive voltage, higher than the supply voltage, to power the switch of the step-down regulator. 26 NC 27 OUT8 Power output Channel 8 power output 28 OUT7 Power output Channel 7 power output 29 OUT6 Power output Channel 6 power output 30 OUT5 Power output Channel 5 power output 31 OUT4 Power output Channel 4 power output 32 OUT3 Power output Channel 3 power output 33 OUT2 Power output Channel 2 power output 34 OUT1 Power output Channel 1 power output 35 NC Not connected 36 NC Not connected TAB TAB Ground Not connected Power supply Exposed tab internally connected to VCC DocID15234 Rev 5 7/37 Maximum ratings 4 VNI8200XP Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit 45 V -0.3 V VCC Power supply voltage -VCC Reverse supply voltage VREG Logic supply voltage -0.3 to +6 V Voltage range at pins TWARN, FAULT, PG -0.3 to +6 V VCC+6 V VFAULT VTWARN VPG VBOOT Bootstrap peak voltage VPHASE = Vcc VROW Voltage range at ROW pins -0.3 to +6 V VCOL Voltage range at COL pins -0.3 to +6 V Vdig Voltage level range at logic input pins -0.3 to +6 IOUT IR Output current (continuous) Reverse output current (per channel) Internally limited V (1) -5 A IGND DC ground reverse current -250 mA IREG VREG input current -1/10 mA Current range at pins TWARN, FAULT, PG -1 to +10 mA Input current range -1 to +10 mA Current range at ROW pins (ROW in ON state) +20 mA Current range at ROW pins (ROW in OFF state) -1 to +10 mA Current range at COL pins (COL in ON state) -10 mA Current range at COL pins (COL in OFF state) -1 to +10 mA IFAULT ITWARN, IPG IIN IROW ICOL VESD Electrostatic discharge (R = 1.5 k; C = 100 pF) 2000 V EAS Single pulse avalanche energy per channel not simultaneously 300 mJ PTOT Power dissipation at Tc = 25 C Internally limited(1) W TJ Junction operating temperature Internally limited C -55 to 150 C TSTG Storage temperature 1. Protection functions are intended to avoid IC damage in fault conditions and are not intended for continuous operation. Continuous and repetitive operation of protection functions may reduce the IC lifetime. 8/37 A DocID15234 Rev 5 VNI8200XP 4.1 Electrical characteristics Thermal data Table 4. Thermal data Symbol Rth(JC) Rth(JA) Parameter Thermal resistance junction-case (1) Thermal resistance junction-ambient (2) Value Unit Max. 2 C/W Max. 15 C/W 1. Per channel. 2. PSSO36 mounted on the evaluation board STEVALIFP022V1 developed on four layer FR4, with about 8 cm2 for each layer. 5 Electrical characteristics 5.1 Power section 10.5 V < VCC < 36 V; -40 C < TJ < 125 C; unless otherwise specified. Table 5. Power section Symbol Vcc Parameter Test conditions Supply voltage IS IDS Current 20 mA Vcc supply current VREG supply current 50 Max. Unit 36 V 52 V 0.11 0.2 All channels in OFF state, DCDC in OFF state, VREG=5 V, SPI OFF(1) 1 mA All channels in ON state, DCDC in ON state VREG=5 V, SPI ON (2) 5.6 mA DC-DC OFF VREG= 5 V SPI OFF WD_EN=0 200 A DC/DC OFF VREG=5 V SPI ON WD_EN=VREG 250 A All pins at 0 V except VOUT = 24 V VOUT(OFF) OFF state output voltage VIN = 0 V, IOUT = 0 A IOUT(OFF) OFF state output current VIN = VOUT = 0 V Charge pump frequency Channel in ON state (3) FCP 45 IOUT = 0.5 A at TJ = 25 C IOUT = 0.5 A On state resistance Output current at GND disconnection ILGND Typ. 10.5 VccClamp Clamp on Vcc RDS(on) Min. 0 1.45 0.5 mA 1 V 2 A MHz 1. SS signal high, NO communication. 2. SS signal low, communication ON. 3. To cover EN55022 class A and class B normatives. DocID15234 Rev 5 9/37 Electrical characteristics 5.2 VNI8200XP SPI characteristics 10.5 V < VCC < 36 V; 2.7 V < VREG < 5 V; -40 <Tj <125; unless otherwise specified. Table 6. SPI characteristics Symbol Typ. Max. Unit SPI clock frequency - 5 MHz tr(CLK), tf(CLK) SPI clock rise/fall time - 20 ns tsu(SS) SS setup time 120 - ns th(SS) SS hold time 120 - ns tw(CLK) CLK high time 80 - ns tsu(SDI) Data input setup time 100 - ns th(SDI) Data input hold time 100 - ns ta(SDO) Data output access time - 100 ns tdis(SDO) Data output disable time - 200 ns tv(SDO) Data output valid time - 100 ns th(SDO) Data output hold time fCLK VSDO 5.3 Parameter Test conditions Voltage on serial data output ISDO = 15 mA Min. 0 - ns VREG-0.8 - V ISDO = -4 mA - 0.8 V Min. Typ. Max. Unit Switching VCC = 24 V; -40 C < TJ < 125 C. Table 7. Switching Symbol td(ON) tr td(OFF) tf Parameter Test condition Turn-ON delay time IOUT = 0.5 A, resistive load, input rise time < 0.1 s - 5 - s Rise time IOUT = 0.5 A, resistive load, input rise time < 0.1 s - 5 - s Turn-OFF delay time IOUT = 0.5 A, resistive load, input rise time < 0.1 s - 10 - s Fall time IOUT = 0.5 A, resistive load, input rise time < 0.1 s - 5 - s IOUT = 0.5 A, resistive load, input rise time < 0.1 s - 3 - V/s IOUT = 0.5 A, resistive load, input rise time < 0.1 s - 4 - V/s dV/dt(ON) Turn-ON voltage slope dV/dt(off) 10/37 Turn-OFF voltage slope DocID15234 Rev 5 VNI8200XP 5.4 Electrical characteristics Logic inputs 10.5 V < VCC < 36 V; -40 C < TJ < 125 C; unless otherwise specified. Table 8. Logic inputs Symbol Parameter VIL Input low level voltage VIH Input high level voltage VI(HYST) IIN 5.5 Test conditions Min. Typ. Max. Unit 0.8 V 2.20 Input hysteresis voltage V 0.15 Input current VIN = 5 V V 8 Protection and diagnostic 10.5 V < VCC < 36 V; -40 C < TJ < 125 C; unless otherwise specified. Table 9. Protection and diagnostic Symbol Parameter VPGH1 Min. Typ. Max. Power Good diagnostic ON threshold 16.6 17.5 18.4 VPGH2 Power Good diagnostic OFF threshold 15.6 16.5 17.4 V VPGHYS Power Good diagnostic hysteresis 10.5 V VUSD VUSDHYS Test conditions Unit 1 Undervoltage ON protection 9.5 Undervoltage OFF protection 9 V 0.5 V VCC-52 VCC-50 VCC-45 V Undervoltage hysteresis 0.4 Vdemag Output voltage at turnOFF IOUT = 0.5 A; LLOAD 1 mH VTWARN TWARN pin low-state output voltage ITWARN = 3 mA (active condition) 0.6 V VFAULT FAULT pin low-state output voltage IFAULT = 3 mA (fault condition) 0.6 V 0.7 V VPG PG pin low-state output IPG = 3 mA (active condition) voltage VREG=3.3 V VCC=0 IPEAK Maximum DC output current before limitation ILIM Short-circuit current limitation per channel 1.4 RLOAD = 0 DocID15234 Rev 5 0.7 1.1 A 1.7 A 11/37 Electrical characteristics VNI8200XP Table 9. Protection and diagnostic (continued) Symbol Hyst Parameter Test conditions ILIM tracking limits RLOAD = 0 ILFAULT FAULT leakage current ITWARN TWARN leakage current IPG PG leakage current TTSD Junction shutdown temperature Min. Typ. Max. 0.3 Vpin = 5 V A 2 A 180 C Junction reset temperature 160 C THIST Junction thermal hysteresis 20 C TCSD Case shutdown temperature TCR Case reset temperature 110 C TCHYST Case thermal hysteresis 20 C TR 160 Unit 115 tWD Watchdog hold time See Figure 6 tWM Watchdog time See Table 14 and Figure 6 tOUT_EN OUT_EN pin propagation delay(1) Vcc= 24 V Iout 72 mA tres OUT_EN hold time tWO Watchdog timeout(2) 130 155 50 C ns 10 us 50 ns tWM + td(off) ms 1. Time from reset active low and power out disable. 2. The time from tWM elapsed to power out disable. 5.6 Step-down switching regulator 10.5 V < VCC < 36 V; -40 C < TJ < 125 C; unless otherwise specified. Table 10. Step-down switching regulator Symbol VDC_out VFB RDS(on) 12/37 Parameter Test conditions Regulated output voltage Ireg from 0 to 100 mA VREG 3.3 V, Figure 8. Min. Typ. Max. 3.1 3.3 3.5 V Ireg from 0 to 100 mA VREG 5 V, Figure 9. Voltage feedback 5 3.1 MOSFET on-resistance DocID15234 Rev 5 Unit 3.3 1.5 3.5 V VNI8200XP Electrical characteristics Table 10. Step-down switching regulator (continued) Symbol Test conditions Ilim Limitation current Iqop Total operating quiescent current Iqst-by Min. Typ. Max. Unit 0.9 A 0.55 Total standby quiescent current Regulator standby 0.6 mA 15.8 A fs Switching frequency 400 kHz Dmax Maximum duty cycle 80% % Minimum on-time 150 ns Frequency in short-circuit condition 50 kHz Tonmin fsc 5.7 Parameter LED driving array 10.5 V < VCC < 36 V; -40 C < TJ < 125 C; unless otherwise specified. Table 11. LED driving array Symbol Parameter VCOL Output source voltage at COL pins Output current 0 to VREG-0.3 VREG-0.2 7 mA VROW Open drain voltage at ROW pins Output current 0 to 15 mA Fsw Test conditions Row refresh frequency with duty=25% DocID15234 Rev 5 Min. Typ. 0.2 780 Max. Unit V 0.3 V Hz 13/37 Reverse polarity protection 6 VNI8200XP Reverse polarity protection The reverse polarity protection (which is not available in this device), could be implemented on the board by a diode or by a resistance in series to the GND. The resistance value has to be calculated considering the maximum operating supply voltage Vcc, the maximum Vcc reverse voltage evaluated as drop on the device (-Vcc) and the maximum reverse current IGND. 14/37 DocID15234 Rev 5 VNI8200XP 7 Truth table Truth table Table 12. Truth table Condition Input Output SPI Status bit Fault Twarn Power Good High On Reset High High High Low Off Reset High High High High Off Set Low X X Off Set(1) High X X Off Set(1) X Low Low Off Set(1) X Low X High Off Reset X X X Low Off Reset X X X On Set(2) High High Low Off Set(2) High High Low Normal operation Junction overtemperature Low High Case overtemperature (1) X Undervoltage High Power Good Low 1. This signal becomes high after the temperature falls below the reset threshold. 2. If fault expires, the reset condition occurs after SPI communication, otherwise it is set again. DocID15234 Rev 5 15/37 Functional pin description VNI8200XP 8 Functional pin description 8.1 SPI/parallel selection mode (SEL2) This pin allows the selection of the IC interfacing mode. The SPI interface is selected if SEL2 = H, while the parallel interface is selected if SEL2 = L, according to Table 13: Table 13. Pin description Function Pin SDO/IN8 SDO SS/IN7 SEL2(1) = H SEL2 = L SPI operation Parallel operation Serial data output IN8 Input to channel 8 SS Slave select IN7 Input to channel 7 CLK/IN6 CLK Serial clock IN6 Input to channel 6 SDI/IN5 SDI Serial data input IN5 Input to channel 5 WD/IN4 WD Watchdog input IN4 Input to channel 4 OUT_EN/IN3 OUT_EN IC OUTPUT enable / disable IN3 Input to channel 3 WD_EN/IN2 WD_EN Watchdog enable / disable and timing preset IN2 Input to channel 2 SEL1/IN1 SEL1 8/16-bit SPI selection mode IN1 Input to channel 1 1. SEL2 has an internal weak pull-down. 8.2 Serial data in (SDI) If SEL2 = H, this pin is the input of the serial control frame. SDI is read on CLK rising edges and, therefore, the microcontroller must change SDI state during the CLK falling edges. After the SS falling edge, the SDI is equal to the most significant bit of the control frame (Figure 3). 8.3 Serial data out (SDO) If SEL2 = H, this pin is the output of the serial fault frame. SDO is updated on CLK falling edges and, therefore, the microcontroller must read SDO state during the CLK rising edges. The SDO pin is tri-stated when SS signal is high and it is equal to the most significant bit of the fault frame after the SS falling edge (Figure 3). 16/37 DocID15234 Rev 5 VNI8200XP 8.4 Functional pin description Serial data clock (CLK) If SEL2 = H, the CLK line is the input clock for serial data sampling. On CLK rising edge the SDI input is sampled by the IC and the SDO output is sampled by the host microcontroller. On CLK falling edge, both SDI and SDO lines are updated to the next bit of the frame, from the most to the less significant one (see Figure 3). When the SS signal is high, slave not selected, the microcontroller should drive the CLK low (the settings for the MCU SPI port are CPHA = 0 and CPOL = 0). 8.5 Slave select (SS) If SEL2 = H, the slave select (SS) signal is used to enable the VNI8200XP serial communication shift register; data is flushed-in through the SDI pin and flushed-out from the SDO pin only when the SS pin is low. On the SS pin falling edge the shift register (containing the fault conditions) is frozen, so any change on the power switches status is latched until the next SS falling edge event and the SDO output is enabled. On the SS pin rising edge event the 8/16 bits present on the SPI shift register are evaluated and the outputs are driven according to this frame. If more than 8/16 bits (depending on the SPI settings) are flushed inside only the last 8/16 are evaluated; the others are flushed out from the SDO pin after fault condition bits; in this way a proper communication is possible also in a daisy chain configuration. Figure 3. SPI mode diagram CPHA=0 SCK CPOL=0 SDO MSBit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSBit SDI MSBit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSBit SS Capture Strobe AM11797v1 8.6 8/16-bit selection (SEL1) If SEL2 = H, SEL1 is used to select between two possible SPI configurations: the 8-bit SPI mode (SEL1 = L) and the 16-bit SPI mode (SEL1 = H). 8/16-bit SPI operation is described below. DocID15234 Rev 5 17/37 Functional pin description 8.7 VNI8200XP Output enable (OUT_EN) If SEL2 = H, the OUT_EN pin provides a fast way to disable all the outputs simultaneously. When the OUT_EN pin is driven low for at least TRES, the outputs are disabled while fault conditions in the SPI register are latched. To enable the outputs it is then necessary to raise the OUT_EN pin and re-program the IC through the SPI interface. As fault conditions are latched inside the IC and SPI interface is working also while the OUT_EN pin is driven low, it's possible to use SPI to detect if a fault condition occurred before than the reset event. The device is ready to operate normally after a TSU period. The OUT_EN pin is the fastest way to disable all the outputs when a fault occurs. Figure 4. Output channel enable/disable behavior OUT_EN t Vin( i) t OUT(i) t tOUT_EN AM12824v1 8.8 IC warning case temperature detection (TWARN) The TWARN pin is an active low open drain output. This pin is activated if the IC case temperature exceeds TCSD. According to the PCB thermal design and RthJC value, this function allows a warning about a PCB overheating condition to be given. The TWARN bit is also available through SPI. This bit is not latched: the TWARN pin is low only while the case overtemperature condition is active (TC > TCSD) and is released when this condition is removed (TC < TCR). 18/37 DocID15234 Rev 5 VNI8200XP 8.9 Functional pin description Fault indication (FAULT) The FAULT pin is an open drain active low fault indication pin. This pin is activated by one or more of the following conditions: * Channel overtemperature (OVT) This pin is activated when at least one of the channels is in junction overtemperature. Unlike the SPI fault detection bits, this signal is not latched: the FAULT pin is low only when the fault condition is active and is released if the input driving signal is off or after the OVT protection condition has been removed. This last event occurs if the channel temperature decreases below the threshold level and the case temperature has not exceeded TCSD or is below TCR. This means that the FAULT pin is low only while the junction overtemperature is active (TJ >TTSD) and is released after this condition has been removed (TJ < TR and TC < TCR). * Parity check fail When SPI mode is used (SEL2 = H), if a parity check fault of the incoming SPI frame is detected or counted, CLK rising edges are different by a multiple of 8, the FAULT pin is kept low. When counted CLK rising edges are a multiple of 8 and parity check is valid, the FAULT pin is kept high. 8.10 Power Good (PG) The PG terminal is an open drain, that indicates the status of the supply voltage. When VCC supply voltage reaches the Vsth1 threshold, PG goes into a high impedance state. It goes into a low impedance state when VCC falls below the Vsth2 threshold. In 16-bit SPI mode, a PG bit is also available. This bit is set high when the Power Good diagnostic is active, it is otherwise cleared. Figure 5. Power Good diagnostic 3* 93*+ 93*+ 9FF !-V DocID15234 Rev 5 19/37 Functional pin description 8.11 VNI8200XP Programmable watchdog counter reset (WD) If SEL2 = H, the VNI8200XP embeds a watchdog counter that must be erased, with a negative pulse on the WD pin, before it expires. If the WD counter elapses, the VNI8200XP goes into an internal RESET state where all the outputs are disabled; to restart normal operation a negative pulse must be applied to the WD pin. The watchdog enable/disable pin should be connected through an external divider to VREG. The watchdog time is fixed in the following Table 14: Table 14. Programmable watchdog time VWD_EN tWM 0.25 VREG > VWD_EN Disable 0.25 VREG VWD_EN < 0.5 VREG 40 12% ms 0.5 VREG VWD_EN < 0.75 VREG 80 12% ms 0.75 VREG VWD_EN = VREG 160 12% ms Figure 6. Watchdog reset WD t WM t WD t AM11802v1 20/37 DocID15234 Rev 5 VNI8200XP SPI operation (SEL2 = H) 9 SPI operation (SEL2 = H) 9.1 8-bit SPI mode (SEL1 = L) If SEL2 = H, the 8-bit SPI mode is based on an 8-bit command frame sent from the microcontroller to the IC; each bit directly drives the corresponding output where LSB drives output 0 and MSB drives output 7. Each bit, set to `1', activates (closes) the corresponding output. At the same time, the IC transfers the channel fault conditions (OVT) to the microcontroller. These fault conditions are latched at the occurrence and cleared after each communication (each time the SS signal has a positive transition). Each bit, set to `1', indicates an OVT condition for the corresponding channel. Table 15. Command 8-bit frame (master to slave) MSB LSB IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 Table 16. Fault 8-bit frame (slave to master) MSB LSB F7 9.2 F6 F5 F4 F3 F2 F1 F0 16-bit SPI mode (SEL1 = H) The 16-bit SPI mode is based on a 16-bit command frame sent from the microcontroller to the IC; the first 8 bits directly drive the output channels (each bit, set to `1', activates the corresponding output), the other 8 bits contain a 4-bit parity check code where the last bit (the inversion of the previous one) is used to detect a communication error condition (providing at least a transition in each frame): P0 = IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 P1 = IN1 IN3 IN5 IN7 P2 = IN0 IN2 IN4 IN6 nP0 = NOT P0 Table 17. Command 16-bit frame (master to slave) MSB IN7 LSB IN6 IN5 IN4 IN3 IN2 IN1 IN0 - - - - P2 P1 P0 nP0 At the same time, the IC transfers to the microcontroller a 16-bit fault frame where the first 8 bits indicate a channel fault (OVT) condition (each bit, set to `1', indicates an OVT event), the following 4 bits provide general fault condition information. FB_OK: this bit is related to the DC-DC regulation: at the DC-DC turn-on, this bit is low and becomes high after FB rises above 90% of the nominal VFB voltage and a correct SPI communication occurred. If the FB DocID15234 Rev 5 21/37 SPI operation (SEL2 = H) VNI8200XP voltage falls below 80% of the nominal VFB voltage, this bit is zero; TWARN (IC warning case temperature, see Section 8.8), PC (parity check fail, the bit, set to `1', indicates a PC fail or the length is not a multiple of 8) and PG (Power Good, see Section 8.10). The last 4 bits are used as parity check bits and communication error condition (see command 16 bit frame): P0 = F0 F1 F2 F3 F4 F5 F6 F7 P1 = PC FB_OK F1 F3 F5 F7 P2 = PG TWARN F0 F2 F4 F6 nP0 = NOT P0 Table 18. Fault 16-bit frame slave to master MSB F7 LSB F6 F5 F4 F3 F2 F1 F0 FB_OK TWARN PC PG P2 Channel indications are latched and cleared after a communication only. 22/37 DocID15234 Rev 5 P1 P0 nP0 VNI8200XP 10 LED driving array LED driving array The LED driving array carries out the status of the output channels (ON or OFF) Figure 7. LED driving array 52: 52: 52: &2/ &2/ 95(* 67$786 67$786 67$786 67$786 67$786 67$786 67$786 52: 67$786 $0Y The following is an indication of how to choose the Rext resistor value. Equation 1 ( VCOLmin ) - ( V ROWmax ) - VF ( LED ) R ext = ------------------------------------------------------------------------------------------IF ( LED ) Note: IF(LED) 7 mA. Where (VCOL min.) and (VROW max.) can be found in Table 11 and VF(LED) and IF(LED) depend on the electrical characteristics of the LEDs. DocID15234 Rev 5 23/37 Step-down switching regulator 11 VNI8200XP Step-down switching regulator The IC embeds a high efficiency 100 mA micropower step-down switching regulator. The regulator is protected against short-circuit or overload conditions. Pulse-by-pulse current limit regulation is obtained in normal operation through a current loop control. A low ESR output capacitor connected to the VREG pin helps to limit the regulated voltage ripple; a low ESR (less than 10 m) capacitor is preferable. The control loop pin FB allows 3.3 V to be regulated, connecting it directly to VREG, or 5 V connecting it through a voltage divider Rl/Rfbl. The DC-DC converter can be turned off by connecting the feedback pin to the DCVDD pin. In some applications it is possible to supply a 5 V or 3.3 V voltage externally or, in the case of two or more VNI8200XPs inside the same board, it's possible to configure the DC-DC converter on only one device and supply also the other ICs. Note: 24/37 if the DC-DC converter is adjusted to provide 3.3 V regulation and the Vdc_out is used to power an external load and not the device, a 33 k resistor has to be connected on Vdc_out pin. DocID15234 Rev 5 SDO 1 SS 1 CLK 1 SDI 1 OUT_EN DocID15234 Rev 5 R47 10k 115R 115R 100nF/10V GND LD9 1 LD10 1 LD11 1 Vreg PGOOD FAULT TWARN DC/DC OFF 3 LEDC-0603 1 CH2 LEDC-0603 LD4 2 1 CH4 LEDC-0603 CH6 2 LD6 1 LEDC-0603 CH8 2LD8 1 LEDC-0603 LD1 CH1 2 1 LEDC-0603 LD3 CH3 2 1 LEDC-0603 CH5 2 LD5 1 LEDC-0603 CH7 2 LD7 1 LD2 10nF/10V R52 10nF/10V R51 VNI8200 470R 2 TWARN LEDC-0603 2 FAULT LEDC-0603 R55 LEDC-0603 470R 470R 2 R53 R54 FB STPS1L60A 5V 2k37 1% R50 low ESR< 10mohm MLCC 2 FB 1 C34 1 2 JP8 1 R57 33k C35 C33 PHASE DC/DC 2 4.7uF/10V 2 3V3 PHASE C23 22nF/50V DC/DC ON JP12 GND_Board 22nF/50V 1k47 1% Vreg C24 C32 10nF/10V C31 22nF/50V D3 R45 C25 10k 1% R44 22nF/50V PG 21 20 19 L1 100uH/0.7R Is>700mA 22nF/50V 22nF/50V C27 C26 FAULT TWARN FB C21 GND_Board C9 22nF/50V C18 13 DCVDD BOOT NC#26 PHASE STPSH100A 1 C8 22nF/50V 18 ROW3 14 VREF 16 ROW1 17 ROW2 12 COL1 15 ROW0 OUT8 OUT7 OUT6 OUT5 OUT4 low ESR MLCC D2 2 C10 C19 C28 4.7pF/10V C22 TAB=Vcc OUT3 OUT2 36 35 34 33 32 31 30 29 28 27 26 25 24 22 GND_DISC 2 JP11 1 1 C30 4.7pF/10V C29 10 VREG 11 COL0 8 SS/IN7 9 SDO/IN8 6 SDI/IN5 7 CLK/IN6 4 OUT_EN/IN3 5 WD/IN4 OUT1 NC#36 NC#35 C15 1uF/50V 8k + 50ZL100MEFC8X11.5 TP2 TP3 TP4 TP5 C20 4.7pF/10V 270R 270R R37 R39 1 SEL2 2 SEL1/IN1 3 WD_EN/IN2 R56 C7 100uF/50V 3.3pF/10V 3 Vreg 270R EP C17 270R 37 OPT_SDO 270R R35 1 OPT_SS 3 R33 1 SEL1 R31 SEL2 C14 100pF/10V C16 100pF/10V U7 CN2 Ext_Vreg 1 2 TRS1 C12 100pF/10V C13 100pF/10V C11 100pF/10V 2 1uF/50V OPT_CLK 2 JP6 D1 STPS1L60 1 4.7nF Y1 / 4kV TRISIL-BIDIR-SMC OPT_SDI 1 3 R30 10k R32 10k R34 10k R36 10k R38 10k R40 100R R41 100R R42 100R R43 140R 2 Vreg JP5 Vreg TP1 4.7nF Y1 / 4kV OPT_SDI OPT_CLK OPT_SS OPT_SDO 1 1 OPT_OUT_EN 1 Vreg JP4 1 OPT_WD_EN OPT_SEL1 OPT_WD 2 JP3 Vreg EXT_WD 2 JP2 2 OPT_OUT_EN OPT_WD_EN OPT_SEL1 OPT_WD Vreg TP7 WD OUT8 CON8 1 2 3 4 5 6 7 8 CN3 EARTH OUT1 TP6 1 VCC CN1 + 1 2 - 12 1 VNI8200XP Typical circuits and conventions Typical circuits and conventions Figure 8. Typical circuit for switching regulation VDC-out = 3.3 V 22nF/50V 100pF/50V 2 PGOOD 23 WD_EN R49 10k R48 10k 3 R46 10k AM11799v1 25/37 26/37 :' 287B(1 6'2 66 &/. 6', DocID15234 Rev 5 /' /' &+ /('& &+ &+ )$8/7 9UHJ 3*22' /' /' /' /('& /('& &+ /('& 7:$51 /('& &+ /('& &+ /('& &+ /('& Q)9 /' Q)9 /' '&'&2)) /('& 7:$51 /('& )$8/7 /('& 3*22' 5 5 5 5 5 5 )% 6736/$ 9 ORZ(65PRKP0/&& N 5 N & Q)9 5 *1' 91, & -3 '&'& X)9 & 3+$6( )% 9 3+$6( & Q)9 & Q)9 5 -3 9UHJ & -3 & Q)9 ' N N 5 & Q)9 '&'&21 5 / X+5,V!P$ Q)9 *1'B%RDUG & Q)9 & & *1'B%RDUG & & Q)9 3* X)9 ORZ(650/&& & Q)9 )$ 8/7 7: $51 )% 3+$6( %22 7 1& 287 287 287 -3 ' 6736+$ & & Q)9 5 5 /' &+ 5 & 9FF (3 287 287 287 287 287 1& 1& & *1'B',6& N & & Q)9 /' /' /' :'B(1 & S)9 9UHJ 6(/ 6(/ ,1 : 'B( 1,1 287B( 1,1 : ',1 6',,1 &/. ,1 66,1 7$% 6'2 ,1 95( * &2/ &2/ 52: 52: 52: 52: 95( ) '&9' ' 5 X)9 S)9 & S)9 & S)9 5 5 5 5 5 6(/ S)9 & S)9 & S)9 & S)9 8 & S)9 & & 6(/ 5 5 5 5 5 -3 &1 =/0()&; 5 5 5 5 5 5 5 5 X)9 5 N 5 N 5 N 5 N 5 N 6736/ 756 73 73 73 73 9UHJ -3 9UHJ Q)<N9 75,6,/%,',560& 237B&/. 237B&/. 237B66 237B66 237B6'2 237B6'2 9UHJ -3 237B287B(1 237B:'B(1 237B6(/ 237B:' -3 ([WB9UHJ ' Q)<N9 237B6',237B6', 237B287B(1 237B:'B(1 237B6(/ 237B:' 9UHJ 73 9UHJ -3 (;7B:' 73 737+$1(//200 &1 9&& &1 287 &21 287 ($57+ 73 Typical circuits and conventions VNI8200XP Figure 9. Typical circuit for switching regulation VDC-out = 5 V S)9 N 5 N 5 5 5 N $0Y VNI8200XP Typical circuits and conventions Figure 10. SPI directional logic convention 6', 9UHJ 66 &/. 287 6'2 287 :' 287 287B(1 :'B(1 7$% 9FF 287 287 287 6(/ 287 6(/ 287 3* )$8/7 7:$51 *1' $0Y DocID15234 Rev 5 27/37 Thermal management 13 VNI8200XP Thermal management The power dissipation in the IC is the main factor that sets the safe operating condition of the device in the application. Therefore, it must be taken into account very carefully. Heatsinking can be achieved using copper on the PCB with proper area and thickness. The following image (Figure 11) shows the junction-to-ambient thermal impedance values for the PSSO36 package. Figure 11. PSSO36 thermal impedance vs. time For instance, three cases have been considered using a PSSO36 packaged with copper slug soldered on a 1.6 mm thickness FR4 board with dissipating footprint (copper thickness of 70 m): 28/37 * single layer PCB with just IC footprint dissipating area * double layer PCB with footprint dissipating area on the top side and a 2 cm2 dissipating layer on the bottom side through 15 via holes * double layer PCB with footprint dissipating area on the top side and an 8 cm2 dissipating layer on the bottom side through 15 via holes. DocID15234 Rev 5 VNI8200XP 13.1 Thermal management Thermal behavior Figure 12. Thermal behavior 9LQ L + 287 L 2Q 67$7 L 2II + 1 12 7M L !7WVG <(6 287 L 2II 67$7 L 2Q / 4 <(6 7F!7FVG 12 2 <(6 12 7F!7FU 12 7M L !7MU <(6 3 $0Y Note: 1 Thermal shutdown. 2 Junction hysteresis. 3 Restore to idle condition. 4 Case hysteresis. DocID15234 Rev 5 29/37 Interface timing diagram 14 VNI8200XP Interface timing diagram Figure 13. Serial timing 15 Switching parameter test conditions Figure 14. dV/dt(ON) and dV/dt(OFF) time diagram test conditions 9RXW G9 21 G9 2)) WU WI W $0Y 30/37 DocID15234 Rev 5 VNI8200XP Switching parameter test conditions Figure 15. td(ON) and td(OFF) time diagram test conditions 66 WG 2)) W 9RXW W WG 21 $0Y DocID15234 Rev 5 31/37 Package mechanical data 16 VNI8200XP Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Table 19. PowerSSO-36 mechanical data mm Symbol Min. Typ. A 2.15 2.47 A2 2.15 2.40 a1 0 0.075 b 0.18 0.36 c 0.23 0.32 D 10.10 10.50 E 7.4 7.6 e 0.5 e3 8.5 F 2.3 G 0.075 G1 0.06 H 10.1 10.5 h L 0.4 0.55 M 0.85 4.3 N 32/37 Max. 10deg O 1.2 Q 0.8 S 2.9 T 3.65 U 1.0 X 4.1 4.7 Y 4.9 5.5 DocID15234 Rev 5 VNI8200XP Package mechanical data Figure 16. PowerSSO-36 package dimensions Figure 17. PowerSSO-36 tube shipment (no suffix) Table 20. PowerSSO-36 tube shipment Note: Base Q.ty 49 Bulk Q.ty 1225 Tube length ( 0.5) 532 A 3.5 B 13.8 C ( 0.1) 0.6 All dimensions are in mm. DocID15234 Rev 5 33/37 Package mechanical data VNI8200XP Figure 18. PowerSSO-36 reel shipment (suffix "TR") Table 21. PowerSSO-36 reel dimensions 34/37 Base Q.ty 1000 Bulk Q.ty 1000 A (max.) 330 B (min.) 1.5 C ( 0.2) 13 F 20.2 G (2 0) 24.4 N (min.) 100 T (max.) 30.4 DocID15234 Rev 5 VNI8200XP Package mechanical data Figure 19. PowerSSO-36 tape dimensions Table 22. PowerSSO-36 tape dimensions Note: Tape width W 24 Tape hole spacing P0 ( 0.1) 4 Component spacing P 12 Hole diameter D ( 0.05) 1.55 Hole diameter D1 (min.) 1.5 Hole position F ( 0.1) 11.5 Compartment depth K (max.) 2.85 Hole spacing P1 ( 0.1) 2 According to the Electronic Industries Association (EIA) standard 481 rev. A, Feb 1986. DocID15234 Rev 5 35/37 Revision history 17 VNI8200XP Revision history Table 23. Document revision history Date Revision 04-Dec-2008 1 Initial release 29-Apr-2009 2 Updated Table 5 on page 9 19-Jun-2012 3 Updated: Features,Section 8.4,Section 8.7,Section 8.9,Section 8.10, Section 11,Table 2,Table 3,Table 5,Table 7,Table 8,Table 9, Table 10,Table 11,Table 14,Figure 1,Figure 2. Changed: Figure 4,Figure 5,Figure 6,Figure 15,Figure 15. Content reworked to improve the readability. 27-Jun-2012 4 Changed: Symbols in 16-bit frame Section 9.2. 5 Updated Table 5, Table 9, Table 10, Table 14. Updated footnote 2. in Table 4. Updated Section 11. Added Section 6. Changed Figure 8 and Figure 9. Added Table 12. Changed product status to production data. 08-Mar-2013 36/37 Changes DocID15234 Rev 5 VNI8200XP Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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