This is information on a product in full production.
March 2013 DocID15234 Rev 5 1/37
37
VNI8200XP
Octal high-side smart power solid state relay with serial/parallel
selectable interface on chip
Datasheet - production data
Features
•Output current: 0.7 A per channel
•Serial/parallel selectable interface
•Short-circuit protection
•8-bit and 16-bit SPI Interface for IC command
and control diagnostic
•Channel overtemperature detection and
protection
•Thermal independence of separate channels
•Drives all type of loads (resistive, capacitive,
inductive load)
•Loss of GND protection
•Power Good diagnostic
•Undervoltage shutdown with hysteresis
•Overvoltage protection (VCC clamping)
•Very low supply current
•Common fault open drain output
•IC warning temperature detection
•Channel output enable
•100 mA high efficiency step-down switching
regulator with integrated boot diode
•Adjustable regulator output
•Switching regulator disable
•5 V and 3.3 V compatible I/Os
•Channel outputs status LED driving 4 x 2
multiplexed array
•Fast demagnetization of inductive loads
•ESD protection
•Designed to meet IEC 61131-2, IEC61000-4-4,
and IEC61000-4-5
Applications
•Programmable logic control
•Industrial PC peripheral input/output
•Numerical control machines
Type Vdemag(1)
1. Per channel
RDS(on)(1) Iout(1) VCC
VNI8200XP VCC-45 V 0.11 Ω0.7 A 45 V
PowerSSO-36
Table 1. Device summary
Part number Package Packing
VNI8200XP PowerSSO-36 Tube
VNI8200XPTR Tape and reel
www.st.com
Contents VNI8200XP
2/37 DocID15234 Rev 5
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.4 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.5 Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.6 Step-down switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.7 LED driving array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8 Functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.1 SPI/parallel selection mode (SEL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.2 Serial data in (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.3 Serial data out (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.4 Serial data clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.5 Slave select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.6 8/16-bit selection (SEL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.7 Output enable (OUT_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.8 IC warning case temperature detection (TWARN) . . . . . . . . . . . . . . . . . . 18
8.9 Fault indication (FAULT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.10 Power Good (PG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DocID15234 Rev 5 3/37
VNI8200XP Contents
8.11 Programmable watchdog counter reset (WD) . . . . . . . . . . . . . . . . . . . . . 20
9 SPI operation (SEL2 = H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.1 8-bit SPI mode (SEL1 = L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.2 16-bit SPI mode (SEL1 = H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10 LED driving array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11 Step-down switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12 Typical circuits and conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.1 Thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
14 Interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
15 Switching parameter test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 30
16 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Description VNI8200XP
4/37 DocID15234 Rev 5
1 Description
The VNI8200XP is a monolithic 8-channel driver featuring a very low supply current, with
integrated SPI interface and high efficiency 100 mA micropower step-down switching
regulator peak current control loop mode. The IC, realized in STMicroelectronics™
VIPower™ technology, is intended for driving any kind of load with one side connected to
ground.
Active channel current limitation combined with thermal shutdown, independent for each
channel, and automatic restart, protect the device against overload.
Additional embedded functions are: loss of GND protection that automatically turns off the
device outputs in case of ground disconnection, undervoltage shutdown with hysteresis,
Power Good diagnostic for valid supply voltage range recognition, output enable function for
immediate power outputs ON/OFF, and programmable watchdog function for
microcontroller safe operation; case overtemperature protection to control the IC case
temperature.
The device embeds a four-wire SPI serial peripheral with selectable 8 or 16-bit operations;
through a select pin the device can also operate with a parallel interface.
Both the 8-bit and 16-bit SPI operations are compatible with daisy chain connection.
The SPI interface allows command of the output driver by enabling or disabling each
channel featuring, in 16-bit format, a parity check control for communication robustness. It
also allows the monitoring of the status of the IC signaling Power Good, overtemperature
condition for each channel, IC pre-warning temperature detection.
Built-in thermal shutdown protects the chip from overtemperature and short-circuit. In
overload condition, the channel turns OFF and ON again automatically after the IC
temperature decreases below a threshold fixed by a temperature hysteresis so that junction
temperature is controlled. If this condition makes case temperature reaching case
temperature limit, TCSD, overloaded channels are turned OFF and restart, non-
simultaneously, when case and junction temperature decrease below their own reset
threshold. If the case of thermal reset, the channels loaded are not switched on until the
junction temperature reset event. Non-overloaded channels continue to operate normally.
Case temperature above TCSD is reported through the TWARN open drain pin.
An internal circuit provides a not latched common FAULT indicator reporting if one of the
following events occurs: channel OVT (overtemperature), parity check fail. The Power Good
diagnostic warns the controller that the supply voltage is below a fixed threshold.
The watchdog function is used to detect the occurrence of a software fault of the host
controller. The watchdog circuitry generates an internal reset on expiry of the internal
watchdog timer. The watchdog timer reset can be achieved by applying a negative pulse on
the WD pin. The watchdog function can be disabled by the WD_EN dedicated pin. This pin
also allows the programming of a wide range of watchdog timings.
An internal LED matrix driver circuitry (4 rows, 2 columns) allows the detection of the status
of the single outputs. An integrated step-down voltage regulator provides supply voltage to
the internal LED matrix driver and logic output buffers and can be used to supply the
external optocouplers if the application requires isolation. The regulator is protected against
short-circuit or overload conditions by means of pulse-by-pulse current limit with a peak
current control loop.
DocID15234 Rev 5 5/37
VNI8200XP Block diagram
2 Block diagram
Figure 1. Block diagram
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Pin connection VNI8200XP
6/37 DocID15234 Rev 5
3 Pin connection
Figure 2. Pin connection (top view)
Table 2. Pin description
Pin Name Type Description
1 SEL2 Logic input SPI/parallel selection mode
2 SEL1/IN1 Logic input 8/16-bit SPI selection mode/channel 1 input
3 WD_EN/ IN2 Logic/analog input Watchdog enable_setting/channel 2 input
4 OUT_EN /IN3 Logic input Output enable/channel 3 input
5 WD/IN4 Logic input Watchdog input. The internal watchdog counter is
cleared on the falling edges/channel 4 input.
6 SDI/IN5 Logic input Serial data input/channel 5 input
7 CLK/IN6 Logic input Serial clock/channel 6 input
8SS
/IN7 Logic input Slave select/channel 7 input
9 SDO/IN8 Logic input/output Serial data output/channel 8 input
10 VREG Power supply SPI/inputs/LED supply voltage
11 COL0 Open source output LED source output
12 COL1 Open source output LED source output
13 DCVDD Analog output Internally generated DC-DC low voltage supply. (To be
connected to external 10 nF capacitor).
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DocID15234 Rev 5 7/37
VNI8200XP Pin connection
14 VREF Analog output Internally generated DC-DC voltage reference (To be
connected to external 10 nF capacitor).
15 ROW0 Open drain output Status channel 1-2
16 ROW1 Open drain output Status channel 3-4
17 ROW2 Open drain output Status channel 5-6
18 ROW3 Open drain output Status channel 7-8
19 PG Open drain output Power Good diagnostic - active low
20 FAULT Open drain output Fault indication - active low
21 TWARN Open drain output IC case warning temperature detection - active low
22 FB Analog input
Step-down feedback input. Connecting the output
voltage directly to this pin results in an output voltage
of 3.3 V. An external resistor divider is required for
higher output voltages.
23 GND Ground
24 PHASE Power output Step-down output
25 BOOT Power output
Step-down bootstrap voltage. Used to provide a drive
voltage, higher than the supply voltage, to power the
switch of the step-down regulator.
26 NC Not connected
27 OUT8 Power output Channel 8 power output
28 OUT7 Power output Channel 7 power output
29 OUT6 Power output Channel 6 power output
30 OUT5 Power output Channel 5 power output
31 OUT4 Power output Channel 4 power output
32 OUT3 Power output Channel 3 power output
33 OUT2 Power output Channel 2 power output
34 OUT1 Power output Channel 1 power output
35 NC Not connected
36 NC Not connected
TAB TAB Power supply Exposed tab internally connected to VCC
Table 2. Pin description (continued)
Pin Name Type Description
Maximum ratings VNI8200XP
8/37 DocID15234 Rev 5
4 Maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC Power supply voltage 45 V
-VCC Reverse supply voltage -0.3 V
VREG Logic supply voltage -0.3 to +6 V
VFAULT
VTWARN
VPG
Voltage range at pins TWARN, FAULT, PG -0.3 to +6 V
VBOOT Bootstrap peak voltage VPHASE = Vcc VCC+6 V
VROW Voltage range at ROW pins -0.3 to +6 V
VCOL Voltage range at COL pins -0.3 to +6 V
Vdig Voltage level range at logic input pins -0.3 to +6 V
IOUT Output current (continuous) Internally limited (1) A
IRReverse output current (per channel) -5 A
IGND DC ground reverse current -250 mA
IREG VREG input current -1/10 mA
IFAULT
ITWARN,
IPG
Current range at pins TWARN, FAULT, PG -1 to +10 mA
IIN Input current range -1 to +10 mA
IROW
Current range at ROW pins (ROW in ON state) +20 mA
Current range at ROW pins (ROW in OFF state) -1 to +10 mA
ICOL
Current range at COL pins (COL in ON state) -10 mA
Current range at COL pins (COL in OFF state) -1 to +10 mA
VESD Electrostatic discharge (R = 1.5 kΩ; C = 100 pF) 2000 V
EAS
Single pulse avalanche energy per channel not
simultaneously 300 mJ
PTOT Power dissipation at Tc = 25 °C Internally limited(1)
1. Protection functions are intended to avoid IC damage in fault conditions and are not intended for
continuous operation. Continuous and repetitive operation of protection functions may reduce the IC
lifetime.
W
TJJunction operating temperature Internally limited °C
TSTG Storage temperature -55 to 150 °C
DocID15234 Rev 5 9/37
VNI8200XP Electrical characteristics
4.1 Thermal data
5 Electrical characteristics
5.1 Power section
10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified.
Table 4. Thermal data
Symbol Parameter Value Unit
Rth(JC) Thermal resistance junction-case (1)
1. Per channel.
Max. 2 °C/W
Rth(JA) Thermal resistance junction-ambient (2)
2. PSSO36 mounted on the evaluation board STEVALIFP022V1 developed on four layer FR4, with about 8
cm2 for each layer.
Max. 15 °C/W
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
Vcc Supply voltage 10.5 36 V
VccClamp Clamp on Vcc Current 20 mA 45 50 52 V
RDS(on) On state resistance IOUT = 0.5 A at TJ = 25 °C
IOUT = 0.5 A
0.11
0.2 Ω
ISVcc supply current
All channels in OFF state, DC-
DC in OFF state, VREG=5 V,
SPI OFF(1)
1. SS signal high, NO communication.
1mA
All channels in ON state, DC-
DC in ON state VREG=5 V, SPI
ON (2)
2. SS signal low, communication ON.
5.6 mA
IDS VREG supply current
DC-DC OFF VREG= 5 V SPI
OFF WD_EN=0 200 µA
DC/DC OFF VREG=5 V SPI ON
WD_EN=VREG
250 µA
ILGND
Output current at
GND disconnection
All pins at 0 V except VOUT =
24 V 0.5 mA
VOUT(OFF)
OFF state output
voltage VIN = 0 V, IOUT = 0 A 1 V
IOUT(OFF)
OFF state output
current VIN = VOUT = 0 V 0 2 µA
FCP
Charge pump
frequency Channel in ON state (3)
3. To cover EN55022 class A and class B normatives.
1.45 MHz
Electrical characteristics VNI8200XP
10/37 DocID15234 Rev 5
5.2 SPI characteristics
10.5 V < VCC < 36 V; 2.7 V < VREG < 5 V; -40 <Tj <125; unless otherwise specified.
5.3 Switching
VCC = 24 V; -40 °C < TJ < 125 °C.
Table 6. SPI characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
fCLK SPI clock frequency - 5 MHz
tr(CLK),
tf(CLK) SPI clock rise/fall time - 20 ns
tsu(SS)SS setup time 120 - ns
th(SS)SS hold time 120 - ns
tw(CLK) CLK high time 80 - ns
tsu(SDI) Data input setup time 100 - ns
th(SDI) Data input hold time 100 - ns
ta(SDO) Data output access time - 100 ns
tdis(SDO) Data output disable time - 200 ns
tv(SDO) Data output valid time - 100 ns
th(SDO) Data output hold time 0 - ns
VSDO Voltage on serial data output ISDO = 15 mA VREG-0.8 - V
ISDO = -4 mA - 0.8 V
Table 7. Switching
Symbol Parameter Test condition Min. Typ. Max. Unit
td(ON) Turn-ON delay time IOUT = 0.5 A, resistive load,
input rise time < 0.1 µs -5 -µs
trRise time IOUT = 0.5 A, resistive load,
input rise time < 0.1 µs -5 -µs
td(OFF) Turn-OFF delay time IOUT = 0.5 A, resistive load,
input rise time < 0.1 µs -10 -µs
tfFall time IOUT = 0.5 A, resistive load,
input rise time < 0.1 µs -5 -µs
dV/dt(ON) Turn-ON voltage slope IOUT = 0.5 A, resistive load,
input rise time < 0.1 µs -3 -V/µs
dV/dt(off) Turn-OFF voltage
slope
IOUT = 0.5 A, resistive load,
input rise time < 0.1 µs -4 -V/µs
DocID15234 Rev 5 11/37
VNI8200XP Electrical characteristics
5.4 Logic inputs
10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified.
5.5 Protection and diagnostic
10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified.
Table 8. Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level voltage 0.8 V
VIH Input high level voltage 2.20 V
VI(HYST)
Input hysteresis
voltage 0.15 V
IIN Input current VIN = 5 V 8 μΑ
Table 9. Protection and diagnostic
Symbol Parameter Test conditions Min. Typ. Max. Unit
VPGH1
Power Good diagnostic
ON threshold 16.6 17.5 18.4
VVPGH2
Power Good diagnostic
OFF threshold 15.6 16.5 17.4
VPGHYS
Power Good diagnostic
hysteresis 1
VUSD
Undervoltage ON
protection 9.5 10.5 V
Undervoltage OFF
protection 9V
VUSDHYS
Undervoltage
hysteresis 0.4 0.5 V
Vdemag
Output voltage at turn-
OFF IOUT = 0.5 A; LLOAD ≥ 1 mH VCC-52 VCC-50 VCC-45 V
VTWARN
TWARN pin low-state
output voltage
ITWARN = 3 mA (active
condition) 0.6 V
VFAULT
FAULT pin low-state
output voltage IFAULT = 3 mA (fault condition) 0.6 V
VPG
PG pin low-state output
voltage
IPG = 3 mA (active condition)
VREG=3.3 V VCC=0 0.7 V
IPEAK
Maximum DC output
current before
limitation
1.4 A
ILIM
Short-circuit current
limitation per channel RLOAD = 0 0.7 1.1 1.7 A
Electrical characteristics VNI8200XP
12/37 DocID15234 Rev 5
5.6 Step-down switching regulator
10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified.
Hyst ILIM tracking limits RLOAD = 0 0.3 A
ILFAULT FAULT leakage current
Vpin = 5 V 2 μAITWARN
TWARN leakage
current
IPG PG leakage current
TTSD
Junction shutdown
temperature 160 180 °C
TR
Junction reset
temperature 160 °C
THIST
Junction thermal
hysteresis 20 °C
TCSD
Case shutdown
temperature 115 130 155 °C
TCR
Case reset
temperature 110 °C
TCHYST
Case thermal
hysteresis 20 °C
tWD Watchdog hold time See Figure 6 50 ns
tWM Watchdog time See Table 14 and Figure 6
tOUT_EN
OUT_EN pin
propagation delay(1) Vcc= 24 V Iout 72 mA 10 us
tres OUT_EN hold time 50 ns
tWO Watchdog timeout(2) tWM +
td(off)
ms
1. Time from reset active low and power out disable.
2. The time from tWM elapsed to power out disable.
Table 9. Protection and diagnostic (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Table 10. Step-down switching regulator
Symbol Parameter Test conditions Min. Typ. Max. Unit
VDC_out Regulated output voltage
Ireg from 0 to 100 mA
VREG 3.3 V, Figure 8. 3.1 3.3 3.5
V
Ireg from 0 to 100 mA
VREG 5 V, Figure 9.5
VFB Voltage feedback 3.1 3.3 3.5 V
RDS(on) MOSFET on-resistance 1.5 Ω
DocID15234 Rev 5 13/37
VNI8200XP Electrical characteristics
5.7 LED driving array
10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified.
Ilim Limitation current 0.55 0.9 A
Iqop
Total operating quiescent
current 0.6 mA
Iqst-by
Total standby quiescent
current Regulator standby 15.8 µA
fsSwitching frequency 400 kHz
Dmax Maximum duty cycle 80% %
Tonmin Minimum on-time 150 ns
fsc
Frequency in short-circuit
condition 50 kHz
Table 10. Step-down switching regulator (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Table 11. LED driving array
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCOL Output source voltage at COL pins Output current 0 to
7 mA VREG-0.3 VREG-0.2 V
VROW Open drain voltage at ROW pins Output current 0 to
15 mA 0.2 0.3 V
Fsw Row refresh frequency with
duty=25% 780 Hz
Reverse polarity protection VNI8200XP
14/37 DocID15234 Rev 5
6 Reverse polarity protection
The reverse polarity protection (which is not available in this device), could be implemented
on the board by a diode or by a resistance in series to the GND. The resistance value has to
be calculated considering the maximum operating supply voltage Vcc, the maximum Vcc
reverse voltage evaluated as drop on the device (-Vcc) and the maximum reverse current
IGND.
DocID15234 Rev 5 15/37
VNI8200XP Truth table
7 Truth table
Table 12. Truth table
Condition Input Output
SPI
Status
bit
Fault Twarn Power
Good
Normal operation High On Reset High High High
Low Off Reset High High High
Junction overtemperature High Off Set Low X X
Low Off Set(1) High X X
Case overtemperature High Off Set(1) XLowX
Low Off Set(1) X Low(1)
1. This signal becomes high after the temperature falls below the reset threshold.
X
Undervoltage High Off Reset X X X
Low Off Reset X X X
Power Good High On Set(2)
2. If fault expires, the reset condition occurs after SPI communication, otherwise it is set again.
High High Low
Low Off Set(2) High High Low
Functional pin description VNI8200XP
16/37 DocID15234 Rev 5
8 Functional pin description
8.1 SPI/parallel selection mode (SEL2)
This pin allows the selection of the IC interfacing mode. The SPI interface is selected if
SEL2 = H, while the parallel interface is selected if SEL2 = L, according to Table 13:
8.2 Serial data in (SDI)
If SEL2 = H, this pin is the input of the serial control frame. SDI is read on CLK rising edges
and, therefore, the microcontroller must change SDI state during the CLK falling edges.
After the SS falling edge, the SDI is equal to the most significant bit of the control frame
(Figure 3).
8.3 Serial data out (SDO)
If SEL2 = H, this pin is the output of the serial fault frame. SDO is updated on CLK falling
edges and, therefore, the microcontroller must read SDO state during the CLK rising edges.
The SDO pin is tri-stated when SS signal is high and it is equal to the most significant bit of
the fault frame after the SS falling edge (Figure 3).
Table 13. Pin description
Pin
Function
SEL2(1) = H
SPI operation
1. SEL2 has an internal weak pull-down.
SEL2 = L
Parallel operation
SDO/IN8 SDO Serial data output IN8 Input to channel 8
SS/IN7 SS Slave select IN7 Input to channel 7
CLK/IN6 CLK Serial clock IN6 Input to channel 6
SDI/IN5 SDI Serial data input IN5 Input to channel 5
WD/IN4 WD Watchdog input IN4 Input to channel 4
OUT_EN/IN3 OUT_EN IC OUTPUT enable /
disable IN3 Input to channel 3
WD_EN/IN2 WD_EN
Watchdog enable /
disable and timing
preset
IN2 Input to channel 2
SEL1/IN1 SEL1 8/16-bit SPI selection
mode IN1 Input to channel 1
DocID15234 Rev 5 17/37
VNI8200XP Functional pin description
8.4 Serial data clock (CLK)
If SEL2 = H, the CLK line is the input clock for serial data sampling. On CLK rising edge the
SDI input is sampled by the IC and the SDO output is sampled by the host microcontroller.
On CLK falling edge, both SDI and SDO lines are updated to the next bit of the frame, from
the most to the less significant one (see Figure 3). When the SS signal is high, slave not
selected, the microcontroller should drive the CLK low (the settings for the MCU SPI port
are CPHA = 0 and CPOL = 0).
8.5 Slave select (SS)
If SEL2 = H, the slave select (SS) signal is used to enable the VNI8200XP serial
communication shift register; data is flushed-in through the SDI pin and flushed-out from the
SDO pin only when the SS pin is low. On the SS pin falling edge the shift register (containing
the fault conditions) is frozen, so any change on the power switches status is latched until
the next SS falling edge event and the SDO output is enabled. On the SS pin rising edge
event the 8/16 bits present on the SPI shift register are evaluated and the outputs are driven
according to this frame. If more than 8/16 bits (depending on the SPI settings) are flushed
inside only the last 8/16 are evaluated; the others are flushed out from the SDO pin after
fault condition bits; in this way a proper communication is possible also in a daisy chain
configuration.
Figure 3. SPI mode diagram
8.6 8/16-bit selection (SEL1)
If SEL2 = H, SEL1 is used to select between two possible SPI configurations: the 8-bit SPI
mode (SEL1 = L) and the 16-bit SPI mode (SEL1 = H). 8/16-bit SPI operation is described
below.
CPHA=0
SCK
CPOL=0
SDO
SDI
Capture
Strobe
SS
Bit 1
Bit 1
Bit 2Bit 3
Bit 2
Bit 5
Bit 3
Bit 4
Bit 4
Bit 6
Bit 5
MSBit
Bit 6
LSBit
MSBit LSBit
AM11797v1
Functional pin description VNI8200XP
18/37 DocID15234 Rev 5
8.7 Output enable (OUT_EN)
If SEL2 = H, the OUT_EN pin provides a fast way to disable all the outputs simultaneously.
When the OUT_EN pin is driven low for at least TRES, the outputs are disabled while fault
conditions in the SPI register are latched. To enable the outputs it is then necessary to raise
the OUT_EN pin and re-program the IC through the SPI interface. As fault conditions are
latched inside the IC and SPI interface is working also while the OUT_EN pin is driven low,
it’s possible to use SPI to detect if a fault condition occurred before than the reset event.
The device is ready to operate normally after a TSU period. The OUT_EN pin is the fastest
way to disable all the outputs when a fault occurs.
Figure 4. Output channel enable/disable behavior
8.8 IC warning case temperature detection (TWARN)
The TWARN pin is an active low open drain output. This pin is activated if the IC case
temperature exceeds TCSD. According to the PCB thermal design and RthJC value, this
function allows a warning about a PCB overheating condition to be given.
The TWARN bit is also available through SPI. This bit is not latched: the TWARN pin is low
only while the case overtemperature condition is active (TC > TCSD) and is released when
this condition is removed (TC < TCR).
OUT_EN
Vin(
i)
OUT(i)
t
t
t
tOUT_EN
AM12824v1
DocID15234 Rev 5 19/37
VNI8200XP Functional pin description
8.9 Fault indication (FAULT)
The FAULT pin is an open drain active low fault indication pin. This pin is activated by one or
more of the following conditions:
•Channel overtemperature (OVT)
This pin is activated when at least one of the channels is in junction overtemperature.
Unlike the SPI fault detection bits, this signal is not latched: the FAULT pin is low only
when the fault condition is active and is released if the input driving signal is off or after
the OVT protection condition has been removed. This last event occurs if the channel
temperature decreases below the threshold level and the case temperature has not
exceeded TCSD or is below TCR. This means that the FAULT pin is low only while the
junction overtemperature is active (TJ >TTSD) and is released after this condition has
been removed (TJ < TR and TC < TCR).
•Parity check fail
When SPI mode is used (SEL2 = H), if a parity check fault of the incoming SPI frame is
detected or counted, CLK rising edges are different by a multiple of 8, the FAULT pin is
kept low. When counted CLK rising edges are a multiple of 8 and parity check is valid,
the FAULT pin is kept high.
8.10 Power Good (PG)
The PG terminal is an open drain, that indicates the status of the supply voltage. When VCC
supply voltage reaches the Vsth1 threshold, PG goes into a high impedance state. It goes
into a low impedance state when VCC falls below the Vsth2 threshold.
In 16-bit SPI mode, a PG bit is also available. This bit is set high when the Power Good
diagnostic is active, it is otherwise cleared.
Figure 5. Power Good diagnostic
9FF
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93*+ 93*+
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Functional pin description VNI8200XP
20/37 DocID15234 Rev 5
8.11 Programmable watchdog counter reset (WD)
If SEL2 = H, the VNI8200XP embeds a watchdog counter that must be erased, with a
negative pulse on the WD pin, before it expires. If the WD counter elapses, the VNI8200XP
goes into an internal RESET state where all the outputs are disabled; to restart normal
operation a negative pulse must be applied to the WD pin.
The watchdog enable/disable pin should be connected through an external divider to VREG
.
The watchdog time is fixed in the following Table 14:
Table 14. Programmable watchdog time
VWD_EN tWM
0.25 VREG > VWD_EN Disable
0.25 VREG ≤ VWD_EN < 0.5 VREG 40 ± 12% ms
0.5 VREG ≤ VWD_EN < 0.75 VREG 80 ± 12% ms
0.75 VREG ≤ VWD_EN = VREG 160 ± 12% ms
Figure 6. Watchdog reset
WD
t
WD
t
WM
t
AM11802v1
DocID15234 Rev 5 21/37
VNI8200XP SPI operation (SEL2 = H)
9 SPI operation (SEL2 = H)
9.1 8-bit SPI mode (SEL1 = L)
If SEL2 = H, the 8-bit SPI mode is based on an 8-bit command frame sent from the
microcontroller to the IC; each bit directly drives the corresponding output where LSB drives
output 0 and MSB drives output 7. Each bit, set to ‘1’, activates (closes) the corresponding
output.
At the same time, the IC transfers the channel fault conditions (OVT) to the microcontroller.
These fault conditions are latched at the occurrence and cleared after each communication
(each time the SS signal has a positive transition). Each bit, set to ‘1’, indicates an OVT
condition for the corresponding channel.
9.2 16-bit SPI mode (SEL1 = H)
The 16-bit SPI mode is based on a 16-bit command frame sent from the microcontroller to
the IC; the first 8 bits directly drive the output channels (each bit, set to ‘1’, activates the
corresponding output), the other 8 bits contain a 4-bit parity check code where the last bit
(the inversion of the previous one) is used to detect a communication error condition
(providing at least a transition in each frame):
P0 = IN0 ⊕ IN1 ⊕ IN2 ⊕ IN3 ⊕ IN4 ⊕ IN5 ⊕ IN6 ⊕ IN7
P1 = IN1 ⊕ IN3 ⊕ IN5 ⊕ IN7
P2 = IN0 ⊕ IN2 ⊕ IN4 ⊕ IN6
nP0 = NOT P0
At the same time, the IC transfers to the microcontroller a 16-bit fault frame where the first 8
bits indicate a channel fault (OVT) condition (each bit, set to ‘1’, indicates an OVT event),
the following 4 bits provide general fault condition information. FB_OK: this bit is related to
the DC-DC regulation: at the DC-DC turn-on, this bit is low and becomes high after FB rises
above 90% of the nominal VFB voltage and a correct SPI communication occurred. If the FB
Table 15. Command 8-bit frame (master to slave)
MSB LSB
IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0
Table 16. Fault 8-bit frame (slave to master)
MSB LSB
F7 F6 F5 F4 F3 F2 F1 F0
Table 17. Command 16-bit frame (master to slave)
MSB LSB
IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 - - - - P2 P1 P0 nP0
SPI operation (SEL2 = H) VNI8200XP
22/37 DocID15234 Rev 5
voltage falls below 80% of the nominal VFB voltage, this bit is zero; TWARN (IC warning
case temperature, see Section 8.8), PC (parity check fail, the bit, set to ‘1’, indicates a PC
fail or the length is not a multiple of 8) and PG (Power Good, see Section 8.10). The last 4
bits are used as parity check bits and communication error condition (see command 16 bit
frame):
P0 = F0 ⊕ F1 ⊕ F2 ⊕ F3 ⊕ F4 ⊕ F5 ⊕ F6 ⊕ F7
P1 = PC ⊕ FB_OK ⊕ F1 ⊕ F3 ⊕ F5 ⊕ F7
P2 = PG ⊕ TWARN ⊕ F0 ⊕ F2 ⊕ F4 ⊕ F6
nP0 = NOT P0
Channel indications are latched and cleared after a communication only.
Table 18. Fault 16-bit frame slave to master
MSB LSB
F7 F6 F5 F4 F3 F2 F1 F0 FB_OK TWARN PC PG P2 P1 P0 nP0
DocID15234 Rev 5 23/37
VNI8200XP LED driving array
10 LED driving array
The LED driving array carries out the status of the output channels (ON or OFF)
Figure 7. LED driving array
The following is an indication of how to choose the Rext resistor value.
Equation 1
Note: IF(LED) ≤ 7 mA.
Where (VCOL min.) and (VROW max.) can be found in Tab le 11 and VF(LED) and IF(LED)
depend on the electrical characteristics of the LEDs.
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VCOLmin
()VROWmax
()VFLED()
––
IFLED()
--------------------------------------------------------------------------------------------=
Step-down switching regulator VNI8200XP
24/37 DocID15234 Rev 5
11 Step-down switching regulator
The IC embeds a high efficiency 100 mA micropower step-down switching regulator. The
regulator is protected against short-circuit or overload conditions. Pulse-by-pulse current
limit regulation is obtained in normal operation through a current loop control.
A low ESR output capacitor connected to the VREG pin helps to limit the regulated voltage
ripple; a low ESR (less than 10 mΩ) capacitor is preferable. The control loop pin FB allows
3.3 V to be regulated, connecting it directly to VREG
, or 5 V connecting it through a voltage
divider Rl/Rfbl. The DC-DC converter can be turned off by connecting the feedback pin to
the DCVDD pin. In some applications it is possible to supply a 5 V or 3.3 V voltage
externally or, in the case of two or more VNI8200XPs inside the same board, it's possible to
configure the DC-DC converter on only one device and supply also the other ICs.
Note: if the DC-DC converter is adjusted to provide 3.3 V regulation and the Vdc_out is used to
power an external load and not the device, a 33 k
Ω
resistor has to be connected on
Vdc_out pin.
DocID15234 Rev 5 25/37
VNI8200XP Typical circuits and conventions
12 Typical circuits and conventions
Figure 8. Typical circuit for switching regulation VDC-out = 3.3 V
Vreg
Vreg
OPT_WD_EN
OPT_SDI
OPT_WD
OPT_CLK
OPT_OUT_EN
OPT_SS
Vreg
OPT_SDO
FB
OPT_SEL1
Vreg
FB
PHASE
PHASE
GND_Board
GND_Board
OPT_SEL1
OPT_WD_EN
OPT_OUT_EN
OPT_WD
OPT_CLK
OPT_SDI
OPT_SS
FAULT
TWARN
PGOOD
OPT_SDO
Vreg
low ESR< 10mohm MLCC
EXT_WD Vreg
Vreg
CH2
CH4
CH6
CH8
CH1
CH3
CH5
CH7
DC/DC ON
SDI
50ZL100MEFC8X11.5
PGOOD
TAB=Vcc
CLK
FAULT
TWARN
SS
low ESR MLCC
EARTH
SDO
DC/DC OFF
OUT1
OUT8
+
-
Vreg
C35
100pF/50V
TP2
1
R51 115R
C23
22nF/50V
R35 270R
R38 10k
L1
100uH/0.7R Is>700mA
C20
4.7pF/10V
LD2
LEDC-0603
2
1
R43 140R
LD5
LEDC-0603
2
1
D1
STPS1L60
21
C12
100pF/10V
TP6
1
C24
22nF/50V
CN1
VCC
1
2
R32 10k
C33
10nF/10V
TP5
1
R52 115R
LD10 LEDC-0603
2
1
STPSH100A
D2
2 1
R37 270R
LD4
LEDC-0603
2
1
22nF/50V
C26
JP8
5V
12
C9
4.7nF Y1 / 4kV
LD7
LEDC-0603
2
1
++
C7
100uF/50V
R45
1k47 1%
C13
100pF/10V
JP4
WD_EN
1
3
2
CN2
Ext_Vreg
1
2
R34 10k
JP2
OUT_EN
1
3
2
TRS1
TRISIL-BIDIR-SMC
C16
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STPS1L60A
D3
2
1
DC/DC
1
3
2
TP3
1
LD3
LEDC-0603
2
1
R36 10k
R40 100R
R39 270R
C31
4.7uF/10V
JP6
SEL2
1
2
C14
100pF/10V
1uF/50V
C10
R46 10k
C8
4.7nF Y1 / 4kV
CN3
CON8
1
2
3
4
5
6
7
8
C15
1uF/50V
470R
R53
R57
33k
22nF/50V
C18
JP5
SEL1
1
3
2
R31 270R
LD9 LEDC-0603
2
1
22nF/50V
C28
C17
3.3pF/10V
R56 8k
TP7
1
R41 100R
22nF/50V
C27
22nF/50V
C25
TP1
1
22nF/50V
C19
JP12
3V3
JP12
12
R48 10k
C22
100nF/10V
C34
10nF/10V
LD11 LEDC-0603
2
1
TP4
1
LD6
LEDC-0603
2
1
JP3
WD
13
2
R33 270R
JP11
GND_DISC
12
1
R47
C30
4.7pF/10V
R44
10k 1%
R54
470R
R55
470R
LD1
LEDC-0603
2
1
R42 100R
LD8
LEDC-0603
2
1
R50
2k37 1%
C21 22nF/50V
C32 10nF/10V
C29
4.7pF/10V
C11
100pF/10V
U7
VNI8200
SEL2
1
SEL1/IN1
2
WD_EN/IN2
3
OUT_EN/IN3
4
WD/IN4
5
SDI/IN5
6
CLK/IN6
7
SS/IN7
8
SDO/IN8
9
VREG
10
COL0
11
COL1
12
DCVDD
13
VREF
14
ROW0
15
ROW1
16
ROW2
17
ROW3
18
PG
19
FAULT
20
TWARN
21
FB
22
GND
23
PHASE
24
BOOT
25
NC#26
26
OUT8
27
OUT7
28
OUT6
29
OUT5
30
OUT4
31
OUT3
32
OUT2
33
OUT1
34
NC#36
35
NC#35
36
EP
37
R30 10k
R49 10k
10k
AM11799v1
Typical circuits and conventions VNI8200XP
26/37 DocID15234 Rev 5
Figure 9. Typical circuit for switching regulation VDC-out = 5 V
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DocID15234 Rev 5 27/37
VNI8200XP Typical circuits and conventions
Figure 10. SPI directional logic convention
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Thermal management VNI8200XP
28/37 DocID15234 Rev 5
13 Thermal management
The power dissipation in the IC is the main factor that sets the safe operating condition of
the device in the application. Therefore, it must be taken into account very carefully.
Heatsinking can be achieved using copper on the PCB with proper area and thickness. The
following image (Figure 11) shows the junction-to-ambient thermal impedance values for the
PSSO36 package.
Figure 11. PSSO36 thermal impedance vs. time
For instance, three cases have been considered using a PSSO36 packaged with copper
slug soldered on a 1.6 mm thickness FR4 board with dissipating footprint (copper thickness
of 70 μm):
•single layer PCB with just IC footprint dissipating area
•double layer PCB with footprint dissipating area on the top side and a 2 cm2 dissipating
layer on the bottom side through 15 via holes
•double layer PCB with footprint dissipating area on the top side and an 8 cm2
dissipating layer on the bottom side through 15 via holes.
DocID15234 Rev 5 29/37
VNI8200XP Thermal management
13.1 Thermal behavior
Figure 12. Thermal behavior
Note: 1 Thermal shutdown.
2 Junction hysteresis.
3 Restore to idle condition.
4 Case hysteresis.
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Interface timing diagram VNI8200XP
30/37 DocID15234 Rev 5
14 Interface timing diagram
Figure 13. Serial timing
15 Switching parameter test conditions
Figure 14. dV/dt(ON) and dV/dt(OFF) time diagram test conditions
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VNI8200XP Switching parameter test conditions
Figure 15. td(ON) and td(OFF) time diagram test conditions
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Package mechanical data VNI8200XP
32/37 DocID15234 Rev 5
16 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 19. PowerSSO-36 mechanical data
Symbol
mm
Min. Typ. Max.
A 2.15 2.47
A2 2.15 2.40
a1 0 0.075
b 0.18 0.36
c 0.23 0.32
D 10.10 10.50
E7.4 7.6
e0.5
e3 8.5
F2.3
G0.075
G1 0.06
H 10.1 10.5
h0.4
L 0.55 0.85
M4.3
N 10deg
O1.2
Q0.8
S2.9
T3.65
U1.0
X 4.1 4.7
Y 4.9 5.5
DocID15234 Rev 5 33/37
VNI8200XP Package mechanical data
Figure 16. PowerSSO-36 package dimensions
Figure 17. PowerSSO-36 tube shipment (no suffix)
Note: All dimensions are in mm.
Table 20. PowerSSO-36 tube shipment
Base Q.ty 49
Bulk Q.ty 1225
Tube length (± 0.5) 532
A 3.5
B 13.8
C (± 0.1) 0.6
Package mechanical data VNI8200XP
34/37 DocID15234 Rev 5
Figure 18. PowerSSO-36 reel shipment (suffix “TR”)
Table 21. PowerSSO-36 reel dimensions
Base Q.ty 1000
Bulk Q.ty 1000
A (max.) 330
B (min.) 1.5
C (± 0.2) 13
F 20.2
G (2 ± 0) 24.4
N (min.) 100
T (max.) 30.4
DocID15234 Rev 5 35/37
VNI8200XP Package mechanical data
Figure 19. PowerSSO-36 tape dimensions
Note: According to the Electronic Industries Association (EIA) standard 481 rev. A, Feb 1986.
Table 22. PowerSSO-36 tape dimensions
Tape width W 24
Tape hole spacing P0 (± 0.1) 4
Component spacing P 12
Hole diameter D (± 0.05) 1.55
Hole diameter D1 (min.) 1.5
Hole position F (± 0.1) 11.5
Compartment depth K (max.) 2.85
Hole spacing P1 (± 0.1) 2
Revision history VNI8200XP
36/37 DocID15234 Rev 5
17 Revision history
Table 23. Document revision history
Date Revision Changes
04-Dec-2008 1 Initial release
29-Apr-2009 2 Updated Table 5 on page 9
19-Jun-2012 3
Updated:
Features,Section 8.4,Section 8.7,Section 8.9,Section 8.10,
Section 11,Table 2,Table 3,Table 5,Tabl e 7,Table 8,Table 9,
Table 10,Table 11 ,Table 14,Figure 1,Figure 2.
Changed:
Figure 4,Figure 5,Figure 6,Figure 15,Figure 15.
Content reworked to improve the readability.
27-Jun-2012 4 Changed:
Symbols in 16-bit frame Section 9.2.
08-Mar-2013 5
Updated Table 5, Table 9 , Table 10, Table 14.
Updated footnote 2. in Table 4.
Updated Section 11.
Added Section 6.
Changed Figure 8 and Figure 9.
Added Table 12.
Changed product status to production data.
DocID15234 Rev 5 37/37
VNI8200XP
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