PWP RHB NT
1
FEATURES APPLICATIONS
DESCRIPTION
Delay
x0
12−BitGrayscale
PWMControl
DCRegister
GSRegister
DCEEPROM
ConstantCurrent
Driver
LEDOpenDetection
Temperature
ErrorFlag
(TEF)
Max.OUTn
Current
Delay
x1
12−BitGrayscale
PWMControl
DCRegister
GSRegister
DCEEPROM
ConstantCurrent
Driver
LEDOpenDetection
Delay
x15
6−BitDot
12−BitGrayscale
PWMControl
DCRegister
GSRegister
DCEEPROM
ConstantCurrent
Driver
LEDOpenDetection
OUT0
OUT1
OUT15
SOUT
SINSCLK
IREF
XERR
XLAT
GSCLK
BLANK
DCPRG
DCPRG
DCPRG
VPRG
VPRG
VPRG
GNDVCC
VPRG
Input
Shift
Register
Input
Shift
Register
VPRG 110
2312
191180
9590
116
5
VPRG
0
0
95
96
191
LEDOpen
Detection
(LOD)
5
9590
6 11
DCPRG
0
192
96
0
1
01 0
1
01
GSCounter CNT
CNT
CNT
CNT
96
96
Status
Information:
LOD,
TED,
DCDATA
192
0
191
1
0
0
1
VREF =1.24V
Correction
6−BitDot
Correction
6−BitDot
Correction
01
Blank
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007www.ti.com
16 CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL
•Monocolor, Multicolor, Full-Color LED Displays2
•16 Channels
•LED Signboards•12 bit (4096 Steps) Grayscale PWM Control
•Display Backlighting•Dot Correction
•General, High-Current LED Drive– 6 bit (64 Steps)– Storable in Integrated EEPROM•Drive Capability (Constant-Current Sink)
The TLC5940 is a 16-channel, constant-current sink– 0 mA to 60 mA (V
CC
< 3.6 V)
LED driver. Each channel has an individually– 0 mA to 120 mA (V
CC
> 3.6 V)
adjustable 4096-step grayscale PWM brightnesscontrol and a 64-step, constant-current sink (dot•LED Power Supply Voltage up to 17 V
correction). The dot correction adjusts the brightness•V
CC
= 3 V to 5.5 V
variations between LED channels and other LED•Serial Data Interface
drivers. The dot correction data is stored in anintegrated EEPROM. Both grayscale control and dot•Controlled In-Rush Current
correction are accessible via a serial interface. A•30MHz Data Transfer Rate
single external resistor sets the maximum current•CMOS Level I/O
value of all 16 channels.•Error Information
The TLC5940 features two error information circuits.– LOD: LED Open Detection
The LED open detection (LOD) indicates a broken ordisconnected LED at an output terminal. The thermal– TEF: Thermal Error Flag
error flag (TEF) indicates an overtemperaturecondition.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS.
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
A
PACKAGE
(1)
PART NUMBER
28-pin HTSSOP PowerPAD™ TLC5940PWP– 40 °C to 85 °C 32-pin 5mm x 5mm QFN TLC5940RHB28-pin PDIP TLC5940NT
(1) For the most current package and ordering information, see the Package Option Addendum at the endof this document, or see the TI website at www.ti.com .
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
I
Input voltage range
(2)
VCC – 0.3V to 6VI
O
Output current (dc) 130mAV
I
Input voltage range V
(BLANK)
, V
(DCPRG)
, V
(SCLK)
, V
(XLAT)
, V
(SIN)
, V
(GSCLK)
, V
(IREF)
– 0.3V to V
CC
+0.3VV
(SOUT)
, V
(XERR)
– 0.3V to V
CC
+0.3VV
O
Output voltage range
V
(OUT0)
to V
(OUT15)
– 0.3V to 18VEEPROM program range V
(VPRG)
– 0.3V to 24VEEPROM write cycles 50HBM (JEDEC JESD22-A114, Human Body Model) 2kVESD rating
CBM (JEDEC JESD22-C101, Charged Device Model) 500VT
stg
Storage temperature range – 55 °C to 150 °CT
A
Operating ambient temperature range – 40 °C to 85 °CHTSSOP (PWP)
(4)
31.58 °C/WPackage thermal impedance
(3)
QFN (RHB) 35.9 °C/WPDIP (NP) 48 °C/W
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.(3) The package thermal impedance is calculated in accordance with JESD 51-7.(4) With PowerPAD soldered on PCB with 2 oz. (56,7 grams) trace of copper. See SLMA002 for further information.
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RECOMMENDED OPERATING CONDITIONS
DISSIPATION RATINGS
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
MIN NOM MAX UNIT
DC CHARACTERISTICS
V
CC
Supply Voltage 3 5.5 VV
O
Voltage applied to output (OUT0 – OUT15) 17 VV
IH
High-level input voltage 0.8 V
CC
V
CC
VV
IL
Low-level input voltage GND 0.2 V
CC
VI
OH
High-level output current V
CC
= 5V at SOUT – 1 mAI
OL
Low-level output current V
CC
= 5V at SOUT, XERR 1 mAOUT0 to OUT15, V
CC
< 3.6V 60 mAI
OLC
Constant output current
OUT0 to OUT15, V
CC
> 3.6V 120 mAV
(VPRG)
EEPROM program voltage 20 22 23 VT
A
Operating free-air temperature range -40 85 °C
AC CHARACTERISTICS
V
CC
= 3 V to 5.5 V, T
A
= – 40 °C to 85 °C (unless otherwise noted)f
(SCLK)
Data shift clock frequency SCLK 30 MHzf
(GSCLK)
Grayscale clock frequency GSCLK 30 MHzt
wh0
/t
wl0
SCLK pulse duration SCLK = H/L (see Figure 11 ) 16 nst
wh1
/t
wl1
GSCLK pulse duration GSCLK = H/L (see Figure 11 ) 16 nst
wh2
XLAT pulse duration XLAT = H (see Figure 11 ) 20 nst
wh3
BLANK pulse duration BLANK = H (see Figure 11 ) 20 nst
su0
SIN to SCLK ↑
(1)
(see Figure 11 ) 5 nst
su1
SCLK ↓to XLAT ↑(see Figure 11 ) 10 nst
su2
VPRG ↑↓to SCLK ↑(see Figure 11 ) 10 nst
su3
Setup time VPRG ↑ ↓ XLAT ↑(see Figure 11 ) 10 nst
su4
BLANK ↓to GSCLK ↑(see Figure 11 ) 10 nst
su5
XLAT ↑to GSCLK ↑(see Figure 11 ) 30 nst
su6
VPRG ↑to DCPRG ↑(see Figure 16 ) 1 mst
h0
SCLK ↑to SIN (see Figure 11 ) 3 nst
h1
XLAT ↓to SCLK ↑(see Figure 11 ) 10 nst
h2
SCLK ↑to VPRG ↑↓(see Figure 11 ) 10 nsHold Timet
h3
XLAT ↓to VPRG ↑↓(see Figure 11 ) 10 nst
h4
GSCLK ↑to BLANK ↑(see Figure 11 ) 10 nst
h5
DCPRG ↓to VPRG ↓(see Figure 11 ) 1 mst
prog
Programming time for EEPROM (see Figure 16 ) 20 ms
(1) ↑and ↓indicates a rising edge, and a falling edge respectively.
POWER RATING DERATING FACTOR POWER RATING POWER RATINGPACKAGE
T
A
< 25 °C ABOVE T
A
= 25 °C T
A
= 70 °C T
A
= 85 °C
28-pin HTSSOP with
3958mW 31.67mW/C 2533mW 2058mWPowerPAD™
(1)
soldered28-pin HTSSOP with PowerPAD™ 2026mW 16.21mW/ °C 1296mW 1053mWunsoldered
32-pin QFN
(1)
3482mW 27.86mW/ °C 2228mW 1811mW28-pin PDIP 2456mW 19.65mW/ °C 1572mW 1277mW
(1) The PowerPAD is soldered to the PCB with a 2 oz. (56,7 grams) copper trace. See SLMA002 for further information.
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ELECTRICAL CHARACTERISTICS
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
V
CC
= 3 V to 5.5 V, T
A
= – 40 °C to 85 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High-level output voltage I
OH
= -1mA, SOUT V
CC
– 0.5 VV
OL
Low-level output voltage I
OL
= 1mA, SOUT 0.5 VV
I
= V
CC
or GND; BLANK, DCPRG, GSCLK, SCLK, SIN,
– 1 1XLAT
µAV
I
= GND; VPRG – 1 1I
I
Input current
V
I
= V
CC
; VPRG 50V
I
= 22V; VPRG; DCPRG = V
CC
4 10 mANo data transfer, all output OFF,
0.9 6V
O
= 1V, R
(IREF)
= 10k Ω
No data transfer, all output OFF,
5.2 12V
O
= 1V, R
(IREF)
= 1.3k ΩI
CC
Supply current mAData transfer 30MHz, all output ON,
16 25V
O
= 1V, R
(IREF)
= 1.3k Ω
Data transfer 30MHz, all output ON,
30 60V
O
= 1V, R
(IREF)
= 640 Ω
Constant sink current (seeI
O(LC)
All output ON, V
O
= 1V, R
(IREF)
= 640 Ω54 61 69 mAFigure 2 )
All output OFF, V
O
= 15V, R
(IREF)
= 640 Ω,I
lkg
Leakage output current 0.1 µAOUT0 to OUT15All output ON, V
O
= 1V, R
(IREF)
= 640 Ω,
1 ± 4OUT0 to OUT15, – 20 °C to 85 °CAll output ON, V
O
= 1V, R
(IREF)
= 640 Ω,
1 8OUT0 to OUT15
(1)Constant sink current errorΔI
O(LC0)
%(see Figure 2 )
All output ON, V
O
= 1V, R
(IREF)
= 320 Ω,
1 6OUT0 to OUT15, – 20 °C to 85 °CAll output ON, V
O
= 1V, R
(IREF)
= 320 Ω,
± 1 ± 8V
CC
= 4.5V to 5.5V, OUT0 to OUT15
(1)
– 2Constant sink current error Device to device, Averaged current from OUT0 toΔI
O(LC1)
4 %(see Figure 2 ) OUT15, R
(IREF)
= 1920 Ω(20mA)
(2)
+0.4
– 2.7Constant sink current error Device to device, Averaged current from OUT0 toΔI
O(LC2)
± 4 %(see Figure 2 ) OUT15, R
(IREF)
= 480 Ω(80mA)
(2)
+2All output ON, V
O
= 1V, R
(IREF)
= 640 Ω
1 ± 4 %/VOUT0 to OUT15, V
CC
= 3V to 5.5V
(3)
ΔI
O(LC3)
Line regulation (see Figure 2 )
All output ON, V
O
= 1V, R
(IREF)
= 320 Ω,
± 1 ± 6 %/VOUT0 to OUT15, V
CC
= 3V to 5.5V
(3)
All output ON, V
O
= 1V to 3V, R
(IREF)
= 640 Ω,
± 2 ± 6 %/VOUT0 to OUT15
(4)
ΔI
O(LC4)
Load regulation (see Figure 2 )
All output ON, V
O
= 1V to 3V, R
(IREF)
= 320 Ω,
2 8 %/VOUT0 to OUT15
(4)
T
(TEF)
Thermal error flag threshold Junction temperature
(5)
150 170 CV
(LED)
LED open detection threshold 0.3 0.4 VReference voltageV
(IREF)
R
(IREF)
= 640 Ω1.20 1.24 1.28 Voutput
(1) The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Table 1 .(2) The deviation of average of OUT1-15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Table 1 .The ideal current is calculated by Equation 3 in Table 1 .(3) The line regulation is calculated by Equation 4 in Table 1 .(4) The load regulation is calculated by Equation 5 in Table 1 .(5) Not tested. Specified by design
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100
I
II
(%)
150_OUTavg
150_OUTavgOUTn ´
-
=D
-
-
(1)
100
I
II
(%)
)IDEAL(OUT
)IDEAL(OUTOUTavg ´
-
=D
(2)
÷
÷
ø
ö
ç
ç
è
æ
´=
IREF
)IDEAL(OUT R
V24.1
5.31I
(3)
5.2
100
)V0.3VatI(
)V0.3VatI()V5.5VatI(
)V/(%
CCOUTn
CCOUTnCCOUTn ´
=
=-=
=D
(4)
0.2
100
)V0.1VatI(
)V0.1VatI()V0.3VatI(
)V/(%
OUTnOUTn
OUTnOUTnOUTnOUTn ´
=
=-=
=D
(5)
SWITCHING CHARACTERISTICS
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
Table 1. Test Parameter Equations
V
CC
= 3V to 5.5V, T
A
= -40 °C to 85 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
r0
SOUT 16Rise time nst
r1
OUTn, V
CC
= 5V, T
A
= 60 °C, DCn = 3Fh 10 30t
f0
SOUT 16Fall time nst
f1
OUTn, V
CC
= 5V, T
A
= 60 °C, DCn = 3Fh 10 30t
pd0
SCLK to SOUT (see Figure 11 ) 30 nst
pd1
BLANK to OUT0 60 nst
pd2
OUTn to XERR (see Figure 11 ) 1000 nsPropagation delay timet
pd3
GSCLK to OUT0 (see Figure 11 ) 60 nst
pd4
XLAT to I
OUT
(dot correction) (see Figure 11 ) 60 nst
pd5
DCPRG to OUT0 (see Figure 11 ) 30 nst
d
Output delay time OUTn to OUT(n+1) (see Figure 11 ) 20 30 nst
on-err
Output on-time error t
outon
– T
gsclk
(see Figure 11 ), GSn = 01h, GSCLK = 11 MHz 10 – 50 – 90 ns
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DEVICE INFORMATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
BLANK
XLAT
SCLK
SIN
VPRG
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VCC
IREF
DCPRG
GSCLK
SOUT
XERR
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
PWP PACKAGE
(TOP VIEW)
Thermal
PAD
THERMAL
PAD
GSCLK24 SOUT23 XERR22 OUT1521 OUT1420 OUT1319 OUT1218 OUT1117
OUT1016 OUT915 OUT814 NC13 NC12 OUT711 OUT610 OUT59
OUT4 8
OUT3 7
OUT2 6
OUT1 5
OUT0 4
VPRG 3
SIN 2
SCLK 1
DCPRG 25
IREF 26
VCC 27
NC 28
NC 29
GND 30
BLANK 31
XLAT 32
RHB PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
22
21
20
19
26
25
24
23
28
27
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
GND
VCC
IREF
DCPRG
GSCLK
SOUT
XERR
OUT15
SCLK
XLAT
BLANK
OUT0
VPRG
SIN
NT PACKAGE
(TOP VIEW)
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
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TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
TERMINAL FUNCTION
TERMINAL
NO. I/O DESCRIPTIONNAME
DIP PWP RHB
Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is alsoBLANK 23 2 31 I
reset. When BLANK = L, OUTn are controlled by grayscale PWM control.Switch DC data input. When DCPRG = L, DC is connected to EEPROM. When DCPRG = H,DC is connected to the DC register.DCPRG 19 26 25 I
DCPRG also controls EEPROM writing, when VPRG = V
(PRG)
. EEPROM data = 3Fh (default)GND 22 1 30 G GroundGSCLK 18 25 24 I Reference clock for grayscale PWM controlIREF 20 27 26 I Reference current terminal12, 13,NC – – No connection28, 29OUT0 28 7 4 O Constant current outputOUT1 1 8 5 O Constant current outputOUT2 2 9 6 O Constant current outputOUT3 3 10 7 O Constant current outputOUT4 4 11 8 O Constant current outputOUT5 5 12 9 O Constant current outputOUT6 6 13 10 O Constant current outputOUT7 7 14 11 O Constant current outputOUT8 8 15 14 O Constant current outputOUT9 9 16 15 O Constant current outputOUT10 10 17 16 O Constant current outputOUT11 11 18 17 O Constant current outputOUT12 12 19 18 O Constant current outputOUT13 13 20 19 O Constant current outputOUT14 14 21 20 O Constant current outputOUT15 15 22 21 O Constant current outputSCLK 25 4 1 I Serial data shift clockSIN 26 5 2 I Serial data inputSOUT 17 24 23 O Serial data outputVCC 21 28 27 I Power supply voltageMultifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = V
CC
, theVPRG 27 6 3 I device is in DC mode. When VPRG = V
(VPRG)
, DC register data can programmed into DCEEPROM with DCPRG=HIGH. EEPROM data = 3Fh (default)XERR 16 23 22 O Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected.Level triggered latch signal. When XLAT = high, the TLC5940 writes data from the input shiftXLAT 24 3 32 I register to either GS register (VPRG = low) or DC register (VPRG = high). When XLAT = low,the data in GS or DC register is held constant.
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PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
Resistor values are equivalent resistances, and they are not tested.
Figure 1. Input and Output Equivalent Circuits
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SOUT
OUTn
t ,t ,t
r0 f0 pd0 t ,t ,t ,t ,t ,t ,t ,t
r1 f1 pd1 pd2 pd3 pd4 pd5 d
VO=4V
Testpoint
C =15pF
L
Testpoint
R =51W
L
C =15pF
L
V =1V
O
OUTn
V =1Vto3V
O
OUTn
IREF
R470kΩ
(IREG)
Testpoint
V(IREF)
VCC
XERR
tpd3
I , I , I , I , I
O(LC) O(LC0) O(LC1) O(LC2) O(LC3)
DDDD
DIO(LC4)
=640W
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 2. Parameter Measurement Circuits
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TYPICAL CHARACTERISTICS
100
1k
10k
I − OutputCurrent − mA
O
0 20 60 100
ReferenceResistor,R -
(IREF)W
40 80 120
7.68kΩ
1.92kΩ
0.96kΩ
0.64kΩ
0.38kΩ
0.32kΩ
0.48kΩ
0
1k
3k
4k
2k
T − Free-AirTemperature − C
A
o
0-20 20 100
PowerDissipationRate-mW
-40 80
6040
TLC5940PWP
PowerPADSoldered
TLC5940PWP
PowerPADUnsoldered
TLC5940RHB
TLC5940NT
0
20
40
60
80
100
120
140
0 0.5 1 1.5 2 2.5 3
V -OutputVoltage-V
O
I -OutputCurrent-mA
O
T =25 C,
V =5V
A
CC
°I =120mA
O
I =100mA
O
I =80mA
O
I =60mA
O
I =40mA
O
I =20mA
O
I =5mA
O
55
56
57
58
59
60
61
62
63
64
65
0 0.5 1 1.5 2 2.5 3
V -OutputVoltage-V
O
I-OutputCurrent-mA
O
I =60mA,
V =5V
O
CC T =85 C
A
°
T =-40 C
A
°
T =25 C
A
°
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
REFERENCE RESISTOR POWER DISSIPATION RATEvs vsOUTPUT CURRENT FREE-AIR TEMPERATURE
Figure 3. Figure 4.
OUTPUT CURRENT OUTPUT CURRENTvs vsOUTPUT VOLTAGE OUTPUT VOLTAGE
Figure 5. Figure 6.
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-8
-6
-4
-2
0
2
4
6
8
0 20 40 60 80
I -OutputCurrent-mA
O
Δ I -ConstantOutputCurrent-%
OLC
T =25 C,
V =5V
A
CC
°
-8
-6
-4
-2
0
2
4
6
8
-40 -20 0 20 40 60 80 100
T - AmbientTemperature- C
A
°
Δ I -ConstantOutputCurrent-%
OLC
V =3.3V
CC
V =5V
CC
I =60mA
O
0
20
40
60
80
100
120
140
0 10 20 30 40 50 60 70
DotCorrectionData-dec
I -OutputCurrent-mA
O
I =5mA
O
I =60mA
O
I =80mA
O
I =120mA
O
I =30mA
O
T =25 C,
V =5V
A
CC
°
0
10
20
30
40
50
60
70
0 10 20 30 40 50 60 70
DotCorrectionData-dec
I -OutputCurrent-mA
O
T =-40 C
A
°
T =25 C
A
°
T =85 C
A
°
I =60mA,
V =5V
O
CC
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
CONSTANT OUTPUT CURRENT, ΔI
OLC
CONSTANT OUTPUT CURRENT, ΔI
OLCvs vsAMBIENT TEMPERATURE OUTPUT CURRENT
Figure 7. Figure 8.
OUTPUT CURRENT OUTPUT CURRENTvs vsDOT CORRECTION LINEARITY (ABS VALUE) DOT CORRECTION LINEARITY (ABS VALUE)
Figure 9. Figure 10.
Copyright © 2004 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 11
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PRINCIPLES OF OPERATION
SERIAL INTERFACE
VPRG
XLAT
SIN
SCLK
SOUT
BLANK
GSCLK
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
196
DC
MSB DC
LSB
DC
MSB
1 192 193 1192 193 1
1 4096
tsu4
th4
twh3
1
GS1
MSB GS1
LSB
GS1
MSB GS2
MSB
GS2
LSB
GS2
MSB
SID2
MSB
SID2
MSB-1
SID1
MSB
SID1
MSB-1
SID1
LSB
GS3
MSB
- --
twh2
tsu2 tsu1 twh0
twl0
tsu0 th0
tpd0
tpd1
t +t
pd1 d
t +15xt
pd1 d
tpd3
td
15xtd
tpd2
t +t
pd3 d
tpd3
tpd4
twl1
twh1
DCDataInputMode GSDataInputMode
1stGSDataInputCycle 2ndGSDataInputCycle
1stGSDataOutputCycle 2ndGSDataOutputCycle
tsu3
th3
th2 th1
tsu5
Tgsclk
touton
SIN SOUT
SIN(a) SOUT(b)
TLC5940(a)
GSCLK,
BLANK,
SIN SOUT
TLC5940(b)
SCLK,XLAT,
VPRG
DCPRG,
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
The TLC5940 has a flexible serial interface, which can be connected to microcontrollers or digital signalprocessors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signalshifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of XLATsignal latches the serial data to the internal registers. The internal registers are level-triggered latches of XLATsignal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending on theprogramming mode. Grayscale data and dot correction data can be entered during a grayscale cycle. Althoughnew grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the grayscaledata at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the existinggrayscale data. Figure 11 shows the timing chart. More than two TLC5940s can be connected in series byconnecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading twoTLC5940s is shown in Figure 12 and the timing chart is shown in Figure 13 . The SOUT pin can also beconnected to the controller to receive status information from TLC5940 as shown in Figure 22 .
Figure 11. Serial Data Input Timing Chart
Figure 12. Cascading Two TLC5940 Devices
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VPRG
XLAT
SIN(a)
SCLK
SOUT(b)
BLANK
GSCLK
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
1
192X2
DCb
MSB
DCa
LSB
DCb
MSB
1 384 385 1384 385 1
14096 1
GSb1
MSB
GSa1
LSB
GSb1
MSB
GSb2
MSB
GSa2
LSB
GSb2
MSB
SIDb2
MSB
SIDb2
MSB
-1
SIDb1
MSB
SIDb1
MSB-1
SIDa1
LSB
GSb3
MSB
- --
192
96X2
ERROR INFORMATION OUTPUT
TEF: THERMAL ERROR FLAG
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
Figure 13. Timing Chart for Two Cascaded TLC5940 Devices
The open-drain output XERR is used to report both of the TLC5940 error flags, TEF and LOD. During normaloperating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR ispulled up to V
CC
through an external pullup resistor. If TEF or LOD is detected, the internal transistor is turnedon, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together andpulled up to V
CC
with a single pullup resistor. This reduces the number of signals needed to report a system error(see Figure 22 ).
To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.
Table 2. XERR Truth Table
ERROR CONDITION ERROR INFORMATION SIGNALS
TEMPERATURE OUTn VOLTAGE TEF LOD BLANK XERR
T
J
< T
(TEF)
Don't Care L X HHT
J
> T
(TEF)
Don't Care H X LOUTn > V
(LED)
L L HT
J
< T
(TEF)
OUTn < V
(LED)
L H LLOUTn > V
(LED)
H L LT
J
> T
(TEF)
OUTn < V
(LED)
H H L
The TLC5940 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. Ifthe junction temperature exceeds the threshold temperature (160C typical), TEF becomes H and XERR pin goesto low level. When the junction temperature becomes lower than the threshold temperature, TEF becomes L andXERR pin becomes high impedance. TEF status can also be read out from the TLC5940 status register.
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LOD: LED OPEN DETECTION
DELAY BETWEEN OUTPUTS
OUTPUT ENABLE
SETTING MAXIMUM CHANNEL CURRENT
Imax +
V(IREF)
R(IREF) 31.5
(6)
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
The TLC5940 has an LED-open detector that detects broken or disconnected LEDs. The LED open detectorpulls the XERR pin to GND when an open LED is detected. XERR and the corresponding error bit in the StatusInformation Data is only active under the following open-LED conditions.1. OUTn is on and the time tpd2 (1 µs typical) has passed.2. The voltage of OUTn is < 0.3V (typical)
The LOD status of each output can be also read out from the SOUT pin. See STATUS INFORMATION OUTPUTsection for details. The LOD error bits are latched into the Status Information Data when XLAT returns to a lowafter a high. Therefore, the XLAT pin must be pulsed high then low while XERR is active in order to latch theLOD error into the Status Information Data for subsequent reading via the serial shift register.
The TLC5940 has graduated delay circuits between outputs. These circuits can be found in the constant currentdriver block of the device (see the functional block diagram). The fixed-delay time is 20ns (typical), OUT0 has nodelay, OUT1 has 20ns delay, and OUT2 has 40ns delay, etc. The maximum delay is 300ns from OUT0 toOUT15. The delay works during switch on and switch off of each output channel. These delays prevent largeinrush currents which reduces the bypass capacitors when the outputs turn on.
All OUTn channels of the TLC5940 can be switched off with one signal. When BLANK is set high, all OUTnchannels are disabled, regardless of logic operations of the device. The grayscale counter is also reset. WhenBLANK is set low, all OUTn channels work under normal conditions. If BLANK goes low and then back highagain in less than 300ns, all outputs programmed to turn on still turn on for either the programmed number ofgrayscale clocks, or the length of time that the BLANK signal was low, which ever is lower. For example, if alloutputs are programmed to turn on for 1ms, but the BLANK signal is only low for 200ns, all outputs still turn onfor 200ns, even though some outputs are turning on after the BLANK signal has already gone high.
Table 3. BLANK Signal Truth Table
BLANK OUT0 - OUT15
LOW Normal conditionHIGH Disabled
The maximum output current per channel is programmed by a single resistor, R
(IREF)
, which is placed betweenIREF pin and GND pin. The voltage on IREF is set by an internal band gap V
(IREF)
with a typical value of1.24V. The maximum channel current is equivalent to the current flowing through R
(IREF)
multiplied by a factor of31.5. The maximum output current per channel can be calculated by Equation 6 :
where:
V
(IREF)
= 1.24 VR
(IREF)
= User-selected external resistor.
I
max
must be set between 5 mA and 120 mA. The output current may be unstable if I
max
is set lower than 5 mA.Output currents lower than 5 mA can be achieved by setting Imax to 5 mA or higher and then using dotcorrection.
Figure 3 shows the maximum output current I
O
versus R
(IREF)
. R
(IREF)
is the value of the resistor between IREFterminal to GND, and I
O
is the constant output current of OUT0 to OUT15. A variable power supply may beconnected to the IREF pin through a resistor to change the maximum output current per channel. The maximumoutput current per channel is 31.5 times the current flowing out of the IREF pin.
14 Submit Documentation Feedback Copyright © 2004 – 2007, Texas Instruments Incorporated
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POWER DISSIPATION CALCULATION
P =V xI +
D CC CC V xI
OUT MAX x
DCn
63
xdPWM xN
(
()
)
(7)
OPERATING MODES
SETTING DOT CORRECTION
IOUTn +Imax DCn
63
(8)
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
The device power dissipation must be below the power dissipation rating of the device package to ensure correctoperation. Equation 7 calculates the power dissipation of device:
where:
V
CC
: device supply voltageI
CC
: device supply currentV
OUT
: TLC5940 OUTn voltage when driving LED currentI
MAX
: LED current adjusted by R
(IREF)
ResistorDC
n
: maximum dot correction value for OUTnN: number of OUTn driving LED at the same timed
PWM
: duty cycle defined by BLANK pin or GS PWM value
The TLC5940 has operating modes depending on the signals DCPRG and VPRG. Table 4 shows the availableoperating modes. The TPS5940 GS operating mode (see Figure 11 ) and shift register values are not definedafter power up. One solution to solve this is to set dot correction data after TLS5940 power-up and switch backto GS PWM mode. The other solution is to overflow the input shift register with 193 bits of dummy data and latchit while TLS540 is in GS PWM mode. The values in the input shift register, DC register and GS register areunknown just after power on. The DC and GS register values should be properly stored through the serialinterface before starting the operation.
Table 4. TLC5940 Operating Modes Truth Table
SIGNAL
INPUT SHIFT REGISTER MODE DC VALUEDCPRG VPRG
L EEPROMGND 192 bit Grayscale PWM ModeH DC RegisterL EEPROMV
CC
96 bit Dot Correction Data Input ModeH DC RegisterL EEPROMV
(VPRG)
X EEPROM Programming ModeH Write dc register value to EEPROM. (Defaultdata: 3Fh)
The TLC5940 has the capability to fine adjust the output current of each channel OUT0 to OUT15 independently.This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected tothe output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. Thechannel output can be adjusted in 64 steps from 0% to 100% of the maximum output current I
max
. Dot correctionfor all channels must be entered at the same time. Equation 8 determines the output current for each output n:
where:
I
max
= the maximum programmable output current for each output.DCn = the programmed dot correction value for output n (DCn = 0 to 63).n = 0 to 15
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DC0.0
0
DC1.0
6
DC15.0
90
DC15.5
95
DC0.5
5
DC14.5
89
MSB LSB
DCOUT15 DCOUT0
DCOUT14 − DCOUT2
tsu1
DCn
MSB
DCn
MSB−1
DCn
MSB−2
DCn
LSB+1
DCn
LSB
DCn
MSB
DCn+1
MSB
DCn+1
MSB−1
DCn
MSB−1
DCn
MSB−2
DCn−1
LSB
DCn−1
LSB+1
DCn−1
MSB
DCn−1
MSB−1
DCn−1
MSB−2
1 2 3 95 96 1 2
SCLK
SOUT
SIN
VPRG
XLAT
DCModeData
InputCyclen DCModeData
InputCyclen+1
VCC
twh0
twl0
DCn−1
LSB
twh2
th1
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
Figure 14 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. Theformat is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc. The DC15.5 in Figure 14 stands for the 5
th
most significant bit for output 15.
Figure 14. Dot Correction Data Packet Format
When VPRG is set to VCC, the TLC5940 enters the dot correction data input mode. The length of input shiftregister becomes 96 bits. After all serial data are shifted in, the TLC5940 writes the data in the input shift registerto DC register when XLAT is high, and holds the data in the DC register when XLAT is low. The DC register is alevel triggered latch of XLAT signal. Since XLAT is a level-triggered signal, SCLK and SIN must not be changedwhile XLAT is high. After XLAT goes low, data in the DC register is latched and does not change. BLANK signaldoes not need to be high to latch in new data. XLAT has setup time (tsu1) and hold time (th1) to SCLK as shownin Figure 15 .
Figure 15. Dot Correction Data Input Timing Chart
The TLC5940 also has an EEPROM to store dot correction data. To store data from the dot correction register toEEPROM, DCPRG is set to high after applying V
PRG
to the VPRG pin. Figure 16 shows the EEPROMprogramming timings. The EEPROM has a default value of all 1s.
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VPRG
DCPRG
XLAT
SIN
SCLK
SOUT
196
DC
MSB
-
DC
MSB DC
LSB
VCC
V(PRG)
tsu6 tprog th5
DCPRG
OUT0
(Current)
tpd5 tpd5
OUT15
(Current)
SETTING GRAYSCALE
Brightness in % +GSn
4095 100
(9)
GS0.0
0
GS1.0
12
GS15.0
180
GS15.11
191
GS0.11
11
GS14.11
179
MSB LSB
GSOUT15 GSOUT0GSOUT14 − GSOUT2
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
Figure 16. EEPROM Programming Timing Chart
Figure 17. DCPRG and OUTn Timing Diagram
The TLC5940 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12 bitsper channel results in 4096 different brightness steps, respective 0% to 100% brightness. Equation 9 determinesthe brightness level for each output n:
where:
GSn = the programmed grayscale value for output n (GSn = 0 to 4095)n = 0 to 15Grayscale data for all OUTn
Figure 18 shows the grayscale data packet format which consists of 12 bits x 16 channels, totaling 192 bits. Theformat is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc.
Figure 18. Grayscale Data Packet Format
When VPRG is set to GND, the TLC5940 enters the grayscale data input mode. The device switches the inputshift register to 192-bit width. After all data is clocked in, a rising edge of the XLAT signal latches the data into
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STATUS INFORMATION OUTPUT
LOD15 DC15.5 DC0.0 X
XX
023
LODData DCValues Reserved
MSB LSB
119 120
24
TEF
LOD0 TEF
16
X
15 191
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
the grayscale register (see Figure 11 ). New grayscale data immediately becomes valid at the rising edge of theXLAT signal; therefore, new grayscale data should be latched at the end of a grayscale cycle when BLANK ishigh.The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal tocomplete the grayscale update cycle. All GS data in the input shift register is replaced with status informationdata (SID) after updated the grayscale register.
The TLC5940 does have a status information register, which can be accessed in grayscale mode (VPRG=GND).After the XLAT signal latches the data into the GS register the input shift register data will be replaced with statusinformation data (SID) of the device (see Figure 18 ). LOD, TEF, and dot correction EEPROM data(DCPRG=LOW) or dot correction register data (DCPRG=HIGH) can be read out at SOUT pin. The statusinformation data packet is 192 bits wide. Bits 0-15 contain the LOD status of each channel. Bit 16 contains theTEF status. If DCPRG is low, bits 24-119 contain the data of the dot-correction EEPROM. If DCPRG is high, bits24-119 contain the data of the dot-correction register.The remaining bits are reserved. The complete statusinformation data packet is shown in Figure 19 .
SOUT outputs the MSB of the SID at the same time the SID are stored in the SID register, as shown Figure 20 .The next SCLK pulse, which will be the clock for receiving the SMB of the next grayscale data, transmits MSB-1of SID. If output voltage is < 0.3 V (typical) when the output sink current turns on, LOD status flage becomesactive. The LOD status flag is an internal signal that pulls XERR pin down to low when the LOD status flagbecomes active. The delay time, tpd2 (1 µs maximum), is from the time of turning on the output sink current tothe time LOD status flage becomes valid. The timing for each channel's LOD status to become valid is shifted bythe 30-ns (maximum) channel-to-channel turn-on time. After the first GSCLK goes high, OUT0 LOD status isvalid; tpd3 + tpd2 = 60 ns + 1 µs. OUT1 LOD status is valid; tpd3 + td + tpd2 = 60 ns + 30 ns + 1 µs = 1.09 µs.OUT2 LOD status is valid; tpd3 + 2*td + tpd2 = 1.12 µs, and so on. It takes 1.51 µs maximum (tpd3 + 15*td +tpd2) from the first GSCLK rising edge until all LOD become valid; tsuLOD must be > 1.51 µs (see Figure 20 ) toensure that all LOD data are valid.
Figure 19. Status Information Data Packet Format
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VPRG
XLAT
SIN
SCLK
SOUT
BLANK
GSCLK
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
1 192 193 1192
14096
GS1
MSB
GS1
LSB
GS1
MSB
GS2
MSB
GS2
LSB
GS2
MSB
SID1
MSB
SID1
MSB-1
SID1
LSB
- -
t +15xt +t
pd3 d pd2
tpd3
td
15xtd
tpd2
GSDataInputMode
1stGSDataInputCycle 2ndGSDataInputCycle
(1stGSDataOutputCycle)
tsuLOD
>tpd4+15xtd+tpd3
GRAYSCALE PWM OPERATION
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
Figure 20. Readout Status Information Data (SID) Timing Chart
The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK goes lowincreases the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each followingrising edge of GSCLK increases the grayscale counter by one. The TLC5940 compares the grayscale value ofeach output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the counter valuesare switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero andcompletes the grayscale PWM cycle (see Figure 21 ). When the counter reaches a count of FFFh, the counterstops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh immediately resetsthe counter to zero.
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GSCLK
BLANK
GSPWM
Cyclen
1 2 3 1
GSPWM
Cyclen+1
OUT0
OUT1
OUT15
XERR
nxt d
tpd1
tpd1 +td
tpd1 +15xtd
tpd2
tpd3
twh1
twl1
twl1 tpd3
4096
th4 twh3
tpd3+nxt d
tsu4
(Current)
(Current)
(Current)
SERIAL DATA TRANSFER RATE
f(GSCLK) +4096 f(update)
f(SCLK) +193 f(update) n
(10)
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
Figure 21. Grayscale PWM Cycle Timing Chart
Figure 22 shows a cascading connection of nTLC5940 devices connected to a controller, building a basicmodule of an LED display system. The maximum number of cascading TLC5940 devices depends on theapplication system and is in the range of 40 devices. Equation 10 calculates the minimum frequency needed:
where:
f
(GSCLK)
: minimum frequency needed for GSCLKf
(SCLK)
: minimum frequency needed for SCLK and SINf
(update)
: update rate of whole cascading systemn: number cascaded of TLC5940 device
20 Submit Documentation Feedback Copyright © 2004 – 2007, Texas Instruments Incorporated
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APPLICATION EXAMPLE
TLC5940
SIN SOUT
OUT0 OUT15
SCLK
GSCLK
XLAT
VPRG
BLANK
IREF
XERR
DCPRG
TLC5940
SIN SOUT
OUT0 OUT15
SCLK
GSCLK
XLAT
VPRG
BLANK
IREF
XERR
DCPRG
IC 0 IC n
7
SIN
SCLK
GSCLK
XLAT
BLANK
XERR
DCPRG
Controller
SOUT
VPRG_D
VPRG_OE
W_EEPROM
100 k
50 k
50 k
50 k
50 k
50 k
50 k
VPRG
100 nF
V(LED)
V(LED)
V(LED)
V(LED)
VCC
100 nF
V(22V)
V(22V)
VCC VCC
TLC5940
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
Figure 22. Cascading Devices
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PACKAGE OPTION ADDENDUM
www.ti.com 25-Nov-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC5940NT ACTIVE PDIP NT 28 13 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
TLC5940NTG4 ACTIVE PDIP NT 28 13 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
TLC5940PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TLC5940PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TLC5940PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TLC5940PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TLC5940RHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TLC5940RHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Nov-2010
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC5940 :
•Enhanced Product: TLC5940-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC5940PWPR HTSSOP PWP 28 2000 330.0 16.4 7.1 10.4 1.6 12.0 16.0 Q1
TLC5940RHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC5940PWPR HTSSOP PWP 28 2000 367.0 367.0 38.0
TLC5940RHBR QFN RHB 32 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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