Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 TPA3110D2-Q1 15-W Filter-Free Stereo Class-D Audio Power Amplifier With SpeakerGuardTM 1 Features 3 Description * * The TPA3110D2-Q1 is a 15-W (per channel) efficient, Class-D audio power amplifier for driving bridged-tied stereo speakers. Advanced EMI suppression technology enables the use of inexpensive ferrite bead filters at the outputs while meeting EMC requirements. SpeakerGuard protection circuitry includes an adjustable power limiter and a DC detection circuit. The adjustable power limiter allows the user to set a virtual voltage rail lower than the chip supply to limit the amount of current through the speaker. The DC detect circuit measures the frequency and amplitude of the PWM signal and shuts off the output stage if the input capacitors are damaged or shorts exist on the inputs. 1 * * * * * * * * * * * * Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: - Device Temperature Grade 1: -40C to 125C Ambient Operating Temperature Range - Device HBM ESD Classification Level H2 - Device CDM ESD Classification Level C2 15-W/ch Into 8- Loads at 10% THD+N From a 16-V Supply 10-W/ch Into 8- Loads at 10% THD+N From a 13-V Supply 30-W Into a 4- Mono Load at 10% THD+N From a 16-V Supply 90% Efficient Class-D Operation Eliminates Need for Heat Sinks Wide Supply Voltage Range Allows Operation from 8 V to 26 V Filter-Free Operation SpeakerGuardTM Protection Circuitry Includes Adjustable Power Limiter Plus DC Protection Flow Through Pin Out Facilitates Easy Board Layout Robust Pin-to-Pin Short-Circuit Protection and Thermal Protection with Auto Recovery Option Excellent THD+N and Pop-Free Performance Four Selectable Fixed Gain Settings Differential Inputs The TPA3110D2-Q1 can drive stereo speakers as low as 4 . The high efficiency of the device, 90%, eliminates the need for an external heat sink when playing music. The outputs are also fully protected against shorts to GND, VCC, and output-to-output. The short-circuit protection and thermal protection includes an autorecovery feature. Device Information(1) PART NUMBER TPA3110D2-Q1 PACKAGE BODY SIZE (NOM) HTSSOP (28) 9.70 mm x 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. TPA3110D2-Q1 Simplified Application Schematic 1mF 2 Applications * * * * * * Automotive Noise Generation for HEV/EV Automotive Emergency Call Systems (eCall) Automotive Infotainment Systems (i.e. Head Unit, Connectivity Gateway, Cluster, Telematics, Navigation) ADAS Noise Generation for Blind Spot Detection, Security and Alarm Systems Professional Audio Equipment (Performance Amplifiers, Premium Microphones) Aerospace and Aviation Audio Systems Audio Source OUTL+ LINP OUTL- LINN OUTR+ RINP OUTR- RINN TPA3110D2-Q1 OUTPL OUTNL FERRITE BEAD FILTER 15W 8W FERRITE BEAD FILTER 15W 8W GAIN0 GAIN1 OUTPR OUTNR PLIMIT PBTL Fault SD PVCC 8 to 26V 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 4 4 4 5 5 5 6 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions...................... Thermal Information .................................................. DC Characteristics .................................................... DC Characteristics .................................................... AC Characteristics .................................................... AC Characteristics .................................................... Typical Characteristics ............................................. Detailed Description ............................................ 13 7.1 Overview ................................................................. 13 7.2 Functional Block Diagram ....................................... 14 7.3 Feature Description................................................. 14 7.4 Device Functional Modes........................................ 15 8 Application and Implementation ........................ 18 8.1 Application Information............................................ 18 8.2 Typical Application .................................................. 18 9 Power Supply Recommendations...................... 25 10 Layout................................................................... 26 10.1 Layout Guidelines ................................................. 26 10.2 Layout Example .................................................... 27 11 Device and Documentation Support ................. 28 11.1 11.2 11.3 11.4 11.5 11.6 Device Support .................................................... Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 28 28 28 28 28 28 12 Mechanical, Packaging, and Orderable Information ........................................................... 28 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2012) to Revision B * Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1 Changes from Original (September, 2012) to Revision A * 2 Page Page Changed TA from 25C to -40C to 125C in DC and AC Characteristics tables.................................................................. 5 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 5 Pin Configuration and Functions PWP Package 28-Pin HTSSOP With PowerPADTM IC Package Top View SD FAULT 1 28 2 27 LINP LINN GAIN0 GAIN1 3 26 4 25 AVCC AGND GVDD PLIMIT RINN RINP NC PBTL 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 PVCCL PVCCL BSPL OUTPL PGND OUTNL BSNL BSNR OUTNR PGND OUTPR BSPR PVCCR PVCCR Pin Functions PIN NO. NAME TYPE DESCRIPTION 1 SD I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled), TTL logic levels with compliance to AVCC. 2 FAULT O Open drain output used to display short circuit or DC detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both short circuit faults and DC detect faults must be reset by cycling PVCC. 3 LINP I Positive audio input for left channel, biased at 3 V. 4 LINN I Negative audio input for left channel, biased at 3 V. 5 GAIN0 I Gain select least significant bit, TTL logic levels with compliance to AVCC. 6 GAIN1 I Gain select most significant bit, TTL logic levels with compliance to AVCC. 7 AVCC P Analog supply 8 AGND -- Analog signal ground, connect to the thermal pad. 9 GVDD O High-side FET gate drive supply. The nominal voltage is 7 V. GVDD should also be used as a supply for the PLIMIT function. 10 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit. 11 RINN I Negative audio input for right channel, biased at 3 V. 12 RINP I Positive audio input for right channel, biased at 3 V. 13 NC -- 14 PBTL I Parallel BTL mode switch 15 PVCCR P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally. 16 PVCCR P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally. Not connected 17 BSPR I Bootstrap I/O for right channel, positive high-side FET 18 OUTPR O Class-D H-bridge positive output for right channel 19 PGND -- Power ground for the H-bridges 20 OUTNR O Class-D H-bridge negative output for right channel 21 BSNR I Bootstrap I/O for right channel, negative high-side FET 22 BSNL I Bootstrap I/O for left channel, negative high-side FET 23 OUTNL O Class-D H-bridge negative output for left channel 24 PGND -- Power ground for the H-bridges 25 OUTPL O Class-D H-bridge positive output for left channel 26 BSPL I Bootstrap I/O for left channel, positive high-side FET Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 3 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Pin Functions (continued) PIN TYPE DESCRIPTION NO. NAME 27 PVCCL P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally. 28 PVCCL P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage AVCC, PVCC SD, GAIN0, GAIN1, PBTL, FAULT (2) Interface pin voltage VI Minimum load resistance RL MIN MAX UNIT -0.3 30 V -0.3 VCC + 0.3 V < 10 V/ms PLIMIT -0.3 GVDD + 0.3 V RINN, RINP, LINN, LINP -0.3 6.3 V BTL: PVCC > 15 V 4.8 BTL: PVCC 15 V 3.2 PBTL 3.2 Continuous total power dissipation See the Thermal Information Table TA Operating free-air temperature -40 125 C TJ Operating junction temperature (3) -40 150 C Tstg Storage temperature -65 150 C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-k resistor in series with the pins, per application note SLUA626. The TPA3110D2-Q1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Brief SLMA002 for more information about using the TSSOP thermal pad. 6.2 ESD Ratings VALUE V(ESD) (1) 6.3 Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) 4000 Charged-device model (CDM), per AEC Q100-011 250 Machine Model (MM) per JESD22-A115 200 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX 26 UNIT VCC Supply voltage PVCC, AVCC 8 VIH High-level input voltage SD, GAIN0, GAIN1, PBTL 2 VIL Low-level input voltage SD, GAIN0, GAIN1, PBTL 0.8 VOL Low-level output voltage FAULT, RPULL-UP = 100k, VCC = 26 V 0.8 V IIH High-level input current SD, GAIN0, GAIN1, PBTL, VI = 2 V, VCC = 18 V 50 A IIL Low-level input current SD, GAIN0, GAIN1, PBTL, VI = 0.8 V, VCC = 18 V 5 A TA Operating free-air temperature 125 C 4 -40 Submit Documentation Feedback V V V Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 6.4 Thermal Information TPA3110D2-Q1 THERMAL METRIC (1) (2) PWP (HTSSOP) UNIT 28 Pins JA Junction-to-ambient thermal resistance 30.3 C/W JCtop Junction-to-case (top) thermal resistance 33.5 C/W JB Junction-to-board thermal resistance 17.5 C/W JT Junction-to-top characterization parameter 0.9 C/W JB Junction-to-board characterization parameter 7.2 C/W JCbot Junction-to-case (bottom) thermal resistance 0.9 C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. 6.5 DC Characteristics TA = -40C to 125C, VCC = 24 V, RL = 8 (unless otherwise noted) PARAMETER TEST CONDITIONS | VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB ICC Quiescent supply current SD = 2 V, no load, PVCC = 24 V ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 24 V rDS(on) Drain-source on-state resistance VCC = 12 V, IO = 500 mA, TJ = 25C GAIN1 = 0.8 V G Gain GAIN1 = 2 V ton Turn-on time SD = 2 V tOFF Turn-off time SD = 0.8 V GVDD Gate drive supply IGVDD = 100 A tDCDET DC detect time V(RINN) = 6 V, VRINP = 0 V MIN TYP MAX 1.5 15 mV 32 50 mA 250 400 A High side 240 Low side 240 m GAIN0 = 0.8 V 19 20 21 GAIN0 = 2 V 25 26 27 GAIN0 = 0.8 V 31 32 33 GAIN0 = 2 V 35 36 37 14 6.9 dB dB ms s 2 6.4 UNIT 7.4 420 V ms 6.6 DC Characteristics TA = -40C to 125C, VCC = 12 V, RL = 8 (unless otherwise noted) PARAMETER TEST CONDITIONS | VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB ICC Quiescent supply current SD = 2 V, no load, PVCC = 12 V ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 12 V rDS(on) Drain-source on-state resistance VCC = 12 V, IO = 500 mA, TJ = 25C GAIN1 = 0.8 V G Gain GAIN1 = 2 V tON Turn-on time SD = 2 V tOFF Turn-off time SD = 0.8 V GVDD Gate drive supply IGVDD = 2 mA VO Output voltage maximum under PLIMIT control V(PLIMIT) = 2 V; VI = 1 VRMS MIN TYP MAX 1.5 15 mV 20 35 mA 200 High side 240 Low side 240 A m GAIN0 = 0.8 V 19 20 21 GAIN0 = 2 V 25 26 27 GAIN0 = 0.8 V 31 32 33 GAIN0 = 2 V 35 36 37 14 Product Folder Links: TPA3110D2-Q1 dB dB ms s 2 6.4 6.9 7.4 V 6.75 7.90 8.75 V Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated UNIT 5 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com 6.7 AC Characteristics TA = -40C to 125C, VCC = 24 V, RL = 8 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN KSVR Power supply ripple rejection 200 mVPP ripple at 1 kHz, Gain = 20 dB, inputs AC-coupled to AGND PO Continuous output power THD+N = 10%, f = 1 kHz, VCC = 16 V THD+N Total harmonic distortion + noise VCC = 16 V, f = 1 kHz, PO = 7.5 W (half-power) Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB Crosstalk VO = 1 VRMS, Gain = 20 dB, f = 1 kHz SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted fOSC Oscillator frequency TYP MAX UNIT -70 dB 15 W 0.1% 250 Thermal trip point Thermal hysteresis 65 V -80 dBV -100 dB 102 dB 310 350 kHz 150 C 15 C 6.8 AC Characteristics TA = -40C to 125C, VCC = 12 V, RL = 8 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN KSVR Supply ripple rejection 200 mVPP ripple from 20 Hz-1 kHz, Gain = 20 dB, inputs AC-coupled to AGND PO Continuous output power THD+N = 10%, f = 1 kHz; VCC = 13 V THD+N Total harmonic distortion + noise RL = 8 , f = 1 kHz, PO = 5 W (half-power) Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB Crosstalk Po = 1 W, Gain = 20 dB, f = 1 kHz SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted fOSC Oscillator frequency Thermal hysteresis 6 Submit Documentation Feedback MAX UNIT -70 dB 10 W 0.06% 250 Thermal trip point TYP 65 V -80 dBV -100 dB 102 dB 310 350 kHz 150 C 15 C Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 6.9 Typical Characteristics All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the measurements. 10 Gain = 20 dB VCC = 12 V ZL = 8 + 66 H THD - Total Harmonic Distortion - % THD - Total Harmonic Distortion - % 10 1 0.1 PO = 5 W PO = 0.5 W 0.01 Gain = 20 dB VCC = 18 V ZL = 8+ 66 H 1 0.1 PO = 10 W PO = 1 W 0.01 PO = 5 W PO = 2.5 W 0.001 20 100 1k 10k 0.001 20 20k 100 1k f - Frequency - Hz 10k Figure 1. Total Harmonic Distortion vs Frequency (BTL) G002 Figure 2. Total Harmonic Distortion vs Frequency (BTL) 10 Gain = 20 dB VCC = 24 V ZL = 8 + 66 H THD - Total Harmonic Distortion - % THD - Total Harmonic Distortion - % 10 1 0.1 20k f - Frequency - Hz G001 PO = 10 W PO = 1 W 0.01 Gain = 20 dB VCC = 12 V ZL = 6 + 47 H 1 0.1 PO = 5 W PO = 0.5 W 0.01 PO = 2.5 W PO = 5 W 0.001 20 100 1k 10k 0.001 20 20k 100 1k 10k G003 Figure 3. Total Harmonic Distortion vs Frequency (BTL) G004 Figure 4. Total Harmonic Distortion vs Frequency (BTL) 10 10 Gain = 20 dB VCC = 18 V ZL = 6 + 47 H THD - Total Harmonic Distortion - % THD - Total Harmonic Distortion - % 20k f - Frequency - Hz f - Frequency - Hz 1 PO = 10 W 0.1 0.01 PO = 1 W Gain = 20 dB VCC = 12 V ZL = 4 + 33 H 1 0.1 PO = 10 W PO = 1 W 0.01 PO = 5 W PO = 5 W 0.001 20 100 1k 10k 20k 0.001 20 f - Frequency - Hz 100 1k 10k 20k f - Frequency - Hz G005 Figure 5. Total Harmonic Distortion vs Frequency (BTL) G006 Figure 6. Total Harmonic Distortion vs Frequency (BTL) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 7 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the measurements. 10 Gain = 20 dB VCC = 12 V ZL = 8 + 66 H 1 f = 20 Hz 0.1 f = 1 kHz 0.01 f = 10 kHz 0.001 0.01 0.1 1 10 PO - Output Power - W Gain = 20 dB VCC = 18 V ZL = 8 + 66 H THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 10 50 1 f = 1 kHz 0.01 f = 10 kHz 0.001 0.01 G007 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 1 f = 1 kHz 0.1 0.01 f = 20 Hz f = 10 kHz 0.1 1 10 PO - Output Power - W G008 1 f = 1 kHz 0.1 f = 20 Hz 0.01 f = 10 kHz 0.1 1 10 PO - Output Power - W G009 50 G010 Figure 10. Total Harmonic Distortion + Noise vs Output Power (BTL) 10 10 Gain = 20 dB VCC = 18 V ZL = 6 + 47 H THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 50 Gain = 20 dB VCC = 12 V ZL = 6 + 47 H 0.001 0.01 50 Figure 9. Total Harmonic Distortion + Noise vs Output Power (BTL) 1 f = 1 kHz f = 20 Hz 0.1 0.01 f = 10 kHz 0.1 1 PO - Output Power - W 10 50 Gain = 20 dB VCC = 12 V ZL = 4 + 33 H 1 f = 1 kHz 0.1 0.01 f = 20 Hz f = 10 kHz 0.001 0.01 0.1 1 PO - Output Power - W G011 Figure 11. Total Harmonic Distortion + Noise vs Output Power (BTL) 8 10 10 Gain = 20 dB VCC = 24 V ZL = 8 + 66 H 0.001 0.01 1 Figure 8. Total Harmonic Distortion + Noise vs Output Power (BTL) 10 0.001 0.01 0.1 PO - Output Power - W Lighter color represents thermally limited region. Figure 7. Total Harmonic Distortion + Noise vs Output Power (BTL) f = 20 Hz 0.1 10 50 G012 Figure 12. Total Harmonic Distortion + Noise vs Output Power (BTL) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 Typical Characteristics (continued) All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the measurements. 16 35 Gain = 20 dB VCC = 24 V ZL = 8 + 66 H PO(Max) - Maximum Output Power - W 14 Gain = 20 dB VCC = 12 V ZL = 4 + 33 H 30 PO - Output Power - W 12 10 8 6 25 20 15 10 4 5 2 0 0 0.0 0 0.5 1.0 1.5 2.0 2.5 1 3.0 VPLIMIT - PLIMIT Voltage - V 2 3 4 5 6 VPLIMIT - PLIMIT Voltage - V G014 Note: Dashed lines represent thermally limited regions. G013 Figure 13. Maximum Output Power vs PLIMIT Voltage (BTL) Figure 14. Output Power vs PLIMIT Voltage (BTL) 40 100 30 35 50 25 Gain = 20 dB ZL = 8 + 66 H 25 -50 Gain 20 -100 15 -150 CI = 1 F Gain = 20 dB Filter = Audio Precision AUX-0025 VCC = 12 V VI = 0.1 Vrms ZL = 8 + 66 H 10 5 0 20 100 -200 THD = 10% 15 THD = 1% 10 5 0 6 -300 100k 8 10 12 14 16 18 20 22 24 26 VCC - Supply Voltage - V f - Frequency - Hz G015 Figure 15. Gain/Phase vs Frequency (BTL) G016 Note: Dashed lines represent thermally limited regions. Figure 16. Output Power vs Supply Voltage (BTL) 25 100 Gain = 20 dB ZL = 4 + 33 H VCC = 12 V 90 20 VCC = 18 V VCC = 24 V 80 70 THD = 10% h - Efficiency - % PO - Output Power - W 20 -250 10k 1k PO - Output Power - W 0 Phase - Gain - dB Phase 30 15 THD = 1% 10 60 50 40 30 5 20 Gain = 20 dB ZL = 8 + 66 H 10 0 0 6 8 10 12 14 16 18 VCC - Supply Voltage - V 0 Note: Dashed lines represent thermally limited regions. Figure 17. Output Power vs Supply Voltage (BTL) 5 10 15 20 25 30 35 40 PO - Output Power - W G017 G018 Note: Dashed lines represent thermally limited regions. Figure 18. Efficiency vs Output Power (BTL) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 9 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the measurements. 100 100 VCC = 12 V 90 VCC = 18 V 90 VCC = 24 V VCC = 18 V 70 h - Efficiency - % 70 h - Efficiency - % VCC = 12 V 80 80 60 50 40 60 50 40 30 30 20 20 Gain = 20 dB LC Filter = 22 H + 0.68 F RL = 8 10 0 0 0 0 5 10 15 20 G032 15 20 25 G019 Note: Dashed lines represent thermally limited regions. Figure 20. Efficiency vs Output Power (BTL) 100 100 90 90 VCC = 12 V VCC = 12 V 80 80 VCC = 18 V 70 h - Efficiency - % 70 h - Efficiency - % 10 PO - Output Power - W Figure 19. Efficiency vs Output Power (BTL With LC Filter) 60 50 40 30 60 50 40 30 20 20 Gain = 20 dB LC Filter = 22 H + 0.68 F RL = 6 10 Gain = 20 dB ZL = 4 + 33 H 10 0 0 0 5 10 15 20 25 PO - Output Power - W 0 3 6 9 12 15 18 PO - Output Power - W G033 Figure 21. Efficiency vs Output Power (BTL With LC Filter) G020 Figure 22. Efficiency vs Output Power (BTL) 2.6 100 2.4 90 VCC = 18 V 2.2 VCC = 12 V 80 ICC - Supply Current - A 2.0 70 h - Efficiency - % 5 25 PO - Output Power - W 60 50 40 30 1.8 1.6 VCC = 12 V 1.4 1.2 VCC = 24 V 1.0 0.8 0.6 20 0.4 Gain = 20 dB LC Filter = 22 H + 0.68 F RL = 4 10 Gain = 20 dB ZL = 8 + 66 H 0.2 0.0 0 0 0 5 10 15 PO - Output Power - W 20 25 G034 Figure 23. Efficiency vs Output Power (BTL With LC Filter) 10 Gain = 20 dB ZL = 6 + 47 H 10 5 10 15 20 25 30 35 40 PO(Tot) - Total Output Power - W G021 Note: Dashed lines represent thermally limited regions. Figure 24. Supply Current vs Total Output Power (BTL) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 Typical Characteristics (continued) All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the measurements. -20 3.2 Gain = 20 dB ZL = 4 + 33 H 2.8 Gain = 20 dB VCC = 12 V VO = 1 Vrms ZL = 8 + 66 H -30 -40 -50 2.0 Crosstalk - dB VCC = 12 V 1.6 1.2 -60 -70 -80 Right to Left -90 0.8 -100 0.4 -110 Left to Right -120 0.0 0 5 10 15 20 25 30 PO(Tot) - Total Output Power - W -130 20 100 1k G022 Figure 26. Crosstalk vs Frequency (BTL) 10 Gain = 20 dB Vripple = 200 mVpp ZL = 8 + 66 H THD - Total Harmonic Distortion - % KSVR - Supply Ripple Rejection Ratio - dB 0 -40 -60 VCC = 12 V -80 -100 -120 20 100 1k 10k Gain = 20 dB VCC = 24 V ZL = 4 + 33 H 1 PO = 5 W 0.1 PO = 0.5 W 0.01 PO = 2.5 W 0.001 20 20k 100 f - Frequency - Hz Figure 27. Supply Ripple Rejection Ratio vs Frequency (BTL) 1k 10k 20k f - Frequency - Hz G024 G025 Figure 28. Total Harmonic Distortion vs Frequency (PBTL) 10 100 40 Gain = 20 dB VCC = 24 V ZL = 4 + 33 H 35 50 Phase 1 30 0 f = 1 kHz 25 Gain - dB THD+N - Total Harmonic Distortion + Noise - % 20k G023 Figure 25. Supply Current vs Total Output Power (BTL) -20 10k f - Frequency - Hz Note: Dashed lines represent thermally limited regions. 0.1 -50 Gain 20 -100 15 0.01 10 f = 20 Hz 5 f = 10 kHz 0.001 0.01 0.1 1 10 PO - Output Power - W 50 Phase - ICC - Supply Current - A 2.4 -150 CI = 1 F Gain = 20 dB Filter = Audio Precision AUX-0025 VCC = 24 V VI = 0.1 Vrms ZL = 8 + 66 H 0 20 100 1k -200 -250 10k -300 100k f - Frequency - Hz G026 Figure 29. Total Harmonic Distortion + Noise vs Output Power (PBTL) G027 Figure 30. Gain/Phase vs Frequency (PBTL) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 11 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the measurements. 40 100 Gain = 20 dB ZL = 4 + 33 H 35 90 80 VCC = 18 V 70 25 h - Efficiency - % PO - Output Power - W 30 THD = 10% 20 THD = 1% 15 VCC = 12 V 60 50 40 30 10 20 5 Gain = 20 dB ZL = 4 + 33 H 10 0 6 8 10 12 14 16 18 20 0 0 VCC - Supply Voltage - V G028 10 15 20 25 30 35 40 45 G029 Figure 32. Efficiency vs Output Power (PBTL) Figure 31. Output Power vs Supply Voltage (PBTL) 0 2.8 2.4 KSVR - Supply Ripple Rejection Ratio - dB Gain = 20 dB ZL = 4 + 33 H 2.6 2.2 ICC - Supply Current - A 5 PO - Output Power - W Note: Dashed lines represent thermally limited regions. 2.0 1.8 VCC = 12 V 1.6 1.4 VCC = 18 V 1.2 1.0 0.8 0.6 0.4 -20 Gain = 20 dB Vripple = 200 mVpp ZL = 8 + 66 H -40 -60 VCC = 12 V -80 -100 0.2 0.0 0 5 10 15 20 25 30 PO - Output Power - W 35 40 -120 20 45 1k 10k 20k f - Frequency - Hz G030 Figure 33. Supply Current vs Output Power (PBTL) 12 100 G031 Figure 34. Supply Ripple Rejection Ratio vs Frequency (PBTL) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 7 Detailed Description 7.1 Overview The TPA3110D2-Q1 is AEC-Q100 qualified with a temperature grade 1 (-40C to 125C), HBM ESD classification level H2, and CDM ESD classification level C2. This automotive audio amplifier also features several protection mechanisms as follows: * DC Current Detection - The TPA3110D2-Q1 protects speakers from DC current by reporting a fault on the FAULT pin and turning the amplifier outputs to a Hi-Z state when a DC current is detected. The PVCC supply must be cycled to clear this fault. * Short-Circuit Protection and Automatic Recovery - The TPA3110D2-Q1 has short circuit protection from the output pins to VCC, GND, or to each other. If a short circuit is detected, it will be reported on the FAULT pin and the amplifier outputs will be switched to a Hi-Z state. The fault can be cleared by cycling the SD pin. * Thermal Protection - When the die temperature exceeds 150C (15C) the device enters the shutdown state and the amplifier outputs are disabled. The TPA3110D2-Q1 recovers automatically when the temperature decreases by 15C Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 13 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com 7.2 Functional Block Diagram GVDD PVCCL BSPL PVCCL PBTL Select OUTPL FB Gate Drive OUTPL OUTPL FB LINP Gain Control PGND PWM Logic PLIMIT GVDD LINN PVCCL BSNL PVCCL OUTNL FB OUTNL FB FAULT Gate Drive OUTNL SD GAIN0 TTL Buffer SC Detect Gain Control GAIN1 Ramp Generator Biases and References Startup Protection Logic PLIMIT Reference PLIMIT PGND DC Detect Thermal Detect UVLO/OVLO GVDD AVDD AVCC PVCCL BSNR PVCCL LDO Regulator GVDD Gate Drive GVDD OUTNR OUTNN FB OUTNR FB RINN Gain Control PLIMIT PGND PWM Logic GVDD RINP PVCCL BSPR PVCCL OUTNP FB Gate Drive PBTL TTL Buffer PBTL Select OUTPR PBTL Select OUTPR FB AGND PGND 7.3 Feature Description 7.3.1 DC Detect TPA3110D2-Q1 has circuitry which protects the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault is reported on the FAULT pin as a low state. The DC detect fault also causes the amplifier to shut down by changing the state of the outputs to Hi-Z. To clear the DC detect it is necessary to cycle the PVCC supply. Cycling SD does NOT clear a DC detect fault. A DC detect fault is issued when the output differential duty-cycle of either channel exceeds 14% (for example, 57%, -43%) for more than 420 msec at the same polarity. This feature protects the speaker from large DC currents or AC currents less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults. The minimum differential input voltages required to trigger the DC detect are shown in Table 1. The inputs must remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect. 14 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 Table 1. DC Detect Threshold AV (dB) VIN (mV, Differential) 20 112 26 56 32 28 36 17 7.3.2 Short-Circuit Protection and Automatic Recovery Feature TPA3110D2-Q1 has protection from overcurrent conditions caused by a short circuit on the output stage. The short-circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z state when the short-circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through the low state. If automatic recovery from the short-circuit protection latch is desired, connect the FAULT pin directly to the SD pin. This allows the FAULT pin function to automatically drive the SD pin low, which clears the short-circuit protection latch. 7.3.3 Thermal Protection Thermal protection on the TPA3110D2-Q1 prevents damage to the device when the internal die temperature exceeds 150C. There is a 15C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15C. The device begins normal operation at this point with no external system interaction. Thermal protection faults are NOT reported on the FAULT terminal. 7.3.4 GVDD Supply The GVDD supply is used to power the gates of the output full bridge transistors. It can also be used to supply the PLIMIT voltage divider circuit. Add a 1-F capacitor to ground at this pin. 7.4 Device Functional Modes 7.4.1 PBTL Select Use the PBTL pin to select between PBTL mode when held high or BTL mode when held low. Connect the speaker between the right and left outputs, with the positive and negative output from each channel tied together. 7.4.2 Gain Setting Through GAIN0 and GAIN1 Inputs The gain of the TPA3110D2-Q1 is set to one of four options by the state of the GAIN0 and GAIN1 pins. Changing the gain setting also changes the input impedance of the TPA3110D2-Q1. Refer to Table 2 for a list of the gain settings. Table 2. Gain Setting AMPLIFIER GAIN (dB) INPUT IMPEDANCE (k) TYP TYP 0 20 60 0 1 26 30 1 0 32 15 1 1 36 9 GAIN1 GAIN0 0 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 15 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 7.4.3 www.ti.com SD Operation The SD pin can be used to enter the shutdown mode which mutes the amplifier and causes the TPA3110D2-Q1 to enter a low-current state. This mode can also be triggered to improve power-off pop performance. 7.4.4 PLIMIT The PLIMIT pin limits the output peak-to-peak voltage based on the voltage supplied to the PLIMIT pin. The peak output voltage is limited to four times the voltage at the PLIMIT pin. Vinput PLIMIT = 6.96V Pout = 11.8W PLIMIT = 3V Pout = 10W PLIMIT = 1.8V Pout = 5W TPA3110D2-Q1 Power Limit Function Vin=1.13VPP Freq=1kHz RLoad=8W Figure 35. PLIMIT Circuit Operation The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply connected to PVCC. This virtual rail is four times the voltage at the PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance. POUT aeae o o RL cc c / x VP // e RL + 2 x RS o o = e 2 x RL 2 for unclipped power (1) Where: RS is the total series resistance including RDS(on), and any resistance in the output filter. RL is the load resistance. VP is the peak amplitude of the output possible within the supply rail. VP = 4 x PLIMIT voltage if PLIMIT < 4 x VP POUT (10%THD) = 1.25 x POUT (unclipped) 16 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 Table 3. PLIMIT Typical Operation TEST CONDITIONS PLIMIT VOLTAGE OUTPUT POWER (W) Output Voltage Amplitude (VP-P) PVCC = 24 V, VIN = 1 VRMS, RL = 8 , Gain = 26 dB 6.97 36.1 (thermally limited) 43 PVCC = 24 V, VIN = 1 VRMS, RL = 8 , Gain = 26 dB 2.94 15 25.2 PVCC = 24 V, VIN = 1 VRMS, RL = 8 , Gain = 26 dB 2.34 10 20 PVCC = 24 V, VIN = 1 VRMS, RL = 8 , Gain = 26 dB 1.62 5 14 PVCC = 24 V, VIN = 1 VRMS, RL = 8 , Gain = 20 dB 6.97 12.1 27.7 PVCC = 24 V, VIN = 1 VRMS, RL = 8 , Gain = 20 dB 3 PVCC = 24 V, VIN = 1 VRMS, RL = 8 , Gain = 20 dB 1.86 5 14.8 PVCC = 12 V, VIN = 1 VRMS, RL = 8 , Gain = 20 dB 6.97 10.55 23.5 PVCC = 12 V, VIN = 1 VRMS, RL = 8 , Gain = 20 dB 1.76 5 15 23 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 17 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPA3110D1-Q1 device is an automotive class-D audio amplifier. It accepts either a stereo single ended or differential analog input, amplifies the signal, and drives up to 15W across two bridge tied loads, usually stereo speakers. Because an analog input is needed, this device is often paired with a codec or audio DAC if the audio source is digital. The four digital input/output pins, GAIN0, GAIN1, SD, and FAULT, can be pulled up to PVCC. When connecting these terminals to PVCC, a 100 k-resistor must be put in series to limit the slew rate. One of four gain settings is used depending on the configuration of GAIN0 and GAIN1. The SD pin is used to put the device in shutdown or normal mode. The FAULT pin is used to indicate if a DC detect or short circuit fault was detected. The next few sections explains design considerations and how to choose the external components. 8.2 Typical Application PVCC 100 F 0.1 F 1000 pF 100 k Control System 1 SD PVCCL FAULT PVCCL 28 1 k 2 1 mF 3 1 mF 4 5 6 PVCC 10 LINP LINN BSPL OUTPL GAIN0 PGND GAIN1 OUTNL 27 26 1000 pF 24 23 BSNL AVCC TPA3110D2-Q1 21 8 BSNR AGND 1 mF 9 FB 25 1000 pF 22 7 1 mF 0.22 F GVDD OUTNR PLIMIT PGND 0.22 F 0.22 F FB FB 20 1000 pF 1 mF 10 k 10 19 10 k 1 mF Audio Source 11 12 1 mF 13 14 RINN OUTPR RINP BSPR NC PBTL PVCCR PVCCR 18 1000 pF 17 FB 0.22 F 16 15 100 F 0.1 F 1000 pF GND 29 PowerPAD PVCC Figure 36. Stereo Class-D Amplifier With BTL Output and Single-Ended Inputs With Power Limiting 18 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 Typical Application (continued) PVCC 100 F 0.1 F 1000 pF 100 k Control System 1 SD PVCCL FAULT PVCCL 28 1 k 2 3 4 5 6 AVCC PVCC LINP LINN BSPL OUTPL GAIN0 PGND GAIN1 OUTNL 27 26 0.47 F 25 24 FB 23 1000 pF 7 22 AVCC BSNL TPA3110D2-Q1 8 21 BSNR AGND 10 1 mF 9 1 mF 10 11 1 mF Audio Source 12 1 mF 100 kW AVCC 13 GVDD PLIMIT OUTNR PGND RINN OUTPR RINP BSPR NC PVCCR PBTL PVCCR 1000 pF 20 FB 19 0.47 F 18 17 16 100 F (1) 14 0.1 F 1000 pF 15 GND 29 PowerPAD PVCC (1) A 100-k resistor is needed if the PVCC slew rate is more than 10 V/ms. Figure 37. Stereo Class-D Amplifier With PBTL Output and Single-Ended Input 8.2.1 Design Requirements The typical requirements for designing the external components around the TPA3110D1-Q1 include efficiency and EMI/EMC performance. For most applications, only a ferrite bead is needed to filter unwanted emissions. The ripple current is low enough that an LC filter is typically not needed. As the output power increases, causing the ripple current to increase, an LC filter can be added to improve efficiency. An LC filter can also be added in cases where additional EMI suppression is needed. In addition to discussing how to choose a ferrite bead and when to use an LC filter, the following sections also discuss the input filter and power supply decoupling. The input filter must be chosen with the input impedance of the amplifier in mind. The cut-off frequency should be chosen so that bass performance is not impacted. Power supply decoupling is important to ensure that noise from the power line does not impact the audio quality of the amplifier output. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 19 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Typical Application (continued) 8.2.2 Detailed Design Procedure 8.2.2.1 TPA3110D2-Q1 Modulation Scheme The TPA3110D2-Q1 uses a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The OUTP and OUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which reduces any I2R losses in the load. See Figure 42 for a plot of the output waveforms. 8.2.2.2 Ferrite Bead Filter Considerations Using the advanced emissions suppression technology in the TPA3110D2-Q1 amplifier, it is possible to design a high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite bead used in the filter. One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite material is alike, so it is important to select a material that is effective in the 10- to 100-MHz range which is key to the operation of the Class-D amplifier. Many of the specifications regulating consumer electronics have emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30-MHz and above range from appearing on the speaker wires and the power supply lines which are good antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance, the resonant frequency of the ferrite bead and capacitor filter should be less than 10 MHz. Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier sees. If these specifications are not available, it is also possible to estimate the bead current handling capability by measuring the resonant frequency of the filter output at low power and at maximum power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of tested ferrite beads that work well with the TPA3110D2-Q1 include 28L0138-80R-10 and HI1812V101R-10 from Steward and the 742792510 from Wurth Electronics. A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good temperature and voltage characteristics works best. Additional EMC improvements may be obtained by adding snubber networks from each of the Class-D outputs to ground. Suggested values for a simple RC series snubber network would be 10 in series with a 330-pF capacitor although design of the snubber network is specific to every application and must be designed taking into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make sure the layout of the snubber network is tight and returns directly to the PGND or the PowerPADTM integrated circuit package beneath the chip. 20 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 Typical Application (continued) 70 FCC Class B Limit Level - dBmV/m 60 50 40 30 20 10 0 30M 230M 430M 630M 830M f - Frequency - Hz Figure 38. TPA3110D2-Q1 EMC Spectrum With FCC Class-B Limits 8.2.2.3 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme The main reason that the traditional Class-D amplifier needs an output filter is because the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC Filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC Filter is almost purely reactive. The TPA3110D2-Q1 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC Filter for increased efficiency, but for most applications the filter is not needed. An LC Filter with a cutoff frequency less than the Class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency. 8.2.2.4 When to Use an Output Filter for EMI Suppression The TPA3110D2-Q1 has been tested with a simple ferrite bead filter for a variety of applications including long speaker wires up to 125 cm and high power. The TPA3110D2-Q1 EVM passes FCC Class-B specifications under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency. There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic second order Butterworth filter similar to those shown in the figures below can be used. Some systems have little power supply decoupling from the AC line but are also subject to line conducted interference (LCI) regulations. These include systems powered by wall warts and power bricks. In these cases, the LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using low frequency ferrite material can also be effective at preventing line conducted interference. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 21 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Typical Application (continued) 33 mH OUTP L1 C2 1 mF 33 mH OUTN L2 C3 1 mF Figure 39. Typical LC Output Filter, Cutoff Frequency Of 27 kHz, Speaker Impedance = 8 15 mH OUTP L1 C2 2.2 mF 15 mH OUTN L2 C3 2.2 mF Figure 40. Typical LC Output Filter, Cutoff Frequency Of 27 kHz, Speaker Impedance = 4 Ferrite Chip Bead OUTP 1 nF Ferrite Chip Bead OUTN 1 nF Figure 41. Typical Ferrite Chip Bead Filter (Chip Bead Example) 22 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 Typical Application (continued) 8.2.2.5 Input Resistance Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 k 20%, to the largest value, 60 k 20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency may change when changing gain steps. Zf Ci IN Input Signal Zi The -3-dB frequency can be calculated using Equation 2. Use the ZI values given in Table 2. f = 1 2p Zi Ci (2) 8.2.2.6 Input Capacitor, CI In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a highpass filter with the corner frequency determined in Equation 3. -3 dB fc = 1 2p Zi Ci fc (3) The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where ZI is 60 k and the specification calls for a flat bass response down to 20 Hz. Equation 3 is reconfigured as Equation 4. Ci = 1 2p Zi fc (4) In this example, CI is 0.13 F; so, one would likely choose a value of 0.15 F as this value is commonly used. If the gain is known and is constant, use ZI from Table 2 to calculate CI. A further consideration for this capacitor is the leakage path from the input source through the input network (CI) and the feedback network to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at 3 V, which is likely higher than the source DC level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create DC offset voltages and it is important to ensure that boards are cleaned properly. 8.2.2.7 BSN and BSP Capacitors The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 0.22-F ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 0.22-F capacitor must be connected from OUTPx to BSPx, and one 0.22-F capacitor must be connected from OUTNx to BSNx. (See the application circuit diagram in TPA3110D2-Q1 Simplified Application Schematic .) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 23 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com Typical Application (continued) The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on. 8.2.2.8 Differential Inputs The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3110D2-Q1 with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3110D2-Q1 with a single-ended source, AC-ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application, the unused input should be ACgrounded at the audio source instead of at the device input for best noise performance. For good transient performance, the impedance seen at each of the two differential inputs should be the same. The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to allow the input DC blocking capacitors to become completely charged during the 14 ms power-up time. If the input capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching which can result in pop if the input components are not well matched. 8.2.2.9 Using Low-ESR Capacitors Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. 8.2.3 Application Curve OUTP OUTN OUTP OUTP-OUTN No Output 0V Speaker Current OUTP OUTN Positive Output PVCC OUTP-OUTN 0V Speaker Current 0A OUTP Negative Output OUTN OUTP-OUTN 0V -PVCC Speaker 0A Current Figure 42. The TPA3110D2-Q1 Output Voltage and Current Waveforms into an Inductive Load 24 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 9 Power Supply Recommendations The TPA3110D2-Q1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper trace inductances as well as lead frame capacitance, a good quality low equivalent-seriesresistance (ESR) ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be placed as close to the device PVCC pins and system ground (either PGND pins or PowerPADTM integrated circuit package) as possible. For mid-frequency noise due to filter resonances or PWM switching transients as well as digital hash on the line, another good quality capacitor typically 0.1 F to 1 F placed as close as possible to the device PVCC leads works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 F or greater placed near the audio power amplifier is recommended. The 220-F capacitor also serves as a local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 220-F or larger capacitor should be placed on each PVCC terminal. A 10F capacitor on the AVCC terminal is adequate. Also, a small decoupling resistor between AVCC and PVCC can be used to keep high frequency Class-D noise from entering the linear input amplifiers. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 25 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com 10 Layout 10.1 Layout Guidelines The TPA3110D2-Q1 can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the printed circuit board. The following suggestions help to meet EMC requirements. * Decoupling capacitors--The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. Large (220-F or greater) bulk power supply decoupling capacitors should be placed near the TPA3110D2-Q1 on the PVCCL and PVCCR supplies. Local, high-frequency bypass capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between 220 pF and 1000 pF and a larger good quality mid-frequency cap of value between 0.1 F and 1 F to the PVCC connections at each end of the chip. * Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to PGND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna. * Grounding--The AVCC (pin 7) decoupling capacitor should be grounded to analog ground (AGND). The PVCC decoupling capacitors should connect to PGND. Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the TPA3110D2-Q1. * Output filter--The ferrite EMI filter (Figure 41) should be placed as close to the output terminals as possible for the best EMI performance. The LC Filter (Figure 39 and Figure 40) should be placed close to the outputs. The capacitors used in both the ferrite and LC Filters should be grounded to power ground. * Thermal pad--The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35 mm. Seven rows of solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB footprints, see the figures at the end of this data sheet. For an example layout, see the TPA3110D2-Q1 Evaluation Module User's Guide, SLOU263. Both the EVM user's guide and the thermal pad application report are available on the TI website at http://www.ti.com. 26 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 TPA3110D2-Q1 www.ti.com SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 10.2 Layout Example Large bulk decoupling capacitor Smaller high frequency decoupling capacitors To PVCC supply SD PVCCL FAULT PVCCL LINP BSPL LINN Thermal Pad OUTPL Speaker Connect to PVCC supply Audio input GAIN0 PGND GAIN1 OUTNL AVCC BSNL AGND BSNR GVDD OUTNR PLIMIT PGND RINN OUTPR RINP BSPR NC PVCCR PBTL PVCCR Connect to ground plane layer Ferrite Bead Vias to ground plane Ferrite Bead To PVCC supply Smaller high frequency decoupling capacitors Via Copper trace/pour Large bulk decoupling capacitor Thermal pad Figure 43. TPA3110D2-Q1 Layout Example for PBTL Output Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 27 TPA3110D2-Q1 SLOS794B - SEPTEMBER 2012 - REVISED SEPTEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support TI PCB Thermal Calculator 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: Maximum Slew Rate on High-Voltage Pins for TPA3111D1, SLUA626 PowerPAD TM Thermally Enhanced Package, SLMA002 TPA3110D2-Q1 Evaluation Module User's Guide, SLOU263 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks SpeakerGuard, PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 28 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPA3110D2-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) TPA3110D2QPWPRQ1 ACTIVE Package Type Package Pins Package Drawing Qty HTSSOP PWP 28 2000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Op Temp (C) Device Marking (4/5) -40 to 125 TPA3110Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2015 OTHER QUALIFIED VERSIONS OF TPA3110D2-Q1 : * Catalog: TPA3110D2 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPA3110D2QPWPRQ1 HTSSOP PWP 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA3110D2QPWPRQ1 HTSSOP PWP 28 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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