LINP
LINN
RINP
RINN
SDSD
FaultFault
PLIMIT
PBTL
PVCC 8 to 26V
1 Fm
OUTNL
FERRITE
BEAD
FILTER
OUTPL 15W
FERRITE
BEAD
FILTER
FERRITE
BEAD
FILTER 8W
OUTR+
OUTR-
OUTL+
OUTL-
Audio
Source
TPA3110D2-Q1
GAIN0
GAIN1
OUTNR
FERRITE
BEAD
FILTER
OUTPR 15W
8W
FERRITE
BEAD
FILTER
FERRITE
BEAD
FILTER
Product
Folder
Sample &
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Technical
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Tools &
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TPA3110D2-Q1
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
TPA3110D2-Q1 15-W Filter-Free Stereo Class-D
Audio Power Amplifier With SpeakerGuard™
1 Features 3 Description
The TPA3110D2-Q1 is a 15-W (per channel) efficient,
1• Qualified for Automotive Applications Class-D audio power amplifier for driving bridged-tied
• AEC-Q100 Qualified With the Following Results: stereo speakers. Advanced EMI suppression
– Device Temperature Grade 1: –40°C to 125°C technology enables the use of inexpensive ferrite
Ambient Operating Temperature Range bead filters at the outputs while meeting EMC
requirements. SpeakerGuard protection circuitry
– Device HBM ESD Classification Level H2 includes an adjustable power limiter and a DC
– Device CDM ESD Classification Level C2 detection circuit. The adjustable power limiter allows
• 15-W/ch Into 8-ΩLoads at 10% THD+N From a the user to set a virtual voltage rail lower than the
16-V Supply chip supply to limit the amount of current through the
speaker. The DC detect circuit measures the
• 10-W/ch Into 8-ΩLoads at 10% THD+N From a frequency and amplitude of the PWM signal and
13-V Supply shuts off the output stage if the input capacitors are
• 30-W Into a 4-ΩMono Load at 10% THD+N From damaged or shorts exist on the inputs.
a 16-V Supply The TPA3110D2-Q1 can drive stereo speakers as
• 90% Efficient Class-D Operation Eliminates Need low as 4 Ω. The high efficiency of the device, 90%,
for Heat Sinks eliminates the need for an external heat sink when
• Wide Supply Voltage Range Allows Operation playing music.
from 8 V to 26 V The outputs are also fully protected against shorts to
• Filter-Free Operation GND, VCC, and output-to-output. The short-circuit
• SpeakerGuard™ Protection Circuitry Includes protection and thermal protection includes an auto-
recovery feature.
Adjustable Power Limiter Plus DC Protection
• Flow Through Pin Out Facilitates Easy Board Device Information(1)
Layout PART NUMBER PACKAGE BODY SIZE (NOM)
• Robust Pin-to-Pin Short-Circuit Protection and TPA3110D2-Q1 HTSSOP (28) 9.70 mm × 4.40 mm
Thermal Protection with Auto Recovery Option (1) For all available packages, see the orderable addendum at
• Excellent THD+N and Pop-Free Performance the end of the data sheet.
• Four Selectable Fixed Gain Settings TPA3110D2-Q1 Simplified Application Schematic
• Differential Inputs
2 Applications
• Automotive Noise Generation for HEV/EV
• Automotive Emergency Call Systems (eCall)
• Automotive Infotainment Systems (i.e. Head Unit,
Connectivity Gateway, Cluster, Telematics,
Navigation)
• ADAS Noise Generation for Blind Spot Detection,
Security and Alarm Systems
• Professional Audio Equipment (Performance
Amplifiers, Premium Microphones)
• Aerospace and Aviation Audio Systems
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3110D2-Q1
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
7.3 Feature Description................................................. 14
1 Features.................................................................. 17.4 Device Functional Modes........................................ 15
2 Applications ........................................................... 18 Application and Implementation ........................ 18
3 Description............................................................. 18.1 Application Information............................................ 18
4 Revision History..................................................... 28.2 Typical Application.................................................. 18
5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 25
6 Specifications......................................................... 410 Layout................................................................... 26
6.1 Absolute Maximum Ratings ...................................... 410.1 Layout Guidelines ................................................. 26
6.2 ESD Ratings.............................................................. 410.2 Layout Example .................................................... 27
6.3 Recommended Operating Conditions...................... 411 Device and Documentation Support................. 28
6.4 Thermal Information.................................................. 511.1 Device Support .................................................... 28
6.5 DC Characteristics.................................................... 511.2 Documentation Support ....................................... 28
6.6 DC Characteristics.................................................... 511.3 Community Resources.......................................... 28
6.7 AC Characteristics .................................................... 611.4 Trademarks........................................................... 28
6.8 AC Characteristics .................................................... 611.5 Electrostatic Discharge Caution............................ 28
6.9 Typical Characteristics ............................................. 711.6 Glossary................................................................ 28
7 Detailed Description............................................ 13 12 Mechanical, Packaging, and Orderable
7.1 Overview................................................................. 13 Information........................................................... 28
7.2 Functional Block Diagram....................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2012) to Revision B Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
Changes from Original (September, 2012) to Revision A Page
• Changed TAfrom 25°C to –40°C to 125°C in DC and AC Characteristics tables.................................................................. 5
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1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
22
21
20
19
SD
FAULT
LINP
LINN
GAIN0
GAIN1
AVCC
AGND
GVDD
PLIMIT
PVCCL
PVCCL
BSPL
OUTPL
PGND
OUTNL
BSNL
BSNR
OUTNR
PGND
RINN
RINP
NC
11
12
13
14
18
17
16
15
OUTPR
BSPR
PVCCR
PVCCR
PBTL
TPA3110D2-Q1
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SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP With PowerPAD™ IC Package
Top View
Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled), TTL
1 SD I logic levels with compliance to AVCC.
Open drain output used to display short circuit or DC detect fault status. Voltage compliant to
2 FAULT O AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin.
Otherwise, both short circuit faults and DC detect faults must be reset by cycling PVCC.
3 LINP I Positive audio input for left channel, biased at 3 V.
4 LINN I Negative audio input for left channel, biased at 3 V.
5 GAIN0 I Gain select least significant bit, TTL logic levels with compliance to AVCC.
6 GAIN1 I Gain select most significant bit, TTL logic levels with compliance to AVCC.
7 AVCC P Analog supply
8 AGND — Analog signal ground, connect to the thermal pad.
High-side FET gate drive supply. The nominal voltage is 7 V. GVDD should also be used as
9 GVDD O a supply for the PLIMIT function.
Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit.
10 PLIMIT I Connect directly to GVDD for no power limit.
11 RINN I Negative audio input for right channel, biased at 3 V.
12 RINP I Positive audio input for right channel, biased at 3 V.
13 NC — Not connected
14 PBTL I Parallel BTL mode switch
Power supply for right channel H-bridge. Right channel and left channel power supply inputs
15 PVCCR P are connect internally.
Power supply for right channel H-bridge. Right channel and left channel power supply inputs
16 PVCCR P are connect internally.
17 BSPR I Bootstrap I/O for right channel, positive high-side FET
18 OUTPR O Class-D H-bridge positive output for right channel
19 PGND — Power ground for the H-bridges
20 OUTNR O Class-D H-bridge negative output for right channel
21 BSNR I Bootstrap I/O for right channel, negative high-side FET
22 BSNL I Bootstrap I/O for left channel, negative high-side FET
23 OUTNL O Class-D H-bridge negative output for left channel
24 PGND — Power ground for the H-bridges
25 OUTPL O Class-D H-bridge positive output for left channel
26 BSPL I Bootstrap I/O for left channel, positive high-side FET
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Pin Functions (continued)
PIN TYPE DESCRIPTION
NO. NAME
Power supply for left channel H-bridge. Right channel and left channel power supply inputs
27 PVCCL P are connect internally.
Power supply for left channel H-bridge. Right channel and left channel power supply inputs
28 PVCCL P are connect internally.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage AVCC, PVCC –0.3 30 V
–0.3 VCC + 0.3 V
SD, GAIN0, GAIN1, PBTL, FAULT(2) < 10 V/ms
Interface pin
VIvoltage PLIMIT –0.3 GVDD + 0.3 V
RINN, RINP, LINN, LINP –0.3 6.3 V
BTL: PVCC > 15 V 4.8
Minimum load
RLBTL: PVCC ≤15 V 3.2
resistance PBTL 3.2
Continuous total power dissipation See the Thermal Information Table
TAOperating free-air temperature –40 125 °C
TJOperating junction temperature(3) –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-kΩresistor in series
with the pins, per application note SLUA626.
(3) The TPA3110D2-Q1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal
protection shutdown. See TI Technical Brief SLMA002 for more information about using the TSSOP thermal pad.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1) ±4000
V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 ±250 V
Machine Model (MM) per JESD22-A115 ±200
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage PVCC, AVCC 8 26 V
VIH High-level input voltage SD, GAIN0, GAIN1, PBTL 2 V
VIL Low-level input voltage SD, GAIN0, GAIN1, PBTL 0.8 V
VOL Low-level output voltage FAULT, RPULL-UP = 100k, VCC = 26 V 0.8 V
IIH High-level input current SD, GAIN0, GAIN1, PBTL, VI= 2 V, VCC = 18 V 50 µA
IIL Low-level input current SD, GAIN0, GAIN1, PBTL, VI= 0.8 V, VCC = 18 V 5 µA
TAOperating free-air temperature –40 125 °C
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6.4 Thermal Information TPA3110D2-Q1
THERMAL METRIC(1)(2) PWP (HTSSOP) UNIT
28 Pins
θJA Junction-to-ambient thermal resistance 30.3 °C/W
θJCtop Junction-to-case (top) thermal resistance 33.5 °C/W
θJB Junction-to-board thermal resistance 17.5 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 7.2 °C/W
θJCbot Junction-to-case (bottom) thermal resistance 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
6.5 DC Characteristics
TA= –40°C to 125°C, VCC = 24 V, RL= 8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage (measured
| VOS | VI= 0 V, Gain = 36 dB 1.5 15 mV
differentially)
ICC Quiescent supply current SD = 2 V, no load, PVCC = 24 V 32 50 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 24 V 250 400 µA
High side 240
VCC = 12 V, IO= 500 mA,
rDS(on) Drain-source on-state resistance mΩ
TJ= 25°C Low side 240
GAIN0 = 0.8 V 19 20 21
GAIN1 = 0.8 V dB
GAIN0 = 2 V 25 26 27
G Gain GAIN0 = 0.8 V 31 32 33
GAIN1 = 2 V dB
GAIN0 = 2 V 35 36 37
ton Turn-on time SD = 2 V 14 ms
tOFF Turn-off time SD = 0.8 V 2 μs
GVDD Gate drive supply IGVDD = 100 μA 6.4 6.9 7.4 V
tDCDET DC detect time V(RINN) = 6 V, VRINP = 0 V 420 ms
6.6 DC Characteristics
TA= –40°C to 125°C, VCC = 12 V, RL= 8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage (measured
| VOS | VI= 0 V, Gain = 36 dB 1.5 15 mV
differentially)
ICC Quiescent supply current SD = 2 V, no load, PVCC = 12 V 20 35 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 12 V 200 µA
High side 240
VCC = 12 V, IO= 500 mA,
rDS(on) Drain-source on-state resistance mΩ
TJ= 25°C Low side 240
GAIN0 = 0.8 V 19 20 21
GAIN1 = 0.8 V dB
GAIN0 = 2 V 25 26 27
G Gain GAIN0 = 0.8 V 31 32 33
GAIN1 = 2 V dB
GAIN0 = 2 V 35 36 37
tON Turn-on time SD = 2 V 14 ms
tOFF Turn-off time SD = 0.8 V 2 μs
GVDD Gate drive supply IGVDD = 2 mA 6.4 6.9 7.4 V
Output voltage maximum under PLIMIT
VOV(PLIMIT) = 2 V; VI= 1 VRMS 6.75 7.90 8.75 V
control
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6.7 AC Characteristics
TA= –40°C to 125°C, VCC = 24 V, RL= 8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
200 mVPP ripple at 1 kHz,
KSVR Power supply ripple rejection –70 dB
Gain = 20 dB, inputs AC-coupled to AGND
POContinuous output power THD+N = 10%, f = 1 kHz, VCC = 16 V 15 W
THD+N Total harmonic distortion + noise VCC = 16 V, f = 1 kHz, PO= 7.5 W (half-power) 0.1%
65 µV
VnOutput integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB –80 dBV
Crosstalk VO= 1 VRMS, Gain = 20 dB, f = 1 kHz –100 dB
Maximum output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 102 dB
Gain = 20 dB, A-weighted
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 °C
Thermal hysteresis 15 °C
6.8 AC Characteristics
TA= –40°C to 125°C, VCC = 12 V, RL= 8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
200 mVPP ripple from 20 Hz–1 kHz,
KSVR Supply ripple rejection –70 dB
Gain = 20 dB, inputs AC-coupled to AGND
POContinuous output power THD+N = 10%, f = 1 kHz; VCC = 13 V 10 W
THD+N Total harmonic distortion + noise RL= 8 Ω, f = 1 kHz, PO= 5 W (half-power) 0.06%
65 µV
VnOutput integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB –80 dBV
Crosstalk Po= 1 W, Gain = 20 dB, f = 1 kHz –100 dB
Maximum output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 102 dB
Gain = 20 dB, A-weighted
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 °C
Thermal hysteresis 15 °C
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f − Frequency − Hz
20 100 1k 10k
THD − T
otal Harmonic Distortion − %
0.001
0.1
10
20k
0.01
1
G005
PO= 10 W
PO= 5 W
Gain = 20 dB
VCC = 18 V
ZL= 6 Ω+ 47 µH
PO= 1 W
f − Frequency − Hz
20 100 1k 10k
THD − T
otal Harmonic Distortion − %
0.001
0.1
10
20k
0.01
1
G006
PO= 1 W
PO= 5 W
PO= 10 W
Gain = 20 dB
VCC = 12 V
ZL= 4 Ω+ 33 µH
f − Frequency − Hz
20 100 1k 10k
THD − T
otal Harmonic Distortion − %
0.001
0.1
10
20k
0.01
1
G003
PO= 1 W
PO= 10 W
PO= 5 W
Gain = 20 dB
VCC = 24 V
ZL= 8 Ω+ 66 µH
f − Frequency − Hz
20 100 1k 10k
THD − T
otal Harmonic Distortion − %
0.001
0.1
10
20k
0.01
1
G004
PO= 0.5 W
PO= 5 W
PO= 2.5 W
Gain = 20 dB
VCC = 12 V
ZL= 6 Ω+ 47 µH
f − Frequency − Hz
20 100 1k 10k
THD − T
otal Harmonic Distortion − %
0.001
0.1
10
20k
0.01
1
G001
PO= 0.5 W
PO= 5 W
PO= 2.5 W
Gain = 20 dB
VCC = 12 V
ZL= 8 Ω+ 66 µH
f − Frequency − Hz
20 100 1k 10k
THD − T
otal Harmonic Distortion − %
0.001
0.1
10
20k
0.01
1
G002
PO= 1 W
PO= 10 W
PO= 5 W
Gain = 20 dB
VCC = 18 V
ZL= 8 + 66 µHΩ
TPA3110D2-Q1
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SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
6.9 Typical Characteristics
All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the
measurements.
Figure 1. Total Harmonic Distortion vs Frequency (BTL) Figure 2. Total Harmonic Distortion vs Frequency (BTL)
Figure 3. Total Harmonic Distortion vs Frequency (BTL) Figure 4. Total Harmonic Distortion vs Frequency (BTL)
Figure 5. Total Harmonic Distortion vs Frequency (BTL) Figure 6. Total Harmonic Distortion vs Frequency (BTL)
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PO− Output Power − W
0.01 0.1 1 10
THD+N − T
otal Harmonic Distortion + Noise − %
0.001
0.1
10
50
0.01
1
G011
f = 1 kHz
Gain = 20 dB
VCC = 18 V
ZL= 6 Ω+ 47 µH
f = 20 Hz
f = 10 kHz
PO− Output Power − W
0.01 0.1 1 10
THD+N − T
otal Harmonic Distortion + Noise − %
0.001
0.1
10
50
0.01
1
G012
f = 20 Hz
f = 10 kHz
Gain = 20 dB
VCC = 12 V
ZL= 4 Ω+ 33 µH
f = 1 kHz
PO− Output Power − W
0.01 0.1 1 10
THD+N − T
otal Harmonic Distortion + Noise − %
0.001
0.1
10
50
0.01
1
G009
f = 20 Hz
f = 10 kHz
f = 1 kHz
Gain = 20 dB
VCC = 24 V
ZL= 8 Ω+ 66 µH
PO− Output Power − W
0.01 0.1 1 10
THD+N − T
otal Harmonic Distortion + Noise − %
0.001
0.1
10
50
0.01
1
G010
f = 1 kHz
f = 10 kHz
Gain = 20 dB
VCC = 12 V
ZL= 6 Ω+ 47 µH
f = 20 Hz
PO− Output Power − W
0.01 0.1 1 10
THD+N − T
otal Harmonic Distortion + Noise − %
0.001
0.1
10
50
0.01
1
G007
f = 1 kHz
f = 10 kHz
Gain = 20 dB
VCC = 12 V
ZL= 8 Ω+ 66 µH
f = 20 Hz
TPA3110D2-Q1
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
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Typical Characteristics (continued)
All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the
measurements.
Lighter color represents thermally limited region.
Figure 8. Total Harmonic Distortion + Noise vs Output
Figure 7. Total Harmonic Distortion + Noise vs Output Power (BTL)
Power (BTL)
Figure 9. Total Harmonic Distortion + Noise vs Output Figure 10. Total Harmonic Distortion + Noise vs Output
Power (BTL) Power (BTL)
Figure 11. Total Harmonic Distortion + Noise vs Output Figure 12. Total Harmonic Distortion + Noise vs Output
Power (BTL) Power (BTL)
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VCC − Supply Voltage − V
0
5
10
15
20
25
6 8 10 12 14 16 18
PO− Output Power − W
G017
THD = 10%
THD = 1%
Gain = 20 dB
ZL= 4 Ω+ 33 µH
PO− Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30 35 40
h − Efficiency − %
G018
VCC = 12 V VCC = 18 V VCC = 24 V
Gain = 20 dB
ZL= 8 Ω+ 66 µH
f − Frequency − Hz
Phase − °
100
50
0
−300
0
5
10
15
20
25
30
35
40
Gain − dB
−50
−100
−150
20 100 10k 100k
1k
G015
Phase
Gain
−200
−250
CI= 1 µF
Gain = 20 dB
Filter = Audio Precision AUX-0025
VCC = 12 V
VI= 0.1 Vrms
ZL= 8 Ω+ 66 µH
VCC − Supply Voltage − V
0
5
10
15
20
25
30
6 8 10 12 14 16 18 20 22 24 26
PO− Output Power − W
G016
THD = 10%
THD = 1%
Gain = 20 dB
ZL= 8 Ω+ 66 µH
VPLIMIT − PLIMIT Voltage − V
0
2
4
6
8
10
12
14
16
0.0 0.5 1.0 1.5 2.0 2.5 3.0
PO(Max) − Maximum Output Power − W
G013
Gain = 20 dB
VCC = 24 V
ZL= 8 Ω+ 66 µH
VPLIMIT − PLIMIT Voltage − V
0
5
10
15
20
25
30
35
0 1 2 3 4 5 6
PO− Output Power − W
G014
Gain = 20 dB
VCC = 12 V
ZL= 4 Ω+ 33 µH
TPA3110D2-Q1
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SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Typical Characteristics (continued)
All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the
measurements.
Note: Dashed lines represent thermally limited regions.
Figure 13. Maximum Output Power vs PLIMIT Voltage (BTL) Figure 14. Output Power vs PLIMIT Voltage (BTL)
Note: Dashed lines represent thermally limited regions.
Figure 16. Output Power vs Supply Voltage (BTL)
Figure 15. Gain/Phase vs Frequency (BTL)
Note: Dashed lines represent thermally limited regions. Note: Dashed lines represent thermally limited regions.
Figure 17. Output Power vs Supply Voltage (BTL) Figure 18. Efficiency vs Output Power (BTL)
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PO− Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25
h − Efficiency − %
G034
VCC = 12 V
Gain = 20 dB
LC Filter = 22 µH + 0.68 µF
RL= 4 Ω
PO(Tot) − Total Output Power − W
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
0 5 10 15 20 25 30 35 40
ICC − Supply Current − A
G021
VCC = 12 V
VCC = 18 V
VCC = 24 V
Gain = 20 dB
ZL= 8 Ω+ 66 µH
PO− Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25
h − Efficiency − %
G033
VCC = 12 V
VCC = 18 V
Gain = 20 dB
LC Filter = 22 µH + 0.68 µF
RL= 6 Ω
PO− Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 3 6 9 12 15 18
h − Efficiency − %
G020
VCC = 12 V
Gain = 20 dB
ZL= 4 Ω+ 33 µH
PO− Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25
h − Efficiency − %
G032
VCC = 12 V VCC = 18 V
VCC = 24 V
Gain = 20 dB
LC Filter = 22 µH + 0.68 µF
RL= 8 Ω
PO− Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25
h − Efficiency − %
G019
VCC = 12 V VCC = 18 V
Gain = 20 dB
ZL= 6 Ω+ 47 µH
TPA3110D2-Q1
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com
Typical Characteristics (continued)
All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the
measurements.
Note: Dashed lines represent thermally limited regions.
Figure 19. Efficiency vs Output Power (BTL With LC Filter) Figure 20. Efficiency vs Output Power (BTL)
Figure 21. Efficiency vs Output Power (BTL With LC Filter) Figure 22. Efficiency vs Output Power (BTL)
Note: Dashed lines represent thermally limited regions.
Figure 23. Efficiency vs Output Power (BTL With LC Filter) Figure 24. Supply Current vs Total Output Power (BTL)
10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: TPA3110D2-Q1
PO− Output Power − W
0.01 0.1 1 10
THD+N − T
otal Harmonic Distortion + Noise − %
0.001
0.1
10
50
0.01
1
G026
f = 20 Hz
f = 10 kHz
f = 1 kHz
Gain = 20 dB
VCC = 24 V
ZL= 4 Ω+ 33 µH
f − Frequency − Hz
Phase − °
100
50
0
−300
0
5
10
15
20
25
30
35
40
Gain − dB
−50
−100
−150
20 100 10k 100k
1k
G027
Phase
Gain
−200
−250
CI= 1 µF
Gain = 20 dB
Filter = Audio Precision AUX-0025
VCC = 24 V
VI= 0.1 Vrms
ZL= 8 Ω+ 66 µH
f − Frequency − Hz
20 100 1k 10k
THD − T
otal Harmonic Distortion − %
0.001
0.1
10
20k
0.01
1
G025
PO= 0.5 W
PO= 5 W
PO= 2.5 W
Gain = 20 dB
VCC = 24 V
ZL= 4 Ω+ 33 µH
−120
−100
−80
−60
−40
−20
0
f − Frequency − Hz
KSVR − Supply Ripple Rejection Ratio − dB
20 100 1k 10k 20k
G024
Gain = 20 dB
Vripple = 200 mVpp
ZL= 8 Ω+ 66 µH
VCC = 12 V
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
f − Frequency − Hz
Crosstalk − dB
20 100 1k 10k 20k
G023
Left to Right
Right to Left
Gain = 20 dB
VCC = 12 V
VO= 1 Vrms
ZL= 8 Ω+ 66 µH
PO(Tot) − Total Output Power − W
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
0 5 10 15 20 25 30
ICC − Supply Current − A
G022
VCC = 12 V
Gain = 20 dB
ZL= 4 Ω+ 33 µH
TPA3110D2-Q1
www.ti.com
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Typical Characteristics (continued)
All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the
measurements.
Note: Dashed lines represent thermally limited regions.
Figure 26. Crosstalk vs Frequency (BTL)
Figure 25. Supply Current vs Total Output Power (BTL)
Figure 27. Supply Ripple Rejection Ratio vs Frequency Figure 28. Total Harmonic Distortion vs Frequency (PBTL)
(BTL)
Figure 29. Total Harmonic Distortion + Noise vs Output Figure 30. Gain/Phase vs Frequency (PBTL)
Power (PBTL)
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Product Folder Links: TPA3110D2-Q1
PO− Output Power − W
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
0 5 10 15 20 25 30 35 40 45
ICC − Supply Current − A
G030
VCC = 12 V
Gain = 20 dB
ZL= 4 Ω+ 33 µH
VCC = 18 V
−120
−100
−80
−60
−40
−20
0
f − Frequency − Hz
KSVR − Supply Ripple Rejection Ratio − dB
20 100 1k 10k 20k
G031
Gain = 20 dB
Vripple = 200 mVpp
ZL= 8 Ω+ 66 µH
VCC = 12 V
PO− Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30 35 40 45
h − Efficiency − %
G029
Gain = 20 dB
ZL= 4 Ω+ 33 µH
VCC = 12 V
VCC = 18 V
VCC − Supply Voltage − V
0
5
10
15
20
25
30
35
40
6 8 10 12 14 16 18 20
PO− Output Power − W
G028
THD = 10%
THD = 1%
Gain = 20 dB
ZL= 4 Ω+ 33 µH
TPA3110D2-Q1
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com
Typical Characteristics (continued)
All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the
measurements.
Note: Dashed lines represent thermally limited regions.
Figure 32. Efficiency vs Output Power (PBTL)
Figure 31. Output Power vs Supply Voltage (PBTL)
Figure 33. Supply Current vs Output Power (PBTL) Figure 34. Supply Ripple Rejection Ratio vs Frequency
(PBTL)
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TPA3110D2-Q1
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SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
7 Detailed Description
7.1 Overview
The TPA3110D2-Q1 is AEC-Q100 qualified with a temperature grade 1 (-40°C to 125°C), HBM ESD
classification level H2, and CDM ESD classification level C2. This automotive audio amplifier also features
several protection mechanisms as follows:
• DC Current Detection
– The TPA3110D2-Q1 protects speakers from DC current by reporting a fault on the FAULT pin and turning
the amplifier outputs to a Hi-Z state when a DC current is detected. The PVCC supply must be cycled to
clear this fault.
• Short-Circuit Protection and Automatic Recovery
– The TPA3110D2-Q1 has short circuit protection from the output pins to VCC, GND, or to each other. If a
short circuit is detected, it will be reported on the FAULT pin and the amplifier outputs will be switched to a
Hi-Z state. The fault can be cleared by cycling the SD pin.
• Thermal Protection
– When the die temperature exceeds 150°C (±15°C) the device enters the shutdown state and the amplifier
outputs are disabled. The TPA3110D2-Q1 recovers automatically when the temperature decreases by
15°C
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPA3110D2-Q1
PWM
Logic
Gate
Drive
Gate
Drive
PVCCL
PVCCL
GVDD
PVCCL
PVCCL
BSPL
PGND
OUTPL
OUTNL
PGND
GVDD
BSNL
PWM
Logic
Gate
Drive
Gate
Drive
PVCCL
PVCCL
GVDD
PVCCL
PVCCL
BSNR
PGND
OUTNR
OUTPR
PGND
GVDD
BSPR
LINP
LINN
RINP
RINN
UVLO/OVLO
SC Detect
DC Detect
Thermal
Detect
Startup Protection
Logic
Biases and
References
FAULT
SD
GAIN0
PLIMIT
AGND
AVCC
GAIN1
Gain
Control
TTL
Buffer
Ramp
Generator
AVDD
GVDD
GVDD
LDO
Regulator
Gain
Control PLIMIT
PLIMIT
Reference
PBTL
Gain
Control
TTL
Buffer PBTL
Select
PBTL Select
PBTL Select
OUTPL FB
OUTNL FB
OUTNN FB
OUTNP FB
OUTPR FB
OUTNR FB
OUTNL FB
OUTPL FB
PLIMIT
TPA3110D2-Q1
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 DC Detect
TPA3110D2-Q1 has circuitry which protects the speakers from DC current which might occur due to defective
capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault is reported on the
FAULT pin as a low state. The DC detect fault also causes the amplifier to shut down by changing the state of
the outputs to Hi-Z. To clear the DC detect it is necessary to cycle the PVCC supply. Cycling SD does NOT clear
a DC detect fault.
A DC detect fault is issued when the output differential duty-cycle of either channel exceeds 14% (for example,
57%, –43%) for more than 420 msec at the same polarity. This feature protects the speaker from large DC
currents or AC currents less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low
at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive
and negative inputs to avoid nuisance DC detect faults.
The minimum differential input voltages required to trigger the DC detect are shown in Table 1. The inputs must
remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect.
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Product Folder Links: TPA3110D2-Q1
TPA3110D2-Q1
www.ti.com
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Table 1. DC Detect Threshold
AV (dB) VIN (mV, Differential)
20 112
26 56
32 28
36 17
7.3.2 Short-Circuit Protection and Automatic Recovery Feature
TPA3110D2-Q1 has protection from overcurrent conditions caused by a short circuit on the output stage. The
short-circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a
Hi-Z state when the short-circuit protection latch is engaged. The latch can be cleared by cycling the SD pin
through the low state.
If automatic recovery from the short-circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This allows the FAULT pin function to automatically drive the SD pin low, which clears the short-circuit
protection latch.
7.3.3 Thermal Protection
Thermal protection on the TPA3110D2-Q1 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device
begins normal operation at this point with no external system interaction.
Thermal protection faults are NOT reported on the FAULT terminal.
7.3.4 GVDD Supply
The GVDD supply is used to power the gates of the output full bridge transistors. It can also be used to supply
the PLIMIT voltage divider circuit. Add a 1-μF capacitor to ground at this pin.
7.4 Device Functional Modes
7.4.1 PBTL Select
Use the PBTL pin to select between PBTL mode when held high or BTL mode when held low. Connect the
speaker between the right and left outputs, with the positive and negative output from each channel tied together.
7.4.2 Gain Setting Through GAIN0 and GAIN1 Inputs
The gain of the TPA3110D2-Q1 is set to one of four options by the state of the GAIN0 and GAIN1 pins.
Changing the gain setting also changes the input impedance of the TPA3110D2-Q1.
Refer to Table 2 for a list of the gain settings.
Table 2. Gain Setting
AMPLIFIER GAIN (dB) INPUT IMPEDANCE (kΩ)
GAIN1 GAIN0 TYP TYP
0 0 20 60
0 1 26 30
1 0 32 15
1 1 36 9
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Product Folder Links: TPA3110D2-Q1
LP
L S
OUT
L
2
Rx V
R + 2 x R
P = for unclipped power
2 x R
æ ö
æ ö
ç ÷
ç ÷
ç ÷
è ø
è ø
TPA3110D2-Q1
Power Limit Function
Vin=1.13 Freq=1kHz RLoad=8WVPP
PLIMIT = 1.8V Pout = 5W
PLIMIT = 3V Pout = 10W
PLIMIT = 6.96V Pout = 11.8W
Vinput
TPA3110D2-Q1
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com
7.4.3 SD Operation
The SD pin can be used to enter the shutdown mode which mutes the amplifier and causes the TPA3110D2-Q1
to enter a low-current state. This mode can also be triggered to improve power-off pop performance.
7.4.4 PLIMIT
The PLIMIT pin limits the output peak-to-peak voltage based on the voltage supplied to the PLIMIT pin. The peak
output voltage is limited to four times the voltage at the PLIMIT pin.
Figure 35. PLIMIT Circuit Operation
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply
connected to PVCC. This virtual rail is four times the voltage at the PLIMIT pin. This output voltage can be used
to calculate the maximum output power for a given maximum input voltage and speaker impedance.
(1)
Where:
RSis the total series resistance including RDS(on), and any resistance in the output filter.
RLis the load resistance.
VPis the peak amplitude of the output possible within the supply rail.
VP= 4 × PLIMIT voltage if PLIMIT < 4 × VP
POUT (10%THD) = 1.25 × POUT (unclipped)
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Product Folder Links: TPA3110D2-Q1
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SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Table 3. PLIMIT Typical Operation
OUTPUT POWER Output Voltage
TEST CONDITIONS PLIMIT VOLTAGE (W) Amplitude (VP-P)
PVCC = 24 V, VIN = 1 VRMS, 36.1 (thermally
6.97 43
RL= 8 Ω, Gain = 26 dB limited)
PVCC = 24 V, VIN = 1 VRMS,2.94 15 25.2
RL= 8 Ω, Gain = 26 dB
PVCC = 24 V, VIN = 1 VRMS,2.34 10 20
RL= 8 Ω, Gain = 26 dB
PVCC = 24 V, VIN = 1 VRMS,1.62 5 14
RL= 8 Ω, Gain = 26 dB
PVCC = 24 V, VIN = 1 VRMS,6.97 12.1 27.7
RL= 8 Ω, Gain = 20 dB
PVCC = 24 V, VIN = 1 VRMS,3 23
RL= 8 Ω, Gain = 20 dB
PVCC = 24 V, VIN = 1 VRMS,1.86 5 14.8
RL= 8 Ω, Gain = 20 dB
PVCC = 12 V, VIN = 1 VRMS,6.97 10.55 23.5
RL= 8 Ω, Gain = 20 dB
PVCC = 12 V, VIN = 1 VRMS,1.76 5 15
RL= 8 Ω, Gain = 20 dB
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPA3110D2-Q1
PVCC
PVCC
GAIN1
6
AVCC
7
8AGND
9GVDD
OUTNL
BSNL
BSNR
OUTNR
23
22
21
20
TPA3110D2-Q1
FAULT
2
LINP
3
4LINN
5GAIN0
PVCCL
BSPL
OUTPL
PGND
27
26
25
24
PLIMIT
10
RINN
11
12 RINP
13 NC
PGND
OUTPR
BSPR
PVCCR
19
18
17
16
PBTL
14 PVCCR 15
GND
29
PowerPAD
SD
1PVCCL 28
PVCC
100 μF 0.1 μF 1000 pF
100 μF 0.1 μF 1000 pF
Audio
Source
Control
System
100 kΩ
10 Ω
1 kΩ
FB
FB
0.22 μF
1000 pF
0.22 μF
1000 pF
1 Fm
1 Fm
0.22 μF
FB
FB
1000 pF
1000 pF
0.22 μF
10 kΩ
10 kΩ
1 Fm
1 Fm
1 Fm
1 Fm
1 Fm
TPA3110D2-Q1
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPA3110D1-Q1 device is an automotive class-D audio amplifier. It accepts either a stereo single ended or
differential analog input, amplifies the signal, and drives up to 15W across two bridge tied loads, usually stereo
speakers. Because an analog input is needed, this device is often paired with a codec or audio DAC if the audio
source is digital.
The four digital input/output pins, GAIN0, GAIN1, SD, and FAULT, can be pulled up to PVCC. When connecting
these terminals to PVCC, a 100 kΩ-resistor must be put in series to limit the slew rate. One of four gain settings
is used depending on the configuration of GAIN0 and GAIN1. The SD pin is used to put the device in shutdown
or normal mode. The FAULT pin is used to indicate if a DC detect or short circuit fault was detected. The next
few sections explains design considerations and how to choose the external components.
8.2 Typical Application
Figure 36. Stereo Class-D Amplifier With BTL Output and Single-Ended Inputs With Power Limiting
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Product Folder Links: TPA3110D2-Q1
PVCC
PVCC
GAIN1
6
AVCC
7
8AGND
9GVDD
23
22
21
20
TPA3110D2-Q1
FAULT
2
LINP
3
4LINN
5GAIN0
27
26
25
24
PLIMIT
10
RINN
11
12 RINP
13 NC
19
18
17
16
PBTL
14 15
GND
29
PowerPAD
SD
1 28
PVCC
100 μF 0. 1 μF 1000 pF
100 μF 0.1 μF 1000 pF
Audio
Source
Control
System
100 kΩ
10
100 kW(1)
Ω
1 kΩ
FB
FB
0.47 μF
1000 pF
0.47 μF
1000 pF
AVCC
1 Fm
1 Fm
1 Fm
1 Fm
OUTNL
BSNL
BSNR
OUTNR
PVCCL
BSPL
OUTPL
PGND
PGND
OUTPR
BSPR
PVCCR
PVCCR
PVCCL
AVCC
TPA3110D2-Q1
www.ti.com
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Typical Application (continued)
(1) A 100-kΩresistor is needed if the PVCC slew rate is more than 10 V/ms.
Figure 37. Stereo Class-D Amplifier With PBTL Output and Single-Ended Input
8.2.1 Design Requirements
The typical requirements for designing the external components around the TPA3110D1-Q1 include efficiency
and EMI/EMC performance. For most applications, only a ferrite bead is needed to filter unwanted emissions.
The ripple current is low enough that an LC filter is typically not needed. As the output power increases, causing
the ripple current to increase, an LC filter can be added to improve efficiency. An LC filter can also be added in
cases where additional EMI suppression is needed.
In addition to discussing how to choose a ferrite bead and when to use an LC filter, the following sections also
discuss the input filter and power supply decoupling. The input filter must be chosen with the input impedance of
the amplifier in mind. The cut-off frequency should be chosen so that bass performance is not impacted. Power
supply decoupling is important to ensure that noise from the power line does not impact the audio quality of the
amplifier output.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
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TPA3110D2-Q1
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com
Typical Application (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 TPA3110D2-Q1 Modulation Scheme
The TPA3110D2-Q1 uses a modulation scheme that allows operation without the classic LC reconstruction filter
when the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The OUTP
and OUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty
cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of
OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load
sits at 0 V throughout most of the switching period, reducing the switching current, which reduces any I2R losses
in the load.
See Figure 42 for a plot of the output waveforms.
8.2.2.2 Ferrite Bead Filter Considerations
Using the advanced emissions suppression technology in the TPA3110D2-Q1 amplifier, it is possible to design a
high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to
accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite
bead used in the filter.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, so it is important to select a material that is effective in the 10- to 100-MHz range which is key to
the operation of the Class-D amplifier. Many of the specifications regulating consumer electronics have
emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30-MHz
and above range from appearing on the speaker wires and the power supply lines which are good antennas for
these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the
range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance,
the resonant frequency of the ferrite bead and capacitor filter should be less than 10 MHz.
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In
this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak
current the amplifier sees. If these specifications are not available, it is also possible to estimate the bead current
handling capability by measuring the resonant frequency of the filter output at low power and at maximum power.
A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of tested
ferrite beads that work well with the TPA3110D2-Q1 include 28L0138-80R-10 and HI1812V101R-10 from
Steward and the 742792510 from Wurth Electronics.
A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics works best.
Additional EMC improvements may be obtained by adding snubber networks from each of the Class-D outputs to
ground. Suggested values for a simple RC series snubber network would be 10 Ωin series with a 330-pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the PGND or the PowerPAD™ integrated
circuit package beneath the chip.
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Product Folder Links: TPA3110D2-Q1
FCCClassB
f-Frequency-Hz
830M
LimitLevel-dB V/mm
30M
20
230M 430M 630M
0
40
10
60
30
70
50
TPA3110D2-Q1
www.ti.com
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Typical Application (continued)
Figure 38. TPA3110D2-Q1 EMC Spectrum With FCC Class-B Limits
8.2.2.3 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional Class-D amplifier needs an output filter is because the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is
half the period for the traditional modulation scheme. An ideal LC Filter is needed to store the ripple current from
each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC Filter is almost purely reactive.
The TPA3110D2-Q1 modulation scheme has little loss in the load without a filter because the pulses are short
and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making
the ripple current larger. Ripple current could be filtered with an LC Filter for increased efficiency, but for most
applications the filter is not needed.
An LC Filter with a cutoff frequency less than the Class-D switching frequency allows the switching current to
flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
8.2.2.4 When to Use an Output Filter for EMI Suppression
The TPA3110D2-Q1 has been tested with a simple ferrite bead filter for a variety of applications including long
speaker wires up to 125 cm and high power. The TPA3110D2-Q1 EVM passes FCC Class-B specifications
under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic
second order Butterworth filter similar to those shown in the figures below can be used.
Some systems have little power supply decoupling from the AC line but are also subject to line conducted
interference (LCI) regulations. These include systems powered by wall warts and power bricks. In these cases,
the LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using low
frequency ferrite material can also be effective at preventing line conducted interference.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TPA3110D2-Q1
1nF
Ferrite
ChipBead
OUTP
OUTN
Ferrite
ChipBead
1nF
2.2 mF
15 Hm
15 mH
OUTP
OUTN
L1
L2
C2
C3
2.2 mF
1mF
1mF
33 Hm
33 mH
OUTP
OUTN
L1
L2
C2
C3
TPA3110D2-Q1
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com
Typical Application (continued)
Figure 39. Typical LC Output Filter, Cutoff Frequency Of 27 kHz, Speaker Impedance = 8 Ω
Figure 40. Typical LC Output Filter, Cutoff Frequency Of 27 kHz, Speaker Impedance = 4 Ω
Figure 41. Typical Ferrite Chip Bead Filter (Chip Bead Example)
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Product Folder Links: TPA3110D2-Q1
C =
i
1
2 Z fpi c
f =
c
1
2 Z Cpi i
-3dB
fc
f= 1
2 Z Cpi i
Ci
IN Zi
Zf
Input
Signal
TPA3110D2-Q1
www.ti.com
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Typical Application (continued)
8.2.2.5 Input Resistance
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ±20%, to the
largest value, 60 kΩ±20%. As a result, if a single capacitor is used in the input high-pass filter, the –3 dB or
cutoff frequency may change when changing gain steps.
The –3-dB frequency can be calculated using Equation 2. Use the ZIvalues given in Table 2.
(2)
8.2.2.6 Input Capacitor, CI
In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper DC level for optimum operation. In this case, CIand the input impedance of the amplifier (ZI) form a high-
pass filter with the corner frequency determined in Equation 3.
(3)
The value of CIis important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZIis 60 kΩand the specification calls for a flat bass response down to 20 Hz. Equation 3 is
reconfigured as Equation 4.
(4)
In this example, CIis 0.13 µF; so, one would likely choose a value of 0.15 μF as this value is commonly used. If
the gain is known and is constant, use ZIfrom Table 2 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network (CI) and the feedback network to the load. This
leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the DC level there is held at 3 V, which is likely higher than the source DC level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create DC offset
voltages and it is important to ensure that boards are cleaned properly.
8.2.2.7 BSN and BSP Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 0.22-μF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 0.22-μF capacitor must be
connected from OUTPx to BSPx, and one 0.22-μF capacitor must be connected from OUTNx to BSNx. (See the
application circuit diagram in TPA3110D2-Q1 Simplified Application Schematic .)
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OUTP
OUTN
OUTP
Speaker
Current
OUTP
OUTN
OUTP-OUTN
Speaker
Current
OUTP
OUTN
OUTP-OUTN
Speaker
Current
0V
0V
PVCC
NoOutput
PositiveOutput
NegativeOutput
0A
0A
0V
-PVCC
OUTP-OUTN
TPA3110D2-Q1
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com
Typical Application (continued)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
8.2.2.8 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3110D2-Q1 with a differential source, connect the positive lead of the audio source to the INP input
and the negative lead from the audio source to the INN input. To use the TPA3110D2-Q1 with a single-ended
source, AC-ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP
and apply the audio source to either input. In a single-ended input application, the unused input should be AC-
grounded at the audio source instead of at the device input for best noise performance. For good transient
performance, the impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input DC blocking capacitors to become completely charged during the 14 ms power-up time. If the
input capacitors are not allowed to completely charge, there will be some additional sensitivity to component
matching which can result in pop if the input components are not well matched.
8.2.2.9 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
8.2.3 Application Curve
Figure 42. The TPA3110D2-Q1 Output Voltage and Current Waveforms into an Inductive Load
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SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
9 Power Supply Recommendations
The TPA3110D2-Q1 is a high-performance CMOS audio amplifier that requires adequate power supply
decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply
decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker.
Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of
noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond
wire and copper trace inductances as well as lead frame capacitance, a good quality low equivalent-series-
resistance (ESR) ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be
placed as close to the device PVCC pins and system ground (either PGND pins or PowerPAD™ integrated
circuit package) as possible. For mid-frequency noise due to filter resonances or PWM switching transients as
well as digital hash on the line, another good quality capacitor typically 0.1 μF to 1 µF placed as close as
possible to the device PVCC leads works best.
For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 μF or greater placed
near the audio power amplifier is recommended. The 220-μF capacitor also serves as a local storage capacitor
for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the
power to the output transistors, so a 220-µF or larger capacitor should be placed on each PVCC terminal. A 10-
µF capacitor on the AVCC terminal is adequate. Also, a small decoupling resistor between AVCC and PVCC can
be used to keep high frequency Class-D noise from entering the linear input amplifiers.
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SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
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10 Layout
10.1 Layout Guidelines
The TPA3110D2-Q1 can be used with a small, inexpensive ferrite bead output filter for most applications.
However, since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the
printed circuit board. The following suggestions help to meet EMC requirements.
• Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC terminals as possible. Large (220-µF or greater) bulk power supply decoupling capacitors should
be placed near the TPA3110D2-Q1 on the PVCCL and PVCCR supplies. Local, high-frequency bypass
capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the
thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR
ceramic capacitor between 220 pF and 1000 pF and a larger good quality mid-frequency cap of value
between 0.1 μF and 1 μF to the PVCC connections at each end of the chip.
• Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
PGND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
• Grounding—The AVCC (pin 7) decoupling capacitor should be grounded to analog ground (AGND). The
PVCC decoupling capacitors should connect to PGND. Analog ground and power ground should be
connected at the thermal pad, which should be used as a central ground connection or star ground for the
TPA3110D2-Q1.
• Output filter—The ferrite EMI filter (Figure 41) should be placed as close to the output terminals as possible
for the best EMI performance. The LC Filter (Figure 39 and Figure 40) should be placed close to the outputs.
The capacitors used in both the ferrite and LC Filters should be grounded to power ground.
• Thermal pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35 mm. Seven rows
of solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application
Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB
footprints, see the figures at the end of this data sheet.
For an example layout, see the TPA3110D2-Q1 Evaluation Module User's Guide, SLOU263. Both the EVM
user's guide and the thermal pad application report are available on the TI website at http://www.ti.com.
26 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: TPA3110D2-Q1
SD
FAULT
LINP
LINN
GAIN0
GAIN1
AVCC
AGND
GVDD
PLIMIT
RINN
RINP
NC
PBTL
PVCCL
BSPL
PVCCL
OUTPL
PGND
OUTNL
BSNL
BSNR
OUTNR
PGND
OUTPR
BSPR
PVCCR
PVCCR
Thermal Pad
Connect to PVCC supply
Via
Copper trace/pour
Thermal pad
To PVCC
supply
Large bulk
decoupling
capacitor
Smaller high
frequency
decoupling
capacitors
Smaller high
frequency
decoupling
capacitors Large bulk
decoupling
capacitor
To PVCC
supply
Vias to ground
plane
Ferrite Bead Speaker
Connect to ground
plane layer
Ferrite Bead
Audio input
TPA3110D2-Q1
www.ti.com
SLOS794B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
10.2 Layout Example
Figure 43. TPA3110D2-Q1 Layout Example for PBTL Output
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 27
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
TI PCB Thermal Calculator
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
Maximum Slew Rate on High-Voltage Pins for TPA3111D1, SLUA626
PowerPAD ™ Thermally Enhanced Package,SLMA002
TPA3110D2-Q1 Evaluation Module User's Guide,SLOU263
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
SpeakerGuard, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Sep-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPA3110D2QPWPRQ1 ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPA3110Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Sep-2015
Addendum-Page 2
OTHER QUALIFIED VERSIONS OF TPA3110D2-Q1 :
•Catalog: TPA3110D2
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA3110D2QPWPRQ1 HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Sep-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA3110D2QPWPRQ1 HTSSOP PWP 28 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Sep-2015
Pack Materials-Page 2
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