FAN6754AMRMY - Fairchild - Datasheet.Wiki

April 2012

FAN6754A • Rev. 1.0.3

FAN6754A — Highly Integrated Green-Mode PWM Controller

FAN6754A

Highly Integrated Green- Mode PWM Controller

Brownout and VLimit Adjustment by HV Pin

Features

 High-Voltage Startup

 AC Input Brownout Protection with Hysteresis

 Monitor HV to Adjust VLimit

 Low Operating Current: 1.5mA

 Linearly Decreasing PWM Frequency to 22KHz

 Frequency Hopping to Reduce EMI Emission

 Fixed PWM Frequency: 65KHz

 Peak-Current-Mode Control

 Cycle-by-Cycle Current Limiting

 Leading-Edge Blanking (LEB)

 Internal Open-Loop Protection

 GATE Output Maximum Voltage Clamp: 13V

 VDD Under-Voltage Lockout (UVLO)

 VDD Over-Voltage Protection (OVP)

 Programmable Over-Temperature Protection (OTP)

 Internal Latch Circuit (OVP, OTP)

 Open-Loop Protection (OLP); Restart for MR, Latch

for ML

 SENSE Short-Circuit Protection (SSCP)

 Built-in 8ms Soft-Start Function

Applications

General-purpose switch-mode power supplies and

flyback power converters, including:

 Power Adapters

Description

The highly integrated FAN6754A PWM controller

provides several features to enhance the performance

of flyback converters. To minimize standby power

consumption, a proprietary green-mode function

provides off-time modulation to continuously decrease

the switching frequency under light-load conditions.

Under zero-load and very light-load conditions,

FAN6754A saves PWM pulses by entering deep burst

mode. This burst mode function enables the power

supply to meet international power conservation

requirements.

FAN6754A integrates a frequency-hopping function

internally to reduce EMI emission of a power supply with

minimum line filters. Built-in synchronized slope

compensation is accomplished by proprietary HV

monitor to adjust VLimit for constant output power limit

over universal AC input range. The gate output is

clamped at 13V to protect the external MOSFET from

over-voltage damage.

Other protection functions include AC input brownout

protection with hysteresis, SENSE pin short-circuit

protection, and VDD over-voltage protection. For over-

temperature protection, an external NTC thermistor can

be applied to sense the external switcher’s temperature.

When VDD OVP or OTP are activated, an internal latch

circuit is used to latch-off the controller. The latch mode

is reset when the VDD supply is removed.

FAN6754A is available in an 8-pin SOP package.

Related Resources

 Evaluation Board: FEBFAN6754AMR_CP450v1

Ordering Information

Part Number Operating

Temperature Range Package Packing Method

FAN6754AMRMY -40 to +105°C 8-Pin, Small Outline Package (SOP) Tape & Reel

FAN6754AMLMY

FAN6754A • Rev. 1.0.3 2

FAN6754A — Highly Integrated Green-Mode PWM Controller

Application Diagram

Figure 1. Typical Application

Internal Block Diagram

GATE

SENSE

GND

VDD

RT 5

Startup

Soft

Driver

1.05V

17V/10V

UVLO

Green

Mode

OSC

Blanking

Circuit

OLP

OVP

Delay

Debounce

VDD-OVP

VLimit Adjustment

0.7V

4 3

tD-OTP1

Counter

4.6V

NCHV

Line Voltage

Sample Circuit

Brownout Protection

OTP OLP

Latch

Protection

OVP

OTP

OLP for ML

OLP

Comparator

PWM

Comparator

Internal

BIAS

IRT

tD-OTP2

Counter

Soft-Start

VLimit

Slope

Compensation

Current Limit

Comparator

Soft-Start

Comparator

OLP for MR

Re-Start

Protection

SSCP

Delay 0.05V

SSCP

Comparator

SSCP

Figure 2. Functional Block Diagram

FAN6754A • Rev. 1.0.3 3

FAN6754A — Highly Integrated Green-Mode PWM Controller

F - Fairchild Logo

Z - Plant Code

X - 1-Digit Year Code

Y - 1-Digit Week Code

TT - 2-Digit Die Run Code

T - Package Type (M=SOP)

P - Y: Package (Green)

M - Manufacture Flow Code

Marking Information

Figure 3. Top Mark

Pin Configuration

SOP-8

GND

SENSE

VDD

GATE

Figure 4. Pin Configuration (Top View)

Pin Definitions

Pin # Name Description

1 GND

Ground. This pin is used for the ground potential of all the pins. A 0.1µF decoupling capacitor

placed between VDD and GND is recommended.

2 FB

Feedback. The output voltage feedback information from the external compensation circuit is fed

into this pin. The PWM duty cycle is determined by this pin and the current-sense signal from Pin

6. FAN6754A performs open-loop protection (OLP); if the FB voltage is higher than a threshold

voltage (around 4.6V) for more than 56ms, the controller latches off the PWM.

3 NC

No Connection

4 HV

High-Voltage Startup. This pin is connected to the line input via a 1N4007 and 200kΩ resistor to

achieve brownout and high/low line compensation. Once the voltage on the HV pin is lower than

the brownout voltage, PWM output turns off. High/low line compensation dominates the cycle-by-

cycle current limiting to achieve constant output power limiting with universal input.

5 RT

Over-Temperature Protection. An external NTC thermistor is connected from this pin to GND.

The impedance of the NTC decreases at high temperatures. Once the voltage on the RT pin

drops below the threshold voltage, the controller latches off the PWM. If RT pin is not connected

to NTC resistor for Over-Temperature Protection, a 100KΩ series one resistor is recommended

to ground to prevent from noise interference. This pin is limited by an internal clamping circuit.

6 SENSE

Current Sense. This pin is used to sense the MOSFET current for the current-mode PWM and

current limiting.

7 VDD

Supply Voltage. IC operating current and MOSFET driving current are supplied using this pin.

This pin is connected to an external bulk capacitor of typically 47µF. The threshold voltages for

turn-on and turn-off are 17V and 10V, respectively. The operating current is lower than 2mA.

8 GATE

Gate Drive Output. The totem-pole output driver for the power MOSFET. It is internally clamped

below 13V.

ZXYTT

6754MR

TPM

ZXYTT

6754ML

TPM

FAN6754A • Rev. 1.0.3 4

FAN6754A — Highly Integrated Green-Mode PWM Controller

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VVDD DC Supply Voltage(1,2) 30 V

VFB FB Pin Input Voltage -0.3 7.0 V

VSENSE SENSE Pin Input Voltage -0.3 7.0 V

VRT RT Pin Input Voltage -0.3 7.0 V

VHV HV Pin Input Voltage 500 V

PD Power Dissipation (TA＜50°C) 400 mW

ΘJA Thermal Resistance (Junction-to-Air) 150 °C/W

TJ Operating Junction Temperature -40 +125

°C

TSTG Storage Temperature Range -55 +150 °C

TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 °C

ESD Electrostatic Discharge Capability,

All Pins Except HV Pin

Human Body Model;

JESD22-A114 4500

Charged Device Model;

JESD22-C101 1500

Notes:

1. All voltage values, except differential voltages, are given with respect to the network ground terminal.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

3. ESD with HV pin: CDM=1000V and HBM=500V.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

TA Operating Ambient Temperature -40 +105 °C

RHV HV Startup Resistor 150 200 250 kΩ

FAN6754A • Rev. 1.0.3 5

FAN6754A — Highly Integrated Green-Mode PWM Controller

Electrical Characteristics

VDD=15V and TA=25°C unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

VDD Section

VOP Continuously Operating Voltage 24 V

VDD-ON Start Threshold Voltage 16 17 18 V

VDD-OFF Minimum Operating Voltage 9 10 11 V

VDD-OLP I

DD-OLP Off Voltage 5.5 6.5 7.5 V

VDD-LH Threshold Voltage on VDD Pin for

Latch-Off Release Voltage 3.5 4.0 4.5 V

VDD-AC

Threshold Voltage on VDD Pin for

Disable AC Recovery to Avoid

Startup Failed

VDD-OFF

+2.8

VDD-OFF

+3.3

VDD-OFF

+3.8 V

IDD-ST Startup Current VDD-ON – 0.16V 30 µA

IDD-OP1 Operating Supply Current,

PWM Operation

VDD=20V, FB=3V Gate

Open 1.5 2.0 mA

IDD-OP2 Operating Supply Current,

Gate Stop VDD=20V, FB=3V 1.0 1.5 mA

ILH

Operating Current at PWM-Off

Phase Under Latch-Off

Conduction

VDD=5V 30 60 90 µA

IDD-OLP Internal Sink Current Under Latch-

Off Conduction VDD-OLP+0.1V 170 200 230 µA

VDD-OVP V

DD Over-Voltage Protection 24 25 26 V

tD-VDDOVP VDD Over-Voltage Protection

Debounce Time 75 165 255 µs

HV Section

IHV Supply Current from HV Pin VAC=90V(VDC=120V),

VDD=0V 2.0 3.5 5.0 mA

IHV-LC Leakage Current after Startup HV=700V, VDD=VDD-

OFF+1V 1 20 µA

VAC-OFF Brownout Threshold

DC Source Series

R=200kΩ to HV Pin

See Equation 1

92 102 112 V

VAC-ON Brownin Threshold

DC Source Series

R=200kΩ to HV Pin

See Equation 2

104 114 124 V

ΔVAC VAC-ON - VAC-OFF DC Source Series

R=200kΩ to HV Pin 6 12 18 V

tS-CYCLE Line Voltage Sample Cycle FB > VFB-N 220

µs

FB < VFB-G 650

tH-TIME Line Voltage Hold Period 20 µs

tD-AC-OFF PWM Turn-off Debounce Time FB > VFB-N 65 75 85 ms

FB < VFB-G 180 235 290 ms

Continued on page the following page…

FAN6754A • Rev. 1.0.3 6

FAN6754A — Highly Integrated Green-Mode PWM Controller

Figure 5. Brownout Circuit

Gate

VIN-OFF

VIN-ON

Brownout debounce time

VIN

Gate start Gate stop

Figure 6. Brownout Behavior

Figure 7. VDD-AC and AC Recovery

FAN6754A • Rev. 1.0.3 7

FAN6754A — Highly Integrated Green-Mode PWM Controller

Electrical Characteristics (Continued)

VDD=15V and TA=25°C unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

Oscillator Section

fOSC Frequency in Normal Mode Center Frequency 61 65 69

KHz

Hopping Range ±3.7 ±4.2 ±4.7

tHOP Hopping Period FB > VFB-N 3.9 4.4 4.9 ms

FB=VFB-G 10.2 11.5 12.8 ms

fOSC-G Green-Mode Frequency 19 22 25 KHz

fDV Frequency Variation vs. VDD Deviation VDD=11V to 22V 5 %

fDT Frequency Variation vs. Temperature Deviation TA=-40 to +105°C 5 %

Feedback Input Section

AV Input Voltage to Current-Sense Attenuation 1/4.5 1/4.0 1/3.5 V/V

ZFB Input Impedance 14 16 18 kΩ

VFB-OPEN Output High Voltage FB Pin Open 4.8 5.0 5.2 V

VFB-OLP FB Open-Loop Trigger Level 4.3 4.6 4.9 V

tD-OLP Delay Time of FB Pin Open-Loop Protection 50 56 62 ms

VFB-N Green-Mode Entry FB Voltage

Pin, FB Voltage

(FB =VFB-N) 2.6 2.8 3.0 V

Hopping Range ±3.7 ±4.2 ±4.7 kHz

VFB-G Green-Mode Ending FB Voltage

Pin, FB Voltage

(FB =VFB-G) 2.1 2.3 2.5 V

Hopping Range ±1.27 ±1.45 ±1.62 kHz

VFB-ZDCR FB Threshold Voltage for Zero-Duty Recovery 1.9 2.1 2.3 V

VFB-ZDC FB Threshold Voltage for Zero-Duty 1.8 2.0 2.2 V

Continued on the following page…

Figure 8. VFB vs. PWM Frequency

PWM Frequency

fOSC

fOSC-G

VFB-N

VFB-G

VFB-ZDC VFB

VFB-ZDCR

FAN6754A • Rev. 1.0.3 8

FAN6754A — Highly Integrated Green-Mode PWM Controller

Electrical Characteristics (Continued)

VDD=15V and TA=25°C unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Unit

Current-Sense Section

tPD Delay to Output 100 250 ns

tLEB Leading-Edge Blanking Time 230 280 330 ns

VLimit-L Current Limit at Low Line (VAC=86V) VDC=122V, Series R=200kΩ

to HV 0.43 0.46 0.49 V

VLimit-H Current Limit at High Line (VAC=259V) VDC=366V, Series R=200kΩ

to HV 0.36 0.39 0.42 V

VSSCP Threshold Voltage for SENSE Short-Circuit Protection 0.03 0.05 0.07 V

tON-SSCP On Time for VSSCP Checking 4.0 4.4 4.8 µs

tD-SSCP Delay for SENSE Short-Circuit Protection VSENSE<0.05V 60 120 180 µs

tSS Soft-Start Time Startup Time 7 8 9 ms

GATE Section

DCYMAX Maximum Duty Cycle 86 89 92 %

VGATE-L Gate Low Voltage VDD=15V, IO=50mA 1.5 V

VGATE-H Gate High Voltage VDD=12V, IO=50mA 8 V

IGATE-SINK Gate Sink Current(4) VDD=15V 300 mA

IGATE-

SOURCE Gate Source Current(4) VDD=15V, GATE=6V 250 mA

tr Gate Rising Time VDD=15V, CL=1nF 100

tf Gate Falling Time VDD=15V, CL=1nF 50

VGATE-

CLAMP Gate Output Clamping Voltage VDD=22V 9 13 17

RT Section

IRT Output Current from RT Pin 92 100 108 µA

VRTTH1 Over-Temperature Protection Threshold

Voltage

0.7V ＜ VRT ＜ 1.05V, after

12ms Latch Off 1.000 1.035 1.070

VRTTH2 VRT ＜ 0.7V, After 100µs

Latch Off 0.65 0.70 0.75

tD-OTP1

Over-Temperature Latch-Off Debounce

VRTTH2 ＜ VRT ＜ VRTTH1

FB > VFB-N 14 16 18

VRTTH2 ＜ VRT ＜ VRTTH1

FB < VFB-G 40 51 62

tD-OTP2 VRT< VRTTH2, FB > VFB-N 110 185 260

µs

VRT< VRTTH2, FB < VFB-G 320 605 890

Note:

4. Guaranteed by design.

FAN6754A • Rev. 1.0.3 9

FAN6754A — Highly Integrated Green-Mode PWM Controller

Typical Performance Characteristics

Figure 9. Startup Current (IDD-ST) vs. Temperature Figure 10. Operation Supply Current (IDD-OP1)

vs. Temperature

Figure 11. Start Threshold Voltage (VDD-ON)

vs. Temperature Figure 12. Minimu m Op erating Voltage (VDD-OFF)

vs. Temperature

Figure 13. Supply Current Drawn from HV Pin (IHV)

vs. Temperature Figure 14. HV Pin Leakage Current After Startup

(IHV-LC) vs. Temperature

Figure 15. Frequency in Normal Mode (fOSC)

vs. Temperature Figure 16. Maximum Duty Cycle (DCYMAX)

vs. Temperature

FAN6754A • Rev. 1.0.3 10

FAN6754A — Highly Integrated Green-Mode PWM Controller

Typical Performance Characteristics (Continued)

Figure 17. FB Open-Loop Trigger Level (VFB-OLP)

vs. Temperature Figure 18. Delay Time of FB Pin Open-Loop

Protection (tD-OLP) vs. Temperature

Figure 19. VDD Over-Voltage Protection (VDD-OVP)

vs. Temperature Figure 20. Output Current from RT Pin (IRT)

vs. Temperature

Figure 21. Over-Temperature Protection Threshold

Voltage (VRTTH1) vs. Temperature Figure 22. Over-Temperature Protection Threshold

Voltage (VRTTH2) vs. Temperature

Figure 23. Brownin (VAC-ON) vs. Temperature Figure 24. Brownout (VAC-OFF) vs. Temperature

FAN6754A • Rev. 1.0.3 11

FAN6754A — Highly Integrated Green-Mode PWM Controller

Functional Description

Startup Current

For startup, the HV pin is connected to the line input

through an external diode and resistor; RHV, (1N4007 /

200KΩ recommended). Peak startup current drawn from

the HV pin is (VAC×2) / RHV and charges the hold-up

capacitor through the diode and resistor. When the VDD

capacitor level reaches VDD-ON, the startup current

switches off. At this moment, the VDD capacitor only

supplies the FAN6754A to keep the VDD until the

auxiliary winding of the main transformer provides the

operating current.

Operating Current

Operating current is around 1.5mA. The low operating

current enables better efficiency and reduces the

requirement of VDD hold-up capacitance.

Green-Mode Operation

The proprietary green-mode function provides off-time

modulation to reduce the switching frequency in light-

load and no-load conditions. VFB, which is derived from

the voltage feedback loop, is taken as the reference.

Once VFB is lower than the threshold voltage (VFB-N), the

switching frequency is continuously decreased to the

minimum green-mode frequency of around 22KHz.

Current Sensing / PWM Current Limiting

Peak-current-mode control is utilized to regulate output

voltage and provide pulse-by-pulse current limiting. The

switch current is detected by a sense resistor into the

SENSE pin. The PWM duty cycle is determined by this

current-sense signal and VFB, the feedback voltage.

When the voltage on the SENSE pin reaches around

VCOMP = (VFB–0.6)/4, the switch cycle is terminated

immediately. VCOMP is internally clamped to a variable

voltage around 0.46V for low-line output power limit.

Leading-Edge Blanking (LEB)

Each time the power MOSFET is switched on, a turn-on

spike occurs on the sense-resistor. To avoid premature

termination of the switching pulse, a leading-edge

blanking time is built in. During this blanking period, the

current-limit comparator is disabled and cannot switch

off the gate driver.

Under-Voltage Lockout (UVLO)

The turn-on and turn-off thresholds are fixed internally at

17V and 10V, respectively. During startup, the hold-up

capacitor must be charged to 17V through the startup

resistor to enable the IC. The hold-up capacitor

continues to supply VDD until the energy can be

delivered from auxiliary winding of the main transformer.

VDD must not drop below 10V during startup. This UVLO

hysteresis window ensures that hold-up capacitor is

adequate to supply VDD during startup.

Gate Output / Soft Driving

The BiCMOS output stage is a fast totem-pole gate

driver. Cross conduction has been avoided to minimize

heat dissipation, increase efficiency, and enhance

reliability. The output driver is clamped by an internal

13V Zener diode to protect power MOSFET transistors

against undesirable gate over voltage. A soft driving

waveform is implemented to minimize EMI.

Soft-Start

For many applications, it is necessary to minimize the

inrush current at startup. The built-in 8ms soft-start

circuit significantly reduces the startup current spike and

output voltage overshoot.

Slope Compensation

The sensed voltage across the current-sense resistor is

used for peak-current-mode control and cycle-by-cycle

current limiting. Built-in slope compensation improves

stability and prevents sub-harmonic oscillation.

FAN6754A inserts a synchronized, positive-going, ramp

at every switching cycle.

Constant Output Power Limit

When the SENSE voltage across sense resistor RSENSE

reaches the threshold voltage, around 0.46V for low-line

condition, the output GATE drive is turned off after a

small delay, tPD. This delay introduces an additional

current proportional to tPD • VIN / LP. Since the delay is

nearly constant regardless of the input voltage VIN,

higher input voltage results in a larger additional current

and the output power limit is higher than under low input

line voltage. To compensate this variation for a wide AC

input range, a power-limiter is controlled by the HV pin

to solve the unequal power-limit problem. The power

limiter is fed to the inverting input of the current limiting

comparator. This results in a lower current limit at high-

line inputs than at low-line inputs.

Brownout and Constant Power Limited by

the HV Pin

Unlike previous PWM controllers, FAN6754A’s HV pin

can detect the AC line voltage brownout function and

adjust the current limit. Using a fast diode and startup

resistor to sample the AC line voltage, the peak value

refreshes and is stored in a register at each sampling

cycle. When internal update time is met, this peak value

is used for brownout and current-limit level judgment.

Equation 1 and 2 calculate the level of brownin or

brownout converted to RMS value. For power saving,

FAN6754A enlarges the sampling cycle to lower the

power loss from HV sampling at light-load condition.

2 / )

1.61.6) (R

0.9V ( (RMS) V

ON- AC

×= (1)

2 / )

1.61.6) (R

0.81V ( (RMS) V HV

OFF- AC +

×= (2)

where RHV is in kΩ.

FAN6754A • Rev. 1.0.3 12

FAN6754A — Highly Integrated Green-Mode PWM Controller

The HV pin can perform current limit to shrink the

tolerance of Over-Current Protection (OCP) under full

range of AC voltage, to linearly current limit curve, as

shown in Figure 25. FAN6754A also shrinks the Vlimit

level by half to lower the I2RSENSE loss to increase the

heavy-load efficiency.

0.38

0.39

0.4

0.41

0.42

0.43

0.44

0.45

0.46

0.47

100 120 140 160 180 200 220 240 260 280 300 320 340 360 380

DC Voltage on HV Pin (V)

Vlimit (V)

Figure 25. Linearly Current Limit Curve

VDD Over-Voltage Protection (OVP)

VDD over-voltage protection prevents damage due to

abnormal conditions. If the VDD voltage is over the over-

voltage protection voltage (VDD-OVP) and lasts for tD-

VDDOVP, the PWM pulses are disabled until VDD drops

below the UVLO, then starts again. Over-voltage

conditions are usually caused by open feedback loops.

Sense-Pin Short-Circuit Protection

The FAN6754A provides safety protection for Limited

Power Source (LPS) tests. When the sense resistor is

shorted by soldering during production, the pulse-by-

pulse current limiting loses efficiency for the purpose of

providing over-power protection for the unit. The unit

may be damaged when the loading is larger than the

maximum load. To protect against a short circuit across

the current-sense resistor, the controller is designed to

immediately shut down if a continuously low voltage

(around 0.05V/120µs) on the SENSE pin is detected.

Thermal Protection

An NTC thermistor, RNTC, in series with resistor RA, can

be connected from the RT pin to ground. A constant

current, IRT, is output from the RT pin. The voltage on

the RT pin can be expressed as VRT=IRT • (RNTC + RPTC),

where IRT is 100µA. At high ambient temperature, RNTC

is smaller, such that VRT decreases. When VRT is less

than 1.035V (VRTTH1), the PWM turns off after 16ms

(tD-OTP1). If VRT is less than 0.7V (VRTTH2), the PWM turns

off after 185µs (tD-OTP2). If the RT pin is not connected to

NTC resistor for over-temperature protection,

connecting a series one 100KΩ resistor to ground to

prevent from noise interference is recommended. This

pin is limited by an internal clamping circuit.

Limited Power Control

The FB voltage increases every time the output of the

power supply is shorted or overloaded. If the FB voltage

remains higher than a built-in threshold for longer than

tD-OLP, PWM output is turned off. As PWM output is

turned off, VDD begins decreasing.

When VDD goes below the turn-off threshold (10V) the

controller is totally shut down and VDD is continuously

discharged to VDD-OLP (6.5V) by I

DD-OLP to lower the

average input power. This is called two-level UVLO. VDD

is cycled again. This protection feature continues as

long as the overloading condition persists. This prevents

the power supply from overheating due to overloading

conditions.

Noise Immunity

Noise on the current sense or control signal may cause

significant pulse-width jitter, particularly in continuous-

conduction mode. Slope compensation helps alleviate

this problem. Good placement and layout practices

should be followed. Avoiding long PCB traces and

component leads, locating compensation and filter

components near the FAN6754A, and increasing the

power MOS gate resistance improve performance.

FAN6754A • Rev. 1.0.3 13

FAN6754A — Highly Integrated Green-Mode PWM Controller

Physical Dimensions

8°

0°

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

LAND PATTERN RECOMMENDATION

SEATING PLANE

0.10 C

GAGE PLANE

x 45°

DETAIL A

SCALE: 2:1

PIN ONE

INDICATOR

MBA0.25

5.60

0.65

1.75

1.27

6.20

5.80

3.81

4.00

3.80

5.00

4.80

(0.33)

1.27

0.51

0.33

0.25

0.10

1.75 MAX

0.25

0.19

0.36

0.50

0.25

R0.10

0.90

0.406 (1.04)

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

Figure 26. 8-Pin Small Outline Package (SOP) Package

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN6754A • Rev. 1.0.3 14

FAN6754A— Highly Integrated Green-Mode PWM Controller