PIC18F25K22-I/SO - MICROCHIP

 2010-2012 Microchip Technology Inc. DS41412F

PIC18(L)F2X/4XK22

Data Sheet

28/40/44-Pin, Low-Power,

High-Performance Microcontrollers

with XLP Technology

DS41412F-page 2  2010-2012 Microchip Technology Inc.

Information contained in this publication regarding device

applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce

and may be supers eded by up dates. I t is you r r es ponsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

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IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

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suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC , PIC micro, PI CSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

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countries.

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MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

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chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

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MPLINK, mTouch, Omniscient Code Generation, PICC,

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rfLAB, Select Mode, Total Endurance, TSHARC,

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All other trademarks mentioned herein are property of their

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Printed on recycled paper.

ISBN: 9781620763131

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and d sPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

 2010-2012 Microchip Technology Inc. DS41412F-page 3

PIC18(L)F2X/4XK22

High-Performance RISC CPU:

• C Compiler Optimized Architecture:

- Optional extended instruct ion set designed to

optimize re-en t ran t code

• Up to 1024 Bytes Data EEPROM

• Up to 64 Kbytes Linear Program Memory

Addressing

• Up to 3896 Bytes Linear Data Memory Address-

ing

• Up to 16 MIPS Operation

• 16-bit Wide Instructions, 8-bit Wide Data Path

• Priority Levels for Interrupts

• 31-Level, Software Accessible Hardware Stack

• 8 x 8 Single-Cycle Hardware Multiplier

Flexible Oscil lator St ructure:

• Precision 16 MHz Internal Oscillator Block:

- Factory calibrated to ± 1%

- Select able frequenc ies, 31 kHz to 16 MHz

- 64 MHz performance available u s ing PLL –

no external components required

• Four Crystal modes up to 64 MHz

• Two External Clock modes up to 64 MHz

• 4X Phase Lock Loo p (PLL)

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock

stops

- Two-Speed Oscillator Start-up

Analog Features:

• Analog-to-Digital Converter (ADC) module:

- 10-bit resolution, up to 30 external channels

- Auto-acquis iti on capability

- Conversion available during Sleep

- Fixed Voltage Reference (FVR) channel

- Independent input multiplexing

• Analog Comparator module:

- Two rail-to-rail analog comparators

- Independent input multiplexing

• Digital-to-Analog Converter (DA C) module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- 5-bit rail-to-rail resistive DAC with positive

and negative reference selection

• Charge Time Measurement U nit (CTMU ) mo dul e:

- Supports capacitive touch sensing f or to uch

screens and capacitive switches

Extreme Low-Power Management

PIC18(L)F2X/4XK22 with XLP:

• Sleep mode: 20 nA, typical

• Watchdog Timer: 300 nA, typical

• Timer1 Oscillator: 800 nA @ 32 kHz

• Peripheral Module Disable

S pecial Microcontr o ller Features:

• 2.3V to 5.5V Operation – PIC18FXXK22 devices

• 1.8V to 3.6V Operation – PIC18LFXXK22 devices

• Self-Programmable under Software Control

• High/Low-Voltage Detection (HLVD) module:

- Programmable 16 -Level

- Interrupt on High/Low-Voltage Detection

• Programmable Brown-out Reset (BOR):

- With software enable option

- Configu rable shutdown in Sleep

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• In-Circuit Serial Programming™ (ICSP™):

- Single-Supply 3V

• In-Circuit Debug (ICD)

Peripheral Highl ights:

• Up to 35 I/O Pins plus 1 Input-Only Pin:

- High-Current Sink /So urc e 25 mA/25 mA

- Three programmable external interrupts

- Four programmable interr upt- on-change

- Nine programmable weak pull-ups

- Programmable slew rate

•SR Latch:

- Multiple Set/Reset input options

• Two Captur e/Compare/PWM (CCP) modules

• Three Enhanc ed C CP (ECCP) modu les :

- One, two or four PWM outputs

- Selectab le pol ari ty

- Programmable dead time

- Auto-Shutdown and Auto-Restart

- PWM steering

• Two Master Synchronous Serial Port (MSSP)

modules:

- 3-wire SPI (supports all 4 modes)

-I

2C™ Master and Slave modes with address

mask

28/40/44-Pin, Low-Power, High-Performance

Microcontrollers with XLP Technology

PIC18(L)F2X/4XK22

DS41412F-page 4  2010-2012 Microchip Technology Inc.

• Two Enhanced Universal Synchronous

Asynchronous Receiver Transmitter (EUSART)

modules:

- Supports RS-485, RS-232 and LIN

- RS-232 operation using internal oscillator

- Auto-Wake-up on B reak

- Auto-Baud Detect

Device

Program

Memory Data Memory

I/O(1)

10-bit

A/D Channels(2)

CCP

ECCP

(Full-Bridge)

ECCP

(Half-Bridge)

MSSP

EUSART

Comparator

CTMU

BOR/LVD

SR Latch

8-bit Timer

16-bit Timer

Flash

(Bytes)

# Single-Word

Instructions

SRAM

(Bytes)

EEPROM

(Bytes)

SPI

I2C™

PIC18(L)F23K22 8K 4096 512 256 25 19 2 1 2 2 2 2 2 Y Y Y 3 4

PIC18(L)F24K22 16K 8192 768 256 25 19 2 1 2 2 2 2 2 YYY34

PIC18(L)F25K22 32K 16384 1536 256 25 19 2 1 2 2 2 2 2 YYY34

PIC18(L)F26K22 64k 32768 3896 1024 25 19 2 1 2 2 2 2 2 YYY34

PIC18(L)F43K22 8K 4096 512 256 36 30 2 2 1 2 2 2 2 YYY34

PIC18(L)F44K22 16K 8192 768 256 36 30 2 2 1 2 2 2 2 YYY34

PIC18(L)F45K22 32K 16384 1536 256 36 30 2 2 1 2 2 2 2 YYY34

PIC18(L)F46K22 64k 32768 3896 1024 36 30 2 2 1 2 2 2 2 YYY34

Note 1: One pin is input only.

2: Channel count includes internal FVR and DAC channels.

 2010-2012 Microchip Technology Inc. DS41412F-page 5

PIC18(L)F2X/4XK22

Pin Diagrams (28-pin )

28-pin PDIP, SOIC, SSOP

14 15

MCLR/VPP/RE3

RA0

RA1

RA2

RA3

RA4

RA5

VSS

RA7

RA6

RC0

RC1

RC2

RC3

RB7/PGD

RB6/PGC

RB5

RB4

RB3

RB2

RB1

RB0

VDD

VSS

RC7

RC6

RC5

RC4

PIC18(L)F2XK22

1011

121314 15

716

232425262728

RC0

RB7/PGD

RB6/PGC

RB5

RB4

RB3

RB2

RB1

RB0

VDD

VSS

RC7

RC6

RC5

RC4

MCLR/VPP/RE3

RA0

RA1

RA2

RA3

RA4

RA5/

VSS

RA7

RA6

RC1

RC2

RC3

PIC18(L)F2XK22

28-pin QFN, UQFN(1)

Note 1: The 28-pin UQFN package is available only for PIC18(L)F23K22 and PIC18(L)F24K22.

PIC18(L)F2X/4XK22

DS41412F-page 6  2010-2012 Microchip Technology Inc.

Pin Diagrams (40-pin)

40-pin PDIP

RB7/PGD

RB6/PGC

RB5

RB4

RB3

RB2

RB1

RB0

VDD

VSS

RD7

RD6

RD5

RD4

RC7

RC6

RC5

RC4

RD3

RD2

MCLR/VPP/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RE0

RE1

RE2

VDD

VSS

RA7

RA6

RC0

RC1

RC2

RC3

RD0

RD1

PIC18(L)F4XK22

RA3

RA2

RA1

RA0

MCLR/VPP/RE3

RB3

PGD/RB7

PGC/RB6

RB5

RB4 RC6

RC5

RC4

RD3

RD2

RD1

RD0

RC3

RC2

RC1

RA6

RA7

VSS

VDD

RE2

RE1

RE0

RA5

RA4

RC7

RD4

RD5

RD6

RD7

VSS

VDD

RB0

RB1

RB2

40-pin UQFN

PIC18(L)F4XK22

RC0

 2010-2012 Microchip Technology Inc. DS41412F-page 7

PIC18(L)F2X/4XK22

Pin Diagrams (44-pin)

44-pin QFN

44-pin TQFP

RA3

RA2

RA1

RA0

MCLR/VPP/RE3

PGD/RB7

PGC/RB6

RB5

RB4

NC RC6

RC5

RC4

RD3

RD2

RD1

RD0

RC3

RC2

RC0

RA6

RA7

VSS

VDD

RE2

RE1

RE0

RA5

RA4

RC7

RD4

RD5

RD6

VSS

VDD

RB0

RB1

RB2

RB3

RD7 5

RC1

PIC18(L)F4XK22

RA3

RA2

RA1

RA0

MCLR/VPP/RE3

RB3

PGD/RB7

PGC/RB6

RB5

RB4

NC RC6

RC5

RC4

RD3

RD2

RD1

RD0

RC3

RC2

RC1

RC0

RA6

RA7

VSS

VDD

RE2

RE1

RE0

RA5

RA4

RC7

RD4

RD5

RD6

RD7

VSS

VDD

RB0

RB1

RB2

PIC18(L)F4XK22

PIC18(L)F2X/4XK22

DS41412F-page 8  2010-2012 Microchip Technology Inc.

TABLE 1: PIC18(L)F2XK22 PIN SUMMARY

28-SSOP, SOIC

28-SPDIP

28-QFN, UQFN

I/O

Analog

Comparator

CTMU

SR Latch

Reference

(E)CCP

EUSART

MSSP

Timers

Interrupts

Pull-up

Basic

2 27 RA0 AN0 C12IN0-

328 RA1 AN1 C12IN1-

4 1 RA2 AN2 C2IN+ VREF-

DACOUT

5 2 RA3 AN3 C1IN+ VREF+

6 3 RA4 C1OUT SRQ CCP5 T0CKI

7 4 RA5 AN4 C2OUT SRNQ HLVDIN SS1

10 7 RA6 OSC2

CLKO

9 6 RA7 OSC1

CLKI

21 18 RB0 AN12 SRI CCP4

FLT0 SS2INT0Y

22 19 RB1 AN10 C12IN3- P1C SCK2

SCL2 INT1 Y

23 20 RB2 AN8 CTED1 P1B SDI2

SDA2 INT2 Y

24 21 RB3 AN9 C12IN2- CTED2 CCP2

P2A(1) SDO2 Y

25 22 RB4 AN11 P1D T5G IOC Y

26 23 RB5 AN13 CCP3

P3A(4)

P2B(3)

T1G

T3CKI(2) IOC Y

27 24 RB6 TX2/CK2 IOC Y PGC

28 25 RB7 RX2/DT2 IOC YPGD

11 8 RC0 P2B(3) SOSCO

T1CKI

T3CKI(2)

T3G

12 9RC1 CCP2

P2A(1) SOSCI

13 10 RC2 AN14 CTPLS CCP1

P1A T5CKI

14 11 RC3 AN15 SCK1

SCL1

15 12 RC4 AN16 SDI1

SDA1

16 13 RC5 AN17 SDO1

17 14 RC6 AN18 CCP3

P3A(4) TX1/CK1

18 15 RC7 AN19 P3B RX1/DT1

126RE3 MCLR

VPP

8 5 VSS

19 16 VSS

20 17 VDD

Note 1: CCP2/P2A multiplexed in fuses.

2: T3CKI multiplexed in fuses.

3: P2B multiplexed in fuses.

4: CCP3/P3A multiplexed in fuses.

 2010-2012 Microchip Technology Inc. DS41412F-page 9

PIC18(L)F2X/4XK22

TABLE 2: PIC18(L)F4XK22 PIN SUMMARY

40-PDIP

40-UQFN

44-TQFP

44-QFN

I/O

Analog

Comparator

CTMU

SR Lat ch

Reference

(E)CCP

EUSART

MSSP

Timers

Interrupts

Pull-up

Basic

2 17 19 19 RA0 AN0 C12IN0-

318 20 20 RA1 AN1 C12IN1-

4192121RA2AN2C2IN+ VREF-

DACOUT

520 22 22 RA3 AN3 C1IN+ VREF+

6 21 23 23 RA4 C1OUT SRQ T0CKI

722 24 24 RA5 AN4 C2OUT SRNQ HLVDIN SS1

14 29 31 33 RA6 OSC2

CLKO

13 28 30 32 RA7 OSC1

CLKI

33 8 8 9 RB0 AN12 SRI FLT0 INT0 Y

34 9 9 10 RB1 AN10 C12IN3- INT1 Y

35 10 10 11 RB2 AN8 CTED1 INT2 Y

36 11 11 12 RB3 AN9 C12IN2- CTED2 CCP2

P2A(1) Y

37 12 14 14 RB4 AN11 T5G IOC Y

38 13 15 15 RB5 AN13 CCP3

P3A(3) T1G

T3CKI(2) IOC Y

39 14 16 16 RB6 IOC Y PGC

40 15 17 17 RB7 IOC YPGD

15 30 32 34 RC0 P2B(4) SOSCO

T1CKI

T3CKI(2)

T3G

16 31 35 35 RC1 CCP2(1)

P2A SOSCI

17 32 36 36 RC2 AN14 CTPLS CCP1

P1A T5CKI

18 33 37 37 RC3 AN15 SCK1

SCL1

23 38 42 42 RC4 AN16 SDI1

SDA1

24 39 43 43 RC5 AN17 SDO1

25 40 44 44 RC6 AN18 TX1

CK1

26 1 1 1 RC7 AN19 RX1

DT1

19 34 38 38 RD0 AN20 SCK2

SCL2

20 35 39 39 RD1 AN21 CCP4 SDI2

SDA2

21 36 40 40 RD2 AN22 P2B(4)

22 37 41 41 RD3 AN23 P2C SS2

27 2 2 2 RD4 AN24 P2D SD02

28 3 3 3 RD5 AN25 P1B

29 4 4 4 RD6 AN26 P1C TX2

CK2

30 5 5 5 RD7 AN27 P1D RX2

DT2

8 23 25 25 RE0 AN5 CCP3

P3A(3)

Note 1: CCP2 multiplexed in fuses.

2: T3CKI multiplexed in fuses.

3: CCP3/P3A multiplexed in fuses.

4: P2B multiplexed in fuses.

PIC18(L)F2X/4XK22

DS41412F-page 10  2010-2012 Microchip Technology Inc.

924 26 26 RE1 AN6 P3B

10 25 27 27 RE2 AN7 CCP5

116 18 18 RE3 YMCLR

VPP

32 7, 26 7

28 7,8

28, 29 VDD

31 6, 27 6

29 6

30, 31 VSS

——12, 13

33, 34 13 NC

TABLE 2: PIC18(L)F4XK22 PIN SUMMARY (CONTINUED)

40-PDIP

40-UQFN

44-TQFP

44-QFN

I/O

Analog

Comparator

CTMU

SR Lat ch

Reference

(E)CCP

EUSART

MSSP

Timers

Interrupts

Pull-up

Basic

Note 1: CCP2 multiplexed in fuses.

2: T3CKI multiplexed in fuses.

3: CCP3/P3A multiplexed in fuses.

4: P2B multiplexed in fuses.

 2010-2012 Microchip Technology Inc. DS41412F-page 11

PIC18(L)F2X/4XK22

Table of Contents

1.0 Device Overview ......................................................................................................................... ..... ...... ...... ...... ..... ...... .......... .. 13

2.0 Oscillator Module (With Fail-Safe Clock Monitor)) ................................................................................... .. ...... ..... ...... ...... ...... .. 27

3.0 Power-Managed Modes..................... .... .. ......... .. .... .. .... .. ......... .. .... .. .... ....... .... .. .... .. ......... .. ....................................................... 47

4.0 Reset......................................................................................................................................................................................... 59

5.0 Memory Organization. ............................................................................................................................................................... 69

6.0 Flash Program Memory..... ............... ............................... ............... ..................... ........... ........................................................... 95

7.0 Data EEPROM Memory............. .......... ............... .......... ............... ..................... ............... ............. ..... ...... ...... ......... ...... ...... .... 10 5

8.0 8 x 8 Hardware Multiplier ........................................................................................................... ...... ..... ...... ...... ..... ...... ...... ...... . 111

9.0 Interrupts.................................................................................................................................................................................. 113

10.0 I/O Ports . ............... .......... ............... ..................... ............... .......... ............... ............................................................................ 135

11.0 Timer0 Module ..................................... .... .. ......... .... .... .. ......... .... .... .... .. ......... .... .... .. ...... .............. ..... .......... ...... ..... ...... ...... ...... 159

12.0 Timer1/3/5 Module with Gate Control.............................. ....... .... .. .. .... .. ....... .. .... .. .... .. ....... .. .... .. . ............. ...... ...... ......... ...... ...... 1 6 3

13.0 Timer2/4/6 Module ....................... .. .... .. .... .. ....... .. .... .. .. .... ....... .. .. .... .. .... ....... .. .. .... .. .. ....... . .............. ..... ...... ...... ...... ..... .......... .... 17 5

14.0 Capture/Compare/PWM Modules ............................... .... ......... .... .... .... ......... .... .... .... ......... .... .... ............................................. 179

15.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module.............................................................................................. 211

16.0 Enhanc ed Universal Sync hronous Asynchronous Receiver Transmitter (EUSART).................................................... .. ...... .. 2 6 7

17.0 Analog-t o-Digital Converter (ADC) Module .. ........................................................................................................................... 297

18.0 Comparator Module.......................... .. .... .. ......... .... .. .... .... ....... .... .. .... .... ....... .... .... .. .... ............................................................... 311

19.0 Charge Time Measurement Unit (CTMU).......................................................................... ...................................................... 321

20.0 SR LATCH................................................................................................................................... ...... ..... ...... .......... ..... ...... ...... .. 337

21.0 Fixed Volta ge Refe rence (FV R ) ........................................................... ..................................... .. ..... ...... ...... ...... ..... ...... ...... .... 34 3

22.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................. 345

23.0 High/Low -Voltage Detect (HLVD)............................................................................................................................................ 349

24.0 Special Features of th e CPU................ ................................................................................................................................... 355

25.0 Instruction Set Summary......................................................................................................................................................... 373

26.0 Development Support.................................................................................................................... ..... ...... ...... ...... ..... ...... ...... .. 423

27.0 Electrical Characteristics......................................................................................................... ...... ..... ...... ...... ...... ......... ...... .... 42 7

28.0 DC and AC Characteristics Graphs and Tables............................. .... ........... .... .... .... ......... .... .... .... ......................................... 467

29.0 Packagin g In fo rmation. ............... ............................................................... .......... ........... ......................................................... 523

Appendix A: Revision History . ........................................................................................................................................................... 545

Appendix B: Device Differences. ....................................................................................................................................................... 546

Index ................................................................................................................................................................................................. 547

The Microchip Web Site.................................................................................................................................................................... 557

Customer Change Notification Service........................................................................... ................ ........ .. ..... ...... ...... ..... ...... ...... ...... 557

Customer Support................................................ ................. ................. ...... ................. .................................................................... 557

Reader Response............................................................................................................................................................................. 558

Product Identification System ........................................................................................................................................................... 559

PIC18(L)F2X/4XK22

DS41412F-page 12  2010-2012 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our pu blications to better s uit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions o r c omm ents regardi ng this publication, please c ontact the M arketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer No tific atio n Syst em

 2010-2012 Microchip Technology Inc. DS41412F-page 13

PIC18(L)F2X/4XK22

1.0 DEVICE OVERVIEW

This do cu me nt co nta i ns dev ic e spec if i c in for m at ion fo r

the following devices:

This family offers the advantages of all PIC18

microcontrollers – namely, high computational

performance at an economical price – with the addition

of high-endurance, Flash program memory. On top of

these features, the PIC18(L)F2X/4XK22 family

introduces design enhancements that make these

microcontrollers a logical choice for many high-

performance, power sensitive applications.

1.1 New Core Features

1.1.1 XLP TECHNOLOGY

All of the devices in the PIC18(L)F2X/4XK22 family

incorporate a range of features that can significantly

reduce power consumption during operation. Key

items include:

•Alternate Run Modes: By clocking the cont roller

from the Timer1 source or the internal oscillator

block, power consumption during code execution

can be reduced by as much as 90%.

•Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still

active . In these st ates, powe r consumptio n can be

reduced even further, to as little as 4% of normal

operation requirements.

•On-the-fly Mode Switch ing: The power-

manage d mode s a re invo ked b y user code d urin g

operation, allowing the user to incorporate power-

saving ideas into their application’s software

design.

•Low Consumption in Key Modules: The power

requirements for both Timer1 and the Watchdog

Timer are minimized. See Section 27.0 “Electri-

cal Characteristics”

for values.

1.1.2 MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

All of the devices in the PIC18(L)F2X/4XK22 family

offer ten different oscillator options, allowing users a

wide range of choices in developing application

hardware. These in clude:

• Four Crystal modes, using crystals or ceramic

resonators

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4

clock output) or one pin (oscillator input, with the

second pin reassigned as general I/O)

• Two External RC Oscillator modes with the same

pin options as the External Clock modes

• An internal oscillator block which contains a

16 MHz HFINTOSC oscillator and a 31 kHz

LFINTOSC oscillator , wh ich together provide eight

user selec t able clock frequenci es , from 31 kHz to

16 MHz. This option frees the two oscillator pins

for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both external and internal oscillator

modes, which allows clock speeds of up to

64 MHz. Used with the internal oscillator, the PLL

give s users a com ple te selec tion of cl ock sp eeds,

from 31 kHz to 64 MHz – all witho ut using an

external crystal or clock circuit.

Besides its availability as a clock source, the internal

oscill ato r blo ck pro vid es a s t ab le reference source th at

gives the family additional features for robust

operation:

•Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a

reference signal provided by the LFINTOSC. If a

clock failure occurs, the controller is switched to

the intern al oscill ator block , allowing f or continue d

operation or a safe application shutdown.

•Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source

from Power-on Reset , or wake-up from Sleep

mode, until the primary clock source is available.

• PIC18F23K22 • PIC18LF23K22

• PIC18F24K22 • PIC18LF24K22

• PIC18F25K22 • PIC18LF25K22

• PIC18F26K22 • PIC18LF26K22

• PIC18F43K22 • PIC18LF43K22

• PIC18F44K22 • PIC18LF44K22

• PIC18F45K22 • PIC18LF45K22

• PIC18F46K22 • PIC18LF46K22

PIC18(L)F2X/4XK22

DS41412F-page 14  2010-2012 Microchip Technology Inc.

1.2 Other S pecial Features

•Memory Endurance: The Flash cells for both

program memory and data EEPROM are rated to

last for many thousands of erase/write cycles – up to

10K for program memory and 100K for EEPROM.

Data retention without refresh is conservatively

estimated to be greater than 40 years.

•Self-programmability: These devices can write

to their own program memory spaces und er inter-

nal sof tware control. By using a bo otloader routine

located in the protected Boot Block at the top of

program memory, it becomes possible to create

an application that can update itself in the field.

•Extended Instruction Set: The PIC18(L)F2X/

4XK22 family introduces an optional extension to

the PIC18 instruction set, which adds eight new

instructions and an Indexed Addressing mode.

This ext ensio n, enabl ed as a de vice c onf igurati on

option, has b een specifi cally des igned to opt imize

re-ent rant appli cation c ode origi nally d eveloped in

high-level languages, such as C.

•Enhanced CCP module: In PWM mode, this

module provides 1, 2 or 4 modulated outputs for

controlling half-bridge and full-bridge drivers.

Other features include:

- Auto-Shutdown, for disabling PWM outputs

on interrupt or other select conditions

- Auto-Restart, to reactivate ou tputs once the

conditi on has clea red

- Output steering to selectively enable one or

more of four outputs to provide the PWM

signal.

•Enhanced Addressable EUSART: This serial

communication module is capable of standard

RS-232 operation an d provides support for th e LIN

bus protocol. Other enhancements include

automatic baud rate detection and a 16-bit Baud

Rate Genera tor for improved res olution. Whe n the

microcontroller is using the internal oscillator

block, the EUSART provides stable operation for

applications that talk to the outside world without

using an external crystal (or its accompanying

power requirement).

•10-bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a

channel to be selected and a conversion to be

initiated without wait ing for a sa mp ling period and

thus, reduce code overhead.

•Extended Watchdog Timer (WDT): This

enhanced version incorporates a 16-bit

postscaler, allowing an extended time-out range

that is sta ble acros s ope rati ng vol tage and

temperature. See Section 27.0 “Electrical

Characteristics” for time-out periods.

• Charge Time Measurement Unit (CTMU)

• SR Lat ch Ou tput:

1.3 Details on Individual Family

Members

Devices in the PIC18(L)F2X/4XK22 family are avail-

able in 28-pin and 40/44-pin packages. The block dia-

gram for the device family is shown in Figure 1-1.

The devices have the following differences:

1. Flash program memory

2. Data Memory SRAM

3. Data Memory EEPROM

4. A /D chan nels

5. I/O ports

6. ECCP modules (Full/Half Bridge)

7. Input Voltage Range/Power Consumption

All other feature s for devi ces in th is fami ly are ide ntical.

These are summarized in Table 1-1.

The pinou ts for all devices are listed in the pin s ummary

tables: Table 1 and Table 2, and I/O description tables:

Table 1-2 and Table 1-3.

 2010-2012 Microchip Technology Inc. DS41412F-page 15

PIC18(L)F2X/4XK22

TABLE 1-1: DEVICE FEATURES

Features PIC18F23K22

PIC18LF23K22 PIC18F24K22

PIC18LF24K22 PIC18F25K22

PIC18LF25K22 PIC18F26K22

PIC18LF26K22 PIC18F43K22

PIC18LF43K22 PIC18F44K22

PIC18LF44K22 PIC18F45K22

PIC18LF45K22 PIC18F46K22

PIC18LF46K22

Program Memory (Bytes) 8192 16384 32768 65536 8192 16384 32768 65536

Program Memory

(Instructions) 4096 8192 16384 32768 4096 8192 16384 32768

Data Memory (Bytes) 512 768 1536 3896 512 768 1536 3896

Data EEPROM Memory (Bytes) 256 256 256 1024 256 256 256 1024

I/O Ports A, B, C, E(1) A, B, C, E(1) A, B, C, E(1) A, B, C, E(1) A, B, C, D, E A, B, C, D, E A, B, C, D, E A, B, C, D, E

Capture/Compare/PWM Mod-

ules (CCP) 22222222

Enhanced CCP Modules (ECCP)

- Half Bridge 22221111

Enhanced CCP Modules (ECCP)

- Full Brid ge 11112222

10-bit Analog-to-Digital Module

(ADC) 2 internal

17 input 2 internal

28 input 2 internal

28 input

Packages 28-pin PDIP

28-pin SOIC

28- pin SSOP

28-pin QFN

28-pin UQFN

28-pin PDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

28-pin UQFN

28-pin PDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

28-pin PDIP

28- pin SOIC

28-pin SSOP

28-pin QFN

40- pin PDIP

40-pin UQFN

44-pin QFN

44-pin TQFP

40-pin PDIP

40-pin UQFN

44-pin QFN

44- pin TQFP

40-pin PDIP

40- pin UQFN

44-pin QFN

44-pin TQFP

40-pin PDIP

40-pin UQFN

44-pin QFN

44-p i n TQ F P

Interrupt Sources 33

T imers (16-bit) 4

Se ri al Commu ni c ations 2 MSSP,

2 EUSART

SR Latch Yes

Charge Time Measurement Unit

Module (CTMU) Yes

Programmable

High/Low-Voltage Detect (HLVD) Yes

Programmable Brown-out Reset

(BOR) Yes

Resets (and Delays) POR, BOR,

RESET Instruction,

S t ack Overflow ,

S tack Underflow

(PWRT, OST),

MCLR, WDT

Instruction Set 75 Instructions;

83 with Extended Instruction Set enabled

Operating Frequency DC - 64 MHz

Note 1: PORTE contains the single RE3 read-only bit.

PIC18(L)F2X/4XK22

DS41412F-page 16  2010-2012 Microchip Technology Inc.

FIGURE 1-1: PIC1 8(L) F2X /4XK2 2 FAMI LY BLOCK DI AGRAM

Instruction

Decode and

Control

Data Latch

Data Memory

Address Latch

Dat a Addr ess<12 >

Access

BSR FSR0

FSR1

FSR2

inc/dec

logic

Address

412 4

PCH PCL

PCLATH

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

BITOP 8

ALU<8>

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

PCLATU

PCU

Note 1: RE3 is only available when MCLR functionality is disabled.

2: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information.

3: Full-Bridge operation for PIC18(L)F4XK22, half-bridge operation for PIC18(L)F2XK22.

EUSART1

Comparators MSSP1 10-bit

ADC

Timer2

Timer1 CTMUTimer0

CCP4

HLVD

ECCP1

BOR Data

EEPROM

Instruction Bus <16>

STKPTR Bank

State machine

control signals

Decode

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1(2)

OSC2(2)

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

MCLR(1)

Block

LFINTOSC

Oscillator

16 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

SOSCO

SOSCI

FVR

DAC

Address Latch

Prog ram Memo ry

(8/16/32/64 Kbytes)

Data Latch

PORTA

RA0:RA7

PORTB

RB0:RB7

PORTC

RC0:RC7

PORTD

RD0:RD7

Timer4

Timer6

Timer3

Timer5

SR Latch

EUSART2

MSSP2CCP5

ECCP2

(3)

C1/C2 ECCP3

PORTE

RE0:RE2

RE3(1)

DAC

 2010-2012 Microchip Technology Inc. DS41412F-page 17

PIC18(L)F2X/4XK22

TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS

Pin Number

Pin Nam e Pin

Type Buffer

Type Description

PDIP,

SOIC QFN,

UQFN

227

RA0/C12IN0-/AN0

RA0 I/O TTL Digital I/O.

C12IN0- I Analog Comparators C1 and C2 inverting input.

AN0 I Analog Analog input 0.

328

RA1/C12IN1-/AN1

RA1 I/O TTL Digital I/O.

C12IN1- I Analog Comparators C1 and C2 inverting input.

AN1 I Analog Analog input 1.

RA2/C2IN+/AN2/DACOUT/VREF-

RA2 I/O TTL Digital I/O.

C2IN+ I Analog Comparator C2 non-inverting input.

AN2 I Analog Analog input 2.

DACOUT O Analog DAC Reference output.

VREF- I Analog A/D reference voltage (low) input.

RA3/C1IN+/AN3/VREF+

RA3 I/O TTL Digital I/O.

C1IN+ I Analog Comparator C1 non-inverting input.

AN3 I Analog Analog input 3.

VREF+ I Analog A/D reference voltage (high) input.

RA4/CCP5/C1OUT/SRQ/T0CKI

RA4 I/O ST Digital I/O.

CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output.

C1OUT O CMO S Comparator C1 output.

SRQ O TTL SR latch Q output.

T0CKI I ST Timer0 external clock input.

RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4

RA5 I/O TTL Digital I/O.

C2OUT O CMO S Comparator C2 output.

SRNQ O TTL SR latch Q output.

SS1 I TTL SP I slave select input (MSSP) .

HLVDIN I Analog High/Low-Voltage Detect input.

AN4 I Analog Analog input 4.

10 7 RA6/CLKO/OSC2

RA6 I/O TTL Digital I/O.

CLKO O In RC mode, OSC2 pin outputs CLKOUT which has

1/4 the frequency of OSC1 and denotes the instruction

cycle rate.

OSC2 O Oscillator crystal output. Connects to crystal or resonator

in Crystal Oscillator mode.

Legend: T TL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power .

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

PIC18(L)F2X/4XK22

DS41412F-page 18  2010-2012 Microchip Technology Inc.

9 6 RA7/CLKI/OSC1

RA7 I/O TTL Digital I/O.

CLKI I CMOS External clock source input. Always associated with pin

function OSC1.

OSC1 I ST O scillator crystal input or external clock source input ST

buffer when configured in RC mode; CMOS otherwise.

21 18 RB0/INT0/CCP4/FLT0/SRI/SS2/AN12

RB0 I/O TTL Digital I/O.

INT0 I ST External interrupt 0.

CCP4 I/O ST Capture 4 input/Compare 4 output/PWM 4 output.

FLT0 I ST PWM Fault input for ECCP Auto-Shutdown.

SRI I S T SR latch input.

SS2 I TTL SP I slave select input (MSSP) .

AN12 I Analog Analog input 12.

22 19 RB1/INT1/P1C/SCK2/SCL2/C12IN3-/AN10

RB1 I/O TTL Digital I/O.

INT1 I ST External interrupt 1.

P1C O CMOS Enhanced CCP1 PWM output.

SCK2 I/O ST Synchronous serial clock input/output for SPI mode

(MSSP).

SCL2 I/O ST Synchronous serial clock input/output for I2C™ mode

(MSSP).

C12IN3- I Analog Comparators C1 and C2 inverting input.

AN10 I Analog Analog input 10.

23 20 RB2/INT2/CTED1/P1B/SDI2/SDA2/AN8

RB2 I/O TTL Digital I/O.

INT2 I ST External interrupt 2.

CTED1 I ST CTMU Edge 1 input.

P1B O CMOS Enhanced CCP1 PWM output.

SDI2 I ST SPI data in (MSSP).

SDA2 I/O ST I2C™ data I/O (MSSP).

AN8 I Analog Analog input 8.

24 21 RB3/CTED2/P2A/CCP2/SDO2/C12IN2-/AN9

RB3 I/O TTL Digital I/O.

CTED2 I ST CTMU Edge 2 input.

P2A O CMOS Enhanced CCP2 PWM output.

CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM 2 output.

SDO2 O — SPI data out (MSSP).

C12IN2- IAnalog Comparators C1 and C2 inverting input.

AN9 I Analog Analog input 9.

TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Nam e Pin

Type Buffer

Type Description

PDIP,

SOIC QFN,

UQFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power .

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

 2010-2012 Microchip Technology Inc. DS41412F-page 19

PIC18(L)F2X/4XK22

25 22 RB4/IOC0/P1D/T5G/AN11

RB4 I/O TTL Digital I/O.

IOC0 I TTL Interrupt-on-change pin.

P1D O CMOS Enhanced CCP1 PWM output.

T5G I S T Timer5 external clock gate input.

AN11 I An alog Analog input 11.

26 23 RB5/IOC1/P2B/P3A/CCP3/T3CKI/T1G/AN13

RB5 I/O TTL Digital I/O.

IOC1 I TTL Interrupt-on-change pin.

P2B(1) O CMOS Enhanced CCP2 PWM output.

P3A(1) O CMOS Enhanced CCP3 PWM output.

CCP3(1) I/O ST Capture 3 input/Compare 3 output/PWM 3 output.

T3CKI(2) I ST Timer3 clock input.

T1G I S T Timer1 external clock gate input.

AN13 I An alog Analog input 13.

27 24 RB6/IOC2/TX2/CK2/PGC

RB6 I/O TTL Digital I/O.

IOC2 I TTL Interrupt-on-change pin.

TX2 O — EUSART asynchronous transmit.

CK2 I/O S T EUSART synchronous clock (see related RXx/DTx).

PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin.

28 25 RB7/IOC3/RX2/DT2/PGD

RB7 I/O TTL Digital I/O.

IOC3 I TTL Interrupt-on-change pin.

RX2 I ST EUSART asynchronous receive.

DT2 I/O ST EUSART synchronous data (see related TXx/CKx).

PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin.

11 8 RC0/P2B/T3CKI/T3G/T1CKI/SOSCO

RC0 I /O TTL Digital I/O.

P2B(2) O CMOS Enhanced CCP1 PWM output.

T3CKI(1) I ST Timer3 clock input.

T3G I S T Timer3 external clock gate input.

T1CKI I ST Timer1 clock input.

SOSCO O — Secondary oscillator output.

12 9 RC1/P2A/CCP2/SOSCI

RC1 I/O TTL Digital I/O.

P2A OCMOS Enhanced CCP2 PWM output.

CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output.

SOSCI I Analog Seco ndary oscillator input.

TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Nam e Pin

Type Buffer

Type Description

PDIP,

SOIC QFN,

UQFN

Legend: T TL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power .

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

PIC18(L)F2X/4XK22

DS41412F-page 20  2010-2012 Microchip Technology Inc.

13 10 RC2/CTPLS/P1A/CCP1/T5CKI/AN14

RC2 I/O TTL Digital I/O.

CTPLS O — CTMU pulse generator output.

P1A O CMOS Enhanced CCP1 PWM output.

CCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 output.

T5CKI I ST Timer5 clock input.

AN14 I Analog Analog input 14.

14 11 RC3/SCK1/SCL1/AN15

RC3 I/O TTL Digital I/O.

SCK1 I/O ST Synchronous serial clock input/output for SPI mode

(MSSP).

SCL1 I/O ST Synchronous serial clock input/output for I2C™ mode

(MSSP).

AN15 I Analog Analog input 15.

15 12 RC4/SDI1/SDA1/AN16

RC4 I/O TTL Digital I/O.

SDI1 I ST SPI data in (MSSP).

SDA1 I/O ST I2C™ data I/O (MSSP).

AN16 I Analog Analog input 16.

16 13 RC5/SDO1/AN17

RC5 I/O TTL Digital I/O.

SDO1 O — SPI data out (MSSP).

AN17 I Analog Analog input 17.

17 14 RC6/P3A/CCP3/TX1/CK1/AN18

RC6 I/O TTL Digital I/O.

P3A(2) O CMOS Enhanced CCP3 PWM output.

CCP3(2) I/O ST Capture 3 input/Compare 3 output/PWM 3 output.

TX1 O — EUSART asynchronous transmit.

CK1 I/O S T EUSART synchronous clock (see related RXx/DTx).

AN18 I Analog Analog input 18.

18 15 RC7/P3B/RX1/DT1/AN19

RC7 I/O TTL Digital I/O.

P3B O CMOS Enhanced CCP3 PWM output.

RX1 I ST EUSART asynchronous receive.

DT1 I/O ST EUSART synchronous data (see related TXx/CKx).

AN19 I Analog Analog input 19.

126 RE3/VPP/MCLRRE3 IST Digital input.

VPP P Programming voltage input.

MCLR I ST Active-Low Master Clear (device Reset) input.

TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Nam e Pin

Type Buffer

Type Description

PDIP,

SOIC QFN,

UQFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power .

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

 2010-2012 Microchip Technology Inc. DS41412F-page 21

PIC18(L)F2X/4XK22

20 17 VDD P — Positive supply for logic and I/O pins.

8, 19 5, 16 VSS P — Ground reference for logic and I/O pins.

TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Nam e Pin

Type Buffer

Type Description

PDIP,

SOIC QFN,

UQFN

Legend: T TL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power .

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS

Pin Number Pin Name Pin

Type Bu ffer

Type Description

PDIP TQFP QFN UQFN

21919 17

RA0/C12IN0-/AN0

RA0 I/O TTL Digital I/O.

C12IN0- I Analog Comparators C1 and C2 inverting input.

AN0 I Analog Analog input 0.

32020 18

RA1/C12IN1-/AN1

RA1 I/O TTL Digital I/O.

C12IN1- I Analog Comparators C1 and C2 inverting input.

AN1 I Analog Analog input 1.

42121 19

RA2/C2IN+/AN2/DACOUT/VREF-

RA2 I/O TTL Digital I/O.

C2IN+ I Analog Comparator C2 non-inverting input.

AN2 I Analog Analog input 2.

DACOUT O Analog DAC Reference output.

VREF- I Analog A/D reference voltage (low) input.

52222 20

RA3/C1IN+/AN3/VREF+

RA3 I/O TTL Digital I/O.

C1IN+ I Analog Comparator C1 non-inverting input.

AN3 I Analog Analog input 3.

VREF+ I Analog A/D reference voltage (high) input.

62323 21

RA4/C1OUT/SRQ/T0CKI

RA4 I/O ST Digit al I/O.

C1OUT OCMOS Comparator C1 output.

SRQ OTTL SR latch Q output.

T0CKI I ST Timer0 external clock input.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or out put; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power .

Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX

and CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,

CCP3MX and CCP2MX are clear.

PIC18(L)F2X/4XK22

DS41412F-page 22  2010-2012 Microchip Technology Inc.

72424 22

RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4

RA5 I/O TTL Digital I/O.

C2OUT OCMOS Comparator C2 output.

SRNQ OTTL SR latch Q output .

SS1 ITTL SPI slave select input (MSSP1).

HLVDIN I Analog High/Low-Voltage Detect input.

AN4 I Analog Analog input 4.

14 31 33 29 RA6/CLKO/OSC2

RA6 I/O TTL Digital I/O.

CLKO O — In RC mode, OSC2 pin outputs CLKOUT which

has 1/4 the frequency of OSC1 and denotes the

ins t r u cti on c y cle r ate.

OSC2 O — Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.

13 30 32 28 RA7/CLKI/OSC1

RA7 I/O TTL Digital I/O.

CLKI I CMOS External clock source input. Always associated

with pin function OSC1.

OSC1 I S T Oscillator crystal input or external clock source

input ST buffer when configured in RC mode;

CMOS otherwise.

33 8 9 8 RB0/INT0/FLT0/SRI/AN12

RB0 I/O TTL Digital I/O.

INT0 I ST External interrupt 0.

FLT0 I ST PWM Fault input for ECCP Auto-Shutdown.

SRI I ST SR latch input.

AN12 I Analog Analog input 12.

34 9 10 9 RB1/INT1/C12IN3-/AN10

RB1 I/O TTL Digital I/O.

INT1 I ST External interrupt 1.

C12IN3- I Analog Comparators C1 and C2 inverting input.

AN10 I Analog Analog input 10.

35 10 11 10 RB2/INT2/CTED1/AN8

RB2 I/O TTL Digital I/O.

INT2 I ST External interrupt 2.

CTED1 I ST CTMU Edge 1 input.

AN8 I Analog Analog input 8.

36 11 12 11 RB3/CTED2/P2A/CCP2/C12IN2-/AN9

RB3 I/O TTL Digit a l I/O.

CTED2 I ST CTMU Edge 2 input.

P2A(2) O CMOS Enhanced CCP2 PWM output.

CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM 2 output.

C12IN2- I Analog Comparators C1 and C2 inverting input.

AN9 I Analog Analog input 9.

TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number Pin Name Pin

Type Bu ffer

Type Description

PDIP TQFP QFN UQFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or out put; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power .

Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX

and CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,

CCP3MX and CCP2MX are clear.

 2010-2012 Microchip Technology Inc. DS41412F-page 23

PIC18(L)F2X/4XK22

37 14 14 12 RB4/IOC0/T5G/AN11

RB4 I/O TTL Digit a l I/O.

IOC0 I TT L Interrupt-on-change pin.

T5G I S T Timer5 external clock gate input.

AN11 I Analog Analog input 11.

38 15 15 13 RB5/IOC1/P3A/CCP3/T3CKI/T1G/AN13

RB5 I/O TTL Digital I/O.

IOC1 I TT L Interrupt-on-change pin.

P3A(1) O CMOS Enhanced CCP3 PWM output.

CCP3(1) I/O ST Capture 3 input/Compare 3 output/PWM 3 output.

T3CKI(2) I S T Timer3 clock input.

T1G I S T Timer1 external clock gate input.

AN13 I Analog Analog input 13.

39 16 16 14 RB6/IOC2/PGC

RB6 I/O TTL Digital I/O.

IOC2 I TT L Interrupt-on-change pin.

PGC I/O ST In-Circuit Debugger and ICSP™ programm ing

clock pin.

40 17 17 15 RB7/IOC3/PGD

RB7 I/O TTL Digital I/O.

IOC3 I TT L Interrupt-on-change pin.

PGD I/O ST In-Circuit Debugger and ICSP™ programm ing

data pin.

15 32 34 30 RC0/P2B/T3CKI/T3G/T1CKI/SOSCO

RC0 I/O ST Digital I/O.

P2B(2) O CMOS Enhanced CCP1 PWM output.

T3CKI(1) I S T Timer3 clock input.

T3G I S T Timer3 external clock gate input.

T1CKI I ST Timer1 clock input.

SOSCO O — Secondary oscillator output.

16 35 35 31 RC1/P2A/CCP2/SOSCI

RC1 I/O ST Digital I/O.

P2A(1) OCMOS Enhanced CCP2 PWM output.

CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output.

SOSCI I Analog Seconda ry oscillator input.

17 36 36 32 RC2/CTPLS/P1A/CCP1/T5CKI/AN14

RC2 I/O ST Digital I/O.

CTPLS O — CTMU pulse generator output.

P1A O CMOS Enhanced CCP1 PWM output.

CCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 output.

T5CKI I ST Timer5 clock input.

AN14 IAnalog Analog input 14.

TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number Pin Name Pin

Type Bu ffer

Type Description

PDIP TQFP QFN UQFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or out put; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power .

Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX

and CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,

CCP3MX and CCP2MX are clear.

PIC18(L)F2X/4XK22

DS41412F-page 24  2010-2012 Microchip Technology Inc.

18 37 37 33 RC3/SCK1/SCL1/AN15

RC3 I/O ST Digital I/O.

SCK1 I/O ST Synchronous serial clock input/out put for SPI

mode (MSSP).

SCL1 I/O ST Synchronous serial clock input/out put for I2C™

mode (MSSP).

AN15 I Analog Analog input 15.

23 42 42 38 RC4/SDI1/SDA1/AN16

RC4 I/O ST Digital I/O.

SDI1 I ST SPI data in (MSSP).

SDA1 I/O ST I2C™ data I/O (MSSP ).

AN16 I Analog Analog input 16.

24 43 43 39 RC5/SDO1/AN17

RC5 I/O ST Digital I/O.

SDO1 O — SPI da ta out (MSSP).

AN17 I Analog Analog input 17.

25 44 44 40 RC6/TX1/CK1/AN18

RC6 I/O ST Digital I/O.

TX1 O — EUSART asynchronous transmit.

CK1 I/O ST EUSART synchronous clock (see related RXx/

DTx).

AN18 I Analog Analog input 18.

26 1 1 1 RC7/RX1/DT1/AN19

RC7 I/O ST Digital I/O.

RX1 I ST EUSART asynchronous receive.

DT1 I/O ST EUSART synchronous data (see related TXx/

CKx).

AN19 I Analog Analog input 19.

19 38 38 34 RD0/SCK2/SCL2/AN20

RD0 I/O ST Digital I/O.

SCK2 I/O ST Synchronous serial clock input/out put for SPI

mode (MSSP).

SCL2 I/O ST Synchronous serial clock input/output for I2C™

mode (MSSP).

AN20 I Analog Analog input 20.

20 39 39 35 RD1/CCP4/SDI2/SDA2/AN21

RD1 I/O ST Digital I/O.

CCP4 I/O ST Capture 4 input/Compare 4 output/PWM 4 output.

SDI2 I ST SPI data in (MSSP).

SDA2 I/O ST I2C™ data I/O (MSSP ).

AN21 I Analog Analog input 21.

TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number Pin Name Pin

Type Bu ffer

Type Description

PDIP TQFP QFN UQFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or out put; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power .

Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX

and CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,

CCP3MX and CCP2MX are clear.

 2010-2012 Microchip Technology Inc. DS41412F-page 25

PIC18(L)F2X/4XK22

21 40 40 36 RD2/P2B/AN22

RD2 I/O ST Digital I/O

P2B(1) O CMOS Enhanced CCP2 PWM output.

AN22 I Analog Analog input 22.

22 41 41 37 RD3/P2C/SS2/AN23

RD3 I/O ST Digital I/O.

P2C O CMOS Enhanced CCP2 PWM output.

SS2 I TTL SPI slave select input (MSSP).

AN23 I Analog Analog input 23.

27 2 2 2 RD4/P2D/SDO2/AN24

RD4 I/O ST Digital I/O.

P2D O CMOS Enhanced CCP2 PWM output.

SDO2 O — SPI da ta out (MSSP).

AN24 I Analog Analog input 24.

28 3 3 3 RD5/P1B/AN25

RD5 I/O ST Digital I/O.

P1B O CMOS Enhanced CCP1 PWM output.

AN25 I Analog Analog input 25.

29 4 4 4 RD6/P1C/TX2/CK2/AN26

RD6 I/O ST Digital I/O.

P1C O CMOS Enhanced CCP1 PWM output.

TX2 O — EUSART asynchronous transmit.

CK2 I/O ST EUSART synchronous clock (see related RXx/

DTx).

AN26 I Analog Analog input 26.

30 5 5 5 RD7/P1D/RX2/DT2/AN27

RD7 I/O ST Digital I/O.

P1D O CMOS Enhanced CCP1 PWM output.

RX2 IST EUSART asynchronous receive.

DT2 I/O ST EUS ART synchrono us data (see related TXx/

CKx).

AN27 I Analog Analog input 27.

82525 23

RE0/P3A/CCP3/AN5

RE0 I/O ST Digital I/ O.

P3A(2) O CMOS Enhanced CCP3 PWM output.

CCP3(2) I/O ST Capture 3 input/Compare 3 output/PWM 3 output.

AN5 I Analog Analog input 5.

92626 24

RE1/P3B/AN6

RE1 I/O ST Digital I/ O.

P3B O CMOS Enhanced CCP3 PWM output.

AN6 I Analog Analog input 6.

TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number Pin Name Pin

Type Bu ffer

Type Description

PDIP TQFP QFN UQFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or out put; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power .

Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX

and CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,

CCP3MX and CCP2MX are clear.

PIC18(L)F2X/4XK22

DS41412F-page 26  2010-2012 Microchip Technology Inc.

10 27 27 25 RE2/CCP5/AN7

RE2 I/O ST Digital I/ O.

CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output

AN7 I Analog Analog input 7.

11818 16

RE3/VPP/MCLR

RE3 I ST Digital input.

VPP P Programming voltage input.

MCLR I ST Active-low Master Clear (device Reset) input.

11,32 7, 28 7, 8,

28, 29 7, 26 VDD P— Positive supply for logic and I/O pins.

12,31 6, 29 6,30,

31 6, 27 VSS P — Ground reference for logic and I/O pins.

12,13,

33,34 13 NC

TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number Pin Name Pin

Type Bu ffer

Type Description

PDIP TQFP QFN UQFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or out put; ST = Schmitt Trigger input with CMOS levels;

I = Input; O = Output; P = Power .

Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX

and CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,

CCP3MX and CCP2MX are clear.

 2010-2012 Microchip Technology Inc. DS41412E-page 27

PIC18(L)F2X/4XK22

2.0 OSCILLAT OR M ODULE (WITH

FAIL-SAFE CLOCK MONITOR)

2.1 Overview

The oscillator module has a wide variety of clock

sources and selection features that allo w it to be used

in a wide range of applications while maximizin g perfor-

mance and minimizing power consumption. Figure 2-1

illustrates a block diagram of the oscillator module.

Clock sources can be configured from external

oscilla tors, quartz crystal resonators , ceramic resonators

and Resistor-Capacitor (RC) circuits. In addition, the

system clock sour ce can be c onfigured from one of th ree

internal oscillators, with a choice of speeds selectable via

softw are . Add itio nal clo ck feat ures inc lud e:

• Selectable system clock source between external

or internal sources via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and

code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, EC or RC modes) and switch

automati cally to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources.

The pr imary cloc k module ca n be confi gured to provid e

one of six clock sources as the primary clock.

1. RC External Resistor/C apacitor

2. LP Low-Power Crystal

3. XT Crystal/Resonator

4. INTOSC Internal Oscillator

5. HS High-Speed Crystal/Resonator

6. EC External Clock

The HS and EC oscillator circuits can be optimized for

power co nsumpti on and oscilla tor spee d using sett ings

in FOSC<3:0>. Additional FOSC<3:0> selections

enable RA6 to be used as I/O or CLKO (FOSC/4) for

RC, EC and INTOSC Oscillator modes.

Primary Clock modes are selectable by the

FOSC<3:0> bits of the CONFIG1H Configuration

by these Configuration and register bits:

1. PRICLKEN (CONFIG1H<5>)

2. PRISD (OSCCON2<2>)

3. PLLCFG (CONFIG1H<4>)

4. PLLEN (OSCTUNE<6>)

5. HFOFST (CONFIG3H<3>)

6. IRCF<2:0> (OSCCON<6:4>)

7. MFIOSEL (OSCCON2<4>)

8. INTSRC (OSCTUNE<7>)

The HFINTOSC, MFINTOSC and LFINTOSC are

factory calibrated high, medium and low-frequency

oscillators, respectively, which are used as the internal

clock source s.

PIC18(L)F2X/4XK22

DS41412E-page 28  2010-2012 Microchip Technology Inc.

FIGURE 2-1: SIMPLIFIED OSCILLATOR SYSTEM BLOCK DIAGRAM

Note 1: Details in Figure 2-4.

2: Details in Figure 2-2.

3: Details in Figure 2-3.

4: Details in Table 2-1.

5: The Primary Oscillator MUX uses the INTOSC branch when FOSC<3:0> = 100x.

SOSCO

SOSCI

Secondary

Oscillator

(SOSC)

Secondary Oscillator(1)

OSC2

OSC1

Primary

Oscillator(2)

(OSC)

Primary Oscillator 0

FOSC<3:0>(5)

PLL_Select

(3) (4)

4xPLL

INTOSC

Primary Clock Module

Low-Power Mode

Eve nt Swit c h

(SCS<1:0>)

Secondary

Oscillator

Primary

Clock

INTOSC

Clock Switch MUX

INTOSC

IRCF<2:0>

MFIOSEL INTSRC

HF-16 MHZ

HF-8 MHZ

HF-4 MHZ

HF-2 MHZ

HF-1 MHZ

HF-31.25 kHZ

HF-250 kHZ

HF-500 kHZ

HFINTOSC

MFINTOSC

LFINTOSC

(16 MHz)

(500 kHz)

(31.25 kHz)

INTOSC

Divide

Circuit

Internal Oscillator MUX

(3)

MF-31.25 kHZ

MF-2 50 kHZ

MF-500 kHZ

LF-31. 25 kHz

Internal Oscillator

SOSCOUT

PRICLKEN

PRISD

 2010-2012 Microchip Technology Inc. DS41412E-page 29

PIC18(L)F2X/4XK22

2.2 Oscillator Control

The OSCCON, OSCCON2 and OSCTUNE registers

(Register 2-1 to Register 2-3) control several aspects

of the device clock’s operation, both in full-power

operation and in power-managed modes.

• Main System Clock Selection (SCS)

• Primary Oscillator Circuit Shut d own (PRISD)

• Secondary Oscillator Enable (SOSCGO)

• Primary Clock Frequency 4x multiplier (PLLEN)

• Internal Frequency selection bits (IRCF, INTSRC)

• Clock Status bits (OSTS, HFIOFS, MFIOFS,

LFIOFS. SOSCRUN, PLLRDY)

• Power management selection (IDLEN)

2.2. 1 MAI N SYSTEM CLOCK SELECTION

The System Clock Select bits, SCS<1:0>, select the

main clock source. The available clock sources are

• Primary clock defined by the FOSC<3:0> bits of

CONFIG 1H. The primary clock can be the primary

oscillator, an external clock, or the internal

oscillator block.

• Secondary clock (secondary oscillator)

• Internal oscillato r block (HF INTOSC, MFINTOSC

and LFINTOSC).

The clock source changes immediately after one or

more of the bits is written to, following a brief clock

transition interval. The SCS bits are cleared to select

the primary clock on all forms of Reset.

2.2.2 INTERNAL FREQUENCY

SELECTION

The Internal Oscillator Frequency Select bits

(IRCF<2:0 >) selec t the fr equency output of th e interna l

oscill ator block. The choices are the LF INTOSC so urce

(31.25 kHz), the MFINTOSC source (31.25 kHz,

250 kHz or 500 kHz) and the HFINTOSC source

(16 MHz) or one of the frequencies derived from the

HFINTOSC postscaler (31.25 kHz to 8 MHz). If the

internal oscillator block is supplying the main clock,

changing the states of these bits will have an immedi-

ate change on the internal oscillator’s output. On

device Resets, the output frequency of the internal

oscillator is set to the default frequency of 1 MHz.

2.2.3 LOW FREQUENCY SELECTION

When a nominal output frequency of 31.25 kHz is

selected (IRCF<2:0> = 000), users may choose

which internal oscillator acts as the source. This is

done with the INTSRC bit of the OSCTUNE register

and MFIOSEL bit of the OSCCON2 register. See

Figure 2-2 and Register 2-1 for specific 31.25 kHz

selection. This option allows users to select a

31.25 kHz clock (MFINT OSC or HFINT OSC) th at can

be tuned using the TUN<5:0> bits in OSCTUNE

low clock speed. LFINTOSC always remains the

clock s ource for features such as the W atchdog T imer

and the Fail-Safe Clock Monitor, regardless of the

setting of INTSRC and MFIOSEL bits

This option allows users to select the tunable and more

precise HFINTOSC as a clock source, while

maint aining pow er savings wi th a very low clo ck speed.

2.2.4 POWER MANAGEMENT

The IDLEN bit of the OSCCON register determines

whethe r the devi ce goes into Slee p mode or o ne of th e

Idle modes when the SLEEP instruction is executed.

PIC18(L)F2X/4XK22

DS41412E-page 30  2010-2012 Microchip Technology Inc.

FIGURE 2-2: INTERNAL OSCILLATOR

MUX BLOCK DIAGRAM FIGURE 2-3: PLL_SELECT BLOCK

DIAGRAM

111

110

101

100

001

000

INTOSC

250 kHZ

500 kHZ

31.25 kHZ

IRCF<2:0>

MFIOSEL

INTSRC

HF-16 MHZ

HF-8 MHZ

HF-4 MHZ

HF-2 MHZ

HF-1 MHZ

LF-31.25 KHZ

MF-31.25 KHZ

HF-31.25 KHZ

HF-250 KHZ

MF-250 KHZ

HF-500 KHZ

MF-500 KHZ

011

010

PLL_Select

PLLCFG

FOSC<3:0> = 100x

PLLEN

TABLE 2-1: PLL_SELECT TRUTH TABLE

Primary Clock MUX Source FOSC<3:0> PLLCFG PLLEN PLL_Select

FOSC (any source) 0000-1111 0 0 0

OSC1/OSC2 (ext ern al source ) 0000-0111

1010-1111 1x1

011

INTOSC (internal source) 1000-1001 x 0 0

x11

 2010-2012 Microchip Technology Inc. DS41412E-page 31

PIC18(L)F2X/4XK22

FIGURE 2-4: SECONDARY OSCILLATOR AND EXTERNAL CLOCK INPUTS

SOSCEN SOSCGO

T1SOSCEN

T3SOSCEN

T5SOSCEN To Clock Switch Module

SOSCOUT

Secondary

Oscillator

SOSCI

SOSCO

T1CKI

T3G

T3CKI SOSCEN

SOSCEN

T3G

T3CMX

T1G

T5G

T5CKI

T5G

T3CKI

T1G

T1SOSCEN

T1CLK_EXT_SRC

T3CLK_EXT_SRC

T5CLK_EXT_SRC

T3SOSCEN

T5SOSCEN

PIC18(L)F2X/4XK22

DS41412E-page 32  2010-2012 Microchip Technology Inc.

2.3 Register Defini tions: Oscillator Control

R/W-0 R/W-0 R/W-1 R/W-1 R-q R-0 R/W-0 R/W-0

IDLEN IRCF<2:0> OSTS(1) HFIOFS SCS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Device enters Idle mode on SLEEP instruction

0 = Device enters Sleep mode on SLEEP instructi on

bit 6-4 IRCF<2:0>: Internal RC Oscillator Frequency Select bits(2)

111 = HFINTOSC – (16 MHz)

110 = HFINTOSC/2 – (8 MHz)

101 = HFINTOSC/4 – (4 MHz)

100 = HFINTOSC/8 – (2 MHz)

011 = HFINTOSC/16 – (1 MHz)(3)

If INTSRC = 0 and MFIOSEL = 0:

010 = HFINTOSC/32 – (500 kHz)

001 = HFINTOSC/64 – (250 kHz)

000 = LFINTOSC – (31.25 kHz)

If INTSRC = 1 and MFIOSEL = 0:

010 = HFINTOSC/32 – (500 kHz)

001 = HFINTOSC/64 – (250 kHz)

000 = HFINTOSC/512 – (31.25 kHz)

If INTSRC = 0 and MFIOSEL = 1:

010 = MFINTOSC – (500 kHz)

001 = MFINTOSC/2 – (250 kHz)

000 = LFINTOSC – (31.25 kHz)

If INTSRC = 1 and MFIOSEL = 1:

010 = MFINTOSC – (500 kHz)

001 = MFINTOSC/2 – (250 kHz)

000 = MFINTOSC/16 – (31.25 kHz)

bit 3 OSTS: Oscillator Start-up Time-out Status bit

1 = Device is ru nning from the clock def ined by FOSC<3:0> of the CONFIG 1H register

0 = Device is running from the internal oscillat or (HFINTOSC, MFINTOSC or LFINTOSC)

bit 2 HFIOFS: HFINTOSC Frequency Stable bit

1 = HFINTOSC frequency is stable

0 = HFINTOSC frequency is not stable

bit 1-0 SCS<1:0>: System Clock Select bit

1x = Internal oscillator block

01 = Secondary (SOSC) oscillator

00 = Primary clock (determined by FOSC<3:0> in CONFIG1H).

Note 1: Reset state depends on state of the IESO Configuration bit.

2: INTO SC sou rce ma y be determined by the INTSRC bit in O SCTUNE an d the MF IO SEL bi t in OSCCO N2.

3: Default output frequency of HFINTOSC on Reset.

 2010-2012 Microchip Technology Inc. DS41412E-page 33

PIC18(L)F2X/4XK22

R-0/0 R-0/q U-0 R/W-0/0 R/W-0/u R/W-1/1 R-x/u R-0/0

PLLRDY SOSCRUN —MFIOSEL SOSCGO(1) PRISD MFIOFS LFIOFS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

bit 7 PLLRDY: PLL Run Status bit

1 = Syst em clock co mes from 4xPLL

0 = System c lock comes f rom an osci llator, other than 4xP LL

bit 6 SOSCRUN: SOSC Run Status bit

1 = System clock comes from seco ndary SOSC

0 = Syst em clock comes from an osci llator, other than SOSC

bit 5 Unimplemented: Read as ‘0’.

bit 4 MFIOSEL: MFINTOSC Select bit

1 = MFINTOSC is used in place of HFINTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz

0 = MFINTOSC is not us ed

bit 3 SOSCGO(1): Secondary Oscillator Start Control bit

1 = Secondary osc il la t or is enabled.

0 = Secondary oscillator is shut off if no other sources are requesting it.

bit 2 PRISD: Primary Oscillator Drive Circuit Shutdown bit

1 = Oscillator drive circuit on

0 = Oscillator drive circuit off (zero power)

bit 1 MFIOFS: MFINTOSC Frequency Stable bit

1 = MFINTOSC is stable

0 = MFINTOSC is not stable

bit 0 LFIOFS: LFINTOSC Frequency Stable bit

1 = LFINTOSC is stable

0 = LFINTOSC is not stable

Note 1: The SOSCGO bit is only reset on a POR Reset.

PIC18(L)F2X/4XK22

DS41412E-page 34  2010-2012 Microchip Technology Inc.

2.4 Clock Source Modes

Clock Source modes can be classified as external or

internal.

• External Clo ck mod es rely on e xternal circui try for

the clock source. Examples are: Clock modules

(EC mode), quartz crystal resonators or ceramic

resonators (LP, XT and HS modes) and Resistor-

Capacitor (RC mode) circuits.

• Internal clock sources are contained internally

within the Oscillator block. The Oscillator block

has three internal oscillators: the 16 MHz High-

Frequency Internal Oscillator (HFINTOSC),

500 kHz Medium-Frequency Internal Oscillator

(MFINTOSC) and the 31.25 kHz Low-Frequency

Internal Os ci llator (LFINTOSC ).

The syste m cl oc k can be selected betwee n ex tern al or

internal clock sources via the System Clock Select

(SCS<1:0>) bits of the OSCCON register. See

Section 2.11 “Clock Switching” for additional

information.

2.5 External Clock Modes

2.5.1 OSCILLATOR START-UP TIMER (OST)

When t he os cil lator modu le is co nfi gure d for LP, XT or

HS mo des , the O sc illat or Start-up Timer (OS T) c ounts

1024 oscillations from OSC1. This occurs following a

Power-on Reset (POR) and when the Power-up Timer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not

increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz

cryst al res onator o r ce ramic res onator, has st arted an d

is providing a stable system clock to the oscillator

module. When switching between clock sources, a

delay is required to allow the new clock to stabilize.

These oscillator delays are shown in Table 2-2.

In order to mi nimize laten cy between externa l oscillator

start-up and code execution, the Two-Speed Clock

Start-up mode can be selected (see Section 2.12

“Two-Speed Clock Start-up Mode”).

TABLE 2-2: OSCILLATOR DELAY EXAMPLES

2.5.2 EC MODE

The External Clock (EC) mode allows an externally

generated logic level as the system clock source. When

operating in this mode, an external clock source is

connected to the OSC1 input and the OSC2 is available

for general purpose I/O. Figure 2-5 shows the pin

connections for EC mode.

The Exter nal Clock (EC) offer s different power m odes,

Low Pow er (ECLP), Med ium Power (ECMP) and High

Power (ECHP), selectable by the FOSC<3:0> bits.

Each mode is best suited for a certain range of

frequencies. The ranges are:

• ECLP – below 500 kHz

• ECMP – between 500 kHz and 16 MHz

• ECHP – above 16 MHz

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC® MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

FIGURE 2-5: EXTERNAL CLOCK (EC)

MODE OPERATION

Switch From Switch To Frequency Oscillator Delay

Sleep/POR LFINTOSC

MFINTOSC

HFINTOSC

31.25 kHz

31.25 kHz to 500 kHz

31.25 kHz to 16 MHz Oscillator Warm-Up Delay (TWARM)

Sleep/ POR EC, RC DC – 64 MHz 2 instructi on cycles

LFINTOSC (31.25 kHz) EC, RC DC – 64 MHz 1 cycle of each

Sleep/PO R LP, XT, HS 32 kHz to 40 MHz 1024 Clock Cy cles (OST)

Sleep/POR 4xPLL 32 MHz to 64 MHz 1024 Clock Cycles (OST) + 2 ms

LFIN TO SC (31.25 kHz) LFINTOSC

HFINTOSC 31.25 kHz to 16 MHz 1 s (approx.)

OSC1/CLKIN

OSC2/CLKOUT(1)

I/O

Clock from

Ext. System PIC® MCU

Note 1: Alternate pin functions are listed in

Section 1.0 “Device Overview”.

 2010-2012 Microchip Technology Inc. DS41412E-page 35

PIC18(L)F2X/4XK22

2.5.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 2-6). The mod e select s a low ,

medium or high gain setting of the internal inverter-

amplifi er to support vari ous resonator typ es and spee d.

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier . LP mode current consumption

is the least of the three modes. This mode is bes t suited

to drive resonators with a low drive level specification, for

example, tuning fork type cry st als.

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current c onsumption is the medium of the three mo des.

This mode is best suited to drive resonators with a

medium drive level specification.

HS Oscillator mode offers a Medium Power (MP) and a

High Power ( HP) option selectable by th e FOSC<3:0>

bits. The MP selections are best suited for oscillator

frequencies between 4 MHz and 16 MHz. The HP

selection has the highest gain setting of the internal

inverter-amplifier and is best suited for frequencies

above 16 MHz. HS mode is best suited for resonators

that require a high drive setting.

FIGURE 2-6: QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

FIGURE 2-7: CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

Quartz

RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: Quartz crystal characteristics vary

according to type, package and

manufacturer. The user should consult the

manuf actu rer da ta shee ts for spec ifi catio ns

and recom mended applicati on.

2: Always veri fy oscill ator performan ce over

the VDD and temperature range that is

expected for the application.

3: For oscillator design assistance, refer to the

following Microchip Application Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC® and PIC®

Devices” (DS00826)

• AN849, “Basic PIC® Oscillator Design”

(DS00849)

• AN943, “Practical PIC® Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

C2 Ceramic RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC® MC U

RP(3)

Resonator

OSC2/CLKOUT

PIC18(L)F2X/4XK22

DS41412E-page 36  2010-2012 Microchip Technology Inc.

2.5.4 EXTERN AL RC MODES

The external Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required. There are two modes: RC and RCIO.

2.5.4.1 RC Mode

In RC mode, the RC circuit connects to OSC1. OSC2/

CLKOUT outputs the RC oscillator frequency divided

by four. This signal may be used to provide a clock for

external circuitry, synchronization, calibration, test or

other application requirements. Figure 2-8 shows the

external RC mode connections.

FIGURE 2-8: EXTERNAL RC MODES

2.5.4.2 RCIO Mode

In RCIO mode, the RC circuit is connected to OSC1.

OSC2 becomes a general purpose I/O pin.

The RC oscillator frequency is a function of the supply

voltage, the resi stor (REXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting

the oscillator frequency are:

• input threshold voltage variation

• component tolerances

• pack aging variations in capa citance

The user also needs to take into account variation due

to tolerance of external RC components used.

2.6 Internal Clock Modes

The oscillator module has three independent, internal

oscillators that can be configured or selected as the

system clock source.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at

16 MHz. The frequency of the HFINTOSC can

be user-adjusted via software using the

OSCTUNE register (Register 2-3).

2. The MFINTOSC (Medium-Frequency Internal

Oscillator) is factory calibrated and operates

at 500 k Hz. The frequency of the MFI NTOSC

can be user-adjusted via software using the

OSCTUNE register (Register 2-3).

3. The LFINTOSC (Low-Frequency Internal

Oscillator) is factory calibrated and operates at

31.25 kHz. The LFINTOSC cannot be user-

adjusted, but is designed to be stable over

temperature and voltage.

The sy stem clock s peed can be selecte d via so ftware

using the Internal Oscillator Frequency select bits

IRCF<2:0> of the OSCCON register.

The syste m cl oc k can be selec ted betw ee n external or

internal cloc k sources via the System Clock Selection

(SCS<1:0>) bits of the OSCCON register. See

Section 2.1 1 “Clock Switching” for more i nformation.

2.6.1 INTOSC WITH I/O OR CLOCKOUT

T wo of the clock modes selecta ble with the FOSC<3:0>

bits of the CONFIG1H Configuration register configure

the internal oscillator block as the primary oscillator.

Mode selection determines whether OSC2/CLKOUT/

RA7 will be configu red as general purpos e I/O (RA7) or

FOSC/4 (CLKOUT). In both modes, OSC1/CLKIN/RA7

is configured as general purpose I/O. See

Section 24.0 “Special Features of the CPU” for more

information.

The CLKOU T signal m a y b e u sed to pro vide a c lock for

external circuitry, synchronization, calibration, test or

other applic ation requirements .

OSC2/CLKOUT(1)

CEXT

REXT

PIC® MCU

OSC1/CLKIN

FOSC/4 o r

Internal

Clock

VDD

VSS

Recommended values: 10 k  REXT  100 k

CEXT > 20 pF

Note 1: Alternate pin functions are listed in

Section 1.0 “Device Overview”.

2: Output depend s upon RC or RCIO clock mod e.

I/O(2)

 2010-2012 Microchip Technology Inc. DS41412E-page 37

PIC18(L)F2X/4XK22

2.6.1.1 OSCTUNE Register

The HFINTOSC/MFINTOSC oscillator circuits are

factory calibrated but can be adjusted in software by

writing to the TUN<5:0> bits of the OSCTUNE register

(Register 2-3).

The default value of the TUN<5:0> is ‘000000’. The

value is a 6-bit two’s complement number.

When the OSCTUNE register is modified, the

HFIN TOSC/M FIN TOSC frequency will begin shifting to

the new frequency . Code execution continues during this

shift. There is no indi cation that the shift has occurred.

The TUN<5:0> bits in OSCTUNE do not affect the

LFINTOSC frequency. Operation of features that

depend on the LFINTOSC clock s ource frequency, such

as the Power-up Timer (PWRT), Watchdog Timer

(WDT), Fail-Safe Clock Monitor (FSCM) and

peripherals, are not af fected by the change in frequency .

The OSCTUNE register also implements the INTSRC

and PLLEN bits, which control certain features of the

internal oscillator block.

The INTSRC bit allows users to select which internal

oscillator provides the clock source when the

31.25 kHz frequency option is selected. This is covered

in greater detail in Section 2.2.3 “Low Frequency

Selection”.

The PLLEN bit controls the operation of the frequency

multiplier, PLL, for all primary external clock sources

and internal oscillator modes. However, the PLL is

intended for operation with clock sources between

4 MHz and 16 MHz. For more details about the function

of the PLLEN bit, see Section 2.8.2 “PLL in HFIN-

TOSC Modes”

2.7 Register Defini tions: Oscillator Tuning

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INTSRC PLLEN(1) TUN<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from the MFINTOSC or HFINTOSC source

0 = 31.25 kHz devi ce clock derived directly from LFINTOSC internal oscillator

bit 6 PLLEN: Frequency Multiplier 4xPLL for HFINTOSC Enable bit(1)

1 = PLL enabled

0 = PLL disabled

bit 5-0 TUN<5:0>: Frequency Tuning bits – use to adjust MFINTOSC and HFINTOSC frequencies

011111 = Maximu m frequency

011110 =

• • •

000001 =

000000 = Oscillator module (HFINTOSC and MFINTOSC) are running at the factory calibrated

frequency.

111111 =

• • •

100000 = Minimum fre quency

Note 1: The PLLEN bit is active for all the primary clock sources (internal or external) and is designed to operate

with clock frequencies between 4 MHz and 16 MHz.

PIC18(L)F2X/4XK22

DS41412E-page 38  2010-2012 Microchip Technology Inc.

2.7.1 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is

a 31.25 kHz internal clock source. The LFINTOSC is

not tunab le, but is designed to be stable across temper-

ature and volt age. See Sec tion 27.0 “Electrical Char-

acteristics” for the LFINTOSC accuracy

specifications.

The output of the LFINTOSC can be a clock source to

the primar y cl ock or the INTOSC clock (see Figure 2-1).

The LFINTOSC is also the clock source for the Power-

up T imer (PWRT), W atchdog T imer (WDT) and Fail-Safe

Clock Monit or (FSCM).

2.7.2 FREQUENCY SELECT BITS (IRCF)

The HFINTOSC (16 MHz) and MFINTOSC (500 MHz)

outputs connect to a divide circuit that provides

frequencies of 16 MHz to 31.25 kHz. These divide

circuit frequencies, along with the 31.25 kHz

LFINTOSC output, are multiplexed to provide a single

INTOSC clock output (see Figure 2-1). The IRCF<2 :0 >

bits of the OSCCON register, the MFIOSEL bit of the

OSCCON2 register and the INTSRC bit of the

OSCTUNE register, select the output frequency of the

internal oscillators. One of eight frequencies can be

selected via software:

•16 MHz

•8 MHz

•4 MHz

•2 MHz

• 1 MHz (default after Reset)

• 500 kHz (MFINTOSC or HFINTOSC)

• 250 kHz (MFINTOSC or HFINTOSC)

• 31 kHz (LFINTOSC, MFINTOSC or HFINTOSC)

2.7.3 INTOSC FREQUENCY DRIFT

The factory calibrates the internal oscillator block outputs

(HFINTOSC/MFINTOSC) for 16 MHz/500 kHz. However ,

this frequency may drift as VDD or tempera ture changes.

It is possible to adjust the HFINTOSC/MFINTOSC fre-

quency by modifying the value of the TUN<5:0> bits in the

OSCTUNE register. This has no effect on the LFINTOSC

clock source frequency .

Tuning the HFINTOSC/MFINTOSC source requires

knowing when to make the adjustment, in which direc-

tion it should be made and, in some cases, how large a

change is needed. Three possible compensation tech-

niques are discussed in the following sections. How ever ,

other techniques may be used.

2.7.3.1 Compensating with the EUSART

An adjustment may be required when the EUSART

begins t o genera te frami ng errors or receive s dat a with

errors while in Asynchronous mode. Framing errors

indicate that the device clock frequency is too high; to

adjust for this, decrement the value in OSCTUNE to

reduce the clock frequency. On the other hand, errors

in data may suggest that the clock speed is too low; to

compensate, increment OSCTUNE to increase the

clock frequency.

2.7.3.2 Compensating with the Timers

This technique compares device clock speed to some

reference clock. Two timers may be used; one timer is

clocked by the peripheral clock, while the other is

clocked by a fixed reference source, such as the

Timer1 oscillator.

Both timers are cleared, but the timer clocked by the

reference generates interrupts. When an interrupt

occurs, the internally clocked timer is read and both

timers are cleared. If the internally clocked timer value

is greater than expected, then the internal oscillator

block is running too fast. To adjust for this, decrement

the OSCTUNE register.

2.7.3.3 Compensating with the CCP Module

in Capture Mode

A CCP module can use free running Timer1, Timer3 or

Timer5 clocked by the internal oscillator block and an

external event with a known period (i.e., AC power

frequency). The time of the first event is captured in the

CCPRxH:CCPRxL registers and is recorded for use later .

When the second event causes a capture, the time of the

first event is subtracted from the time of the second

event. Since the period of the external event is known,

the time difference between events can be calculated.

If the measured time is much greater than the calcu-

lated time, the internal oscillator block is running too

fast; to compensate, decrement the OSCTUNE register .

If the measured time is much less than the calculated

time, the int er nal osci llator block is r unning to o slow ; to

compensate, increment the OSCTUNE register .

 2010-2012 Microchip Technology Inc. DS41412E-page 39

PIC18(L)F2X/4XK22

2.8 PLL Frequency Multiplier

A Phase-Locked Loop (PLL) circuit is provided as an

option for users who wish to use a lower frequency

oscillator circuit or to clock the device up to its highest

rated f requenc y from the crys ta l osci llator. This may be

useful for customers who are concerned with EMI due

to high-frequency crystals or users who require higher

clock speeds from an internal oscillator.

2.8.1 PLL IN EXTERNAL OSCILLATOR

MODES

The PLL can be enabled for any of the external

oscillator modes using the OSC1/OSC2 pins by either

setting the PLLCFG bi t (CONFIG1 H<4>), or setti ng the

PLLEN bit (OSCTUNE<6>). The PLL is designed for

input frequencie s of 4 MHz up to 16 MHz. The PLL then

multiplies the oscillator output frequency by four to

produce an internal clock frequency up to 64 MHz.

Oscil lator frequenci es below 4 MHz sh ould not be use d

with the PLL.

2.8.2 PLL IN HFINTOSC MODES

The 4x frequency multiplier can be used with the

internal oscillator block to produce faster device clock

speeds than are normally possible with the internal

oscillator. When enabled, the PLL multiplies the

HFINTOSC by four to produce clock rates up to

64 MHz.

Unlike external clock modes, when internal clock

modes are enabled, the PLL can only be controlled

through software. The PLLEN control bit of the

OSCTUNE register is used to enable or disable the

PLL operation when the HFINTOSC is used.

The PLL is des ig ned for input frequen ci es o f 4 MHz up

to 16 MHz.

PIC18(L)F2X/4XK22

DS41412E-page 40  2010-2012 Microchip Technology Inc.

2.9 Effects of Power-Managed Modes

on the Various Clock Sources

For more information about the modes discussed in this

section see Section 3.0 “Power-Managed Modes”. A

quick reference list is also available in Table 3-1.

When PRI_IDLE mode is selected, the designated

primary oscillator continues to run without interruption.

For all other power-managed modes, the oscillator

using the OSC1 pin is disabled. The OSC1 pin (and

OSC2 pin, if us ed by th e oscillat or) will stop oscil lating.

In secondary clock modes (SEC_RUN and

SEC_IDLE), the secondary oscillator (SOSC) is

operating and providing the device clock. The

secondary oscillator may also run in all power-

managed modes if required to clock Timer1, Timer3 or

Timer5.

In internal oscillator modes (INTOSC_RUN and

INTOSC_IDLE), the internal oscillator block provides

the device clock source. The 31.25 kHz LFINTOSC

output can be used directly to provide the clock and

may be enabled to support various special features,

regardless of the power-managed mode (see

Section 24.3 “Watchdog Timer (WDT)”,

Section 2.12 “Two-Speed Clock S tart- up Mode” and

Section 2.13 “Fail-Safe Clock Monitor” for more

informa tion on WDT, Fail-Safe C lo ck M oni tor a nd Two-

Speed Start-up). The HFINTOSC and MFINTOSC

outpu ts may b e used direct ly to clock the device or may

be divided down by the postscaler. The HFINTOSC

and MFIN TOSC ou tputs a re disab led when t he clock is

provided directly from the LFINTOSC output.

When the Sleep mod e is select ed, all cl ock source s are

stopped. Since all the transistor switching currents

have been stopped, Sleep mode achieves the lowest

current consumption of the device (only leakage

currents).

Enabling any on-chip feature that will operate during

Sleep w ill increase th e current cons umed during S leep.

The LFINTOSC is required to support WDT operation.

Other features may be operating that do not require a

device clock source (i.e., SSP slave, PSP, INTn pins

and others). Peripherals that may add significant

current consumption are listed in Section 27.8 “DC

Characteristics: Input/Output Characteristics,

PIC18(L)F2X/4XK22”.

2.10 Power-up Delays

Power-up delays are controlled by two timers, so that

no external Reset circuitry is required for most

applications. The delays ensure that the device is kept

in Reset until the device power supply is stable under

normal circumstances and the primary clock is

operating and stable. For additional information on

power-up delays, see Section 4.6 “Device Reset

Timers”.

The first timer is the Power-up Timer (PWRT), which

provides a fixed delay on power-up. It is enabled by

clearing (= 0) the PWRTEN Configuration bit.

The second timer is the Oscillator Start-up Timer

(OST), intended to keep the chip in Reset until the

crysta l oscillator is stable (LP, XT and HS modes). The

OST does this by counting 1024 oscillator cycles

before allowing the oscillator to clock the device.

When the PLL is enabled with external oscillator

modes, the device is kept in Reset for an additional

2 ms, f ollowi ng the OST del ay, so the P LL can l ock to

the incoming clock frequency.

There is a delay of interval TCSD, following POR, while

the controller becomes ready to execute instructions.

This delay runs concurrently with any other delays.

This may be the only de lay that occ urs when any of the

EC, RC or INTIOSC modes are used as the primary

clock source .

When the HFINTOSC is selected as the prim ary clock,

the main system clock can be delayed until the

HFINTOSC is stable. This is user selectable by the

HFOFST bit of the CONFIG3H Configuration register.

When the HFOFST bit is cleared, the main system

clock is delayed until the HFINTOSC is stable. When

the HFOFST bit is set, the main system clock starts

immediately.

In eithe r case , the HF IOFS bi t of th e OSCCO N regist er

can be read to determine whether the HFINTOSC is

operating and stable.

 2010-2012 Microchip Technology Inc. DS41412E-page 41

PIC18(L)F2X/4XK22

TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

2.11 Clock Switching

The system clock source can be switched between

external and internal clock sources vi a software using

the System Clock Select (SCS<1:0>) bits of the

OSCCON register.

PIC18(L)F2X/4XK22 devices contain circuitry to pre-

vent clock “glitches” when switching between clock

sources. A short pause in the device clock occurs dur-

ing the clock s witch. The lengt h of this p ause is the sum

of two cycles of the old clock source and three to four

cycles of the new clock source. This formula assumes

that the new clock source is stable.

Clock transitions are discussed in greater detail in

Section 3.1.2 “Entering Power-Managed Modes”.

2.11.1 SYSTEM CLOCK SELECT

(SCS<1:0>) BITS

The System Clock Select (SCS<1:0>) bits of the

OSCCON register select t he syst em clock source t hat

is used for the CPU and peripherals.

• When SCS< 1:0> = 00, the system clock source is

determined by configuration of the FOSC<3:0>

bits in the CONFI G1H Configuration registe r.

• When SCS< 1:0> = 10, the system clock source is

chosen by the internal oscillator frequency

selected by the INTSRC bit of the OSCTUNE

• When SCS< 1:0> = 01, the system clock source is

the 32.768 kHz secondary oscilla tor shared with

Ti mer1, Timer3 and Timer5.

After a Reset, the SCS<1:0> bits of the OSCCON

re g i ster are alwa ys cleared.

2.11.2 OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of

the OSCCON register indicates whether the system

clock is running from the external clock source, as

defined by the FOSC<3:0> bits in the CONFIG1H

Configuration register, or from the internal clock

source. In particular, when the primary oscillator is the

source of the primary clock, OSTS indicates that the

Oscillator Start-up Timer (OST) has timed out for LP,

XT or HS modes.

OSC Mode OSC1 Pin OSC2 Pin

RC, INTOSC with CLKOUT Floating, external resistor should pull high At logic low (clock/4 output)

RC with IO Floating, external resistor should pull high Configured as PORTA, bit 6

INTOSC with IO Configured as PORTA, bit 7 Configured as PORTA, bit 6

EC with IO Floating, pulled by external clock Configured as PORTA, bit 6

EC with CLKOUT Floating, pulled by external clock At logic low (clock/4 output)

LP, XT, HS Feedback in verter disabled at quiescent

voltage level Feedback inverter disabled at quiescent

voltage level

Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.

Note: Any automatic clock switch, which may

occur from Two-Speed Start-up or Fail-

Safe Clock Monitor, does not update the

SCS<1:0> bits of the OSCCON register.

The user can monitor the SOSCRUN,

MFIOFS and LFIOFS bits of the

OSCCON2 register, and the HFIOFS and

OSTS bits of the OSCCON register to

determine the c urrent system clock source.

PIC18(L)F2X/4XK22

DS41412E-page 42  2010-2012 Microchip Technology Inc.

2.11.3 CLOCK SWITCH TIMING

When switching between one oscillator and another,

the new oscillator may not be operating which saves

power (see Figure 2-9). If this is the case, there is a

del ay afte r the SCS<1:0> bits of the OSCCON register

are modified before the frequ en cy change takes pl ac e.

The OSTS and IOFS bits of the OSCCON register will

reflect the current active status of the external and

HFINTOSC oscillators. The timing of a frequency

selection is as follows:

1. SCS<1:0> bits of the OSCCO N register are mod-

ified.

2. The old c lo ck continues to operate until the new

clock is ready.

3. Cloc k switch circuit ry waits for two con secutive

rising edges of the ol d clock after the new clock

ready signal goes true.

4. The syste m clock is h eld lo w s t arti ng at the next

falling edge of the old clock.

5. Clock switc h ci rcu itry wai t s for an addit ional two

rising edges of the new clock.

6. On the ne xt fallin g edg e of the n ew clock the low

hold on the system clock is released and new

clock is switched in as the system clock.

7. Cloc k switch is complete.

See Figure 2-1 for more details.

If the H FI N T O SC i s the so urc e of both the old an d new

frequency, there is no start-up delay before the new

frequency is active. This is because the old and new

frequencies are derived from the HFINTOSC via the

postscaler and multiplexer.

Start-up delay specifications are located in

Sect ion 27. 0 “E lect rical Char acter istic s”, under AC

Specifications (Oscillator Module).

2.12 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up

time from the time spent awake and can reduce the

overall power consumption of the device.

This mode allows the application to wake-up from

Sleep , perform a few instructions using the HFINTOSC

as the clock source and go back to Sleep without

waiting for the primary oscillator to become stable.

When the oscillat or module is configured for LP, XT or

HS modes, the Oscillator Start-up Timer (OST) is

enabled (see Section 2.5.1 “Oscillator Start-up Timer

(OST)”). The OST will suspend program execution until

1024 oscillations are counted. Two-Speed Start-up

mode minimizes the delay in code execution by

operating from the internal oscillator as the OST is

counting. When the OST count reaches 1024 and the

OSTS bit of the OSCCON register is set, program

executi on switches to the external oscillator.

2.12.1 TWO-SPEED START-UP MODE

CONFIGURATION

Two-Speed Start-up mode is enabled when all of the

following settings are configured as noted:

• Two-Speed Start-up mode is enab led w hen the

IESO of the CONFIG1H Configuration regi ster is

set.

• SCS<1:0> (of the OSCCON register) = 00.

• FOSC<2:0> bits of the CONFIG1H Configuration

Two-Speed Start-up mode becomes active after:

• Power- on Reset ( POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

Note: Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit of the OSCCON register to

remain clear.

 2010-2012 Microchip Technology Inc. DS41412E-page 43

PIC18(L)F2X/4XK22

2.12 .2 TWO-SPEED START-UP

SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin executing by the internal

osci lla tor at t he f req uen cy se t i n the IRCF<2:0>

bits of the O SCCO N re gis ter.

3. OST enabled to count 1024 external clock

cycles.

4. OST timed out. Exter nal clock is ready.

5. OSTS is set.

6. Clock switch finishes according to Figure 2-9

2.12.3 CHECKI NG TW O-SPEED CLOCK

STATUS

Checking the state of the OSTS bit of the OSCCON

from the external clock source, as defined by the

FOSC<2:0> bits in CONFIG1H Configuration register,

or the internal oscillator. OSTS = 0 when the external

oscillator is not ready, which indicates that the system

is running from the internal oscillator.

FIGURE 2-9: CLOCK SWITCH TIMING

Old Clock

New Clock

IRCF <2:0>

System Clock

Start-up Time(1) Clock Sync Running

High Speed Low Speed

Select Old Select New

New Clk Ready

Low Speed High Speed

Old Clock

New Clock

IRCF <2:0>

System Clock

Start-up Time(1) Clock Sync Running

Select Old Select New

New Clk Ready

Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.

PIC18(L)F2X/4XK22

DS41412E-page 44  2010-2012 Microchip Technology Inc.

2.13 Fail-Safe Clock Monitor

The Fail-Saf e Cl oc k Mo nit or (F SCM) al low s the devic e

to continue operating sh oul d th e e xte rna l os ci ll ator fail.

The FSCM can detect oscillator failure any time after

the Oscillator Start-up Timer (OST) has expired. The

FSCM is enabled by setting the FCMEN bit in the

CONFIG1H Configuration register. The FSCM is

applicable to all external oscillator modes (LP, XT, HS,

EC, RC and RCIO).

FIGURE 2-10: FSCM BLOCK DIAGRAM

2.13.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

compari ng the extern al osci llat or to the FSCM sa mple

clock. The sample clock is generated by dividing the

LFINTOSC by 64 (see Figure 2-10). Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock cle ars the latch on each rising edge of the

sample c loc k. A fail ure is d ete cte d w h en an entire half-

cycle of the sample clock elapses before the primary

clock goes low.

2.13 .2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

devi ce clock to an interna l clock s ource and s ets the b it

flag OSC FIF of the PIR2 registe r. The OSCFIF flag will

generate an interrupt if the OSCFIE bit of the PIE2

steps to mitigate the problems that may arise from a

failed clock. The system clock will continue to be

sourced from the internal clock source until the device

firmware successfully restarts the external oscillator

and switches back to external operation. An automatic

transition back to the failed clock source will not occur.

The internal clock source chosen by the FSCM is

determined by the IRCF<2:0> bits of the OSCCON

configured before a failure occurs.

2.13.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared by either one of the

following:

•Any Reset

• By togg ling the SCS1 bit of the OSCCON register

Both of these conditions restart the OST. While the

OST is running, the device continues to operate from

the INTOSC selected in OSCCON. When the OST

times out, the Fail-Safe condition is cleared and the

device automatically switches over to the extern al clock

source. The Fail-Safe condition need not be cleared

before the OSCFIF flag is cleared.

2.13.4 RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after

any type of Reset. The OST is not used w ith the EC or

RC Clock modes so that the FSCM will be active as

soon as the Reset or wake-up has completed. .

External

LFINTOSC ÷ 64

31 kHz

(~32 s) 488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Sample Clock

Note: Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

OSTS bit of the OSCCON register to verify

the oscillator start-up and that the system

clock switchover has successfully

completed.

Note: When the device is configured for Fail-

Safe clock monitoring in either HS, XT, or

LS Oscillator mode s then the IESO config-

uration bit should also be set so that the

clock will automatically switch from the

internal clock to the external oscillator

when the OST times out.

 2010-2012 Microchip Technology Inc. DS41412E-page 45

PIC18(L)F2X/4XK22

FIGURE 2-11: FSCM TIMING DIAGRAM

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note: The syste m clock is normally at a m uch higher frequency than the sam ple clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Test Test Test

Clock Monitor Output

TABLE 2-4: REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129

OSCCON IDLEN IRCF<2:0> OSTS HFIOFS SCS<1:0> 32

OSCCON2 PLLRDY SOSCRUN —MFIOSEL SOSCGO PRISD MFIOFS LFIOFS 33

OSCTUNE INTSRC PLLEN TUN<5:0> 37

PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125

PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120

Legend: — = unimp lemented locations , read as ‘0’. Shaded bits are not used by clock sources.

TABLE 2-5: CONFIGURATION REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CONFIG1H IESO FCMEN PRICLKEN PLLCFG FOSC<3:0> 357

CONFIG2L — — — BORV<1:0> BOREN<1:0> PWRTEN 358

CONFIG3H MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360

Legend: — = unimp lemented locations , read as ‘0’. Shaded bits are not used for clock sources.

PIC18(L)F2X/4XK22

DS41412E-page 46  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F-page 47

PIC18(L)F2X/4XK22

3.0 POWER-MANAGED MODES

PIC18(L)F2X/4XK22 devices offer a total of seven

operating modes for more efficient power manage-

ment. These modes provide a variety of options for

selective power conservation in applications where

resources may be limited (i.e., battery-powered

devices).

There are three categories of power-managed modes:

• Run modes

• Idle mo des

• Sleep mode

These categories define which portions of the device

are clo cked and some times , what sp eed. The R un and

Idle modes may use any of the three available clock

sources (primary, secondary or internal oscillator

bloc k). The Sleep mode does not use a cl ock source .

The power-managed modes include several power-

saving features of fered on previous PIC® microcontroller

devices. One of the clock switching features allows the

controller to use the secondary oscillator (SOSC) in

place of the primary oscill ator . Also included is the Sleep

mode, of fered by all PIC® microcontroller devices, where

all device clock s are stopped .

3.1 Selecting Power-Managed Modes

Selecting a power-managed mode requires two

decisions:

• Whether or not the CPU is to be clocked

• The selectio n of a cl ock source

The IDLEN bit (OSCCON<7>) controls CPU c locking,

while the SCS<1:0> bits (OSCCON<1:0>) select the

clock source. The individual modes, bit settings, clock

sources and affected modules are summarized in

Table 3-1.

3.1.1 CLOCK SOURCES

The SCS<1:0> bits allow the selection of one of three

clock sources for power-managed modes. They are:

• the primary clock, as defined by the FOSC<3:0>

Configuration bits

• the secondary clock (the SOSC oscillator)

• the internal oscillator block

3.1.2 ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another

begins by loading the OSCCON register. The

SCS<1:0> bits select the clock source and determine

which Run or Idle mode is to be used. Changing these

bits causes an immediate switch to the new clock

source, assuming that it is running. The switch may

also be subject to clock transition delays. Refer to

Section 2.1 1 “Clock Switching” for more i nformation.

Entry to the power-managed Idle or Sleep modes is

triggered by the execution of a SLEEP instruction. The

actual mode that results depends on the status of the

IDLEN bit.

Depending on the current mode and the mode being

switched to, a change to a power-managed mode does

not always require setting all of these bits. Many

transitions may be done by changing the oscillator select

bits, or changing the IDL EN bit, prior to issuing a SLEEP

instruction. If the IDLEN bit is already configured

correctly, it may only be necessary to perform a SLEEP

instruction to switch to the de sired mod e.

TABLE 3-1: POWER-MANAGED MODES

Mode OSCCON Bits Module Clocking Available Clock and Oscillator Source

IDLEN(1) SCS<1:0> CPU Peripherals

Sleep 0N/A Off Off None – All clocks are disabled

PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, RC, EC and Internal

Oscillator Block(2).

This is the norma l full-power execution mod e.

SEC_RUN N/A 01 Clocked Clocked Secondary – SOSC Oscillator

RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2)

PRI_IDLE 100Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC

SEC_IDLE 101Off Clocked Secondary – SOSC Oscillator

RC_IDLE 11xOff Clocked Internal Oscillator Block(2)

Note 1: IDLEN reflects its value when the SLEEP instruction is executed.

2: Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.

PIC18(L)F2X/4XK22

DS41412F-page 48  2010-2012 Microchip Technology Inc.

3.1.3 MULTIPLE FUNCTIONS OF THE

SLEEP COMMAND

The power-managed mode that is invoked with the

SLEEP instruction is determined by the value of the

IDLEN bit at the time the instruction is executed. If

IDLEN = 0, when SLEEP is executed, the device enters

the Sleep mode and all clocks stop and minimum

power is consumed. If IDLEN = 1, when SLEEP is

executed, the device enters the IDLE mode and the

system clock continues to supply a clock to the

peripherals but is disconnected from the CPU.

3.2 Run Modes

In the Run modes, clocks to both the core and

peripherals are active. The difference between these

modes is the clock source.

3.2.1 PRI_RUN MODE

The PRI_RUN mode is the normal, full-power

execution mode of the microcontroller. This is also the

default mode upon a device Reset, unless Two-Speed

Start-up is enabled (see Section 2.12 “Two-Speed

Clock Start-up Mode” for details). In this mode, the

device is operated off the oscillator defined by the

FOSC<3:0> bits of the CONFIG1H Configuration

3.2.2 SEC_RUN MODE

In SEC_RUN mode, the CPU and peripherals are

clocked from the secondary external oscillator. This

gives users the option of lower power consumption

while still using a high accuracy clock source.

SEC_RUN mode is entered by setting the SCS<1:0>

bits to ‘ 01’. When SEC_RUN mod e is active , all of the

following are true:

• The device clock source is switched to the SOSC

oscillator (see Figure 3-1)

• The primary oscillator is shut down

• The SOSCRUN bit (OSCCON2<6>) is set

• The OSTS bit (OSCCON2<3>) is cleared

On transitions from SEC_RUN mode to PRI_RUN

mode, th e perip herals and C PU co ntinue to be c locke d

from the SOSC oscillator, while the primary clock is

started. When the primary clock becomes ready, a

clock switch back to the primary clock occurs (see

Figure 3-2). When the clock switch is complete, the

SOSCRUN bit is cleared, the OSTS bit is set and the

primary clock is providing the clock. The IDLEN and

SCS bits are not affected by the wake-up and the

SOSC oscillator continues to run.

3.2.3 RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are

clocked from the internal oscillator block using the

INTOSC multiplexer. In this mode, the primary clock is

shut down. When using the LFINTOSC source, this

mode provides the best power conservation of all the

Run mo des , whi le s till executing cod e. It wo rks we ll for

user applications which are not highly timing-sensitive

or do not require high-speed clocks at all times. If the

primary clock source is the internal oscillator block –

either LFINTOSC or INTOSC (MFINTOSC or

HFINTOSC) – there are no distinguishable differences

between the PRI_RUN and RC_RUN modes during

execution. Entering or exiting RC_RUN mode,

howev er, causes a clock s w itc h de lay. Therefore, if the

primary clock source is the internal oscillator block,

using RC_RUN mode is not recommended.

This mode is entered by setting the SCS1 bit to ‘1’. To

maint ain s oftw are co mp atibil ity w ith future devices , it is

recommended that the SCS0 bit also be cleared, even

though the bit is ignored. When the clock source is

switched to the INTOSC multiplexer (see Figure 3-1),

the primary oscill ator is shut down and the OSTS bit is

cleared. The IRCF<2:0> bits (OSCCON<6:4>) may be

modified at any time to immediately change the clock

speed.

When the IRCF bits and the INTSRC bit are all clear,

the INTOSC output (HFINTOSC/MFINTOSC) is not

enabled and the HFIOFS and MFIOFS bits will remain

clear. There will be no indication of the current clock

source. The LFINTOSC source is providing the device

clocks.

If the IRCF bits are changed from all clear (thus,

enabling the INT OSC output) or if INTSRC or MFIOSEL

is set, then the HFIOFS or MFIOFS bit is set after the

INTOSC output becomes stable. For details, see

Table 3-2.

Clocks t o the device continue wh ile the INTOSC source

stabilizes after an interval of TIOBST.

If the IR CF bits were previously at a non-ze r o val ue, or

if INTSRC was set before setting SCS1 and the

INTOSC source was already stab le, then the HFIOFS

or MFIOFS bit will remain set.

Note: The secondary external oscillator should

already be running prior to entering

SEC_RUN mode. If the SOSCGO bit or

any of the TxSOSCEN bits are not set

when the SCS<1:0> bits are set to ‘01’,

entry to SEC_RUN mode will not occur

until SOSCGO bit is set and secondary

external oscillator is ready.

 2010-2012 Microchip Technology Inc. DS41412F-page 49

PIC18(L)F2X/4XK22

On transitions from RC_RUN mode to PRI_RUN mode,

the device continues to be clocked from the INTOSC

multipl exer while the prima ry clock is st arted. When the

prim ary cl oc k b ec om es ready, a cloc k s witc h to the pri-

mary clock occurs (see Figure 3-3). When the clock

switch is complete, the HFIOFS or MFIOFS bit is

cleared, the OSTS bit is set and the primary clock is

providing the device clock. The IDLEN and SCS bits

are not affected by the switch. The LFINTOSC source

will continue to run if either the WDT or the Fail-Safe

Clock Monitor is enabled.

FIGURE 3-1: TRANSITION T I MING FOR EN TRY TO SEC_RUN MODE

FIGURE 3-2: TRAN SITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

Q4Q3Q2

OSC1

Peripheral

Program

SOSCI

Counter

Clock

CPU

Clock

PC + 2PC

123 n-1n

Clock Transition(1)

Q4Q3Q2 Q1 Q3Q2

PC + 4

Note 1: Clock transition typically occurs within 2-4 TOSC.

Q1 Q3 Q4

OSC1

Peripheral

Program PC

SOSC

PLL Clock

PC + 4

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 TOSC.

SCS<1:0> bits Changed

TPLL(1)

12 n-1n

Clock

OSTS bit Set

Transition(2)

TOST(1)

PIC18(L)F2X/4XK22

DS41412F-page 50  2010-2012 Microchip Technology Inc.

FIGURE 3-3: TRANSITION TI MING FROM RC_RUN MODE TO PRI_RUN MODE

TABLE 3-2: INTERNAL OSCILLATOR FREQUENCY STABILITY BITS

IRCF<2:0> INTSRC MFIOSEL Selected Oscillator Selected Oscillator Stable when:

000 0 x LFINTOSC LFIOFS = 1

000 1 0 HFINTOSC HFIOFS = 1

000 1 1 MFINTOSC MFIOFS = 1

010 or 001 x 0 HFINTOSC HFIOFS = 1

010 or 001 x 1 MFINTOSC MFIOFS = 1

011 – 111 x x HFINTOSC HFIOFS = 1

Q1 Q3 Q4

OSC1

Peripheral

Program PC

INTOSC

PLL Clock

PC + 4

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). Th ese intervals are not shown to sca le.

2: Clock transition typically occurs within 2-4 TOSC.

SCS<1:0> bits Changed

TPLL(1)

12 n-1n

Clock

OSTS bit Set

Transition(2)

Multiplexer

TOST(1)

 2010-2012 Microchip Technology Inc. DS41412F-page 51

PIC18(L)F2X/4XK22

3.3 Sleep Mode

The Po wer-Mana ged Slee p mode in the P IC18 (L)F2X/

4XK22 devices is identical to the legacy Sleep mode

offered in all other PIC® microcontroller devices. It is

entered by clearing the IDLEN bit of the OSCCON

down the selected oscillator (Figure 3-4) and all clock

source Status bits are cleared.

Entering the Sleep mode from either Run or Idle mode

does not require a clock switch. This is because no

clocks are needed once the controller has entered

Sleep. If the WDT is selected, the LFINTOSC source

will continue to operate. If the SOSC oscillator is

enabled, it will also continue to run.

When a wake even t occurs i n Sleep mo de (by int errupt,

Reset or WDT time-o ut), the device will not be clocked

until the clock source selected by the SCS<1:0> bits

becomes ready (see Figure 3-5), or it will be clocked

from the internal oscillator block if either the Two-S peed

Start-up or the Fail-Safe Clock Monitor are enabled

(see Section 24.0 “Spe cial Features o f the CPU”). In

either case, th e OSTS b it is s et when t he p rimary clock

is providing the device clocks. The IDLEN and SCS bits

are not affect ed by the w ake-up.

3.4 Idle Modes

The Idle modes allow the controller’s CPU to be

selectively sh ut down while the p eriph erals continue to

operate. Selecting a particular Idle mode allows users

to further manage power consumption.

If the IDLEN bit i s set to a ‘1’ when a SLEEP in struction is

exec uted, the periph erals will be cl ocked fr om the cl ock

source selected by the SCS<1:0> bits; however , the CPU

will not be clocked . The clock so urce status bits are not

affected. Setting IDLEN an d executing a SLEEP instruc-

tion provides a quick method of switching from a given

Run mode to its c orre s pon di ng I dl e m o de.

If the WDT is se lec ted , the LFINTOSC source will con-

tinue t o operate. If the SOSC oscillator is enable d, it wil l

also continue to run.

Since the CPU is not executing instructions, the only

exits from any of the Idle modes are by interrupt, WDT

time-out, or a Reset. When a wake event occurs, CPU

execution is delayed by an interval of TCSD while it

becomes ready to execute code. When the CPU

begins executing co de , it re sumes with the same clock

source for the current Idle mode. For example, when

waking from RC_IDLE mode, the internal oscillator

block will clock the CPU and peripherals (in other

words, RC_RUN mode). The IDLEN and SCS bits are

not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT

time-out will result in a WDT wake-up to the Run mode

currently specified by the SCS<1:0> bits.

FIGURE 3-4: TRAN SITION TIMING FOR ENTRY TO SLEEP MODE

Q4Q3Q2

OSC1

Peripheral

Sleep

Program

Q1Q1

Counter

Clock

CPU

Clock

PC + 2PC

PIC18(L)F2X/4XK22

DS41412F-page 52  2010-2012 Microchip Technology Inc.

FIGURE 3-5: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

3.4.1 PRI_IDLE MODE

This mode is unique among the three low-power Idle

modes, in that it does not disable the primary device

clock. For timing sensitive applications, this allows for

the faste st resump tion of device op eration with its more

accur ate prima ry clock s ource, si nce the cl ock source

does not have to “warm-up” or transition from another

oscillator.

PRI_IDLE mode is entered from PRI_RUN mode by

setting the IDLEN bit and executing a SLEEP instruc-

tion. If the device is in another Run mode, set IDLEN

first, then clear the SCS bits and execute SLEEP.

Although the C PU is disab led, th e peri pherals continu e

to be clocked from the primary clock source specified

by the FOSC<3:0> Configuration bits. The OSTS bit

remains set (see Figure 3-6).

When a wake event occurs, the CPU is clocked from the

primary clock source. A delay of interval TCSD is

required between the wake event and when code

execution starts. This is required to allow the CPU to

become rea dy to execute instructions. After the wake-

up, the OSTS bit remains set. The IDLEN and SCS bits

are not affected by the wake-up (see Figure 3-7).

3.4.2 SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the SOSC

oscillator . This mode is entered from SEC_RUN by set-

ting the IDLEN bit and exec uting a SLEEP instruction. If

the device is in another Run mode, set the IDLEN bit

first, then set the SCS<1:0> bits to ‘01’ and execute

SLEEP. When the clock source is switched to the SOSC

oscill ator , the prima ry oscillat or is shut down , the OSTS

bit is cleared and the SOSCRUN bit is set.

When a wake event occurs, the peripherals continue to

be clocked from the SOSC oscillator. After an interval

of TCSD following t he wa ke eve nt, the C PU begi ns ex e-

cuting co de be ing clocked by the SOSC os ci lla tor. The

IDLEN and SCS bits are not affected by the wake-up;

the SOSC oscillator continues to run (see Figure 3-7).

FIGURE 3-6: TRANSITION TIMING FOR ENTRY TO IDLE MODE

Q3 Q4 Q1 Q2

OSC1

Peripheral

Program PC

PLL Clock

Q3 Q4

Output

CPU Clock

Q1 Q2 Q3 Q4 Q1 Q2

Clock

Counter PC + 6

PC + 4

Q1 Q2 Q3 Q4

Wake Event

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

TOST(1) TPLL(1)

OSTS bit set

PC + 2

Note: The SOSC oscillator should already be

running prior to entering SEC_IDLE

mode. At lea st one of the se condary os cil-

lator enable bits (SOSCGO, T1SOSCEN,

T3SOSCEN or T5SOSCEN) must be set

when the SLEEP instruction is executed.

Otherwise, the main system clock will con-

tinue to o perate in the prev iou sl y s el ec ted

mode and the corresponding IDLE mode

will be entered (i.e., PRI_IDLE or

RC_IDLE).

Peripheral

Program PC PC + 2

OSC1

Q3 Q4 Q1

CPU Clock

Clock

Counter

 2010-2012 Microchip Technology Inc. DS41412F-page 53

PIC18(L)F2X/4XK22

FIGURE 3-7: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

3.4.3 RC_IDLE MODE

In RC_I DL E m od e, t he CPU is disabl ed but the periph-

erals co nti nue to b e c loc ke d from the i nter nal os cil lator

block from the HFINTOSC multiplexer output. This

mode allows for controllable power conservation during

Idle period s.

From RC_RUN, this mode is entered by setting the

IDLEN bit and executing a SLEEP instruction. If the

device is in a nother Run m ode, first s et IDLEN, th en set

the SCS1 bit and execute SLEEP. It is recommended

that SCS0 also be cleared, although its value is

ignored, to maintain software compatibility with future

devices. The HFINTOSC multiplexer may be used to

select a higher clock frequency by modify ing the IRCF

bits be for e ex ecut in g the SLEEP instruction. When the

clock source is switched to the HFINTOSC multiplexer ,

the primary oscillator is shut down and the OSTS bit is

cleared.

If the IRCF bits are set to any non-zero value, or ei ther

the INTSRC or MFIOSEL bits are set, the HFINTOSC

output is enabled. Either the HFIOFS or the MFIOFS

bits become set, after the HFINTOSC output stabilizes

after an interval of TIOBST. For information on the

HFIOFS and MFIOFS bits, see Table 3-2.

Clocks to the peripherals continue while the

HFINTOSC source stabilizes. The HFIOFS and

MFIOFS bits will remain set if the IRCF bits were

previ ously set at a non-zero valu e or if INTSRC was set

before the SLEEP instruction was executed and the

HFINT O SC so urc e was al read y s t a ble. If the IRCF bit s

and INTSRC are all clear, the HFINTOSC output will

not be enabled, the HFIOFS and MFIOFS bits will

remain clear and there will be no indication of the

current clock source.

When a wake event occurs, the peripherals continue to

be clocked from the HFINTOSC multiplexer output.

After a delay of TCSD following the wake event, the

CPU begins executing code being clocked by the

HFINTOSC multiplexer. The IDLEN and SCS bits are

not affected by the wake-up. The LFINTOSC source

will continue to run if either the WDT or the Fail-Safe

Clock Moni tor is ena ble d.

OSC1

Peripheral

Program PC

CPU Clock

Q1 Q3 Q4

Clock

Counter

Wake Event

TCSD

PIC18(L)F2X/4XK22

DS41412F-page 54  2010-2012 Microchip Technology Inc.

3.5 Exiting Idle and Sleep Modes

An exit from Sleep mode or any of the Idle modes is

triggered by any one of the following:

• an interrupt

•a Reset

• a Watchdog Time-out

This section discusses the triggers that cause exits

from power-managed modes. The clocking subsystem

actions are discussed in each of the power-managed

modes (see Section 3.2 “Run Modes”, Section 3.3

“Sleep Mode” and Section 3.4 “Idle Modes”).

3.5. 1 EXIT BY INTERRUPT

Any of the available interrupt sources can cause the

device to exit from an Idle mode or the Sleep mode to

a Run mode. To enable this functionality, an interrupt

source m us t be enabled by setting i ts enable bit in one

of the INTCON or PIE registers. The exit sequence is

initiate d when the c orrespondin g interrupt flag bit is set.

The instruction immediately following the SLEEP

instruc tion is exec uted on all exit s by interr upt from Idle

or Sleep modes. Code execution then branches to the

interrupt vector if the GIE/GIEH bit of the INTCON

without branching (see Section 9.0 “Interrupt s ”).

A fixed dela y of int erval TCSD followi ng the wake event

is required when leaving Sleep and Idle modes. This

delay is requi red for the CPU to prepare f or execution.

Instruction execution resumes on the first clock cycle

following this delay.

3.5.2 EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending

on which power-managed mode the device is in when

the time-out occurs.

If th e dev ice i s not ex ecut ing code (all Idle mo des a nd

Sleep mod e), th e time-o ut wi ll res ul t in an ex it fro m the

power-managed mode (see Section 3.2 “Run

Modes” a nd Section 3.3 “Sleep Mode ”). If the device

is executing code (all Run modes), the time-out will

result in a WDT Reset (see Section 24.3 “Watchdog

Timer (WDT)”).

The WDT timer and postscaler are cleared by any one

of the fo llowing:

• executin g a SLEEP instruction

• executin g a CLRWDT instruction

• the loss of the currently selected clock source

when the Fail-Safe Clock Monitor is enabled

• modifying the IRCF bits in the OSCCON register

when the internal oscillator block is the device

clock source

3.5. 3 EXIT BY RESET

Exiting Sleep and Idle modes by Reset causes code

execution to restart at address 0. See Section 4.0

“Reset” for more details.

The exit delay time from Reset to the start of code

execution depends on both the clock sources before

and after the wake-up and the type of oscillator.

3.5.4 EXIT WITHOUT AN OSCILLATOR

START-UP DELAY

Certain exits from power-managed modes do not

invoke the OST at all. There are two cases:

• PRI_IDLE mode, where the primary clock source

is not stopped and

• the primary clock source is not any of the LP, XT,

HS or HSPLL modes.

In these instances, the primary clock source either

does not require an oscillator start-up delay since it is

already running (PRI_IDLE), or normally does not

require an oscillator start-up delay (RC, EC, INTOSC,

and INTOSCIO modes). However, a fixed delay of

interval TCSD following the wake event is still required

when leaving Sleep and Idle modes to allow the CPU

to pr epare for execution. Instruction execution resumes

on the first clock cycle following this delay.

 2010-2012 Microchip Technology Inc. DS41412F-page 55

PIC18(L)F2X/4XK22

3.6 Selective Peripheral Module

Control

Idle mode allows users to substantially reduce power

consumption by stopping the CPU clock. Even so,

peripheral modules still remain clocked, and thus, con-

sume power. There may be cases where the applica-

tion needs what IDLE mode does not provide: the

allocation of power resources to the CPU processing

with minimal power consumption from the peripherals.

PIC18(L)F2X/4XK22 family devices address this

requirement by allowing peripheral modules to be

selectively disabled, reducing or eliminating their

power consumption. This can be done with control bits

in the Peripheral Module Disable (PMD) registers.

These bits generically named XXXMD are located in

control regi sters PMD0, PMD1 or PMD2.

Setting the PMD bit for a module disables all clock

sources to that module, reducing its power

consumption to an absolute minimum. In this state,

power to the control and status registers associated

with the peripheral is removed. Writes to these

registers have no effect and read values are invalid.

Clearing a set PMD bit restores power to the

assoc iated co ntrol an d st atus reg isters , thereby settin g

those registers to their default values.

3.7 Register Definitions: Peripheral Module Disable

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 UART2MD: UART2 Peripheral Module Dis ab le Contro l bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 6 UART1MD: UART1 Peripheral Module Dis ab le Contro l bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 5 TMR6MD: Timer6 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 4 TMR5MD: Timer5 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 3 TMR4MD: Timer4 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 2 TMR3MD: Timer3 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 1 TMR2MD: Timer2 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 0 TMR1MD: Timer1 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

PIC18(L)F2X/4XK22

DS41412F-page 56  2010-2012 Microchip Technology Inc.

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

MSSP2MD MSSP1MD —CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 MSSP2MD: MSSP2 Peri pheral Module Disab le Contro l bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 6 MSSP1MD: MSSP1 Peri pheral Module Disab le Contro l bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 5 Unimplemented: Read as ‘0’

bit 4 CCP5MD: CCP5 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 3 CCP4MD: CCP4 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 2 CCP3MD: CCP3 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 1 CCP2MD: CCP2 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 0 CCP1MD: CCP1 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

 2010-2012 Microchip Technology Inc. DS41412F-page 57

PIC18(L)F2X/4XK22

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — CTMUMD CMP2MD CMP1MD ADCMD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’

bit 3 CTMUMD: CTMU Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 2 CMP2MD: Comparator C2 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 1 CMP1MD: Comparator C1 Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

bit 0 ADCMD: ADC Peripheral Module Disable Control bit

1 = Module is disabled, Clock Source is disconnected, module does not draw digital power

0 = Module is enabled, Clock Source is connected, module draws digital power

PIC18(L)F2X/4XK22

DS41412F-page 58  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F-page 59

PIC18(L)F2X/4XK22

4.0 RESET

The PIC18(L)F2X/4XK22 devices differentiate between

various kin ds of Re set:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during power-managed modes

d) Watchdog Timer (WDT) Reset (during

execution)

e) Programmable Brown-out Reset (BOR)

f) RESET Inst ruction

g) Stack Full Res et

h) Stack Underflow Reset

This section discusses Resets generated by MCLR,

POR and BO R and cov ers the ope rati on of the various

start-up timers. Stack Reset events are covered in

Section 5.2.0.1 “Stack Full and Underflow Resets”.

WDT Re sets a r e co v ere d i n Section 24.3 “Watchdog

Timer (WDT)”.

A simplif ied block diagra m of the On-Chip Rese t Circu it

is shown i n Figure 4-1.

4.1 RCON Register

Device Reset events are tracked through the RCON

occurred . In most cases, th ese bit s can on ly be cl eared

by the event and must be set by the application after

the event. The state of these flag bits, taken together,

can be read to indicate the type of Reset that just

occurred. This is described in more detail in

Section 4.7 “Reset State of Registers”.

The RCON register also has control bits for setting

interrupt priority (IPEN) and software control of the

BOR (SBOREN). Interrupt priority is discussed in

Section 9.0 “Interrupts”. BOR is covered in

Section 4.5 “Brown-out Reset (BOR)”.

FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset

MCLR

VDD

OSC1

WDT

Time-out

VDD

Detect

OST/PWRT

LFINTOSC

POR

OST(2)

10-bit Ripple Counter

PWRT(2)

11-bit Ripple Counter

Enable OST(1)

Enable PWRT

Note 1: See Table 4-2 for time-out situations.

2: PWRT and OST counters are reset by POR and BOR. See Sections 4.4 and 4.5.

Brown-out

Reset BOREN

RESET

Instruction

Stack

Pointer Stack Full/Underflow Reset

Sleep

( )_IDLE

1024 Cycles

65.5 ms

32 s

MCLRE

RQChip_Reset

PIC18(L)F2X/4XK22

DS41412F-page 60  2010-2012 Microchip Technology Inc.

4.2 Regist er D e finition s : R e se t Control

R/W-0/0 R/W-q/u U-0 R/W-1/q R-1/q R-1/q R/W-q/u R/W-0/q

IPEN SBOREN(1) —RITO PD POR(2) BOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown u = unchanged q = depends on condition

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts

0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6 SBOREN: BOR Software Enable bit(1)

If BOREN<1:0> = 01:

1 = BOR is enabled

0 = BOR is disabled

If BOREN<1:0> = 00, 10 or 11:

Bit is disabled and read as ‘0’.

bit 5 Unimplemented: Read as ‘0’

bit 4 RI: RESET Instruction Flag bit

1 = The RESET in struction was not executed (set by firmware or Power-on Reset)

0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a

code-executed Reset occurs)

bit 3 TO: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 2 PD: Power-down Detection Flag bit

1 = Set by power-up or by the CLRWDT ins tru cti on

0 = Set by executi on of the SLEEP instruction

bit 1 POR: Power-on Reset Status bi t(2)

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit(3)

1 = A Brown-out Reset has not occurred (set by firmware only)

0 = A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs)

Note 1: When CONFIG2L[2:1] = 01, then the SBOREN Reset state is ‘1’; otherwise, it is ‘0’.

2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this

3: See Table 4-1.

Note 1: Brown-ou t Reset is ind icated when BOR is ‘0’ and POR is ‘1’ (assuming th at both POR and BOR were set

to ‘1’ by firmware immediately after POR).

2: It is recommended th at the POR bit be set afte r a Power-on Reset has bee n detecte d so that su bsequ ent

Power-on Resets may be detected.

 2010-2012 Microchip Technology Inc. DS41412F-page 61

PIC18(L)F2X/4XK22

4.3 Master Clear (MCLR)

The MCLR pin provides a method for triggering an

external Reset of the device. A Reset is generated by

hold ing the pin low . T hese devi ces have a noise fi lter in

the MCLR Reset path which detects and ignores small

pulses. An internal weak pull-up is enabled when the

pin is configured as the MCLR input.

The MCLR pin i s not driven l ow b y any i nter nal Res ets ,

including the WDT.

In PIC18(L)F2X/4XK22 devices, the MCLR input can

be disabled with the MCLRE Configuration bit. When

MCLR is disabled, the pin be comes a digit al in put. See

Section 10.6 “PORTE Registers” for more

information.

4.4 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip

whenever VDD rises above a certain threshold. This

allows the device to start in the initialized state when

VDD is adequate for operation.

To take advantage of the POR circuitry either leave the

pin floating, or tie the MCLR pin through a resistor to

VDD. This will eliminate external RC components

usually needed to create a Power-on Reset delay. A

minimu m rise rate for VDD is specified. For a slow rise

time, see Figure 4-2.

When the device sta rt s norm al ope ration (i.e., exit s the

Reset condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure proper operation. If these conditions are not

met, the device must be held in Reset until the operat-

ing conditions are met.

POR events are captured by the POR bit of the RC ON

POR occurs; it does not change for any other Reset

event. POR is not reset to ‘1’ by any hardware event.

To capture m ult ipl e ev en t s, the user must manu all y s et

the bit to ‘1’ by software following any POR.

FIGURE 4-2: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: 15 k < R < 40 k  is recommended to make

sure that the voltage drop ac ross R does not

violate the device’s electrical specification.

3: R1  1 k will limit any current flowing into

MCLR from external capacitor C, i n the event

of MCLR/VPP pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

VDD

MCLR

VDD

PIC® MCU

PIC18(L)F2X/4XK22

DS41412F-page 62  2010-2012 Microchip Technology Inc.

4.5 Brown-out Reset (BOR)

PIC18(L)F2X/4XK22 devices implement a BOR circuit

that provides the user with a numb er of co nfigurati on and

power-saving options. The BOR is controlled by the

BORV<1:0> and BOREN<1:0> bits of the CONFIG2L

Configuration register. There are a total of four BOR

confi gurations wh ic h are s um m ari ze d in Table 4-1.

The BOR threshold is set by the BORV<1:0> bits. If

BOR is enabled (any values of BOREN<1:0>, except

‘00’), any drop of VDD below VBOR for greater than

TBOR will reset the device. A Reset may or may not

occur if VDD falls below VBOR for less than TBOR. The

chip will remain in Brown-out Reset until VDD rises

above VBOR.

If the Powe r-up Ti mer is enabled , it will be invoke d after

VDD rises above VBOR; it then will keep the chip in

Reset for an add itional t ime de lay, TPWRT. If VDD drops

below VBOR while the Power-up Timer is running, the

chip will go back into a Brown-out Reset and the

Power-up Timer will be initialized. Once VDD rises

above VBOR, the Power-up Timer will execute the

additional time delay.

BOR and the Power-on Timer (PWRT) are

independently configured. Enabling BOR Reset does

not automatically enable the PW RT.

The BOR ci rcui t h as an output th at fee ds into the POR

circuit and r earms the POR within th e operating range

of the BOR. This early rearming of the POR ensures

that the device will remain in Reset in the event that VDD

falls below the operating range of the BOR circuitry.

4.5.1 DETECTING BOR

When BO R is enab led, the BO R bi t alway s re set s to ‘0’

on any BOR or POR event. This makes it difficult to

deter mi ne if a BOR ev ent ha s occ urred just by reading

the state of BOR alone. A more reliable method is to

simultaneously check the state of both POR and BOR.

This assumes that the POR and BOR bits are reset to

‘1’ by software immediately after any POR event. If

BOR is ‘0’ wh il e POR is ‘1’, it can be reliably assumed

that a BOR event has occurred.

4.5.2 SOFTWARE ENABLED BOR

When BOREN<1:0> = 01, the BOR can be enabled or

disabled by the user in software. This is done with the

SBOREN control bit of the RCON register. Setting

SBOREN enables the BOR to function as previously

described. Clearing SBOREN disables the BOR

entirely. The SBOREN bit operates only in this mode;

otherwise it is read as ‘0’.

Placing the BOR under software control gives the user

the additional flexibility of tailoring the application to the

environment without having to reprogram the device to

change BOR configuration. It also allows the user to

tailor device power consumption in software by

eliminating the incremental current that the BOR

consumes. While the BOR current is typically very small,

it may have some im p act in low -pow er applic ations.

4.5.3 DISABLING BOR IN SLEEP MODE

When BOREN<1:0> = 10, the BOR remains under

hardware control and operates as previously

described. Whenever the device enters Sleep mode,

howev er, the BOR is automatica lly dis abl ed . When the

device returns to any other operating mode, BOR is

automati cally re-enabled.

This mode allows for applications to recover from

brown-out situations, while actively executing code,

when the device requires BOR protection the most. At

the same time, it save s additional po wer in Sleep mode

by eliminating the small incremental BOR current.

4.5.4 MINIMUM BOR ENABLE TIME

Enabling the BOR also enables the Fixed Voltage

Reference (FVR) when no other peripheral requiring the

FVR is acti ve. The BOR be comes active only afte r the

FVR stabilizes. Therefore, to ensure BOR protection,

the FVR settling time must be considered when

enabling the BOR in software or when the BOR is

automatically enabled after waking from Sleep. If the

BOR is disabled, in software or by reentering Sleep

before the FVR stabilizes, the BOR circuit will not sense

a BOR condition. The FVRST bit of the VREFCON0

Note: Even when BOR is under software

control, the BOR Reset voltage lev el is still

set by the BORV<1:0> Configuration bits.

It cannot be changed by software.

 2010-2012 Microchip Technology Inc. DS41412F-page 63

PIC18(L)F2X/4XK22

4.6 Device Reset Timers

PIC18(L)F2X/4XK22 devices incorporate three

separate on-chip timers that help regulate the Power-

on Reset process. Their main function is to ensure that

the device clock is stable before code is executed.

These timers are:

• Power-up Timer (PWRT)

• Oscillator Start-up Ti mer (OST)

• PLL Lock Time-out

4.6.1 POWER-UP TIMER (PWRT)

The Power-up Timer (PWRT) of PIC18(L)F2X/4XK22

devices is an 11-bit counter which uses the

LFINTOSC source as the clock input. Th is yields an

approximate time interval of 2048 x 32 s=65.6ms.

While the PWRT is counting, the device is held in

Reset.

The power-up time delay depends on the LFINTOSC

clock and will vary from chip-to -chip due to temperature

and process variation.

The PWRT is enabled by clearing the PWRTEN

Configuration bit.

4.6.2 OSCILLA TOR STAR T-UP TIMER

(OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal

oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on P ower- on R eset, o r on ex it fr om al l

power-managed modes that stop the external oscillator .

4.6.3 PLL LOCK TIME-OUT

With the PLL enabled, the time-out sequence following a

Power-on Reset is slightly different from other os cillator

modes. A separate timer is used to provide a fixed time-

out that is sufficient for the PLL to lock to the main

oscillator frequency. This PLL lock time-out (TPLL) is

typic ally 2 m s and fo llows the os cilla tor star t-up ti me-out .

4.6.4 TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows:

1. After the POR pulse has cleared, PWRT time-out

is invoked (if en abled).

2. Then, the OST is activated.

The total time-out will vary based on oscillator

configuration and the status of the PWRT. Figure 4-3,

Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all

depict time-out sequences on power-up, with the

Power-up Timer enabled and the device operating in

HS Oscillator mode. Figures 4-3 through 4-6 also

apply to devices operating in XT or LP modes. For

devices in RC mode and with the PWRT disabled, on

the other hand, there will be no time-out at all.

Since the time-outs occur from the PO R pulse, if MCLR

is k ept l ow lo ng en ough, all time- outs wi ll ex pire , afte r

which, bringing MCLR high will allow program

execution to begin immediately (Figure 4-5). This is

useful for testing purpo ses or to synchroniz e more than

one PIC® MCU device operating in parallel.

TABLE 4-1: BOR CONFIGURATIONS

BOR Configuration Stat us of

SBOREN

(RCON<6>) BOR Operation

BOREN1 BOREN0

00Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.

01Av ailable BO R enabled by software; operation controlled by SBOREN.

10U navailable BOR enabled by hardware in Run and Idle modes, disabled during Sleep mode.

11Unavailable BOR enabled by hardware; must be disabled by reprogramming the Configuration bits.

PIC18(L)F2X/4XK22

DS41412F-page 64  2010-2012 Microchip Technology Inc.

FIGURE 4-3: TIME-OUT SEQU ENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS

Oscillator

Configuration

Power-up(2) and Brown-out Exit from

Power-Managed Mode

PWRTEN = 0PWRTEN = 1

HSPLL 66 ms(1) + 1024 TOSC + 2

ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)

HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC

EC, ECIO 66 ms(1) ——

RC, RCIO 66 ms(1) ——

INTIO1, INTIO2 66 ms(1) ——

Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.

2: 2 ms is the nominal time required for the PLL to lock.

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTER N AL PO R

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

 2010-2012 Microchip Technology Inc. DS41412F-page 65

PIC18(L)F2X/4XK22

FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, V DD RISE > TPWRT)

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL R ESET

0V 5V

TPWRT

TOST

PIC18(L)F2X/4XK22

DS41412F-page 66  2010-2012 Microchip Technology Inc.

FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-O UT

INTERNAL RESET

PLL TIME-OUT

TPLL

Note: TOST = 1024 clock cycles.

TPLL  2 ms max. First three stages of the PWRT timer.

 2010-2012 Microchip Technology Inc. DS41412F-page 67

PIC18(L)F2X/4XK22

4.7 Reset State of Registers

Some registers are unaffected by a Reset. Their status

is unknown on POR and unchanged by all other

Resets. All other reg isters are forc ed to a “R es et s t a te”

depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal

operation. Status bits from the RCON register, RI, TO,

PD, POR and BOR, are set or cleared differently in

different Reset situations, as indicated in Table 4-3.

These bits are used by software to determine the

nature of the Reset.

Table 5-2 describes the Reset states for all of the

Special Function Registers. The table identifies

differences between Power-On Reset (POR)/Brown-

Out Reset (BOR) and all other Resets, (i.e., Master

Clear, WDT Resets, STKFUL, STKUNF, etc.).

Additionally, the table identifies register bits that are

changed when the device receives a wake-up from

WDT or other interrupts.

TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION

FOR RCON REGISTER

Condition Program

Counter

RCON Register STKPTR Register

SBOREN RI TO PD POR BOR STKFUL STKUNF

Power-on Reset 0000h 1 11100 0 0

RESET Instruction 0000h u(2) 0uuuu u u

Brown-out Reset 0000h u(2) 111u0 u u

MCLR during Power-Managed

Run Modes 0000h u(2) u1uuu u u

MCLR during Power-Managed

Idle Modes and Sleep Mode 0000h u(2) u10uu u u

WDT T ime-out during Full Power

or Power-Managed Run Mode 0000h u(2) u0uuu u u

MCLR during Full Power

Execution 0000h u(2) uuuuu u u

Stack Full Reset (STVREN = 1) 0000h u(2) uuuuu 1 u

Stack Underflow Reset

(STVREN = 1)0000h u(2) uuuuu u 1

Stack Underflow Error (not an

actual Reset, STVREN = 0)0000h u(2) uuuuu u 1

WDT Time-out during Power-

Managed Idle or Sleep Modes PC + 2 u(2) u00uu u u

Interrupt Exit from Power-

Managed Modes PC + 2(1) u(2) uu0uu u u

Legend: u = unchanged

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

inter rupt ve cto r (008h or 0018 h).

2: Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled

(BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is ‘0’.

TABLE 4-4: REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

RCON IPEN SBOREN —RITO PD POR BOR 60

STKPTR STKFUL STKUNF —STKPTR<4:0> 72

Legend: — = unimplemented locations, r ead as ‘0’. Shaded bits are not used for Resets.

PIC18(L)F2X/4XK22

DS41412F-page 68  2010-2012 Microchip Technology Inc.

TABLE 4-5: CONFIGURATION REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CONFIG2L — — — BORV<1:0> BOREN<1:0> PWRTEN 358

CONFIG2H — — WDPS<3:0> WDTEN<1:0> 359

CONFIG3H MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360

CONFIG4L DEBUG XINST — — — LVP —STRVEN 361

Legend: — = unimplemented locations, r ead as ‘0’. Shaded bits are not used for Resets.

 2010-2012 Microchip Technology Inc. DS41412F-page 69

PIC18(L)F2X/4XK22

5.0 MEMORY ORGANIZATION

There are three types of memory in PIC18 Enhanced

microcontroller devices:

• Program Memory

• Data RAM

• Data EEPROM

As Harvard arc hitecture devices, the da ta and progra m

memories use separate buses; this allows for

concurr ent access of the two memory spaces. The data

EEPROM, for practical purposes, can be regarded as

a peripheral device, since it is addressed and accessed

through a set of control registers.

Additional detailed information on the operation of the

Flash program memory is provided in Section 6.0

“Flash Program Memory”. Data EEPROM is

discussed separately in Section 7.0 “Data EEPROM

Memory”.

5.1 Program Memory Organization

PIC18 microcontrollers implement a 21-bit program

counter, which is capable of addressing a 2-Mbyte

progra m memory sp ace. Acces sing a lo cation b etween

the upper boundary of the physically implemented

memory and the 2-Mbyte address will return all ‘0’s (a

NOP instr ucti on).

This family of devices contain the following:

• PIC18(L)F23K22, PIC18(L)F43K22: 8 Kbytes of

Flash Memory, up to 4,096 single-word instructions

• PIC18(L)F24K22, PIC18(L)F44K22: 16 Kbytes of

Flash Memory, up to 8,192 single-word instructions

• PIC18(L)F25K22, PIC18(L)F45K22: 32 Kbytes of

Flash Memory, up to 16,384 single-word instruc-

tions

• PIC18(L)F26K22, PIC18(L)F46K22: 64 Kbytes of

Flash Memory, up to 37,768 single-word

instructions

PIC18 devices have two interrupt vectors. The Reset

vector address is at 0000h and the interrupt vector

addresses are at 0008h and 0018h.

The program memory map for PIC18(L)F2X/4XK22

devices is shown in Figure 5-1. Memory block details

are shown in Figure 20-2.

PIC18(L)F2X/4XK22

DS41412F-page 70  2010-2012 Microchip Technology Inc.

FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18(L)F2X/4XK22 DEVICES

5.1.1 PROGRAM COUNTER

The Progra m Counter (PC) s pecifies the address of the

instruction to fetch for execution. The PC is 21 bits wide

and is contained in three separate 8-bit registers. The

low byte, known as the PCL register, is both readable

and wr itable. Th e high byt e, or PCH regi ster, contains

the PC<1 5:8> bits; it is not directly re adable or writ able.

Update s to the PCH register are performe d through the

PCLATH register. The upper byte is called PCU. This

directly readable or writable. Updates to the PCU

The contents of PCLATH and PCLATU are transferred

to the program counter by any operation that writes

PCL. Similarly, the upper two bytes of the program

counter are tran sferred to PCL ATH and PCLATU by an

operation that reads PCL. This is useful for computed

offsets to the PC (see Section 5.2.2.1 “Computed

GOTO”).

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the Least Signific ant bit of PCL is fixed to

a value of ‘0’. The PC increments by two to address

sequential instructions in the program memory.

The CALL, RCALL, GOTO and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

5.1.2 RETURN ADDRESS STACK

The r eturn a ddre ss s tack allows a ny co mb ination of up

to 31 program calls and interrupts to occur. The PC is

pushed onto the stack when a CALL or RCALL

instruction is executed or an interrupt is Acknowled ged.

The PC value is pulled off the stack on a RETURN,

RETLW or a RETFIE instruction . PCLATU and PCLATH

are not affected by any of the RETURN or CALL

instructions.

The stac k operates as a 31-word by 21-bit RAM and a

5-bit Stack Pointer, STKPTR. The stack space is not

part of either program or data sp ace. The Stack Pointer

is readable and writable and the address on the top of

the stac k is readable and writable through the Top-of-

Stack (TOS) Special File Registers. Data can also be

pushed to, or popped from the stack, using these

registers.

PC<20:0>

Stack Level 1



Stack Level 31

Reset Vector

Low Priority Interrupt Vector



CALL,RCALL,RETURN

RETFIE,RETLW 21

0000h

0018h

On-Chip

Program Memory

High Priority Interrupt Vector 0008h

User Memory Space

1FFFFFh

4000h

3FFFh

Read ‘0’

200000h

8000h

7FFFh

On-Chip

Program Memory

Read ‘0’

1FFFh

2000h

On-Chip

Program Memory

Read ‘0’

PIC18(L)F25K22

PIC18(L)F45K22

PIC18(L)F24K22

PIC18(L)F44K22

PIC18(L)F23K22

PIC18(L)F43K22

Read ‘0’

FFFFh

PIC18(L)F26K22

PIC18(L)F46K22

On-Chip

Program Memory

10000h

 2010-2012 Microchip Technology Inc. DS41412F-page 71

PIC18(L)F2X/4XK22

A CALL type instruction causes a push onto the stack;

the Stack Pointer is first incremented and the location

pointed to by the Stack Pointer is written with the

contents of the PC (already pointing to the instruction

follow in g the CALL). A RETURN type ins tru cti on c au se s

a pop from the stack; the contents of the location

pointed to by the STKPTR are transferred to the PC

and then the Stack Pointer is decremented.

The Stack Pointer is initialized to ‘00000’ after all

Resets. There is no RAM associated with the location

corresponding to a Stack Pointer value of ‘00000’; this

is only a R es et v alu e. Status bit s in dic at e if the stack is

full or has overflowed or has underflowed.

5.1.2.1 Top-of-Stack Access

Only the top of the return address stack (TOS) is readable

and writable. A set of three registers, TOSU:TOSH:TOSL,

hold the contents of the stack location pointed to by the

STKPTR register (Figure 5-2). This allows users to

implement a software stack if necessary. After a CALL,

RCALL or interrupt, the software can read the pushed

value by reading the TOSU:TOSH:TOSL registers. These

values can be placed on a user defined software stack. At

return time, the software can return these values to

TOSU:TOSH:TOSL and do a return.

The user must disable the Global Interrupt Enable (GIE)

bits while accessing the stack to prevent inadvertent

stack corruption.

FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

5.1.2.2 Return Stack Pointer (STKPTR)

The STKPTR regis ter (Register 5-1) cont ains the S tac k

Pointer value, the STKFUL (stack full) Status bit and

the STKUNF (Stack Underflow) Status bits. The value

of the Stack Pointer can be 0 through 31. The Stack

Pointer increments before values are pushed onto the

stack and decrements after values are popped off the

stack. On Reset, the Stack Pointer value will be zero.

The user may read and write the Stack Pointer value.

This feature can be used by a Real-Time Operating

System (RTOS) for return stack maintenance.

Aft er the PC is pu shed ont o the st a ck 31 ti mes (w itho ut

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit is cleared by software or by a

POR.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack Over-

flow Reset Enable) Configuration bit. (Refer to

Section 24.1 “Configuration Bit s” for a desc ription of

the device Configuration bits.) If STVREN is set

(default), the 31st push will push the (PC + 2) value

onto the stack, set the STKFUL bit and reset the

device. The STKFUL bit will remain set and the Stack

Pointer will be set to zero.

If STVREN is clea red, the STKFUL bit will be se t on the

31st push and the Stack Pointer will increment to 31.

Any additional pushes will not overwrite the 31st push

and STKPTR will remain at 31.

When the stack has been popped enough times to

unload th e stack, the ne xt pop will return a value of zero

to the PC and sets the STKUNF bit, while the Stack

Pointer remains at zero. The STKUNF bit will remain

set until cleared by software or until a POR occurs.

00011

001A34h

11111

11110

11101

00010

00001

00000

00010

Return Address Stack <20:0>

Top-of-Stack 000D58h

TOSLTOSHTOSU 34h1Ah00h STKPTR<4:0>

Top-of-Stack Registers S tack Pointer

Note: Ret urni ng a value of ze ro to the PC on an

underflow has the effect of vectoring the

program to the Reset vector, where the

stack conditions can be verified and

appropriate actions can be taken. This is

not t he same as a R ese t, as the conte nts

of the SFRs are not affected.

PIC18(L)F2X/4XK22

DS41412F-page 72  2010-2012 Microchip Technology Inc.

5.1.2.3 PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, the

ability t o pus h va lue s on to the st ac k and pull values of f

the stack without disturbing normal program execution

is a desirable feature. The PIC18 instruction set

includes two instructions, PUSH and POP, that permit

the TOS to be manipulated under software control.

TO SU, T OSH and TOSL ca n be modi fied to pl ace da ta

or a return address on the stack.

The PUSH instruction places the current PC value onto

the stack. This increments the Stack Pointer and loads

the current PC value onto the stack.

The POP instruction discards the current TOS by decre-

menting the Stack Pointer. The previous value pushed

onto the stack then becomes the TOS value.

5.2 Register Definitions: Stack Pointer

5.2.0.1 Stack Full and Underflow Resets

Devic e Rese t s on Stack Overfl ow an d Stack U nderf low

conditions are enabled by setting the STVREN bit in

Config ura tion Regi ster 4L. When STVREN is set, a full

or underflow will set the appropriate STKFUL or

STKUNF bit and then cause a device Reset. When

STVREN is cleared, a full or underflow co ndition will set

the appropriate STKFUL or STKUNF bit but not cause

a device Reset. The STKFUL or STKUNF bits are

cleared by the user software or a Power-on Reset.

5.2.1 FAST REGISTER STACK

A fast register stack is provided for the Status, WREG

and BSR registers, to provide a “fast return” option for

interrupts. The stack for each register is only one level

deep and is neither readable nor writable. It is loaded

with the current value of the corresponding register

when the processor vectors for an interrupt. All inter-

rupt sources will push values into the stack registers.

The values in the registers are then loaded back into

their associated registers if the RETFIE, FAST

instruction is used to return from the interrupt.

If both low and high priority interrupts are enabled, the

stack registers cannot be used reliably to return from

low priority interrupts . If a high priority interrupt occurs

while s ervicing a low pri ority interru pt, the stac k register

values stored by the low priority interrupt will be

overwritten. In these cases, users must save the key

registers by software during a low priority interrupt.

If interru pt priority i s not used, all interrupt s may use th e

fast register stack for returns from interrupt. If no

interrupts are used, the fast regis ter s t ac k c an be use d

to restore the Status, WREG and BSR registers at the

end of a subroutine call. To use the fast register stack

for a subroutine call, a CALL label,FAST instru ction

must be executed to save the Status, WREG and BSR

registers to the fast register stack. A RETURN,FAST

instruction is then executed to restore these registers

from the fast regist er st a ck.

Example 5-1 shows a sou rce code e xampl e that uses

the fast register stack during a subroutine call and

return.

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL(1) STKUNF(1) — STKPTR<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 STKFUL: Stack Full Flag bit(1)

1 = Stack became full or overflowed

0 = Stack has not become full or overflowed

bit 6 STKUNF: Stack Underflow Flag bit(1)

1 = Stack Underflo w oc cur red

0 = Stack Underflo w did not occu r

bit 5 Unimplemented: Read as ‘0’

bit 4-0 STKPTR<4:0>: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

 2010-2012 Microchip Technology Inc. DS41412F-page 73

PIC18(L)F2X/4XK22

EXAMPLE 5-1: FAST REGISTER STACK

CODE EXAMPLE

5.2.2 LOOK-UP TABLES IN PROGRAM

MEMORY

There may be programming situations that require the

creation of data structures, or look-up tables, in

program memory. For PIC18 devices, look-up tables

can be imple me nted in two ways :

• Computed GOTO

• Table Reads

5.2.2.1 Computed GOTO

A comput ed GOTO is a ccom pli shed by adding an offset

to the program counter. An example is shown in

Example 5-2.

A look-up table can be formed with an ADDWF PCL

instruction and a group of RETLW nn instructions. The

W register is loa ded wi th an offset into the ta bl e befo re

execut ing a c al l to tha t table. The first instruction of th e

called routine is the ADDWF PCL instruction. The next

instruction executed will be one of the RETLW nn

instructions that returns the value ‘nn’ to the calling

function.

The offset value (in WREG) specifies the number of

bytes that the program counter should advance and

should be multiples of two (LSb = 0).

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

EXAMPLE 5-2: COMP UTED GOTO USIN G

AN OFFSET VALUE

5.2.2.2 Table Reads and Table Writes

A better method of storing data in program memory

allow s two bytes of dat a to be stored in each instruc tion

location.

Look-up table data may be stored two bytes per

program word by using table reads and writes. The

Table Pointer (TBLPTR) register specifies the byte

address and the Table Latch (TABLAT) register

cont ains the da ta that is read from o r written to pro gram

memory. Data is transferred to or from program

memory one byte at a time.

Table read and table write operations are discussed

further in Section 6.1 “Table Reads and Table

Writes”.

CALL SUB1, FAST ;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK



SUB1 



RETURN, FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

MOVF OFFSET, W

CALL TABLE

ORG nn00h

TABLE ADDWF PCL

RETLW nnh

PIC18(L)F2X/4XK22

DS41412F-page 74  2010-2012 Microchip Technology Inc.

5.3 PIC18 Instruction Cycle

5.3.1 CLOCKING SCHEME

The microcontroller clock input, whether from an

internal or external source, is internally divided by four

to generate four non-overlapping quadrature clocks

(Q1, Q2, Q3 and Q4). Interna lly, the program counter i s

incremented on every Q1; the instruction is fetched

from the program memory and latched into the

instruction register during Q4. The instruction is

decode d and exec uted during the follow ing Q1 th rough

Q4. The clocks and instruction execution flow are

shown in Figure 5-3.

5.3.2 INSTRUCTION FLOW/PIPELINING

An “Instruction Cycle” consists of four Q cycles: Q1

through Q4. The instruction fetch and execute are

pipelined in such a manner that a fetch takes one

instruction cycle, while the decode and execute take

another instruction cycle. However, due to the

pipelining, each instruction effectively ex ecutes in one

cycle. If an instruction causes the program counter to

change (e.g., GOTO), then two cycles are required to

complete the instruct ion (Example 5-3).

A fetch cycle begins with the Program Counter (PC)

incrementing in Q1.

In the ex ecution cycle , the fetched instruction i s latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q 3 and Q4 c ycles. Dat a mem ory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 5-3: CLOCK/INSTRUCTION CYCLE

EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKOUT

(RC mode)

PC PC + 2 PC + 4

Fetch INST (PC)

Execute INST (PC – 2)

Fetch INST (PC + 2)

Execute IN ST (P C)

Fetch INST (PC + 4)

Execute INST (PC + 2)

Internal

Phase

Clock

All instruc tions are single cycle, exc ept for any program bran ches. These tak e two cycles sin ce the fetch instruct ion

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. BRA SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

 2010-2012 Microchip Technology Inc. DS41412F-page 75

PIC18(L)F2X/4XK22

5.3.3 INSTRUCTIONS IN PROGRAM

MEMORY

The program memory is addressed in bytes.

Instr uctions are stored as ei ther two byt es or four byte s

in program memory. The Least Significant Byte of an

instruc tion wo rd is alway s stored in a progra m memo ry

location with an even address (LSb = 0). To maintain

alignment with instruction boundaries, the PC

increm ents in step s of two and the LSb will a lways rea d

‘0’ (see Section 5.1.1 “Program Counter”).

Figure 5-4 shows an ex am ple of h ow instruction word s

are stored in the program memory.

The CALL and GOTO instructions have the absolute

program memory address embedded into the

instruction. Since instructions are always stored on word

boundaries, the data contained in the instruction is a

word address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Figure 5-4 shows how the

instruction GOTO 0006h is encoded in the program

memory. Program branch instructions, which encode a

relative address offset, operate in the same manner . The

of fset value stored in a branch instruction represent s the

number of single-word instructions that the PC will be

offset by. Section 25.0 “Instruction Set Summary”

provides further details of the instruction s et.

FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY

5.3.4 TWO-WORD INSTRUCTIONS

The standard PIC18 instruction set has four two-word

instructions: CALL, MOVFF, GOTO and LSFR. In all

cases, the second word of the instruction always has

‘1111’ as its four M ost Si gnific ant bi ts; the ot her 12 bit s

are literal data, usually a data memory address.

The use of ‘1111’ in the 4 MSbs of an instruction

specifies a special form of NOP. If the instruction is

executed in proper sequence – immediately after the

first word – the data in the second word is accessed

and used by the instruction sequence. If the first word

is skipped for some reason and the second word is

executed by itself, a NOP is executed instead. This is

necessary for cases when the two-word instruction is

prec ed ed b y a co nd i ti ona l in s tru ct i on t h at c han g es t he

PC. Example 5-4 shows how this works.

EXAMPLE 5-4: TWO- WORD INSTRUCTIONS

Word Address

LSB = 1LSB = 0

Program Memory

Byte Locations  000000h

000002h

000004h

000006h

Instruction 1: MOVLW 055h 0Fh 55h 000008h

Instruction 2: GOTO 0006h EFh 03h 00000Ah

F0h 00h 00000Ch

Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh

F4h 56h 000010h

000012h

000014h

Note: See Section 5.8 “PIC18 Instruction

Execution and the Extended Instruc-

tion Set” for information on two-word

instructions in the extended instruction set.

CASE 1:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word

1111 0100 0101 0110 ; Execute this word as a NOP

0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word

1111 0100 0101 0110 ; 2nd word of instruction

0010 0100 0000 0000 ADDWF REG3 ; continue code

PIC18(L)F2X/4XK22

DS41412F-page 76  2010-2012 Microchip Technology Inc.

5.4 Data Memory Organizati on

The data memory in PIC18 dev ices is implemented as

static RAM. Each register in the data memory has a

12-bit address, allowing up to 4096 bytes of data

memory. The memory spac e is divid ed into as man y as

16 banks that contain 256 bytes each. Figures 5-5

through 5-7 show the dat a memory orga nization for the

PIC18(L)F2X/4XK22 devices.

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and per ipheral functio ns, while GP Rs are used for dat a

storage and scratchpad operations in the user’s

applic ation. Any read of an unim plement ed locat ion will

read as ‘0’s.

The instruction set and architecture allow operations

across all banks. The entire data memory may be

accessed by Direct, Indirect or Indexed Addressing

modes. Addressing modes are discussed later in this

subsection.

To ensure that commonly used registers (SFRs and

select GP Rs) c an b e ac cess ed i n a si ngle cycle, PI C18

devices implement an Ac ce ss Bank. This is a 256 -by te

memor y space that provid es fa st acc ess to SFRs and

the lower portion of GPR Bank 0 without using the Bank

Select Register (BSR). Section 5.4.2 “Access Bank”

provides a detailed description of the Access RAM.

5.4. 1 BANK SELECT REGISTER (BSR)

Large areas of data memory require an efficient

addressing scheme to make rapid access to any

address possible. Ideally, this means that an entire

address doe s no t need to be provide d for e ach read or

write operation. For PIC18 devices, this is accom-

plished with a RAM banking scheme. This divides the

memory space into 16 contiguous banks of 256 bytes.

Depending on the instruction, each location can be

addressed directly by its full 12-bit address, or an 8-bit

low-order address and a 4-bit Bank Pointer.

Most in struct ions in th e PIC1 8 instruct ion se t make us e

of the Ban k Pointer , known as the Ba nk Select Reg ister

(BSR). This SFR holds the 4 Most Significant bits of a

location’s address; the instruction itself includes the

8 Least Significant bits. Only the four lower bits of the

BSR are implem ented (BSR<3:0 >). The upper fou r bits

are unused; they will always read ‘0’ and cannot be

written to. T he BSR can be l oaded direct ly by using the

MOVLB instructi on.

The value of the BSR indicates the bank in data

memory; the eight bits in the instruction show the

location in the bank and can be thought of as an offset

from the bank’s lower boundary. The relationship

betwee n the BSR’ s valu e an d the ba nk div is ion in data

memory is shown in Figu res 5-5 through 5-7.

Since up to 16 regis ters m ay share the s ame l ow-order

address, the user must always be careful to ensure th at

the proper bank is selected before performing a data

read or write. For example, writing what should be

progra m data to an 8-bit ad dres s of F 9h w h il e th e BSR

is 0Fh will end up resetting the program counter.

While any bank can be sel ec ted, only those bank s that

are actually implemented can be read or written to.

Writes to unimplemented banks are ignored, while

reads from unimplemented banks will return ‘0’s. Eve n

so, the STATUS register will still be affected as if the

operation was successful. The data memory maps in

Figures 5-5 through 5-7 indicate which banks are

implemented.

In the core PIC18 instruction set, only the MOVFF

instruction fully specifies the 12-bit address of the

source a nd target reg isters. This i nstruction ig nores the

BSR comple tely when it ex ecutes. All othe r instruction s

include only the low-order address as an operand and

must use either the BSR or the Access Bank to locate

their targ et regi ster s.

Note: The operation of some aspects of data

memory are changed when the PIC18

extended instruction set is enabled. See

Section 5.7 “Data Memory and the

Extended Instruction Set” for more

information.

 2010-2012 Microchip Technology Inc. DS41412F-page 77

PIC18(L)F2X/4XK22

FIGURE 5-5: DATA MEMORY MAP FOR PIC18(L)F23K22 AND PIC18(L)F43K22 DEVICES

Bank 0

Bank 1

Bank 14

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1111

060h

05Fh

F60h

FFFh

00h

5Fh

60h

FFh

Access Bank

When ‘a’ = 0:

The BSR is ignored and the

Access Bank is used.

The first 96 bytes are

general purpose RAM

(from Bank 0).

The second 160 bytes are

Special Function Registers

(from Bank 15).

When ‘a’ = 1:

The BSR spec ifies t he Ban k

used by the instruction.

F5Fh

F00h

EFFh

1FFh

100h

0FFh

000h

Access RAM

FFh

00h

FFh

00h

FFh

00h

GPR

SFR(1)

Access RAM Hig h

Access RAM Low

Bank 2

= 0110

= 0010

(SFRs)

2FFh

200h

3FFh

300h

4FFh

400h

5FFh

500h

6FFh

600h

7FFh

700h

8FFh

800h

9FFh

900h

AFFh

A00h

BFFh

B00h

CFFh

C00h

DFFh

D00h

E00h

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

= 0011

= 0100

= 0101

= 0111

= 1000

= 1001

= 1010

= 1011

= 1100

= 1101

= 1110

Unused

Read 00h

Unused F38h

F37h

Note 1: Addresses F38h through F5Fh are

also used by SFRs, but are not

part of the Access RAM. Users

must always use the complete

address or load the proper BSR

value to access these registers.

SFR

PIC18(L)F2X/4XK22

DS41412F-page 78  2010-2012 Microchip Technology Inc.

FIGURE 5-6: DATA MEMORY MAP FOR PIC18(L)F24K22 AND PIC18(L)F44K22 DEVICES

Bank 0

Bank 1

Bank 14

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1111

060h

05Fh

F60h

FFFh

00h

5Fh

60h

FFh

Access B ank

When ‘a’ = 0:

The BSR is ignored and the

Access Bank is used.

The first 96 bytes are

general purpose RAM

(from Bank 0).

The second 160 bytes are

Special Function Registers

(from Bank 15).

When ‘a’ = 1:

The BSR spec ifies t he Ban k

used by the instruction.

F5Fh

F00h

EFFh

1FFh

100h

0FFh

000h

Access RAM

FFh

00h

FFh

00h

FFh

00h

GPR

SFR(1)

Access RAM High

Access RAM Low

Bank 2

= 0110

= 0010

(SFRs)

2FFh

200h

3FFh

300h

4FFh

400h

5FFh

500h

6FFh

600h

7FFh

700h

8FFh

800h

9FFh

900h

AFFh

A00h

BFFh

B00h

CFFh

C00h

DFFh

D00h

E00h

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPR

FFh

00h

= 0011

= 0100

= 0101

= 0111

= 1000

= 1001

= 1010

= 1011

= 1100

= 1101

= 1110

Unused

Read 00h

Unused

SFR

Note 1: Addresses F38h through F5Fh are

also used by SFRs, but are not

part of the Access RAM. Users

must always use the complete

address or load the proper BSR

value to access these registers.

F38h

F37h

 2010-2012 Microchip Technology Inc. DS41412F-page 79

PIC18(L)F2X/4XK22

FIGURE 5-7: DATA MEMORY MAP FOR PIC18(L)F25K22 AND PIC18(L)F45K22 DEVICES

Bank 0

Bank 1

Bank 14

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1111

060h

05Fh

F60h

FFFh

00h

5Fh

60h

FFh

Access B ank

When ‘a’ = 0:

The BSR is ignored and the

Access Bank is used.

The first 96 bytes are

general purpose RAM

(from Bank 0).

The second 160 bytes are

Special Function Registers

(from Bank 15).

When ‘a’ = 1:

The BSR spec ifies t he Ban k

used by the instruction.

F5Fh

F00h

EFFh

1FFh

100h

0FFh

000h

Access RAM

FFh

00h

FFh

00h

FFh

00h

GPR

SFR(1)

Access RAM High

Access RAM Low

Bank 2

= 0110

= 0010

(SFRs)

2FFh

200h

3FFh

300h

4FFh

400h

5FFh

500h

6FFh

600h

7FFh

700h

8FFh

800h

9FFh

900h

AFFh

A00h

BFFh

B00h

CFFh

C00h

DFFh

D00h

E00h

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPR

FFh

00h

= 0011

= 0100

= 0101

= 0111

= 1000

= 1001

= 1010

= 1011

= 1100

= 1101

= 1110

Unused

Read 00h

Unused

GPR

SFR

Note 1: Addresses F38h through F5Fh are

also used by SFRs, but are not

part of the Access RAM. Users

must always use the complete

address or load the proper BSR

value to access these registers.

F38h

F37h

PIC18(L)F2X/4XK22

DS41412F-page 80  2010-2012 Microchip Technology Inc.

FIGURE 5-8: DATA MEMORY MAP FOR PIC18(L)F26K22 AND PIC18(L)F46K22 DEVICES

Bank 0

Bank 1

Bank 14

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1111

060h

05Fh

00h

5Fh

60h

FFh

Access B ank

When ‘a’ = 0:

The BSR is ignored and the

Access Bank is used.

The first 96 bytes are

general purpose RAM

(from Bank 0).

The second 160 bytes are

Special Function Registers

(from Bank 15).

When ‘a’ = 1:

The BSR spec ifies t he Ban k

used by the instruction.

1FFh

100h

0FFh

000h

Access RA M

FFh

00h

FFh

00h

GPR

Access RAM High

Access RAM Low

Bank 2

= 0110

= 0010

(SFRs)

2FFh

200h

3FFh

300h

4FFh

400h

5FFh

500h

6FFh

600h

7FFh

700h

8FFh

800h

9FFh

900h

AFFh

A00h

BFFh

B00h

CFFh

C00h

DFFh

D00h

E00h

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPR

FFh

00h

= 0011

= 0100

= 0101

= 0111

= 1000

= 1001

= 1010

= 1011

= 1100

= 1101

= 1110

GPR

Note 1: Addresses F38h through F5Fh are

also used by SFRs, but are not

part of the Access RAM. Users

must always use the complete

address or load the proper BSR

value to access these registers.

F60h

FFFh

F5Fh

F00h

FFh

00h

SFR(1)

GPR

SFR

F38h

F37h

 2010-2012 Microchip Technology Inc. DS41412F-page 81

PIC18(L)F2X/4XK22

FIGURE 5-9: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)

Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to

the registers of the Access Bank.

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Data Memory

Bank Select(2)

From Opcode(2)

0000

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

Bank 3

through

Bank 13

0011 11111111

BSR(1)

PIC18(L)F2X/4XK22

DS41412F-page 82  2010-2012 Microchip Technology Inc.

5.4.2 ACCESS BANK

While the use of the BSR with an embedded 8-bit

address allows users to address the entire range of

data mem ory, it also mean s th at the user must a lways

ensure that the correct bank is selected. Otherwise,

data may be read from or written to the wrong location.

This can be disastrous if a GPR is the intended target

of an operation, but an SFR is written to instead.

Verifying and/or changing the BSR for each read or

write to data memory can become very inefficient.

To streamline ac cess for the most comm only used dat a

memory locations, the data memory is configured with

an Access Bank, which allows users to access a

mapped block of memory without specifying a BSR.

The Acc ess Bank con sist s o f the f irst 96 byte s of mem-

ory (00h-5Fh) i n Bank 0 an d the last 160 bytes of mem-

ory (60h-FFh) in Block 15. The lower half is known as

the “Access RAM” and is composed of GPRs. This

upper half is also where the device’s SFRs are

mapped. These two areas are mapped contiguously in

the Access Bank and can be addressed in a linear

fashion by an 8-bit address (Figures 5-5 thro ugh 5-7).

The Access Bank is used by core PIC18 instructions

that include the Access RAM bit (the ‘a’ parameter in

the instruction). When ‘a’ is equal to ‘1’, the in str uct i on

uses the BSR and the 8-bit address included in the

opcode for the data memory address. When ‘a’ is ‘0’,

however, the instruction is forced to use the Access

Bank address map; the current value of the BSR is

ignored entirely.

Using this “forced” addressing allows the instruction to

operate on a data address in a single cycle, without

updating the BSR first. For 8-bit addresses of 60h and

above, t his mean s that us ers can ev aluate an d operat e

on SFRs more efficiently. The Access RAM below 60h

is a goo d place for da ta values that the user might need

to access rapidly, such as immediate computational

results or common program variables. Access RAM

also allows for faster and more code efficient context

saving and switching of variables.

The mapping of the Access Bank is slightly different

when the extended instruction set is enabled (XINST

Configuration bit = 1). Th is i s di sc us se d i n m ore d etail

in Section 5.7.3 “Mapping the Access Bank in

Indexed Literal Offset Mode”.

5.4.3 GENERAL PURPOSE REGISTER

FILE

PIC18 devices may have banked memory in the GPR

area. This is data RAM, which is available for use by all

instructions. GPRs start at the bottom of Bank 0

(address 000h) and grow upwards towards the bottom of

the SFR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other R eset s.

5.4.4 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral modules for controlling

the desire d operation of the device. These regist ers are

implemented as static RAM. SFRs start at the top of

data memory (FFFh) and extend downward to occupy

the top portion of Bank 15 (F38h to FFFh). A list of

these registers is given in Table 5-1 and Table 5-2.

The SFRs can be classified into two sets: those

associated with the “core” device functionality (ALU,

Resets and interrupts) and those related to the

peripheral functions. The Reset and interrupt registers

are described in their respective chapters, while the

ALU’s STATUS register is described later in this

section. Registers related to the operation of a

peripheral feature are described in the chapter for that

peripheral.

The SFRs are typically distributed among the

periphera ls w ho se functions th ey c ontr ol. U nus ed SFR

locations are unimplemented and read as ‘0’s.

 2010-2012 Microchip Technology Inc. DS41412F-page 83

PIC18(L)F2X/4XK22

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F2X/4XK22 DEVICES

Address Name Address Name Address Name Address Name Address Name

FFFh TOSU FD7h TMR0H FAFh SPBRG1 F87h —(2) F5Fh CCPR3H

FFEh TOSH FD6h TMR0L FAEh RCREG1 F86h —(2) F5Eh CCPR3L

FFDh TOSL FD5h T0CON FADh TXREG1 F85h —(2) F5Dh CCP3CON

FFCh STKPTR FD4h —(2) FACh TXSTA1 F84h PORTE F5Ch PWM3CON

FFBh PCLATU FD3h OSCCON FABh RCSTA1 F83h PORTD(3) F5Bh ECCP3AS

FFAh PCLATH FD2h OSCCON2 FAAh EEADRH(4) F82h PORTC F5Ah PSTR3CON

FF9h PCL FD1h WDTCON FA9h EEADR F81h PORTB F59h CCPR4H

FF8h TBLPTRU FD0h RCON FA8h EEDATA F80h PORTA F58h CCPR4L

FF7h TBLPTRH FCFh TMR1H FA7h EECON2(1) F7Fh IPR5 F57h CCP4CON

FF6h TBLPTRL FCEh TMR1L FA6h EECON1 F7Eh PIR5 F56h CCPR5H

FF5h TABLAT FCDh T1CON FA5h IPR3 F7Dh PIE5 F55h CCPR5L

FF4h PRODH FCCh T1GCON FA4h PIR3 F7Ch IPR4 F54h CCP5CON

FF3h PRODL FCBh SSP1CON3 FA3h PIE3 F7Bh PIR4 F53h TMR4

FF2h INTCON FCAh SSP1MSK FA2h IPR2 F7Ah PIE4 F52h PR4

FF1h INTCON2 FC9h SSP1BUF FA1h PIR2 F79h CM1CON0 F51h T4CON

FF0h INTCON3 FC8h SSP1ADD FA0h PIE2 F78h CM2CON0 F50h TMR5H

FEFh INDF0(1) FC7h SSP1STAT F9Fh IPR1 F77h CM2CON1 F4Fh TMR5L

FEEh POSTINC0(1) FC6h SSP1CON1 F9Eh PIR1 F76h SPBRGH2 F4Eh T5CON

FEDh POSTDEC0(1) FC5h SSP1CON2 F9Dh PIE1 F75h SPBRG2 F4Dh T5GCON

FECh PREINC0(1) FC4h ADRESH F9Ch HLVDCON F74h RCREG2 F4Ch TMR6

FEBh PLUSW0(1) FC3h ADRESL F9Bh OSCTUNE F73h TXREG2 F4Bh PR6

FEAh FSR0H FC2h ADCON0 F9Ah —(2) F72h TXSTA2 F4Ah T6CON

FE9h FSR0L FC1h ADCON1 F99h —(2) F71h RCSTA2 F49h CCPTMRS0

FE8h WREG FC0h ADCON2 F98h —(2) F70h BAUDCON2 F48h CCPTMRS1

FE7h INDF1(1) FBFh CCPR1H F97h —(2) F6Fh SSP2BUF F47h SRCON0

FE6h POSTINC1(1) FBEh CCPR1L F96h TRISE F6Eh SSP2ADD F46h SRCON1

FE5h POSTDEC1(1) FBDh CCP1CON F95h TRISD(3) F6Dh SSP2STAT F45h CTMUCONH

FE4h PREINC1(1) FBCh TMR2 F94h TRISC F6Ch SSP2CON1 F44h CTMUCONL

FE3h PLUSW1(1) FBBh PR2 F93h TRISB F6Bh SSP2CON2 F43h CTMUICON

FE2h FSR1H FBAh T2CON F92h TRISA F6Ah SSP2MSK F42h VREFCON0

FE1h FSR1L FB9h PSTR1CON F91h —(2) F69h SSP2CON3 F41h VREFCON1

FE0h BSR FB8h BAUDCON1 F90h —(2) F68h CCPR2H F40h VREFCON2

FDFh INDF2(1) FB7h PWM1CON F8Fh —(2) F67h CCPR2L F3Fh PMD0

FDEh POSTINC2(1) FB6h ECCP1AS F8Eh —(2) F66h CCP2CON F3Eh PMD1

FDDh POSTDEC2(1) FB5h —(2) F8Dh LATE(3) F65h PWM2CON F3Dh PMD2

FDCh PREINC2(1) FB4h T3GCON F8Ch LATD(3) F64h ECCP2AS F3Ch ANSELE

FDBh PLUSW2(1) FB3h TMR3H F8Bh LATC F63h PSTR2CON F3Bh ANSELD

FDAh FSR2H FB2h TMR3L F8Ah LATB F62h IOCB F3Ah ANSELC

FD9h FSR2L FB1h T3CON F89h LATA F61h WPUB F39h ANSELB

FD8h STATUS FB0h SPBRGH1 F88h —(2) F60h SLRCON F38h ANSELA

Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.

3: PIC18(L)F4XK22 devices only.

4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.

PIC18(L)F2X/4XK22

DS41412F-page 84  2010-2012 Microchip Technology Inc.

TABLE 5-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

FFFh TOSU — — — Top-of-Stack, Upper Byte (TOS<20:16>) ---0 0000

FFEh TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000

FFDh TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000

FFCh STKPTR STKFUL STKUNF —STKPTR<4:0>00-0 0000

FFBh PCLATU — — — Holding R egister for PC<20 :16> ---0 0000

FFAh PCLATH Holding R egister for PC<15:8> 0000 0000

FF9h PCL Holding Register for PC<7:0> 0000 0000

FF8h TBLPTRU —— Program Memory Table Pointe r Upper Byt e(TBLPTR<21:16>) --00 0000

FF7h TBLPTR H Program Memo ry Table Point er H igh By te(T B LP T R<15:8>) 0000 0000

FF6h TBLPTRL Program Memory Table Pointer Low Byte(TBLPTR<7:0>) 0000 0000

FF5h TABLAT Program Memory Table Latch 0000 0000

FF4h PRODH Product Register, High Byte xxxx xxxx

FF3h PRODL Product Register, Low Byte xxxx xxxx

FF2h INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x

FF1h INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1

FF0h INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00

FEFh INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) ---- ----

FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) ---- ----

FED h POSTDEC0 Uses c ontents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) ---- ----

FECh PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) ---- ----

FEBh PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –

value of FSR0 offset by W ---- ----

FEAh FSR0H ———— Indirect Data Memory Address Pointer 0, High Byte ---- 0000

FE9h FSR0L Indirec t Data Memory Address Pointer 0, Low Byte xxxx xxxx

FE8h WREG Working Register xxxx xxxx

FE7h INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) ---- ----

FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) ---- ----

FE5h POSTDEC1 Uses contents of FSR1 to address data memory – valu e of FSR1 post-d ecremented (not a physical register) ---- ----

FE4h PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) ---- ----

FE3h PLUSW1 Use s cont ents of FSR1 to address data memory – value of FSR1 pre-increm ented (not a physical register) –

value of FSR1 offset by W ---- ----

FE2h FSR1H ———— Indirect Data Memory Address Pointer 1, High Byte ---- 0000

FE1h FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx

FE0h BSR ———— Bank Select Register ---- 0000

FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) ---- ----

FDEh POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) ---- ----

FDDh POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) ---- ----

FDCh PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) ---- ----

FDBh PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –

value of FSR2 offset by W ---- ----

FDAh FSR2H ———— Indirect Data Memory Address Pointer 2, High Byte ---- 0000

FD9h FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx

FD8h STATUS — — —NOVZDCC---x xxxx

FD7h TMR0H Timer0 Register, High Byte 0000 0000

FD6h TMR0L Timer0 Register, Low Byte xxxx xxxx

FD5h T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS<2:0> 1111 1111

FD3h OSCCON IDLEN IRCF<2:0> OSTS HFIOFS SCS<1:0> 0011 q000

FD2h OSCCON2 PLLRDY SOSCRUN — MFIOSEL SOSCGO PRISD MFIOFS LFIOFS 00-0 01x0

Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition

Note 1: PIC18(L)F4XK22 devices only.

2: PIC18(L)F2XK22 devices only.

3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only.

4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.

 2010-2012 Microchip Technology Inc. DS41412F-page 85

PIC18(L)F2X/4XK22

FD1hWDTCON————— ——SWDTEN---- ---0

FD0h RCON IPEN SBOREN —RITO PD POR BOR 01-1 1100

FCFh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx

FCEh TMR1L Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx

FCDh T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSCEN T1SYNC T1RD16 TMR1ON 0000 0000

FCCh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE T1GVAL T1GSS<1:0> 0000 xx00

FCBh SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000

FCAh SSP1MSK SSP1 MASK Register bits 1111 1111

FC9h SSP1BUF SSP1 Receive Buffer/Transmit Register xxxx xxxx

FC8h SSP1ADD SSP1 Address Register in I2C Slave Mode. SSP1 Baud Rate Reload Register in I2C Master Mode 0000 0000

FC7h SSP1STAT SMP CKE D/A PSR/WUA BF 0000 0000

FC6h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000

FC5h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000

FC4h ADRESH A/D Result, High Byte xxxx xxxx

FC3h ADRESL A/D Result, Low Byte xxxx xxxx

FC2h ADCON0 — CHS<4:0> GO/DONE ADON --00 0000

FC1h ADCON1 TRIGSEL — — — PVCFG<1:0> NVCFG<1:0> 0--- 0000

FC0h ADCON2 ADFM — ACQT<2:0> ADCS<2:0> 0-00 0000

FBFh CCPR1H Captur e/Co mpar e/P WM R egister 1, High Byt e xxxx xxxx

FBEh CCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxx

FBDh CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000

FBCh T MR2 Timer2 Register 0000 0000

FBBh PR2 T imer2 Period Register 1111 1111

FBAh T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000

FB9h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001

FB8h BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 0100 0-00

FB7h PWM1CON P1RSEN P1DC<6:0> 0000 0000

FB6h ECCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000

FB4h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/

DONE T3GVAL T3GSS<1:0> 0000 0x00

FB3h TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx

FB2h TMR3L Least Significant By te of the 16-bit TMR3 Register xxxx xxxx

FB1h T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 0000 0000

FB0h SPBRGH1 EUSART1 Baud Rate Generator, High Byte 0000 0000

FAFh SPBRG1 EUSART1 Baud Rate Generator, Low Byte 0000 0000

FAEh RCREG1 EUSART1 Receive Register 0000 0000

FADh TXREG1 EUSART1 Transmit Register 0000 0000

FACh TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010

FABh RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x

FAAh EEADRH(5) — — — — — — EEADR<9:8> ---- --00

FA9h EEADR EEADR<7:0> 0000 0000

FA8h EEDATA EEPROM Data Register 0000 0000

FA7h EECON2 EEPROM Control Register 2 (not a physical register) ---- --00

FA6h EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000

FA5h IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 0000 0000

FA4h PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 0000 0000

FA3h PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 0000 0000

TABLE 5-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition

Note 1: PIC18(L)F4XK22 devices only.

2: PIC18(L)F2XK22 devices only.

3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only.

4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.

PIC18(L)F2X/4XK22

DS41412F-page 86  2010-2012 Microchip Technology Inc.

FA2h IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 1111 1111

FA1h PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 0000 0000

FA0h PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 0000 0000

F9Fh IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP -111 1111

F9Eh PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF -000 0000

F9Dh PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE -000 0000

F9Ch HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0> 0000 0000

F9Bh OSCTUNE INTSRC PLLEN TUN<5:0> 00xx xxxx

F96h TRISE WPUE3 — — — —TRISE2

(1) TRISE1(1) TRISE0(1) 1--- -111

F95h TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111

F94h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111

F93h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111

F92h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111

F8Dh LATE(1) — — — — — LATE2 LATE1 LATE0 ---- -xxx

F8Ch LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx

F8Bh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx

F8Ah LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx

F89h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx

F84h PORTE(2) ————RE3— — — ---- x---

PORTE(1) ————RE3RE2RE1RE0---- x000

F83h PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000

F82h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 0000 00xx

F81h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxx0 0000

F80h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000

F7Fh IPR5 — — — — — TMR6IP TMR5IP TMR4IP ---- -111

F7Eh PIR5 — — — — — TMR6IF TMR5IF TMR4IF ---- -111

F7Dh PIE5 — — — — — TMR6IE TMR5IE TMR4IE ---- -000

F7Ch IPR4 — — — — — CCP5IP CCP4IP CCP3IP ---- -000

F7Bh PIR4 — — — — — CCP5IF CCP4IF CCP3IF ---- -000

F7Ah PIE4 — — — — — CCP5IE CCP4IE CCP3IE ---- -000

F79h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH<1:0> 0000 1000

F78h CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH<1:0> 0000 1000

F77h CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 0000 0000

F76h SPBRGH2 EUSART2 Baud Rate Generator, High Byte 0000 0000

F75h SPBRG2 EUSART2 Baud Rate Generator, Low Byte 0000 0000

F74h RCREG2 EUSART2 Receive Register 0000 0000

F73h TXREG2 EUSART2 Transmit Register 0000 0000

F72h TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010

F71h RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x

F70h BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 01x0 0-00

F6Fh SSP2BUF SSP2 Receive Buffer/Transmit Register xxxx xxxx

F6Eh SSP2ADD SSP2 Address Register in I2C Slave Mode. SSP2 Baud Rate Reload Register in I2C Mast er Mode 0000 0000

F6Dh SSP2STAT SMP CKE D/A PSR/WUA BF 0000 0000

F6Ch SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000

F6Bh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000

F6Ah SSP2MSK SSP1 MASK Register bits 1111 1111

F69h SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000

TABLE 5-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition

Note 1: PIC18(L)F4XK22 devices only.

2: PIC18(L)F2XK22 devices only.

3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only.

4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.

 2010-2012 Microchip Technology Inc. DS41412F-page 87

PIC18(L)F2X/4XK22

F68h CCPR2H Capture/Compare/PWM Register 2, High Byte xxxx xxxx

F67h CCPR2L Capture/Compare/PWM Register 2, Low Byte xxxx xxxx

F66h CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 0000 0000

F65h PWM2CON P2RSEN P2DC<6:0> 0000 0000

F64h ECCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 0000 0000

F63h PSTR2CON — — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001

F62h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 1111 ----

F61h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111

F60h SLRCON(2) —————SLRCSLRBSLRA---- -111

SLRCON(1) — — — SLRE SLRD SLRC SLRB SLRA ---1 1111

F5Fh CCPR3 H Captur e/Co mpare /P W M Register 3, High Byte xxxx xxxx

F5Eh CC PR 3 L Captur e/Co mpar e/P WM Regi st er 3, Low Byt e xxxx xxxx

F5Dh CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 0000 0000

F5Ch PWM3CON P3RSEN P3DC<6:0> 0000 0000

F5Bh ECCP3AS CCP3ASE CCP3AS<2:0> PSS3AC<1:0> PSS3BD<1:0> 0000 0000

F5Ah PSTR3CON — — — STR3SYNC STR3D STR3C STR3B STR3A ---0 0001

F59h CCPR4H Capture/Compare/PWM Register 4, High Byte xxxx xxxx

F58h CCPR4L Capture/Compare/PWM Register 4, Low Byte xxxx xxxx

F57h CCP4CON —— DC4B<1:0> CCP4M<3:0> --00 0000

F56h CCPR5H Capture/Compare/PWM Register 5, High Byte xxxx xxxx

F55h CCPR5L Capture/Compare/PWM Register 5, Low Byte xxxx xxxx

F54h CCP5CON —— DC5B<1:0> CCP5M<3:0> --00 0000

F53h TMR4 T imer4 Register 0000 0000

F52 h PR4 T imer4 Period Register 1111 1111

F51h T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000

F50h TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register 0000 0000

F4Fh TMR5L Least Significant Byte of the 16-bit TMR5 Register 0000 0000

F4Eh T5CON TMR5CS<1:0> T5CKPS<1:0> T5SOSCEN T5SYNC T5RD16 TMR5ON 0000 0000

F4Dh T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/

DONE T5GVAL T5GSS<1:0> 0000 0x00

F4Ch TMR6 Timer6 Register 0000 0000

F4Bh PR6 T imer6 Period Register 1111 1111

F4Ah T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000

F49h CCPTMRS0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> 00-0 0-00

F48h CCPTMRS1 ———— C5TSEL<1:0> C4TSEL<1:0> ---- 0000

F47h SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 0000 0000

F46h SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000

F45h CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 0000 0000

F44h CTMUCONL EDG2POL EDG2SEL<1:0> EDG1POL EDG1SEL<1:0> EDG2STAT EDG1STAT 0000 0000

F43h CTMUICON ITRIM<5:0> IRNG<1:0> 0000 0000

F42h VREFCON0 FVREN FVRST FVRS<1:0> — — — — 0001 ----

F41h VREFCON1 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 000- 00-0

F40h VREFCON2 — — — DACR<4:0> ---0 0000

F3Fh PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 0000 0000

F3Eh PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 00-0 0000

F3Dh PMD2 ———— CTMUMD CMP2MD CMP1MD ADCMD ---- 0000

F3Ch ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 ---- -111

F3Bh ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111

TABLE 5-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition

Note 1: PIC18(L)F4XK22 devices only.

2: PIC18(L)F2XK22 devices only.

3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only.

4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.

PIC18(L)F2X/4XK22

DS41412F-page 88  2010-2012 Microchip Technology Inc.

F3Ah ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 1111 11--

F39h ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111

F38h ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111

TABLE 5-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition

Note 1: PIC18(L)F4XK22 devices only.

2: PIC18(L)F2XK22 devices only.

3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only.

4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.

 2010-2012 Microchip Technology Inc. DS41412F-page 89

PIC18(L)F2X/4XK22

5.4.5 STATUS REGISTER

The STATUS register, shown in Register 5-2, contains

the arithmetic status of the ALU. As with any other SFR,

it can be the operand for any instruction.

If the STATUS register is the des ti nati on for an instruc-

tion that affects the Z, DC, C, OV or N bits, the results

of the instruction are not written; instead, the STATUS

formed. Therefore, the result of an instruction with the

STATUS register as its destination may be different

than intended. As an example, CLRF STATUS will set

the Z bit and leave the remaining Status bits

unchanged (‘000u u1uu’).

It is recommended that only BCF, BSF, SWAPF, MOVFF

and MOVWF instructions are used to alter the STATUS

C, DC, OV or N bits in the STATUS register.

For other i ns truc tions that do not affect Status bi t s , se e

the instruction set summaries in Section 25.2

“Extended Instruction Set” and Table 25-3.

5.5 Regist er D e fi nitio n s : Status

Note: The C and DC bits operate as the borrow

and digit borrow bits, respectively, in

subtraction.

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — NOV ZDC

(1) C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 N: Negative bit

This bit is used f or sign ed arith metic (two’ s co mplem ent). It i ndica tes w hether t he resu lt was negat ive

(ALU MSB = 1).

1 = Result was neg ative

0 = Result was positive

bit 3 OV: Overflow bit

This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the 7-bit

magnitude which causes the sign bit (bit 7 of the result) to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)

0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rot ate (RRF, RLF) instructi ons, this b it is loa ded with ei ther the hi gh-order or low-orde r

bit of the source register.

PIC18(L)F2X/4XK22

DS41412F-page 90  2010-2012 Microchip Technology Inc.

5.6 Data Addressing Modes

While the program memory can be addressed in only

one way – through the program counter – information

in the da ta m emory sp ace can be addr ess ed in severa l

ways. For most instructions, the addressing mode is

fixed. Other instructions may use up to three modes,

dependi ng on whic h operands are us ed and whe ther or

not the extended in struction set is enabled.

The addressing modes are:

• Inherent

• Literal

•Direct

•Indirect

An additional addressing mode, Indexed Literal Offset,

is available when the extended instruction set is

enabled (XINST Configuration bit = 1). Its operation is

discussed in greater detail in Section 5.7.1 “Indexed

Addressing with Literal Offset”.

5.6.1 INHEREN T AND LITERAL

ADDRESSING

Many PIC18 c ontrol in stru ctions do no t need any arg u-

ment at all; they either perform an operation that glob-

ally affects the device or they operate implicitly on one

Address ing. Examples in clude SLEEP, RESET and DAW.

Other instructions work in a similar way but require an

additional explicit argument in the opcode. This is

known as Literal Addressing mode because they

require some literal value as an argument. Examples

include ADDLW and MOVLW, which respectively, add or

move a literal value to the W register. Other examples

include CALL and GOTO, which include a 20-bit

program memory address.

5.6.2 DIRECT ADDRESSING

Direct addressing specifies all or part of the source

and/or destination address of the operation within the

opcode itself. The options are specified by the

arguments accompanying the instruction.

In the co re PIC1 8 inst ruct ion se t, bit-or iented and by te-

oriented instructions use some version of direct

addressing by default. All of these instructions include

some 8-bit literal address as their Least Significant

Byte. This address specifies eithe r a register address in

one o f the banks of d ata RAM ( Section 5.4.3 “General

Purpose Register File”) or a location in the Access

Bank (Section 5.4.2 “Access Bank”) as the data

source for the instruction.

The Acc es s RAM b it ‘a’ de term in es ho w the address is

interpreted. When ‘a’ is ‘1’, the contents of the BSR

(Section 5.4.1 “Bank Select Register (BSR)”) are

used with the addres s to determ ine the com plete 12-b it

addr ess of t he regis ter. W hen ‘a’ is ‘0’, the address is

interpreted as being a register in the Access Bank.

Addressing that uses the Access RAM is sometimes

also known as Direct Forced Addressing mode.

A few instructions, such as MOVFF, include the entire

12-bit address (either source or destination) in their

opcodes. In these cases, the BSR is ignored entirely.

The destin ation of the ope ration’ s result s is determine d

by the destination bit ‘d’. Wh en ‘d ’ is ‘1’, the results are

stor ed ba ck in th e s o ur c e re g is ter, overw rit i n g i ts or i gi-

nal contents. When ‘d’ is ‘0’, the results are stored in

the W register. Instructions without the ‘d’ argument

have a dest ination that is implicit in the inst ruction; their

destination is either the target register being operated

on or the W register.

5.6.3 INDIRECT ADDRESSING

Indirect addressing a llows the use r to access a location

in data memory without giving a fixed address in the

instruction. This is done by using File Select Registers

(FSRs) as pointers to the locations which are to be rea d

or written. Since the FSRs are themselves located in

RAM as Special File Registers, they can also be

directly manipulated under program control. This

makes FSRs very useful in implementing data struc-

tures, such as tables and arrays in data memory.

The registers for indirect addressing are also

implemented with Indirect File Operands (INDFs) that

permit au tomati c mani pulati on of the poi nter value with

auto-incrementing, auto-decrementing or offsetting

with a not her value. This allows for ef fi ci ent code, using

loops, such as the example of clearing an entire RAM

bank in Example 5-5.

EXAMPLE 5-5: HOW TO CLEAR RAM

(BANK 1) USING

INDIRECT ADDRESSING

Note: The execution of some instructions in the

core PIC18 instruction set are changed

when the PIC18 extended instruction set is

enabled. See Section 5.7 “Data Memory

and the Extended Instruction Set” for

more information.

LFSR FSR0, 100h ;

NEXT CLRF POSTINC0 ; Clear INDF

; register then

; inc pointer

BTFSS FSR0H, 1 ; All done with

; Bank1?

BRA NEXT ; NO, clear next

CONTINUE ; YES, continue

 2010-2012 Microchip Technology Inc. DS41412F-page 91

PIC18(L)F2X/4XK22

5.6.3.1 FSR Regist er s and the INDF

Operand

At the core of indirect addressing are three se ts of re g-

isters: FSR0, FSR1 and FSR2. Each represents a pair

of 8-bit registers, FSRnH and FSRnL. Each FSR pair

holds a 12-bit value, therefore, the four upper bits of the

FSRnH register ar e not used. The 12-bit FSR value can

address the entire range o f t he dat a m emory i n a l inear

fashion. The FSR register pairs, then, serve as pointers

to data memory locations.

Indirect addressing is accomplished with a set of

Indirect File Operands, INDF0 through INDF2. These

can be thought of as “virtual” registers: they are

mapped in the SFR space but are not physically

implemented. Reading or writing to a particular INDF

the data at the address indicated by FSR1H:FSR1L.

Instructions that use the INDF registers as operands

actually use the contents of their corresponding FSR as

a pointer to the instruction’s target. The INDF operand

is ju st a conven ient way of using the pointer.

Because indi rect ad dre ssing us es a full 1 2-bit a ddress ,

data RAM banking is not necessary. Thus, the current

contents of the BSR and the Access RAM bit have no

effect on determining the target address.

5.6.3.2 FSR Regis ters and PO S TINC,

POSTDEC, PREINC and PLUSW

In additi on to the INDF o perand, each F SR register p air

also has four additional indirect operands. Like INDF,

these are “virtual” registers which cannot be directly

read or written. Accessing these registers actually

accesses the location to which the associated FSR

on the FSR value. They are:

• POSTDEC: accesses the location to which the

FSR point s , then auto ma tic al ly dec rem en t s the

FSR by 1 afterwa r ds

• POSTINC: acc es se s the loc ati on to which the

FSR point s , then auto ma tic al ly inc rem en ts the

FSR by 1 afterwa r ds

• PREINC: automatical ly inc r em en t s the FSR by

one, then uses the location to which the FSR

points in the operati on

• PLUSW: adds the signed value of the W register

(range o f -127 to 12 8) to that of the F SR a nd us es

the location to which the result points in the

operation.

In this context, accessing an INDF register uses the

value in the associated FSR register without changing

it. Similarly, accessing a PLUSW register gives the

FSR value an offset by tha t in the W re gis ter ; however,

neither W nor the FSR is actually changed in the

operation. Accessing the other virtual registers

changes the value of the FSR register.

FIGURE 5-10: INDIRECT ADDRESSING

FSR1H:FSR1L

Data Memory

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

Bank 3

through

Bank 13

ADDWF, INDF1, 1

Using an instruction with one of the

indirect addressing register s as the

operand....

...uses the 12-bit address stored in

the FSR pair associated with that

...to determine the data memory

location to be used in that operation.

In this case, the FSR1 pair contains

ECCh. This means the contents of

location ECCh will be added t o that

of the W register and stored back in

ECCh.

xxxx1110 11001100

PIC18(L)F2X/4XK22

DS41412F-page 92  2010-2012 Microchip Technology Inc.

Operations on the FSRs with POSTDEC, POSTINC

and PREINC affect the entire register pai r; that is, roll-

overs of the FSRn L regi ster fro m FFh to 0 0h ca rry over

to the FSRnH register. On the other hand, results of

these operations do not change the value of any flags

in the STATUS register (e.g., Z, N, OV, etc.).

The PLUSW register can be used to implement a form

of indexed addressing in the data memory space. By

manipulating the value in the W register, users can

reach addresses that are fixed offsets from pointer

addresses. In some applications, this can be used to

implement some powerful program control structure,

such as software stacks, inside of data memory.

5.6.3.3 Operations by FSRs on FSRs

Indirect addressing operations that target other FSRs

or virtual registers represent special cases. For

example, using an FSR to point to one of the virtual

registers will not result in successful operations. As a

specific case, assume that FSR0H:FSR0L contains

FE7h, the address of INDF1. Attempts to read the

value of the INDF1 using INDF0 as an operand will

return 00h. Attempts to write to INDF1 using INDF0 as

the operand will result in a NOP.

On the other hand, u sing the virtu al reg isters to wr ite to

an F SR p air may n ot oc cur as plan ned. I n t hese cases ,

the val ue will be w ritten to the FSR p air bu t withou t any

incrementing or decrementing. Thus, writing to either

the INDF2 or POSTDEC2 register will write the same

value to the FSR2H:FSR2L.

Since the FSRs are physical registers mapped in the

SFR space, they can be manipulated through all direct

operations. Users should proceed cautiously when

working on these registers, particularly if their code

uses indirect addressing.

Similarly , operations by indirect addressing are generally

permit ted on al l other SFRs. Use rs should exercise the

appropriate caution that they do not i nadvertently chang e

settings that mi gh t a ffect the op er ati on of the device.

5.7 Data Memory and the Extended

Instruction Set

Enabling the PIC18 extended instruction set (XINST

Configuration bit = 1) significantly changes certain

aspects of data memory and its addressing. Specifi-

cally, the use of the Access Bank for many of the core

PIC18 instructions is different; this is due to the intro-

duct ion of a new addressing mode fo r the data memory

space.

What doe s not chan ge is ju st as im po rtant. The size of

the data memory space is unchanged, as well as its

linear addressing. The SFR map remains the same.

Core PIC18 instructions can still operate in both Direct

and Indirect Addressing mode; inherent and literal

instructions do not change at all. Indirect addressing

with FSR0 and FSR1 also remain unchanged.

5.7.1 INDEXED ADDRESSING WITH

LITERAL OFFSET

Enabling the PIC18 extended instruction set changes

the behavior of indirect addressing using the FSR2

conditi ons, instruct ions that use th e Access Ban k – that

is, most bit-oriented and byte-oriented instructions –

can invoke a form of indexed addressing using an

offset specified in the instruction. This special

address ing mod e is kn own as I ndexed Ad dressing with

Literal Offset, or Indexed Literal Offset mode.

When using the extended instruction set, this

addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0) and

• The f ile ad dres s arg um ent is le ss th an or equal to

5Fh.

Under these conditions, the file address of the

instruction is not interpreted as the lower byte of an

address (used with the BSR in direct addres sing), or as

an 8- bit addres s in the Acc ess Bank . Instead , the valu e

is interpreted as an offset value to an Address Pointer,

specified by FSR2. The offset and the contents of

FSR2 are added to obtain the target address of the

operation.

5.7.2 INSTRUCTIONS AFFECTED BY

INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use direct

addressing are potentially affected by the Indexed

Literal Offset Addressing mode. This includes all

byte-oriented and bit-oriented instructions, or almost

one-half of the standard PIC18 instruction set.

Instruct ions that only use Inherent or Literal Addressing

modes are una ffected.

Additionally, byte-oriented and bit-oriented instructions

are not affected if they do not use the Access Bank

(Access RAM bit is ‘1’), or inc lud e a fi le ad dres s of 60h

or above. Instructions meeting these criteria will

continue to execute as before. A comparison of the

different possible addressing modes when the

extended instruction set is enabled is shown in

Figure 5-11.

Those who desire to use byte-oriented or bit-oriented

instructions in the Indexed Literal Offset mode should

note the changes to assembler syntax for this mode.

This is described in more detail in Section 25.2.1

“Extended Instruction Syntax”.

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PIC18(L)F2X/4XK22

FIGURE 5-11: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND

BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

When ‘a’ = 0 and f  60h:

The instruction executes in

Direct Forced mode. ‘f’ is inter-

preted as a location in the

Access RAM between 060h

and 0FFh. Th is is th e sam e as

locations F60h to FFFh

(Bank 15) of data memory.

Locations below 60h are not

available in this addressing

mode.

When ‘a’ = 0 and f5Fh:

The instruction executes in

Indexed Literal Offset mode. ‘f’

is interpre ted as an offset to the

address value in FSR2. The

two are added together to

obtain the address of the target

address can be anywhere in

the data memory space.

Note that in this mode, the

correct syn tax is now:

ADDWF [k], d

where ‘k’ is the same as ‘f’.

When ‘a’ = 1 (all values of f):

The instruction executes in

Direct mode (also known as

Direct Long mode). ‘f’ is inter-

preted as a location in one of

the 16 banks of the data

memory space. The bank is

design ated by the Bank Sel ect

can be in any implemented

bank in the data memory

space.

000h

060h

100h

F00h

F60h

FFFh

Valid range

00h

60h

FFh

Data Memory

Access RAM

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

000h

060h

100h

F00h

F60h

FFFh Data Memory

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

FSR2H FSR2L

ffffffff001001da

000h

060h

100h

F00h

F60h

FFFh Data Memory

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

for ‘f’

BSR

00000000

PIC18(L)F2X/4XK22

DS41412F-page 94  2010-2012 Microchip Technology Inc.

5.7.3 MAPPING THE ACCESS BANK IN

INDEXED LITERAL OFFSET MODE

The use of Indexed Literal Offset Addressing mode

effe ctively chan ges how the first 96 locat ions of Access

RAM (0 0h to 5Fh ) are mapped. Rather than contai nin g

just the contents of the bottom section of Bank 0, this

mode ma p s the co nte nts from a user define d “window”

that can be located anywhere in the data memory

space. The val ue of FSR2 establishes the lower bound-

ary of the addresses mappe d into the window , while the

upper boundary is defined by FSR2 plus 95 (5Fh).

Address es in the A cces s RA M abo ve 5F h are ma ppe d

as previously described (see Section 5.4.2 “Access

Bank”). An example of Access Bank remapping in this

addressing mode is shown in Figure 5-12.

Remapping of the Access Bank applies only to opera-

tions u sing the I ndexed Lite ral Offset mode. Ope rations

that use the BSR (Access RAM bit is ‘1’) will continue

to use dir ect addressing as before.

5.8 PIC18 Instruction Execution and

the Extended Instruction Set

Enabling the extended instruction set adds eight

additional commands to the existing PIC18 instruction

set. These instructions are executed as described in

Section 25.2 “Extended Instruction Set”.

FIGURE 5-12: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET

ADDRESSING

Data Memory

000h

100h

200h

F60h

F00h

FFFh

Bank 1

Bank 15

Bank 2

through

Bank 14

SFRs

ADDWF f, d, a

FSR2H:FSR2L = 120h

Locations in the region

from the FSR2 pointer

(120h) to the pointer plus

05Fh (17Fh) are mapped

to the bottom of the

Access RAM (000h-05Fh).

Special File Registers at

F60h through FFFh are

mapped to 60h through

FFh, as usual.

Bank 0 addresses below

5Fh can still be addressed

by using the BSR. Access Bank

00h

60h

FFh

SFRs

Bank 1 “Window”

Bank 0

Window

Example Situation:

120h

17Fh

5Fh

Bank 1

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PIC18(L)F2X/4XK22

6.0 FLASH PROGRAM MEMORY

The Flash program memory is readable, writable and

erasable during normal operation over the entire VDD

range.

A read from program memory is executed one byte at

a time. A write to program memory is executed on

blocks of 64 bytes at a time. Program memory is

erased in blocks of 64 bytes at a time. A bulk erase

operation cannot be issued from user code.

Writing or erasing program memory will cease

instruction fetches until the operation is complete. The

program memory cannot be accessed during the write

or erase, therefore, code cannot execute. An internal

programming timer terminates program memory writes

and erases.

A value wri tten to program memory does not n eed to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP.

6.1 Table Reads and Table Writes

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16 bits wide, while the

data RAM space is 8 bits wide. Table reads and table

writes move data between these two memory spaces

through an 8-bit register (TABLAT).

The table read operation retrieves one byte of data

directly from program memory and places it into the

TABLAT register. Figure 6-1 shows the operation of a

tabl e read.

The table write operation stores one byte of data from the

TABLAT register into a write block holding register. The

procedure to write the contents of the holding registers

into program memory is detailed in Section 6.6 “W riting

to Flash Program Memory”. Figure 6-2 shows the

operation of a table write with program memory and data

RAM.

Table operations work with byte entities. Tables

containing data, rather than program instructions, are

not required to be word aligned. Therefore, a table can

start and end at any byte address. If a ta ble write is being

used to write executable code into program memory,

program instructions will need to be word aligned.

FIGURE 6-1: TABLE READ OPER ATION

Table Pointer(1) Table Latch (8-bit)

Program Memory

TBLPTRH TBLPTRL TABLAT

TBLPTRU

Instruction: TBLRD*

Note 1: Table Pointer register points to a byte in program memory .

Program Memory

(TBLPTR)

PIC18(L)F2X/4XK22

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FIGURE 6-2: TABLE WRITE OPERATION

6.2 Control Registers

Several control registers are used in conjunction with

the TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

6.2.1 EECON1 A ND EECON2 REGISTERS

The EECON1 register (Register 6-1) is the control

not a physical register; it is used exclusively in the

memory write and erase sequences. Reading

EECON2 will read all ‘0’s.

The EEPGD control bit determi nes if th e access will be

a program or data EEPROM memory access. When

EEPGD is clear, any subsequent operations will

operate on the data EEPROM memory. When EEPGD

is set, any subsequent operations will operate on the

program memory .

The CFGS control bit determines if the access will be

to the Co nfigur ation/Ca librati on regis ter s or to pro gram

memory/data EEPROM memory. When CFGS is set,

subsequent operations will operate on Configuration

registers regardless of EEPGD (see Section 24.0

“Special Features of the CPU”). When CFGS i s clear ,

memory selection access is determined by EEPGD.

The FREE bit allows the program memory erase

operation. When FREE is set, an erase operation is

initiated on the next WR command. When FREE is

clear, only writes are enabled.

The WREN bit, when set, will allow a write operation.

The WREN bit is clear on power-up.

The WRERR bit is set by hard ware w he n the WR bit i s

set and cleared when the internal programming timer

expires and the write operation is complete.

The WR control bit initiates write operations. The WR

bit cannot be cleared, only set, by firmware. Then WR

bit is cleared b y hardw are at the complet ion of the write

operation.

Table Pointer(1) Table Latch (8-bit)

TBLPTRH TBLPTRL TABLAT

Program Memory

(TBLPTR<MSBs>)

TBLPTRU

Instruction: TBLWT*

Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL

actually point to an address within the write block holding registers. The MSBs of the Table Pointer deter-

mine where the write block will eventually be written. The process for writing the holding registers t o the

program memory array is discussed in Section 6.6 “Writing to Flash Program Memory”.

Holding Registers

Program Memory

Note: During normal operation, the WRERR is

read as ‘1’. This can indicate that a write

operation was prematurely terminated by

a Reset, or a write operation was

attempted improperly.

Note: The EEIF interrupt flag bit of the PIR2

The EEIF flag stays set until cleared by

firmware.

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PIC18(L)F2X/4XK22

6.3 Register Defini tions: Memory Control

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR WREN WR RD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit

S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory

0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configu rati on Sele ct bit

1 = Access Configuration regi ster s

0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row (Block) Erase Enable bit

1 = Erase the program memory block addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0 = Perform write-only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)

1 = A write operatio n is prema ture ly termi nat ed (an y R ese t duri ng se lf-t im ed pro gram m ing in normal

operation, or an improper write attempt)

0 = The write operati on com pl ete d

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM

0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory eras e cycl e or write cy cle.

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) by software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Contr ol bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by ha rdware. The RD bit can only

be set (not cleared) by sof twa re. RD bit cannot be set whe n EEPGD = 1 or CFGS = 1.)

0 = Does not initiate an EEPROM read

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the

error condition.

PIC18(L)F2X/4XK22

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6.3.1 TABLAT – TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR sp ace. The Table Latch regi ster is used to

hold 8-bit data during data transfers between program

memory and data RAM.

6.3.2 TBLPTR – TABLE POINTER

The Table Poin ter (T BLPTR ) re gis ter add res se s a by te

within the progra m memo ry. The TBLPTR is comprise d

of three SFR registers: Table Pointer Upper Byte,

Table Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low-order

21 bits allow the device to address up to 2 Mbytes of

progra m memory sp ace. Th e 22nd b it allow s acce ss to

the device ID, the user ID and the Configuration bits.

The Table Pointer register, TBLPTR, is used by the

TBLRD and TBLWT ins t ru cti ons . T hes e i ns truc tio ns ca n

update the TBLPTR in one of four ways based on the

table operation. These operations on the TBLPTR

affect only the low-order 21 bits.

6.3.3 TABLE POINTE R BOUNDARI ES

TBLPTR is used in reads, writes and erases of the

Flash program memory.

When a TBLRD i s ex ecut ed , all 22 b its of th e T BLPT R

determine which byte is read from program memory

directly into the TABLAT register.

When a TBLWT is executed the byte in the TABLAT

holding registers constitute a write block which varies

depending on the device (see Table 6-1).T he 3, 4, or 5

LSbs of the TBLPTRL register determine which specific

address within the holding register block is written to.

The MSBs of the Table Pointer have no effect during

TBLWT operations .

When a program memory write is executed the entire

holding register block i s wr i tte n to th e Flash memory at

the address determined by the MSbs of the TBLPTR.

The 3, 4, or 5 LSBs are ignored during Flash memory

writes. For more detail, see Section 6.6 “Writing to

Flash Program Memory”.

When an erase of program memory is executed, the

16 MSbs of the Table Pointer register

(TBLPTR<21:6>) point to the 64-byte block that will be

erased. The Least Significant bits (TBLPTR<5:0>) are

ignored.

Figure 6-3 describes the relevant boundaries of

TBLPTR based on Flash program memory operations.

TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRU CTIONS

FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

Example Operation on Table Pointer

TBLRD*

TBLWT* TBLPTR is not modified

TBLRD*+

TBLWT*+ TBLPTR is incremented after the read/write

TBLRD*-

TBLWT*- TBLPTR is decremented after the read/write

TBLRD+*

TBLWT+* TBLPTR is incremented before the read/write

21 16 15 87 0

TABLE ERASE/WRITE TABLE WRITE

TABLE READ – TBLPTR<21:0>

TBLPTRL

TBLPTRH

TBLPTRU

TBLPTR<n:0>(1)

TBLPTR<21:n+1>(1)

Note 1: n = 6 for block sizes of 64 bytes.

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PIC18(L)F2X/4XK22

6.4 Reading the Flash Program

Memory

The TBLRD instruction retrieves data from program

memory and plac es it into data RAM. Table r ead s fro m

program memory are performed one byte at a time.

TBLPTR points to a byte address in program space.

Executing TBLRD places the byte pointed to into

TABLAT. In addition, TBLPTR can be modified

automatically for the next table read operation.

The interna l program memory is typically org anized by

words. The Least Significant b it of th e address selects

between the high and low bytes of the word. Figure 6-4

shows the interface between the internal program

memory and the TABLAT.

FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY

EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD

(Even Byte Address)

Program Memory

(Odd Byte Address)

TBLRD TABLAT

TBLPTR = xxxxx1

FETCH

Instruction Register

(IR) Read Register

TBLPTR = xxxxx0

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base

MOVWF TBLPTRU ; address of the word

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

READ_WORD TBLRD*+ ; read into TABLAT and increment

MOVF TABLAT, W ; get data

MOVWF WORD_EVEN

TBLRD*+ ; read into TABLAT and increment

MOVFW TABLAT, W ; get data

MOVF WORD_ODD

PIC18(L)F2X/4XK22

DS41412F-page 100  2010-2012 Microchip Technology Inc.

6.5 Erasing Flash Program Memory

The mi nimum eras e block is 32 words or 64 byte s. Only

through the use of an external programmer, or through

ICSP™ control, can larger blocks of program memory

be bulk erased. Word erase in the Flash array is not

supported.

When initiating an erase sequence from the

microcontroller itself, a block of 64 bytes of program

memory is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased. The

TBLPTR<5:0> bits are ignored.

The EECON1 regis te r com ma nds the era se opera tio n.

The EEPGD bit must be set to point to the Flash

program m emory. The WREN bit must be set to en able

write op erations. The FREE bit i s set to selec t an erase

operation.

The write initiate sequence for EECON2, shown as

steps 4 through 6 in Section 6.5.1 “Flash Program

Memory Erase Sequence”, is used to guard against

accidental writes. This is sometimes referred to as a

long write.

A long w rite i s nec essary for erasing th e i nternal Fl ash.

Instruction execution is halted during the long write

cycle. The long write is terminated by the internal

program ming timer.

6.5.1 FLASH PROGRAM MEMORY

ERASE SEQUENCE

The sequence of events for erasing a block of internal

program memory is:

1. Load Table Pointer register with address of

block bei ng er as ed .

2. Set the EECON1 register for the erase operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN bit to enable writes;

• set FREE bit to enable the erase.

3. Disable int errup ts.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the block erase

cycle.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

8. Re-enable interrupts.

EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY BLOCK

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

ERASE_BLOCK

BSF EECON1, EEPGD ; point to Flash program memory

BCF EECON1, CFGS ; access Flash program memory

BSF EECON1, WREN ; enable write to memory

BSF EECON1, FREE ; enable block Erase operation

BCF INTCON, GIE ; disable interrupts

Required MOVLW 55h

Sequence MOVWF EECON2 ; write 55h

MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start erase (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

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PIC18(L)F2X/4XK22

6.6 Writing to Flash Program Memory

The programming block size is 64 bytes. Word or byte

program ming is not supported.

Table writes are used internally to load the holding

registers needed to program the Flash memory. There

are only as many holding regi sters as there are bytes

in a write block (64 bytes).

Since the Table Latch (TABLAT) is only a single byte,

the TBLWT instruction needs to be executed 64 times

for each programming operation. All of the table write

operat ions w ill e ssenti ally be sh ort writes bec ause only

the holding registers are written. After all the holding

registers have been written, the programming

operation of that block of memory is started by

configuring the EECON1 register for a program

memory write and performing the l ong w rite se que nc e.

The long write is necessary for programming the

inte rnal Fl ash. I nstruc tion ex ecutio n is hal ted duri ng a

long write cycle. The long write will be terminated by

the internal programming timer.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump, rated to operate over the voltage range

of the device.

FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY

6.6.1 FLASH PROGRAM MEMORY WRITE

SEQUENCE

The sequence of events for programming an internal

program memory location shoul d be:

1. Read 64 bytes int o RAM .

2. Update data values in RAM as necessary.

3. Load Table Pointer register with address being

erased.

4. Execute the block erase proc edure.

5. Load Table Pointer register with address of first

byte being written.

6. Write the 64-byte blo ck into the holdi ng registers

with auto-increment.

7. Set the EECON 1 register for the wri te operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN to enable byte writes.

8. Disable int errup ts.

9. Write 55h to EECON2.

10. Write 0AAh to EECON2.

11. Set the WR bit. This will begin the write cy cl e.

12. The CPU will stall for dura tion of t he write (about

2 ms using internal timer).

13. Re-enable interrupts.

14. Verify the memory (table read).

This procedure will require about 6 ms to update each

write block of memory . An example of the required code

is gi ven in Example 6-3.

Note: The default value of the holding registers on

device R es ets an d afte r wr ite op e rat io ns is

FFh. A write of FFh to a holding register

does not modify that byte. This means that

individual bytes of program memory may

be mo dified, prov ided t hat the chan ge doe s

not atte mpt to cha nge any bi t from a ‘0’ to a

‘1’. When modifying individual bytes, it is

not necessary to load all holding registers

before execu ting a lon g writ e opera tion.

TABLAT

TBLPT R = xxxxYY(1)

TBLPTR = xxxx01TBLPTR = xxxx00

Write Register

TBLPT R = xxxx02

Program Memory

Holding Register Holding Register Holding Register Holding Register

88 8 8

Note 1: YY = 3F for 64 byte write blocks.

Note: Before setting the WR bit, the Table

Pointer address needs to be within the

intended address range of the byte s in the

holding registers.

PIC18(L)F2X/4XK22

DS41412F-page 102  2010-2012 Microchip Technology Inc.

EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY

MOVLW D'64’ ; number of bytes in erase block

MOVWF COUNTER

MOVLW BUFFER_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW BUFFER_ADDR_LOW

MOVWF FSR0L

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

READ_BLOCK TBLRD*+ ; read into TABLAT, and inc

MOVF TABLAT, W ; get data

MOVWF POSTINC0 ; store data

DECFSZ COUNTER ; done?

BRA READ_BLOCK ; repeat

MODIFY_WORD MOVLW BUFFER_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW BUFFER_ADDR_LOW

MOVWF FSR0L

MOVLW NEW_DATA_LOW ; update buffer word

MOVWF POSTINC0

MOVLW NEW_DATA_HIGH

MOVWF INDF0

ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

BSF EECON1, EEPGD ; point to Flash program memory

BCF EECON1, CFGS ; access Flash program memory

BSF EECON1, WREN ; enable write to memory

BSF EECON1, FREE ; enable Erase operation

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

Required MOVWF EECON2 ; write 55h

Sequence MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start erase (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

TBLRD*- ; dummy read decrement

MOVLW BUFFER_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW BUFFER_ADDR_LOW

MOVWF FSR0L

WRITE_BUFFER_BACK MOVLW BlockSize ; number of bytes in holding register

MOVWF COUNTER

MOVLW D’64’/BlockSize ; number of write blocks in 64 bytes

MOVWF COUNTER2

WRITE_BYTE_TO_HREGS MOVF POSTINC0, W ; get low byte of buffer data

MOVWF TABLAT ; present data to table latch

TBLWT+* ; write data, perform a short write

; to internal TBLWT holding register.

 2010-2012 Microchip Technology Inc. DS41412F- page 103

PIC18(L)F2X/4XK22

EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

6.6.2 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

6.6.3 UNEXPECTED TERMINATION OF

WRITE OP ERATION

If a wri te is term in ate d by an unpl anned event, suc h a s

loss of power or an unexpected Reset, the memory

location just programmed should be verified and

reprogrammed if needed. If the write operation is

interrupted by a MCLR Reset or a WDT Time-out Reset

during normal operation, the WRERR bit will be set

which the user can check to decide whether a rewrite

of the location(s) is needed.

6.6.4 PROTECTION AGAINST

SPURIOU S WRITES

To protect against spurious writes to Flash program

memory, the write initiate sequence must also be

followed. See Section 24.0 “Special Features of the

CPU” for more detail.

6.7 Flash Program Operation During

Code Protection

See Section 24.5 “Program Verification and Code

Protection” for details on code protection of Flash

program memory.

DECFSZ COUNTER ; loop until holding registers are full

BRA WRITE_WORD_TO_HREGS

PROGRAM_MEMORY BSF EECON1, EEPGD ; point to Flash program memory

BCF EECON1, CFGS ; access Flash program memory

BSF EECON1, WREN ; enable write to memory

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

Required MOVWF EECON2 ; write 55h

Sequence MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start program (CPU stall)

DCFSZ COUNTER2 ; repeat for remaining write blocks

BRA WRITE_BYTE_TO_HREGS ;

BSF INTCON, GIE ; re-enable interrupts

BCF EECON1, WREN ; disable write to memory

TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name B i t 7 Bit 6 Bi t 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0 Reset

V alues on

page

TBLPTRU —— Program Memory Table Pointer Upp er Byte (TBLPTR<21: 16>) —

TBLPT RH Program Memory Table Pointer High Byte (TBLPTR<15:8>) —

TBLPTRL Program Memory Table Pointe r Low Byte (TBLPT R<7:0>) —

TABLAT Program Memory Table Latch —

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

EECON2 EEPROM Control Register 2 (not a physical register) —

EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 97

IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129

PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120

PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125

Legend: — = unimplement ed, read as ‘0’. Shaded bits are not used during Flash/EEPRO M access .

PIC18(L)F2X/4XK22

DS41412F-page 104  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 105

PIC18(L)F2X/4XK22

7.0 DAT A EEPROM MEMORY

The data EEPROM is a nonvolatile memory array,

separate from the data RAM and program memory,

which is used for long-term storage of program data. It

is not directly mapped in either the register file or

program memory space but is indirectly addressed

through the Special Function Registers (SFRs). The

EEPROM is readable and writable during normal

operation over the entire VDD range.

Four SFRs are used to read and write to the data

EEPROM as well as the program memory. They are:

• EECON1

• EECON2

• EEDATA

• EEADR

• EEADRH

The data EEPROM allows byte read and write. When

interfacing to the data memory block, EEDATA holds

the 8-bit data for read/write and the EEADR:EEADRH

being accessed.

The EEPROM data memory is rated for high erase/write

cycle endurance. A byte write automatically erases the

location and writes the new data (erase-before-write).

The write time is controlled by an on-chip timer; it will

vary with voltage and temperature as well as from chip-

to-chip. Please refer to the Data EEPROM Memory

parameters in Section 27.0 “Electrical Characteris-

tics” for limit s.

7.1 EEADR and EEADRH Registers

The EEADR register is used to address the data

EEPROM for read and write operations. The 8-bit

range of the register can address a memory range of

256 bytes (00h to FFh). The EEADRH register expands

the range to 1024 bytes by adding an additional two

address bits.

7.2 EECON1 and EECON2 Registers

Access to the data EEPROM is controlled by two

registers : EECON1 and EECO N2. These are the same

regi sters which control access to the program memory

and are used in a similar manner for the data

EEPROM.

The EECON1 register (Register 7-1) is the control

bit EEPGD det erm ine s if the access wi ll be to program

or data EEPROM memory. When the EEPGD bit is

clear, operations will access the data EEPROM

memory. When the EEPGD bit is set, pro gram memor y

is ac cessed.

Control bit, CFGS, determines if the access will be to

the Con fig urat ion reg ist ers or to pro gram m em ory /data

EEPROM memory. When the CFGS bit is set,

subseq uent ope rations acce ss Confi gur ation reg isters.

When the CFGS bit is clear, the EEPGD bit selects

either program Flash or data EEPROM memory.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear.

The WRERR bit is set by hard ware w he n the WR bit i s

set and cleared when the internal programming timer

expires and the write operation is complete.

The WR control bit initiates write operations. The bit

can be set but no t cleared b y software . It is cle ared only

by hardware at the completion of the write opera tion.

Control bits, RD and WR, start read and erase/write

operat ions, respec tively . These bi ts are set by fi rmware

and cleared by hardware at the completion of the

operation.

The RD bit cannot be set when accessing program

memory (EEPGD = 1). Program memory is read using

table read instructions. See Section 6.1 “Table Reads

and Table Writes” regarding table reads.

The EECON2 register is not a physical register. It is

used exclusively in the memory write and erase

sequences. Reading EECON2 will read all ‘0’s.

Note: During normal operation, the WRERR

may read as ‘1’. This can indicate that a

write operation was prematurely termi-

nated by a Reset, or a write operation was

attempted improperly.

Note: The EEIF interrupt flag bit of the PIR2

It must be cleared by software.

PIC18(L)F2X/4XK22

DS41412F-page 106  2010-2012 Microchip Technology Inc.

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR WREN WR RD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit

S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory

0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configu rati on Sele ct bit

1 = Access Configuration regi ster s

0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row (Block) Erase Enable bit

1 = Erase the program memory block addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0 = Perform write-only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)

1 = A write operatio n is prema ture ly termi nat ed (any Reset duri ng se lf-t im ed pro gram m ing in norm al

operation, or an improper write attempt)

0 = The write operati on com pl ete d

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM

0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory eras e cycl e or write cy cle.

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) by software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read t akes one cycle. RD is cleared by ha rdware. The RD bit can only

be set (not cleared) by sof tware. RD bit cannot be s et when EEPGD = 1 or CFGS = 1.)

0 = Does not initiate an EEPROM read

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the

error condition.

 2010-2012 Microchip Technology Inc. DS41412F- page 107

PIC18(L)F2X/4XK22

7.3 Reading the Data EEPROM

Memory

To read a data memory location, the user must write

the address to the EEADR register, clear the EEPGD

control bi t of the EECON1 regi st er a nd then set contro l

bit, RD. The data is available on the very next instruc-

tion cycle; therefore, the EEDATA register can be read

by the next instructi on. EEDA T A will hold this va lue until

another read operation, or until it is written to by the

user (during a write operation).

The basic process is shown in Example 7-1.

7.4 Writing to the Data EEPROM

Memory

To write an EEPROM data location, the address must

first be writ ten to the EEAD R r egiste r and the da ta writ-

ten to the EEDATA register. The sequence in

Example 7-2 must be followed to initiate the write cy cle.

The write will not begin if this sequence is not exactly

followed (write 55h to EECON2, write 0AAh to

EECON2, then set WR bi t) for each byte. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in EECON1 must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code

execution (i.e., runaway programs). The WREN bit

should be ke pt clear at all times , excep t whe n upda tin g

the EEPROM. The WREN bit is not cleared by

hardware.

After a write sequence has been initiated, EECON1,

EEADR and EEDATA cannot be modified. The WR bit

will be inhibited from being set unless the WREN bit is

set. Both WR and WREN cannot be set with the same

instruction.

At the completion of the write cycle, the WR bit is

cleared by hardware and the EEPROM Interrupt Flag

bit, EEIF, is set. The user may either enable this

interrupt or poll this bit. EEIF must be cleared by

software.

7.5 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

EXAMPLE 7-1: DATA EEPROM READ

EXAMPLE 7-2: DATA EEPROM WRITE

MOVLW DATA_EE_ADDR ;

MOVWF EEADR ; Data Memory Address to read

BCF EECON1, EEPGD ; Point to DATA memory

BCF EECON1, CFGS ; Access EEPROM

BSF EECON1, RD ; EEPROM Read

MOVF EEDATA, W ; W = EEDATA

MOVLW DATA_EE_ADDR_LOW ;

MOVWF EEADR ; Data Memory Address to write

MOVLW DATA_EE_ADDR_HI ;

MOVWF EEADRH ;

MOVLW DATA_EE_DATA ;

MOVWF EEDATA ; Data Memory Value to write

BCF EECON1, EEPGD ; Point to DATA memory

BCF EECON1, CFGS ; Access EEPROM

BSF EECON1, WREN ; Enable writes

BCF INTCON, GIE ; Disable Interrupts

MOVLW 55h ;

Required MOVWF EECON2 ; Write 55h

Sequence MOVLW 0AAh ;

MOVWF EECON2 ; Write 0AAh

BSF EECON1, WR ; Set WR bit to begin write

BSF INTCON, GIE ; Enable Interrupts

; User code execution

BCF EECON1, WREN ; Disable writes on write complete (EEIF set)

PIC18(L)F2X/4XK22

DS41412F-page 108  2010-2012 Microchip Technology Inc.

7.6 Operation During Code-Protect

Data EEPROM memory has its own code-protect bits

in Configuration Words. External read and write

operations are disabled if code protection is enabled.

The mic rocontroll er its elf can bo th read and write to the

internal data EEPROM, regardless of the state of the

code-protect Configuration bit. Refer to Section 24.0

“Special Features of the CPU” for additional

information.

7.7 Protection Against Spurious Write

There are conditions when the user may not want to

write to the data EEPR OM memory. To protect against

spurious EEPROM writes, various mechanisms have

been implemented. On power-up, the WREN bit is

cleared. In addition, writes to the EEPROM are bloc ked

during the Power-up Timer period (T PWRT).

The write initiate sequence an d the WREN bi t tog eth er

help prevent an accidental write during brown-out,

power glitch or software malfunction.

7.8 Using the Data EEPROM

The data EEPROM is a high-endurance, byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other dat a that are updated of ten).

When variables in one section change frequently, while

variables in another sec tion do not c hange, it is possible

to exceed the total number of write cycles to the

EEPROM without exceeding the total number of write

cycles to a single byte. Refer to the Data EEPROM

Memory parameters in Section 27.0 “Electrical

Characteristics” for write cycle limit s. If this is the case,

then an array refresh must be performed. For this

reason, variables that change infrequently (such as

constants, IDs, calibration, etc.) should be stored in

Flash program memory.

A simple data EEPROM refresh routine is shown in

Example 7-3.

EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE

Note: If data EEPROM is only used to store

const ants and/or dat a that chan ges rarely,

an array re fres h is l ike ly n ot requ ire d. See

specification.

CLRF EEADR ; Start at address 0

BCF EECON1, CFGS ; Set for memory

BCF EECON1, EEPGD ; Set for Data EEPROM

BCF INTCON, GIE ; Disable interrupts

BSF EECON1, WREN ; Enable writes

Loop ; Loop to refresh array

BSF EECON1, RD ; Read current address

MOVLW 55h ;

MOVWF EECON2 ; Write 55h

MOVLW 0AAh ;

MOVWF EECON2 ; Write 0AAh

BSF EECON1, WR ; Set WR bit to begin write

BTFSC EECON1, WR ; Wait for write to complete

BRA $-2

INCFSZ EEADR, F ; Increment address

BRA LOOP ; Not zero, do it again

BCF EECON1, WREN ; Disable writes

BSF INTCON, GIE ; Enable interrupts

 2010-2012 Microchip Technology Inc. DS41412F- page 109

PIC18(L)F2X/4XK22

TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 —

EEADRH(1) — — ———— EEADR9 EEADR8 —

EEDATA EEPROM Data Register —

EECON2 EEPROM Control Register 2 (not a physical register) —

EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 106

IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129

PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120

PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125

Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during EEPROM access.

Note 1: PIC18(L)F26K22 and PIC18(L)F46K22 only.

PIC18(L)F2X/4XK22

DS41412F-page 110  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 111

PIC18(L)F2X/4XK22

8.0 8 x 8 HARDWARE MULTIPLIER

8.1 Introduction

All PIC18 devices include an 8 x 8 hardware multiplier

as part of the ALU. The multiplier performs an unsigned

operation and yields a 16-bit result that is stored in the

product register pair, PRODH:PRODL. The multiplier’s

operation does not affect any flags in the STATUS

Making multiplication a hardware operation allows it to

be com pl eted i n a single instru cti on cycle. This has th e

advantages of higher computational throughput and

reduced code size for multiplication algorithms and

allows the PIC18 devices to be used in many applica-

tions previously reserved for digital signal processors.

A comparison of various hardware and software

multiply operations, along with the savings in memory

and execution time, is show n in Table 8-1.

8.2 Operation

Example 8-1 show s the instruc tion sequen ce for an 8 x 8

unsigned multiplication. Only one instruction is required

when one of the arguments is already loaded in the

WREG regis ter.

Example 8-2 shows the sequenc e to do an 8 x 8 signe d

multiplication. To account for the sign bits of the

argumen ts, e ach argu ment’ s Most Si gnifican t bit (MSb)

is tested and the appropriate subtractions are done.

EXAMPLE 8- 1: 8 x 8 UNSIGNE D

MULTIP LY ROU TI N E

EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

MOVF ARG1, W ;

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

MOVF ARG1, W

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

BTFSC ARG2, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG1

MOVF ARG2, W

BTFSC ARG1, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

Routine Multiply Method Program

Memory

(Words)

Cycles

(Max)

Time

@ 64 MHz @ 40 MHz @ 10 MHz @ 4 MHz

8 x 8 unsigned Without hardware multiply 13 69 4.3 s6.9 s27.6 s69 s

Hardware multiply 1 1 62.5 ns 100 ns 400 ns 1 s

8 x 8 si gned Without hardware multiply 33 91 5.7 s9.1 s36.4 s91 s

Hardware multiply 6 6 375 ns 600 ns 2.4 s6 s

16 x 16 unsigned Without hardware multiply 21 242 15.1 s24.2 s96.8 s242 s

Har dware multiply 28 28 1.8 s2.8 s11.2 s28 s

16 x 16 signed Without hardware multiply 52 254 15.9 s25.4 s 102.6 s254 s

Har dware multiply 35 40 2.5 s4.0 s16.0 s40 s

PIC18(L)F2X/4XK22

DS41412F-page 112  2010-2012 Microchip Technology Inc.

Example 8-3 shows the sequence to do a 16 x 16

unsigned multiplication. Equation 8-1 shows the

algorith m that is us ed. The 32-b it result is stored in fo ur

registers (RES<3:0>).

EQUATION 8-1: 16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 8- 3: 16 x 16 UNSIG NED

MULTIPLY ROUTINE

Example 8-4 shows the sequence to do a 16 x 16

signed multiply. Equation 8-2 shows the algorithm

used. The 32-bit result is stored in four registers

(RES<3:0>). To account for the sign bits of the argu-

ments, the MSb for each argument pair is tested and

the appropriate subtractions are done.

EQUATION 8-2: 16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 8-4: 16 x 16 SIGNED

MU LTIPLY ROUTINE

RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L

= (ARG1H  ARG2H  216) +

(ARG1H  ARG2L  28) +

(ARG1L  ARG2H  28) +

(ARG1L  ARG2L)

MOVF ARG1L, W

MULWF ARG2L ; ARG1L * ARG2L->

; PRODH:PRODL

MOVFF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

; MOVF ARG1H, W

MULWF ARG2H ; ARG1H * ARG2H->

; PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

; MOVF ARG1L, W

MULWF ARG2H ; ARG1L * ARG2H->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

; MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L

= (ARG1H  ARG2H  216) +

(ARG1H  ARG2L  28) +

(ARG1L  ARG2H  28) +

(ARG1L  ARG2L) +

(-1  ARG2H<7>  ARG1H:ARG1L  216) +

(-1  ARG1H<7>  ARG2H:ARG2L  216)

MOVF ARG1L, W

MULWF ARG2L ; ARG1L * ARG2L ->

; PRODH:PRODL

MOVFF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

; MOVF ARG1H, W

MULWF ARG2H ; ARG1H * ARG2H ->

; PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

; MOVF ARG1L, W

MULWF ARG2H ; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

; MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?

BRA SIGN_ARG1 ; no, check ARG1

MOVF ARG1L, W ;

SUBWF RES2 ;

MOVF ARG1H, W ;

SUBWFB RES3

;

SIGN_ARG1

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?

BRA CONT_CODE ; no, done

MOVF ARG2L, W ;

SUBWF RES2 ;

MOVF ARG2H, W ;

SUBWFB RES3

;

CONT_CODE

 2010-2012 Microchip Technology Inc. DS41412F- page 113

PIC18(L)F2X/4XK22

9.0 INTERRUPTS

The PIC18(L)F2X/4XK22 devices have multiple

interrupt sources and an interrupt priority feature that

allows most interrupt sources to be assigned a high or

low pr ior i t y le vel (I NT 0 do es no t hav e a pr i ori t y bi t , it is

always a high prior ity). The hi gh priority interrupt v ector

is at 0008h and the low priority interrupt vector is at

0018h. A hig h priority in terrupt even t will interrupt a low

priority interrupt that may be in progress.

There are 19 registers used to control interrupt

operation.

These registers are:

• INTCON, INTCON2, INTCON3

• PIR1, PIR2, PIR3, PIR4, PIR5

• PIE1, PIE2, PIE3, PIE4, PIE5

• IPR1, IPR2, IPR3, IPR4, IPR5

• RCON

It is recommended that the Microchip header files sup-

plied with MPLAB® IDE be used for the symbolic bit

names in these registers. This allows the assembler/

compil er to automa tical ly ta ke care of the pla ceme nt of

these bits within the specified register.

In ge nera l, in terru pt so urces have thre e bits to cont rol

their operation. They are:

•Flag bit to indicate that an interrupt event

occurred

•Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

•Priority bit to select high priority or low priority

9.1 Mid-Range Compatibility

When the IPEN b it is cleared (default st ate), the interrupt

priority feature is disabled and interrupts are com p atible

with PIC® microcontroller mid-range devices. In

Comp atibility mode, the interrupt priority bit s of the IPRx

registers have no effect. The PEIE/GIEL bit of the

INTCON register is the global interrupt enable for the

peripherals. The PEIE/GIEL bit disables only the

peripheral interrupt sources and enables the peripheral

interrupt sources when the GIE/GIEH b it is also set. The

GIE/GIEH bit of the INTCON register is the global

interrupt enable which enables all non-peripheral

interrupt sources and disables all interrupt sources,

including the peripherals. All interrupts branch to

address 0008h in Compatibility mode.

9.2 Interrupt Priority

The interrupt priority feature is enabled by setting the

IPEN bit of the RCON register. When interrupt priority

is enabled the GIE/GIEH and PEIE/GIEL global inter-

rupt enable bits of Compatibility mode are replaced by

the GIEH high priority, and GIEL low priority, global

interrupt enables. When set, the GIEH bit of the INT-

CON register enables all interrupts that have their

associated IPRx register or INTCONx register priority

bit set (high p riority ). When clea r, the GIEH bit disab les

all interru pt sources including those selected as low pri-

ority. When clear, the GIEL bit of the INTCON register

disables only the interrupts that have their associated

priority b it clea red (low pri ority). Wh en set, the GIEL bit

enables the low priority sources when the GIEH bi t is

also set.

When the interrupt flag, enable bit and appropriate

Global Interrupt Enable (GIE) bit are all set, the

interrupt will vector immediately to address 0008h for

high priority, or 0018h for low priority, depending on

level of the interrupting source’s priority bit. Individual

interrupts can be disabled through their corresponding

interrupt enable bits.

9.3 Interrupt Response

When an i nte rrupt is responded to , t he Global Interru pt

Enable bit is cleared to disable further interrupts. The

GIE/GIEH bit is the Global Interrupt Enable when the

IPEN bit is cleared. When the IPEN bit is set, enabling

interrupt priority levels, the GIEH bit is the high priority

global interrupt enable and the GIEL bit is the low

priority Global Interrupt Enable. High priority interrupt

sources can interrupt a low priority interrupt. Low

priority interrupts are not processed while high priority

interrupts are in progress.

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address (0008h

or 0018h). Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits in the INTCONx and PIRx

registers. The interrupt flag bits must be cleared by

software before re-enabling interrupts to avoid

repeating the same interrupt.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine and sets the GIE/GIEH bit (GIEH

or GIEL if priority levels are used), which re-enables

interrupts.

For external interrupt events, such as the INT pins or

the PORTB interrupt-on-change, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one-cycle or two-cycle

instructions. Individual interrupt flag bits are set,

regardless of the status of their corresponding enable

bits or the Global Interrupt Enable bit.

PIC18(L)F2X/4XK22

DS41412F-page 114  2010-2012 Microchip Technology Inc.

FIGURE 9-1: PIC18 INTERRUPT LOGIC

Note: Do not use the MOVFF instruction to

modify any of the interrupt control regis-

ters while any interrupt is enabled. Doing

so may cause erratic microcontroller

behavior.

TMR0IE

GIEH/GIE

Wake-up if in

Interrupt to CPU

Vector to Location

0008h

INT2IF

INT2IE

INT2IP

INT1IF

INT1IE

INT1IP

TMR0IF

TMR0IE

TMR0IP

RBIF

RBIE

RBIP

TMR0IF

TMR0IP

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

RBIF

RBIE

RBIP

INT0IF

INT0IE

GIEL/PEIE

Interrupt to CPU

Vector to Location

IPEN

0018h

High Priority Interrupt Generation

Low Priority Interrupt Generation

Idle or Sleep modes

GIEH/GIE

Note 1: The RBIF interrupt also requires the individual pin IOCB enables.

(1)

PIR1<6:0>

PIE1<6:0>

IPR1<6:0>

PIR2<7:0>

PIE2<7:0>

IPR2<7:0>

PIR3<7:0>

PIE3<7:0>

IPR3<7:0>

PIR4<2:0>

PIE4<2:0>

IPR4<2:0>

PIR5<2:0>

PIE5<2:0>

IPR5<2:0>

PIR1<6:0>

PIE1<6:0>

IPR1<6:0>

PIR2<7:0>

PIE2<7:0>

IPR2<7:0>

PIR3<7:0>

PIE3<7:0>

IPR3<7:0>

PIR4<2:0>

PIE4<2:0>

IPR4<2:0>

PIR5<2:0>

PIE5<2:0>

IPR5<2:0>

IPEN

GIEL/PEIE

 2010-2012 Microchip Technology Inc. DS41412F- page 115

PIC18(L)F2X/4XK22

9.4 INTCON Registers

The INTCON registers are readable and writable

registers, which contain various enable, priority and

flag bits.

9.5 PIR Registers

The PIR regi sters c onta in the ind ividu al flag bit s for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are five Peripheral Interrupt

Request Flag registers (PIR1, PIR2, PIR3, PIR4 and

PIR5).

9.6 PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are five Peripheral

Interrupt Enable registers (PIE1, PIE2, PIE3, PIE4 and

PIE5). When IPEN = 0, the PEIE/GIEL bit must be set to

enable any of these peripheral interrupt s.

9.7 IPR Registers

The IPR registers contain the individual priority bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are five Peripheral Interrupt

Priority registers (IPR1, IPR2, IPR3, IPR4 and IPR5).

Using the priority bits requires that the Interrupt Priority

Enable (IPEN) bit be set.

PIC18(L)F2X/4XK22

DS41412F-page 116  2010-2012 Microchip Technology Inc.

9.8 Regist er D e fi nitio n s : In terr u pt C on trol

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:

1 = Enables all unmasked interrupts

0 = Disables all interrupts including peripherals

When IPEN = 1:

1 = Enables all high priority interrupts

0 = Disables all int errupts including low priority

bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN = 0:

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

When IPEN = 1:

1 = Enables all low priority interrupts

0 = Disables all low priority interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt

0 = Disables the TMR0 overflow interrupt

bit 4 INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt

0 = Disables the INT0 external interrupt

bit 3 RBIE: Port B Interrupt-On-Change (IOCx) Interrupt Enable bit(2)

1 = Enables the IOCx port change interrupt

0 = Disables the IOCx port change interrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared by software)

0 = TMR0 register did not overflow

bit 1 INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared by software)

0 = The INT0 external interrupt did not occur

bit 0 RBIF: Port B Interrupt-On-Change (IOCx) Interrupt Flag bit(1)

1 = At least one of the IOC<3:0> (RB<7:4>) pins changed state (must be cleared by software)

0 = None of the IOC<3:0> (RB<7:4>) pins have changed state

Note 1: A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the

mismatch condition and allow the bit to be cleared.

2: RB port change interrupts also require the individual pin IOCB enables.

Note: Interru pt flag bit s are set when an inter rupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit. User software should ensure

the appr opri ate in terrupt f lag bi ts are cl ear

prior to enabling an interrupt. This feature

allows for software polling.

 2010-2012 Microchip Technology Inc. DS41412F- page 117

PIC18(L)F2X/4XK22

R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1

RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled

0 = PORTB pull-up s ar e ena bled pro vided that the pin is an input and the corre spond ing WP UB bit is

set.

bit 6 INTEDG0: External Interrupt 0 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 5 INTEDG1: External Interrupt 1 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 4 INTEDG2: External Interrupt 2 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 3 Unimplemented: Read as ‘0’

bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit

1 =High priority

0 = Low priority

bit 1 Unimplemented: Read as ‘0’

bit 0 RBIP: RB Port Change Interrupt Priority bit

1 =High priority

0 = Low priority

Note: Interru pt flag bit s are set when an inter rupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit. User software should ensure

the appr opri ate in terrupt f lag bi ts are cl ear

prior to enabling an interrupt. This feature

allows for software polling.

PIC18(L)F2X/4XK22

DS41412F-page 118  2010-2012 Microchip Technology Inc.

R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 = High priority

0 = Low priority

bit 6 INT1IP: INT1 External Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5 Unimplemented: Read as ‘0’

bit 4 INT2IE: INT2 External Interrupt Enable bit

1 = Enables the INT2 external interrupt

0 = Disables the INT2 external interrupt

bit 3 INT1IE: INT1 External Interrupt Enable bit

1 = Enables the INT1 external interrupt

0 = Disables the INT1 external interrupt

bit 2 Unimplemented: Read as ‘0’

bit 1 INT2IF: INT2 External Interrupt Flag bit

1 = The INT2 external interrupt occurred (must be cleared by software)

0 = The INT2 external interrupt did not occur

bit 0 INT1IF: INT1 External Interrupt Flag bit

1 = The INT1 external interrupt occurred (must be cleared by software)

0 = The INT1 external interrupt did not occur

Note: Interru pt flag bit s are set when an inter rupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit. User software should ensure

the appr opri ate in terrupt f lag bi ts are cl ear

prior to enabling an interrupt. This feature

allows for software polling.

 2010-2012 Microchip Technology Inc. DS41412F- page 119

PIC18(L)F2X/4XK22

U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’.

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared by software)

0 = The A/D conversion is not complete or has not been started

bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit

1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read)

0 = The EUSART1 receive buffer is empty

bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit

1 = The EUSART1 transm it buffer, TXREG1, is empty (cleared wh en TXREG1 is written)

0 = The EUSART1 transm it buffer is full

bit 3 SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared by software)

0 = Waiting to transmit/receive

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared by software)

0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared by software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Fl ag bit

1 = TMR2 to PR2 match occurred (must be cleared by software)

0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overf lowed (must be cle ared by soft ware)

0 = TMR1 register did not overflow

Note 1: Interrupt flag bits are set when an

interrupt condition occurs, regardless of

the state of its corresponding enable bit

or the Global Interrupt Enable bit, GIE/

GIEH of the INTCON register.

Note: User software should ensure the appro-

priate interrupt flag bits are cleared prior

to enabling an interrupt and after servic-

ing that interrupt.

PIC18(L)F2X/4XK22

DS41412F-page 120  2010-2012 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit

1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software)

0 = Device clock operating

bit 6 C1IF: Comparator C1 Interrupt Flag bit

1 = Comparator C1 output has changed (must be cleared by software)

0 = Comparator C1 output has not changed

bit 5 C2IF: Comparator C2 Interrupt Flag bit

1 = Comparator C2 output has changed (must be cleared by software)

0 = Comparator C2 output has not changed

bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit

1 = The write operation is complete (must be cleared by software)

0 = The write operation is not complete or has not been started

bit 3 BCL1IF: MSSP1 Bus Collision Interrupt Flag bit

1 = A bus collision occurred (must be cleared by software)

0 = No bus collision occurred

bit 2 HLVDIF: Low-Voltage Detect Interrupt Flag bit

1 = A low-voltage condition occurred (direction determined by the VDIRMAG bit of the

HLVDCON register)

0 = A low-voltage condition has not occurred

bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit

1 = TMR3 register overf lowed (must be cle ared by soft ware)

0 = TMR3 register did not overflow

bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared by software )

0 = No TMR1 register capture occur red

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared by software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode .

 2010-2012 Microchip Technology Inc. DS41412F- page 121

PIC18(L)F2X/4XK22

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SSP2IF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit 6 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit

1 = A bus collision has occurred while the SSP2 module configured in I2C master was transmitting

(must be cleared in software)

0 = No bus collision occurred

bit 5 RC2IF: EUSART2 Receive Interrupt Flag bit

1 = The EUSART2 receive buffer, RCREG2, is full (cleared by reading RCREG2)

0 = The EUSART2 receive buffer is empty

bit 4 TX2IF: EUSART2 Transmit Interrupt Flag bit

1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared by writing TXREG2)

0 = The EUSART2 transm it buffer is full

bit 3 CTMUIF: CTMU Interrupt Flag bit

1 = CTMU interrupt occurred (must be cleared in software)

0 = No CTMU interrupt occurred

bit 2 TMR5GIF: TMR5 Gate Interrupt Flag bits

1 = TMR gate interrupt occurred (must be cleared in software)

0 = No TMR gate occurred

bit 1 TMR3GIF: TMR3 Gate Interrupt Flag bits

1 = TMR gate interrupt occurred (must be cleared in software)

0 = No TMR gate occurred

bit 0 TMR1GIF: TMR1 Gate Interrupt Flag bits

1 = TMR gate interrupt occurred (must be cleared in software)

0 = No TMR gate occurred

PIC18(L)F2X/4XK22

DS41412F-page 122  2010-2012 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — CCP5IF CCP4IF CCP3IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2 CCP5IF: CCP5 Interrupt Flag bits

Capture mode:

1 = A TMR register capture occurred (must be cleared in software)

0 = No TMR register capture occurred

Compare mode:

1 = A TMR register compare match occurred (must be cleared in software)

0 = No TMR register compare match occurred

PWM mode:

Unused in PWM mo de.

bit 1 CCP4IF: CCP4 Interrupt Flag bits

Capture mode:

1 = A TMR register capture occurred (must be cleared in software)

0 = No TMR register capture occurred

Compare mode:

1 = A TMR register compare match occurred (must be cleared in software)

0 = No TMR register compare match occurred

PWM mode:

Unused in PWM mo de.

bit 0 CCP3IF: ECCP3 Interrupt Flag bits

Capture mode:

1 = A TMR register capture occurred (must be cleared in software)

0 = No TMR register capture occurred

Compare mode:

1 = A TMR register compare match occurred (must be cleared in software)

0 = No TMR register compare match occurred

PWM mode:

Unused in PWM mo de.

 2010-2012 Microchip Technology Inc. DS41412F- page 123

PIC18(L)F2X/4XK22

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — TMR6IF TMR5IF TMR4IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2 TMR6IF: TMR6 to PR6 Match Interrupt Fl ag bit

1 = TMR6 to PR6 match occurred (must be cleared in software)

0 = No TMR6 to PR6 match occurred

bit 1 TMR5IF: TMR5 Overflow Interrupt Flag bit

1 = TMR5 register overflowed (m ust be cleared in software)

0 = TMR5 register did not overflow

bit 0 TMR4IF: TMR4 to PR4 Match Interrupt Fl ag bit

1 = TMR4 to PR4 match occurred (must be cleared in software)

0 = No TMR4 to PR4 match occurred

PIC18(L)F2X/4XK22

DS41412F-page 124  2010-2012 Microchip Technology Inc.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’.

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D in terrupt

bit 5 RC1IE: EUSART1 Receive Interrupt Enable bit

1 = Enables the EUSART1 receive interrupt

0 = Disables the EUSART1 receive interrupt

bit 4 TX1IE: EU SAR T1 T ran sm it Inter r upt Enab le bit

1 = Enables the EUSART1 transmit interrupt

0 = Disables the EUSART1 transmit interrupt

bit 3 SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit

1 = Enables the MSSP1 interrupt

0 = Disables the MSSP1 interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

 2010-2012 Microchip Technology Inc. DS41412F- page 125

PIC18(L)F2X/4XK22

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 6 C1IE: Comparator C1 Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 5 C2IE: Comparator C2 Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 3 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 2 HLVDIE: Low-Voltage Detect Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enabled

0 =Disabled

PIC18(L)F2X/4XK22

DS41412F-page 126  2010-2012 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SSP2IE: TMR5 Gate Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 6 BCL2IE: Bus Collision Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 3 CTMUIE: CTMU Inte rrupt Enable bit

1 = Enabled

0 =Disabled

bit 2 TMR5GIE: TMR5 Gate Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 1 TMR3GIE: TMR3 Gate Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 0 TMR1GIE: TMR1 Gate Interrupt Enable bit

1 = Enabled

0 =Disabled

 2010-2012 Microchip Technology Inc. DS41412F- page 127

PIC18(L)F2X/4XK22

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — CCP5IE CCP4IE CCP3IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2 CCP5IE: CCP5 Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 1 CCP4IE: CCP4 Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 0 CCP3IE: CCP3 Interrupt Enable bit

1 = Enabled

0 =Disabled

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — TMR6IE TMR5IE TMR4IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit

1 = Enables the TMR6 to PR6 match interrupt

0 = Disables the TMR6 to PR6 match interrupt

bit 1 TMR5IE: TMR5 Overflow Interrupt Enable bit

1 = Enables the TMR5 overflow interrupt

0 = Disables the TMR5 overflow interrupt

bit 0 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit

1 = Enables the TMR4 to PR4 match interrupt

0 = Disables the TMR4 to PR4 match interrupt

PIC18(L)F2X/4XK22

DS41412F-page 128  2010-2012 Microchip Technology Inc.

U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 ADIP: A/D Converter Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5 RC1IP: EUSART1 Receive Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4 TX1IP: EUSART1 Transmit Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3 SSP1IP: Master Synchronous Serial Port 1 Interrupt Prio rity bit

1 = High priority

0 = Low priority

bit 2 CCP1IP: CCP1 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Prio rity bit

1 = High priority

0 = Low priority

bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

 2010-2012 Microchip Technology Inc. DS41412F- page 129

PIC18(L)F2X/4XK22

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit

1 = High priority

0 = Low priority

bit 6 C1IP: Comparator C1 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5 C2IP: Comparator C2 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3 BCL1IP: MSSP1 Bus Collision Interrupt Priority bit

1 = High priority

0 = Low priority

bit 2 HLVDIP: Low-Voltage Detect Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0 CCP2IP: CCP2 Interrupt Priority bit

1 = High priority

0 = Low priority

PIC18(L)F2X/4XK22

DS41412F-page 130  2010-2012 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SSP2IP: Synchronous Serial Port 2 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 6 BCL2IP: Bus Co ll is ion 2 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3 CTMUIP: CTMU Inte rrupt Priority bit

1 = High priority

0 = Low priority

bit 2 TMR5GIP: TMR5 Gate Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1 TMR3GIP: TMR3 Gate Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0 TMR1GIP: TMR1 Gate Interrupt Priority bit

1 = High priority

0 = Low priority

 2010-2012 Microchip Technology Inc. DS41412F- page 131

PIC18(L)F2X/4XK22

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — CCP5IP CCP4IP CCP3IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2 CCP5IP: CCP5 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1 CCP4IP: CCP4 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0 CCP3IP: CCP3 Interrupt Priority bit

1 = High priority

0 = Low priority

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — TMR6IP TMR5IP TMR4IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2 TMR6IP: TMR6 to PR6 Match Interrupt Prio rity bit

1 = High priority

0 = Low priority

bit 1 TMR5IP: TMR5 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0 TMR4IP: TMR4 to PR4 Match Interrupt Prio rity bit

1 = High priority

0 = Low priority

PIC18(L)F2X/4XK22

DS41412F-page 132  2010-2012 Microchip Technology Inc.

9.9 INTn Pin Interrupts

External interrupts on the RB0/INT0, RB1/INT1 and

RB2/INT2 p ins are edge-triggered. If the corresponding

INTEDGx bit in the INTCON2 register is set (= 1), the

interrupt is triggered by a rising edge; if the bit is clear,

the trigger is on the falling edge. When a valid edge

appears on the RBx/INTx pin, the corresponding flag

bit, INTxF, is set. This interrupt can be disabled by

clearing the corresponding enable bit, INTxE. Flag bit,

INTxF, must be cleared by software in the Interrupt

Service Routine before re-enabling the interrupt.

All extern al interrupt s (INT0, INT1 an d INT2) can wake-

up the processor from Idle or Sleep modes if bit INTxE

was set prior to going into those modes. If the Global

Interrupt Enable bit, GIE/GIEH, is set, the processor

will branch to the interrupt vector following wake-up.

Interrupt priority for INT1 and INT2 is determined by

the value cont ain ed in the interrupt priority bit s, INT1IP

and INT2IP of the INTCON3 registe r . There is no prior-

ity bit associated with INT0. It is always a high priority

interrupt source.

9.10 TMR0 Interrupt

In 8-b it mod e (whic h is the de faul t), a n overfl ow in t he

TMR0 register (FFh 00h) will se t flag bit, TM R0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L regis-

ter pair (FFFFh 0000h) will set TMR0IF. The interrupt

can be enabled/disabled by setting/clearing enable bit,

TMR0IE of the INTCON register. Interrupt priority for

Timer0 is determined by the value contained in the

interrupt priority bit, TM R0IP of the INTCON2 register.

See Sec tio n 11 .0 “Tim er0 Mo dul e” for further details

on the Timer0 module.

9.11 PORTB Interrupt-on-Change

An input c ha nge on PO RTB<7:4> sets f lag bi t, R BIF of

the INTCON register. The interrupt can be enabled/

disabled by setting/clearing enable bit, RBIE of the

INTCON register. Pins must also be individually

enabled with the IOCB register. Interrupt priority for

PORTB in terrupt-on-change is determined by the value

contained in the interrupt priority bit, RBIP of the

INTCON2 regi ste r.

9.12 Context Saving During Interr upts

During interrupts, the return PC address is saved on

the stack. Additionally, the WREG, STATUS and BSR

registers are saved on the fast return stack. If a fast

return from interrupt is not used (see Section 5.2.1

“Fast R egister S tac k”), the user may need to sa ve the

WREG, STATUS and BSR registers on entry to the

Interrupt Service Routine. Depending on the user’s

applic ation, o the r regist ers ma y also ne ed to be save d.

Example 9-1 saves and restores the WREG, STATUS

and BSR regi sters d uring an In terrupt Serv ice Rou tine.

EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF W_TEMP ; W_TEMP is in virtual bank

MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere

MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere

;

; USER ISR CODE

;

MOVFF BSR_TEMP, BSR ; Restore BSR

MOVF W_TEMP, W ; Restore WREG

MOVFF STATUS_TEMP, STATUS ; Restore STATUS

 2010-2012 Microchip Technology Inc. DS41412F- page 133

PIC18(L)F2X/4XK22

TABLE 9-1: REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 155

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP117

INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 118

IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 158

IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129

IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130

IPR4 — — — — — CCP5IP CCP4IP CCP3IP 131

IPR5 — — — — — TMR6IP TMR5IP TMR4IP 131

PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125

PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126

PIE4 — — — — — CCP5IE CCP4IE CCP3IE 127

PIE5 — — — — — TMR6IE TMR5IE TMR4IE 127

PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

PIR4 — — — — — CCP5IF CCP4IF CCP3IF 122

PIR5 — — — — — TMR6IF TMR5IF TMR4IF 123

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 153

RCON IPEN SBOREN — RI TO PD POR BOR 60

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts.

TABLE 9-2: CONFIGURATION REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CONFIG3H MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360

CONFIG4L DEBUG XINST — — — LVP — STRVEN 361

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts.

PIC18(L)F2X/4XK22

DS41412F-page 134  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 135

PIC18(L)F2X/4XK22

10.0 I/O PORTS

Depending on the device selected and features

enabled, there are up to five ports available. All pins of

the I/O port s are multiple xed with one or more alte rnate

functions from the peripheral features on the device. In

general, when a perip heral is ena bled, that pi n may not

be used as a general purpose I/O pin.

Each port has five registers for its operation. These

registers are:

• TRIS register (data direction register)

• PORT register (rea ds the lev els on the pin s of the

device)

• LAT register (output latch)

• ANSEL register (analog input control)

• SLRCON register (port slew rate control)

The Dat a Latch (LAT register ) is usef ul for read-modif y-

write operations on the value that the I/O pins are

driving.

A simplified model of a generic I/O port, without the

inter faces to other peripherals, is s hown in Figure 10-1.

FIGURE 10-1: GENERIC I/O PORT

OPERATION

10.1 PORTA Registers

PORTA is an 8-bit wide, bidirectional port. The

correspo ndi ng data direction re gis ter is TR ISA. Se ttin g

a TRISA bit (= 1) will make the corresponding PORTA

pin an input (i.e., disable the output driver). Clearing a

TRISA bit (= 0) will make the corresponding PORTA

pin an output (i.e., enable t he ou tput drive r and pu t the

contents of the output latch on the sel ected pin).

Reading the PORTA register reads the status of the

pins, whe reas wri ting to it, will write to the P OR T la tch.

The Data La tch (LA TA) register is also memory mapped.

Read-modify-write operations on the LATA register read

and write the latched output valu e for PORTA.

The RA4 pin is multiplexed with the Timer0 module

clock input and one of the comparator outputs to

become the RA4/T0CKI/C1OUT pin. Pins RA6 and

RA7 are multiplexed with the main oscillator pins; they

are enabled as oscillator or I/O pins by the selection of

the main oscillator in the Configuration register (see

Section 24.1 “Configuration Bits” for details). When

they are not used as port pins, RA6 and RA7 and their

associated TRIS and LAT bits are read as ‘0’.

The other PORTA pins are multiplexed with analog

inputs, the analog VREF+ and VREF- inputs, and the

comparator voltage reference output . The operati on of

pins RA<3:0> and RA5 as analog is selected by setting

the ANSELA<5, 3:0> bits in the ANSELA register which

is the default setting after a Power-on Reset.

Pins RA0 through RA5 may also be used as comparator

inputs or outputs by setting the appropriate bits in the

CM1CON0 and CM2CON0 registers.

The R A4 / T0 CK I /C 1O UT pi n is a S c hm itt Trigg e r in p ut .

All other PORTA pins have TTL input levels and full

CMOS out put driv ers.

The TRISA register controls the drivers of the PORTA

pins, ev en w he n th ey a re being used as analog inputs.

The user should ensure the bits in the TRISA register

are maintained se t whe n using t hem as a nal og inp uts.

EXAMPLE 10-1: INITIA LI ZING PORTA

Data

Bus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latc h

RD TRIS

Input

Buffer

I/O pin(1)

RD LAT

or Port

Note 1: I/O pins have diode protection to VDD and VSS.

TRISx

ANSELx

Note: On a Power-on Reset, RA5 and RA<3:0>

are configured as analog inputs and read

as ‘0’. RA4 is co nfigur ed as a digital input.

MOVLB 0xF ; Set BSR for banked SFRs

CLRF PORTA ; Initialize PORTA by

; clearing output

; data latches

CLRF LATA ; Alternate method

; to clear output

; data latches

MOVLW E0h ; Configure I/O

MOVWF ANSELA ; for digital inputs

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISA ; Set RA<3:0> as inputs

; RA<5:4> as outputs

PIC18(L)F2X/4XK22

DS41412F-page 136  2010-2012 Microchip Technology Inc.

TABLE 10-1: PORTA I/O SUMMARY

Pin Name Function TRIS

Setting ANSEL

Setting Pin

Type Buffer

Type Description

RA0/C12IN0-/AN0 RA0 00O DIG LATA<0> data output; not affected by analog input.

10I T TL PORTA<0> data input; disabled when analog input

enabled.

C12IN0- 11I AN Comparators C1 and C2 inverting input.

AN0 11I AN Analog input 0.

RA1/C12IN1-/AN1 RA1 00O DIG LATA<1> data output; not affected by analog input.

10I T TL PORTA<1> data input; disabled when analog input

enabled.

C12IN1- 11I AN Comparators C1 and C2 inverting input.

AN1 11I AN Analog input 1.

RA2/C2IN+/AN2/

DACOUT/VREF-RA2 00O DIG LATA<2> data output; not affected by analog input ; disabled

when DACOUT enabled.

10I T TL PORTA<2> data input; dis abled when analog input

enabled; disabled when DACOUT enabled.

C2IN+ 11I AN Com parator C2 non-inverting input.

AN2 11I AN Analog output 2.

DACOUT x1O AN DAC Reference output.

VREF-11I AN A/D reference voltage (low) input.

RA3/C1IN+/AN3/

VREF+RA3 0O DIG LATA<3> data output; not affected by analog input.

10I T TL PORTA<3> data input; disabled when analog input

enabled.

C1IN+ 11I AN Com parator C1 non-inverting input.

AN3 11I AN Analog input 3.

VREF+11I AN A/D reference voltage (high) input.

RA4/CCP5/

C1OUT/SRQ/

T0CKI

RA4 0—O DIG LATA<4> data output.

1—I ST PORTA<4> data input; default configuration on POR.

CCP5 0—O DIG CCP 5 Compare output/PWM output, takes priority over

RA4 output.

1—I ST Capture 5 input/Compare 5 output/ PWM 5 output.

C1OUT 0—O DIG Comparator C1 output.

SRQ 0—O DIG SR latch Q output; ta ke priority over CCP 5 output.

T0CKI 1—I ST Timer0 external clock input.

RA5/C2OUT/

SRNQ/SS1/

HLVDIN/AN4

RA5 00O DIG LATA<5> data output; not affected by analog input.

10I T TL PORTA<5> data input; disabled when analog input

enabled.

C2OUT 00O DIG Comparator C2 output.

SRNQ 00O DIG SR latch Q output.

SS1 10I TTL SPI slave select input (MSSP1).

HLVDIN 11I AN High/ Lo w-Voltage Detect input.

AN4 11I AN A/D input 4.

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal;

CMOS = CMOS compatible input or output; ST = Schmitt T rigger i nput with CMOS levels; I2CTM = Schmitt Trigger input

with I2C.

 2010-2012 Microchip Technology Inc. DS41412F- page 137

PIC18(L)F2X/4XK22

RA6/CLKO/OSC2 RA6 0—O DIG LATA<6> data output; enabled in INTOSC modes when

CLKO is not enabled.

1—I TTL PORTA<6> data input; enabled in INTOSC modes when

CLKO is not enabled.

CLKO x—O DIG In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the

frequency of OSC1 and denotes the instruction cycle rate.

OSC2 x—O XTAL Oscillator crystal output; connects to crystal or resonator in

Crystal Oscillator mode.

RA7/CLKI/OSC1 RA7 0—O DIG LATA<7> data output; disabled in external oscillator modes.

1—I TTL PORTA<7> data input; disabled in external oscillator

modes.

CLKI x—I AN External clock source input; always associated with pin

fun cti o n OSC1 .

OSC1 x—I XTAL Oscillator crystal input or external clock source input ST

buffer when configured in RC mode; CMOS otherwise.

TABLE 10-1: PORTA I/O SUMMARY (CONTINUED)

Pin Name Function TRIS

Setting ANSEL

Setting Pin

Type Buffer

Type Description

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal;

CMOS = CMOS compatible input or output; ST = Schmitt T rigger i nput with CMOS levels; I2CTM = Schmitt Trigger input

with I2C.

TABLE 10-2: REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELA —— ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 154

CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH<1:0> 317

CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH<1:0> 317

LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 158

VREFCON1 DACEN DACLPS DACOE —DACPSS<1:0> —DACNSS 347

VREFCON2 — — — DACR<4:0> 348

HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0> 349

PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 153

SLRCON — — — SLRE SLRD SLRC SLRB SLRA 158

SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 340

SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 260

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS<2:0> 159

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 156

Legend: — = unimp lemented locations , read as ‘0’. Shaded bits are not used for PORTA.

TABLE 10-3: CONFIGURATION REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CONFIG1H IESO FCMEN PRICLKEN PLLCFG FOSC<3:0> 357

Legend: — = unimp lemented locations , read as ‘0’. Shaded bits are not used for PORTA.

PIC18(L)F2X/4XK22

DS41412F-page 138  2010-2012 Microchip Technology Inc.

10.1.1 PORTA OUTPUT PRIORITY

Each PORTA pin is multiplexed with other functions.

The pins, their combined functions and their output

priorities are briefly described here. For additional

informa tion, refe r to the ap pro priate sec tion in this da ta

sheet.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the higher priority.

Table 10-4 lists the PORTA pin functions from the

highest to the lowest priority.

Analog input functions, such as ADC and comparator,

are not show n in the priority lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx registers. Digital

output function s may control the pin whe n it is in Analog

mode with the priority shown below.

TABLE 10-4: PORT PIN FUNCTION PRIORITY

Port bit Port Function Priority by Port Pin

PORTA PORTB PORTC PORTD(2) PORTE(2)

0 RA0 CCP4(1) SOSCO SCL2 CCP3(8)

RB0 P2B(6) SCK2 P3A(8)

RC0 RD0 RE0

1 RA1 SCL2(1) SOSCI SDA2 P3B

SCK2(1) CCP2(3) CCP4 RE1

P1C(1) P2A(3) RD1

RB1 RC1

2 RA2 SDA2(1) CCP1 P2B CCP5

P1B(1) P1A RD2(4) RE2

RB2 CTPLS

RC2

3 RA3 SDO2(1) SCL1 P2C MCLR

CCP2(6) SCK1 RD3 VPP

P2A(6) RC3 RE3

RB3

4SRQP1D

(1) SDA1 SDO2

C1OUT RB4 RC4 P2D

CCP5(1) RD4

RA4

Note 1: PIC18(L)F2XK22 devices.

2: PIC18(L)F4XK22 devices.

3: Func tion def ault pin.

4: Function default pin (28-pin devices).

5: Func tion def ault pin (40/44-pin devices).

6: Function alternate pin.

7: Function alternate pin (28-pin devices).

8: Function alternate pin (40/44-pin devices)

 2010-2012 Microchip Technology Inc. DS41412F- page 139

PIC18(L)F2X/4XK22

5 SRNQ CCP3(3) SDO1 P1B

C2OUT P3A(3) RC5 RD5

RA5 P2B(1)(4)

RB5

6 OSC2 PGC TX1/CK1 TX2/CK2

CLKO TX2/CK2(1) CCP3(1)(7) P1C

RA6 RB6 P3A(1)(7) RD6

ICDCK RC6

7RA7

OSC1 PGD RX1/DT1 RX2/DT2

RA7 RX2/DT2(1) P3B(1) P1D

RB7 RC7 RD7

ICDDT

TABLE 10-4: PORT PIN FUNCTION PRIORITY (CONTINUED)

Port bit Port Function Priority by Port Pin

PORTA PORTB PORTC PORTD(2) PORTE(2)

Note 1: PIC18(L)F2XK22 devices.

2: PIC18(L)F4XK22 devices.

3: Func tion def ault pin.

4: Function default pin (28-pin devices).

5: Func tion def ault pin (40/44-pin devices).

6: Function alternate pin.

7: Function alternate pin (28-pin devices).

8: Function alternate pin (40/44-pin devices)

PIC18(L)F2X/4XK22

DS41412F-page 140  2010-2012 Microchip Technology Inc.

10.2 PORTB Registers

PORTB is an 8-bit wide, bidirectional port. The

corresp ond ing data direction re gis ter is TR ISB. Se ttin g

a TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., disable the output driver). Clearing a

TRISB bit (= 0) will make the corresponding PORTB

pin an outpu t (i.e., enabl e the output driver and put the

contents of the output latch on the selected pin).

The Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

PORTB.

EXAMPLE 10-2: INITIALIZI NG PORTB

10.2.1 POR TB OUTPUT PRIORITY

Each PORTB pin is multiplexed with other functions.

The pins, their combined functions and their output

priorities are briefly described here. For additional

informa tion, refe r to the ap pro priate sec tion in this da ta

sheet.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the higher priority.

Table 10-4 lists the PORTB pin functions from the

highest to the lowest priority.

Analog input functions, such as ADC, comparator and

SR latch inputs, are not shown in the priority lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx registers. Digital

output function s may control the pin whe n it is in Analog

mode with the priority shown below.

10.3 Additional PORTB Pin Functions

PORTB pins RB<7:4> have an interrupt-on-change

option. All PORTB pins have a weak pull-up option.

10.3.1 WEAK PULL-UPS

Each of the PORTB pins has an individually controlled

weak internal pull-up. When set, each bit of the WPUB

cleared, the RBPU bit of the INTC ON2 register enab les

pull-up s on all pins which also have their co rresponding

WPUB bit set. When set, the RBPU bit disables all

weak pull-ups. The weak pull-up is automatically turned

off when the port pin is configured as an output. The

pull-ups are disabled on a Power-on Reset.

10.3.2 INTERRUPT-ON-CHANGE

Four of the PORTB pins (RB<7:4>) are individually

configurable as interrupt-on-change pins. Control bits

in the IOCB register enable (when set) or disable (whe n

clear) the interrupt function for each pin.

When se t, the RBIE bit of the INTCON reg ister enab les

interrupts on all pins which also have their

corresponding IOCB bit set. When clear, the RBIE bit

disabl es all interru pt-on-changes.

Only pins configured as inputs can cause this interrupt

to occur (i .e., any RB<7:4 > pin co nfigure d as an outp ut

is exclud ed from th e interrupt-o n-change comp arison).

For enabled interrupt-on-change pins, the values are

comp ared with the old val ue latch ed on the la st read of

PORTB. The ‘mismatch’ outputs of the last read are

OR’d together to set the PORTB Change Interrupt flag

bit (RBIF) in the INTCON register.

This interrupt can wake the device from the Sleep

mode, or any of the Idle modes. The user, in the

Interrupt Service Routine, can clear the interrupt in the

following manner:

a) Any read or write of PORTB to clear the mis-

match condition (except when PORTB is the

source or destination of a MOVFF instruction).

b) Execute at least one instruction after reading or

writing PORTB, then clear the flag bit, RBIF.

MOVLB 0xF ; Set BSR for banked SFRs

CLRF PORTB ; Initialize PORTB by

; clearing output

; data latches

CLRF LATB ; Alternate method

; to clear output

; data latches

MOVLW 0F0h ; Value for init

MOVWF ANSELB ; Enable RB<3:0> for

; digital input pins

; (not required if config bit

; PBADEN is clear)

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISB ; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

Note: On a Power-on Reset, RB<5:0> are

configu red as analog inputs by default and

read as ‘0’; RB<7:6> are configured as

digital inputs.

When the PBADEN Configuration bit is

set to ‘1’, RB<5:0> will alternatively be

configured as digital inputs on POR.

 2010-2012 Microchip Technology Inc. DS41412F- page 141

PIC18(L)F2X/4XK22

A mismatch condition will continue to set the RBIF flag bit.

Reading or writing PORTB will end the mismatch

condition and allow the RBIF bit to be cleare d. The latch

holding the last read value is not affected by a MCLR nor

Brown-out Reset. After either one of these Resets, the

RBIF flag will continue to be set if a mismatch is present.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used f or the int errupt-on-change

feature. Polling of PORTB is not recommended while

usin g the interrupt-on-change feature.

10.3.3 ALT ERNATE FUNCTIONS

PORTB i s multiplexed w ith several pe ripheral function s

(Table 10-5) . The pins have TTL input bu ffer s. Some of

these pin functions can be relocated to alternate pins

using the Control fuse bits in CONFIG3H. RB5 is the

default pin for P2B (28-pin devices). Clearing the

P2BMX bit moves the pin function to RC0. RB5 is also

the defau lt p in fo r the CC P3/P3 A peri ph eral pin . Cle ar-

ing the C CP3M X bit m ov es the p in fu nc tio n to th e RC 6

pin (28-pin devices) or RE0 (40/44-pin devices).

T wo other pin functions, T3CKI and CCP2/P2A, can be

relocated from their default pins to PORTB pins by

clearing the control fuses in CONFIG3H. Clearing

T3CMX and CCP2MX moves the pin functions to RB5

and RB3, respectively.

Note: If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF

interrupt flag may not get set. Furthermore,

since a read or write on a port affects all

bits of that port, care must be taken when

using multiple pins in Interrupt-on-change

mode. Changes on one pin may not be

seen while servicing changes on another

pin.

TABLE 10-5: PORTB I/O SUMMARY

Pin Function TRIS

Setting ANSEL

Setting Pin

Type Buffer

Type Description

RB0/INT0/CCP4/

FLT0/SRI/SS2/

AN12

RB0 00O DI G LATB<0> data output; not affected by analog input.

10 I TTL PORTB<0> data input; disabled when analog input

enabled.

INT0 10 I ST External interrupt 0.

CCP4(3) 00O DIG Compare 4 output/PWM 4 output.

10 I ST Capture 4 input.

FLT0 10 I ST PWM Fault input for ECCP auto-shutdown.

SRI 10 I ST SR latch input.

SS2(3) 10 I TTL SPI slave select input (MSSP2).

AN12 11 I AN Analog input 12.

RB1/INT1/P1C/

SCK2/SCL2/

C12IN3-/AN10

RB1 00O DI G LATB<1> data output; not affected by analog input.

10 I TTL PORTB<1> data input; disabled when analog input

enabled.

INT1 10 I ST External Interrupt 1.

P1C(3) 00O DIG Enhanced CCP1 PWM output 3.

SCK2(3) 00O DI G MSSP2 SPI Clock output.

10 I ST MSS P2 SPI Clock input.

SCL2(3) 00ODIGMSSP2 I

2CTM Clock output.

10 II

2C MSS P2 I 2CTM Clock input.

C12IN3- 11 I AN Comparators C1 and C2 inverting input.

AN10 11 I AN Analog input 10.

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XT AL = Crystal; CMOS =

CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.

PIC18(L)F2X/4XK22

DS41412F-page 142  2010-2012 Microchip Technology Inc.

RB2/INT2/CTED1/

P1B/SDI2/SDA2/

AN8

RB2 00O DI G LATB<2> data output; not affected by analog input.

10 I TTL PORTB<2> data input; disabled when analog input

enabled.

INT2 10 I ST External interrupt 2.

CTED1 10 I ST CTMU Edge 1 input.

P1B(3) 00O DIG Enhanced CCP1 PWM output 2.

SDI2(3) 10 I ST MSSP2 SPI data input.

SDA2(3) 00ODIGMSSP2 I

2CTM dat a output.

10 II

2C M SS P2 I2CTM data input.

AN8 11 I AN Analog input 8.

RB3/CTED2/P2A/

CCP2/SDO2/

C12IN2-/AN9

RB3 00O DI G LATB<3> data output; not affected by analog input.

10 ITTL PORTB<3> data input; disabled when analog input

enabled.

CTED2 10 IST CTMU Edge 2 input.

P2A 00O DIG Enhanced CCP1 PWM output 1.

CCP2(2) 00O DIG Compare 2 output/PWM 2 output.

10 I ST Capture 2 input.

SDO2(2) 00O DIG MSSP2 SPI data output.

C12IN2- 11 I AN Comparators C1 and C2 inverting input.

AN9 11 I AN Analog input 9.

RB4/IOC0/P1D/

T5G/AN11 RB4 00O DIG LATB<4> data output; not affected by analog input.

10 I TTL PORTB<4> data input; disabled when analog input

enabled.

IOC0 10 I TTL Interrupt-on-change pin.

P1D 00O DIG Enhanced CCP1 PWM output 4.

T5G 10 I ST Timer5 external clock gate input.

AN11 11 I AN Analog input 11.

RB5/IOC1/P2B/

P3A/CCP3/T3CKI/

T1G/AN13

RB5 00O DI G LATB<5> data output; not affected by analog input.

10 I TTL PORTB<5> data input; disabled when analog input

enabled.

IOC1 10 I TTL Interrupt-on-change pin 1.

P2B(1)(3) 00O DIG Enhanced CCP2 PWM output 2.

P3A(1) 00O DIG Enhanced CCP3 PWM output 1.

CCP3(1) 00O DIG Compare 3 output/PWM 3 output.

10 I ST Capture 3 input.

T3CKI(2) 10 I ST Timer3 clock input.

T1G 10 I ST Timer1 external clock gate input.

AN13 11 I AN Analog input 13.

TABLE 10-5: PORTB I/O SUMMARY (CONTINUED)

Pin Function TRIS

Setting ANSEL

Setting Pin

Type Buffer

Type Description

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XT AL = Crystal; CMOS =

CMOS compatible input or output; ST = Schmitt T r igger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.

 2010-2012 Microchip Technology Inc. DS41412F- page 143

PIC18(L)F2X/4XK22

RB6/KBI2/PGC RB6 0—O DIG LATB<6> data output; not affected by analog input.

1—I TTL PORTB<6> data input; disabled when analog input

enabled.

IOC2 1—I TTL Interrupt-on-change pin.

TX2(3) 1—O DIG EUSART asynchronous transmit data output.

CK2(3) 1—O DIG EUSART synchronous serial clock output.

1—I ST EUSART synchronous serial clock input.

PGC x—I ST In-Circuit Debugger and ICSPTM programming clock input.

RB7/KBI3/PGD RB7 0—O DIG LATB<7> data output; not affected by analog input.

1—I TTL PORTB<7> data input; disabled when analog input

enabled.

IOC3 1—I TTL Interrupt-on-change pin.

RX2(2), (3) 1—I ST EUSART asynchronous receive data input.

DT2(2), (3) 1—O DIG EUSART synchronous serial data output.

1—I ST EUSART synchronous serial data input.

PGD x—O DI G In-Circuit Debugger and ICSPTM programming data output.

x—I ST In-Circuit Debugger and ICSPTM programming data input.

TABLE 10-5: PORTB I/O SUMMARY (CONTINUED)

Pin Function TRIS

Setting ANSEL

Setting Pin

Type Buffer

Type Description

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XT AL = Crystal; CMOS =

CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.

TABLE 10-6: REGISTERS ASSOCIATED WITH PORTB

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Pag e

ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 155

ECCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 209

CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 205

ECCP3AS CCP3ASE CCP3AS<2:0> PSS3AC<1:0> PSS3BD<1:0> 209

CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 205

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP117

INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 118

IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 158

LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 157

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 153

SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 158

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 173

T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 172

T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL T5GSS<1:0> 173

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156

WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 157

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB.

Note 1: Available on PIC18(L)F4XK22 devices.

PIC18(L)F2X/4XK22

DS41412F-page 144  2010-2012 Microchip Technology Inc.

10.4 PORTC Registers

PORTC is an 8-bit wide, bidirectional port. The

corresp onding data directi on regis ter is TRISC. Setting

a TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., disable the output driver). Clearing a

TRISC bit (= 0) will make the corresponding PORTC

pin an outpu t (i.e., enabl e the output driver and put the

contents of the output latch on the selected pin).

The Data Latch register (LATC) is also memory

mapped. Read-modify-write operations on the LATC

PORTC.

PORT C is multip lexed with s everal periphe ral function s

(Table 10-8). Th e pins ha ve Schm itt Trigg er input buf-

fers.

Some of these pin functions can be relocated to alter-

nate pins using the Control fuse bits in CONFIG3H.

RC0 is the default pin for T3CKI. Clearing the T3CMX

bit moves the pin function to RB5. RC1 is the defaul t pin

for the CCP2 peripheral pin. Clearing the CCP2MX bi t

moves the pin function to the RB3 pin.

Two other pin functions, P2B and CCP3, can be relo-

cated from their defau lt pins to PORTC pi ns by clearing

the control fuses in CONFIG3H. Clearing P2BMX and

CCP3MX moves the pin functions to RC0 and RC6(1)/

RE0(2), respectively.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. The

EUSART and MSSP peripherals override the TRIS bit

to make a pin an output or an input, depending on the

peripheral configuration. Refer to the corresponding

peripheral section for additional information.

The contents of the TRISC register are affected by

peripheral overrides. Reading TRISC always returns

the current contents, even though a peripheral device

may be overriding one or more of the pins.

EXAMPLE 10-3: INITIALIZING PORTC

10.4.1 PORTC OUTPUT PRIORITY

Each PORTC pin is multiplexed with other functions.

The pins, their combined functions and their output

priorities are briefly described here. For additional

informat ion, refe r to the ap propria te sec tion in t his dat a

sheet.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the higher priority.

Table 10-4 lists the PORTC pin functions from the

highest to the lowest priority.

Analog input functions, such as ADC, comparator and

SR latch inputs, are not shown in the priority lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx registers. Digital

output functions may control th e pin when it is in Analog

mode with the priority shown below.

TABLE 10-7: CONFIGURATION REGISTERS ASSOCIATED WITH PORTB

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi t 1 B it 0 Register

on Page

CONFIG3H MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360

CONFIG4L DEBUG XINST — — —LVP

(1) —STRVEN 361

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB.

Note 1: Can only be changed when in high voltage programming mode.

Note: On a Power-on Res et, these pins are con-

figured as analog inputs.

MOVLB 0xF ; Set BSR for banked SFRs

CLRF PORTC ; Initialize PORTC by

; clearing output

; data latches

CLRF LATC ; Alternate method

; to clear output

; data latches

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISC ; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

MOVLW 30h ; Value used to

; enable digital inputs

MOVWF ANSELC ; RC<3:2> dig input enable

; No ANSEL bits for RC<1:0>

; RC<7:6> dig input enable

 2010-2012 Microchip Technology Inc. DS41412F- page 145

PIC18(L)F2X/4XK22

TABLE 10-8: PORTC I/O SUMMARY

Pin Name Function TRIS

Setting ANSEL

setting Pin

Type Bu ffer

Type Description

RC0/P2B/T3CKI/T3G/

T1CKI/SOSCO RC0 0—O DIG LATC <0> data output; not affected by analog input.

1—I ST PORTC<0> data input; disabl ed when analog input

enabled.

P2B(2) 0—O DIG E nhanced CCP2 PW M output 2.

T3CKI(1) 1—I ST Timer3 clock input.

T3G 1—I ST Timer3 external clock gate input.

T1CKI 1—I ST Timer1 clock input.

SOSCO x—O XTAL Secondary oscillator output.

RC1/P2A/CCP2/SOSCI RC1 0—O DIG LATC <1> data output; not affected by analog input.

1—I ST PORTC<1> data input; disabl ed when analog input

enabled.

P2A 0—O DIG E nhanced CCP2 PW M output 1.

CCP2(1) 0—O DIG Compare 2 output/PWM 2 output.

1—I S T Capture 2 input.

SOSCI x—I XTAL Secondary oscillator input.

RC2/CTPLS/P1A/

CCP1/T5CKI/AN14 RC2 00O DIG LATC <2> data output; not aff ected by analog input.

10I ST PORTC<2> data input; disabl ed when analog input

enabled.

CTPLS 00O DIG CTMU pulse generator output.

P1A 00O DIG E nhanced CCP1 PW M output 1.

CCP1 00O DIG Compare 1 output/PWM 1 output.

10I S T Capture 1 input.

T5CKI 10I ST Timer5 clock input.

AN14 11I AN Analog input 14.

RC3/SCK1/SCL1/AN15 RC3 00O DIG LATC<3> data output; not affected by analog input.

10I ST PORTC<3> data input; disabl ed when analog input

enabled.

SCK1 00O DIG MSS P1 SPI Clock output.

10I ST M SSP1 SPI Clock inpu t.

SCL1 00ODIGMSSP1 I

2C™ Clock output.

10I I2C MSSP1 I2C™ Clock input.

AN15 11I AN Analog input 15.

RC4/SDI1/SDA1/AN16 RC4 00O DIG LATC<4> data output; not affected by analog input.

10I ST PORTC<4> data input; disabl ed when analog input

enabled.

SDI1 10I ST MSSP1 SPI d ata input.

SDA1 00ODIGMSSP1 I

2C™ data output.

10I I2C MSSP1 I2C™ data input.

AN16 11I AN Analog input 16.

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =

CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.

PIC18(L)F2X/4XK22

DS41412F-page 146  2010-2012 Microchip Technology Inc.

Pin Name Function TRIS

Setting ANSEL

setting Pin

Type Bu ffer

Type Description

RC5/SDO1/AN17 RC5 00O DIG LATC<5> data output; not affected by analog input.

10I ST PORTC<5> data input; disabl ed when analog input

enabled.

SDO1 00O DIG MSS P1 SPI da ta output.

AN17 11I AN Analog input 17.

RC6/P3A/CCP3/TX1/

CK1/AN18 RC6 00O DIG LATC<6> data output; not affected by analog input.

10I ST PORTC<6> data input; disabl ed when analog input

enabled.

P3A(2), (3) 00O CMOS Enhanced CCP3 PW M output 1.

CCP3(2), (3) 00O DIG Compare 3 output/PWM 3 output.

10I S T Capture 3 input.

TX1 10O DIG EUSART asynchronous transmit data output.

CK1 10O DIG EUSART synchronous serial clock output.

10I ST EUSA RT synchronous ser ial clock input.

AN18 11I AN Analog input 18.

RC7/P3B/RX1/DT1/

AN19 RC7 00O DIG LATC<7> data output; not affected by analog input.

10I ST PORTC<7> data input; disabl ed when analog input

enabled.

P3B 00O CMOS Enhanced CCP3 PWM output 2.

RX1 10I ST EUSAR T asynchronous receive data in.

DT1 10O DIG E USA RT synchronous ser ial data output.

10I S T EUSART synchronous serial data input.

AN19 11I AN Analog input 19.

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =

CMOS compatible input or output; ST = Schmitt T r igger input with CMOS levels; I2CTM = Schmitt T rigger input with I2C.

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are clear.

3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.

TABLE 10-8: PORTC I/O SUMMARY (CONTINUED)

 2010-2012 Microchip Technology Inc. DS41412F- page 147

PIC18(L)F2X/4XK22

TABLE 10-9: REGISTERS ASSOCIATED WITH PORTC

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Pag e

ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 155

ECCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 209

CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 205

ECCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 209

CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 205

CTMUCONH CTMUEN —CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 333

LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 157

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 153

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 158

SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 260

T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSCEN T1SYNC T1RD16 TMR1ON 172

T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 172

T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 173

T5CON TMR5CS<1:0> T5CKPS<1:0> T5SOSCEN T5SYNC T5RD16 TMR5ON 172

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 156

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC.

Note 1: Available on PIC18(L)F4XK22 devices.

TABLE 10-10: CONFIGURATION REGISTERS ASSOCIATED WITH PORTC

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi t 1 B it 0 Register

on Page

CONFIG3H MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC.

PIC18(L)F2X/4XK22

DS41412F-page 148  2010-2012 Microchip Technology Inc.

10.5 PORTD Registers

PORTD is an 8-bit wide, bidirectional port. The

corresp onding data directi on regis ter is TRISD. Setting

a TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., disable the output driver). Clearing a

TRISD bit (= 0) will make the corresponding PORTD

pin an outpu t (i.e., enabl e the output driver and put the

contents of the output latch on the selected pin).

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

PORTD.

All pins on PORTD are implemented with Schmitt

Trigger input buffers. Each pin is individually

configurable as an input or output.

All of the PORTD pins are mu ltip lexed with analog an d

digital peripheral modules. See Table 10-11.

EXAMPLE 10-4: INITIALIZING PORTD

10.5.1 PORTD OUTPUT PRIORITY

Each PORTD pin is multiplexed with other functions.

The pins, their combined functions and their output

priorities are briefly described here. For additional

informat ion, refe r to the ap propria te sec tion in t his dat a

sheet.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the higher priority.

Table 10-4 lists the PORTD pin functions from the

highest to the lowest priority.

Analog input functions, such as ADC, comparator and

SR latch inputs, are not shown in the priority lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx registers. Digital

output functions may control th e pin when it is in Analog

mode with the priority shown below.

Note: PORTD is only available on 40-pin and

44-pin devices.

Note: On a Power-on Reset, these pins are

configured as analog inputs.

MOVLB 0xF ; Set BSR for banked SFRs

CLRF PORTD ; Initialize PORTD by

; clearing output

; data latches

CLRF LATD ; Alternate method

; to clear output

; data latches

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISD ; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

MOVLW 30h ; Value used to

; enable digital inputs

MOVWF ANSELD ; RD<3:0> dig input enable

; RC<7:6> dig input enable

 2010-2012 Microchip Technology Inc. DS41412F- page 149

PIC18(L)F2X/4XK22

TABLE 10-11: PORTD I/O SUMMARY

Pin Name Function TRIS

Setting ANSEL

setting Pin

Type Buffer

Type Description

RD0/SCK2/SCL2/AN20 RD0 00O DIG LATD<0> data output; not affected by analog input.

10I ST PO RTD<0> data input; disabled when analog input

enabled.

SCK2 00O DIG MSSP2 SPI Clock output.

10I ST M SSP2 SPI Clock input.

SCL2 00ODIGMSSP2 I

2C™ Clock output.

10II

2C M SS P2 I2C™ Clock input.

AN20 11I AN Analog input 20.

RD1/CCP4/SDI2/SDA2/

AN21 RD1 00O DIG LATD<1> data output; not affected by analog input.

10I ST PO RTD<1> data input; disabled when analog input

enabled.

CCP4 00O DIG Compare 4 output/PWM 4 output.

10I ST Ca pture 4 input.

SDI2 10I ST M SS P2 SP I data input.

SDA2 00ODIGMSSP2 I

2C™ data output.

10II2CMSSP2 I

2C™ data input.

AN21 11I AN Analog input 21.

RD2/P2B/AN22 RD2 00O DIG LA TD<2> dat a output; not affected by analog input.

10I ST PO RTD<2> data input; disabled when analog input

enabled.

P2B(1) 00O DIG Enhanced CCP2 PWM output 2.

AN22 11I AN Analog input 22.

RD3/P2C/SS2/AN23 RD3 00O DIG LATD<3> data output; not affected by analog input.

10I ST PO RTD<3> data input; disabled when analog input

enabled.

P2C 00O DIG Enhanced CCP2 PWM output 4.

SS2 10I TTL MSSP2 SPI slave select input.

AN23 11I AN Analog input 23.

RD4/P2D/SDO2/AN24 RD4 00O DIG LATD<4> data output; not affected by analog input.

10I ST PO RTD<4> data input; disabled when analog input

enabled.

P2D 00O DIG Enhanced CCP2 PWM output 3.

SDO2 00O DIG MSS P2 SPI data output.

AN24 11I AN Analog input 24.

RD5/P1B/AN25 RD5 00O DIG LA TD<5> dat a output; not affected by analog input.

10I ST PO RTD<5> data input; disabled when analog input

enabled.

P1B 00O DIG Enhanced CCP1 PWM output 2.

AN25 11I AN Analog input 25.

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS

= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

PIC18(L)F2X/4XK22

DS41412F-page 150  2010-2012 Microchip Technology Inc.

TABLE 10-13: CONFIGURATION REGISTERS ASSOCIATED WITH PORTD

Pin Name Function TRIS

Setting ANSEL

setting Pin

Type Buffer

Type Description

RD6/P1C/TX2/CK2/

AN26 RD6 00O DIG LATD<6> data output; not affected by analog input.

10I ST PO RTD<6> data input; disabled when analog input

enabled.

P1C 00O DIG Enhanced CCP 1 PWM output 3.

TX2 10O DIG EUSA RT asynchronous transmit data output.

CK2 10O DIG EUSART synchronous serial clock output.

10I ST E USA RT synchronous serial clock input.

AN26 11I AN Analog input 26.

RD7/P1D/RX2/DT2/

AN27 RD7 00O DIG LATD<7> data output; not affected by analog input.

10I ST PO RTD<7> data input; disabled when analog input

enabled.

P1D 00O DIG Enhanced CCP 1 PWM output 4.

RX2 10I ST EUSART asy nchronous receive data in.

DT2 10O DIG E USART synchronous serial data output.

10I ST E USA RT synchronous serial data input.

AN27 11I AN Analog input 27.

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS

= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.

Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and

CCP2MX are set.

TABLE 10-11: PORTD I/O SUMMARY (CONTINUED)

TABLE 10-12: REGISTERS ASSOCIATED WITH PORTD

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on

Page

ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 155

BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 205

CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 205

CCP4CON — — DC4B<1:0> CCP4M<3:0> 205

LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 157

PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 153

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

SLRCON(1) — — — SLRE SLRD SLRC SLRB SLRA 158

SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 260

TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 156

Legend: — = unimplemented locations, r ead as ‘0’. Shaded bits are not used for PORTD.

Note 1: Available on PIC18(L)F4XK22 devices.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CONFIG3H MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360

Legend: — = unimplemented locations, r ead as ‘0’. Shaded bits are not used for PORTD.

 2010-2012 Microchip Technology Inc. DS41412F- page 151

PIC18(L)F2X/4XK22

10.6 PORTE Registers

Depending on the particular PIC18(L)F2X/4XK22

device selected, PORTE is implemented in two

different ways.

10.6.1 PORTE ON 40/44-PIN DEVICES

For PIC18(L)F2X/4XK22 devices, PORTE is a 4-bit

wide port. Three pins (RE0/P3A/CCP3/AN 5, RE1/P3B/

AN6 and RE2/CCP5 /AN7) are i ndividually configu rable

as inputs or outputs. These pins have Schmitt Trigger

input buffers. When sel ec ted a s an ana log input, these

pins will read as ‘0’s.

The corresponding data direction register is TRISE.

Setting a TRISE bit (= 1) will make the corresponding

PORTE pin an input (i.e., disable the output driver).

Clearing a TR ISE bit (= 0) will make the co rres ponding

PORT E pin an output (i .e., e nable th e output dri ver and

put the contents of the output latch on the selected pin).

TRISE controls the direction of the REx pins, even

when they are being used as analog inputs. The user

must make sure to keep the pins configured as inputs

when using them as analog inputs.

The Data Latch register (LATE) is also memory

mapped. Read-modify-write operations on the LATE

PORTE.

The fourth pin of PORTE (MCLR/VPP/RE3) is an input

only pin. Its operation is controlled by the MCLRE

Configuration bit. When selected as a port pin

(MCLRE = 0), it functions as a digital input only pin; as

such, it does not have TRIS or LA T bits associated with its

operation. Otherw ise, it functions as the device’s Master

Clear input. In either configuration, RE3 also functions as

the programming voltage input during programming.

EXAMPLE 10-5: INITIALIZING PORTE

10.6.2 PO RTE ON 28-PI N DEVICES

For PIC18F2XK22 devices, PORTE is only available

when Master Clear functionality is disabled

(MCLR = 0). In these cases, PORTE is a single bit,

input only port comprised of RE3 only . The pin operates

as previously described.

10.6.3 RE3 WEAK PULL-UP

The port RE3 pin has an individually controlled weak

internal pull-up. When set, the WPUE3 (TRISE<7>) bit

enables the RE3 pin pull-up. The RBPU bit of the

INTCON2 register controls pull-ups on both PORTB

and PORTE. When RBPU = 0, the weak pull-ups

become active on all pins which have the WPUE3 or

WPUBx bits set. When set, the RBPU bit disables all

weak pull-ups. The pull-ups are disabled on a Power-

on Reset. When the RE3 port pin is configured as

MCLR, (CONFIG3H<7>, MCLRE=1 and

CONFIG4L<2>, LVP=0), or configur ed fo r Low Voltag e

Programming, (MCLRE=x and LVP=1), the pull-up is

always enabled and the WPUE3 bit has no effect.

10.6.4 PORTE OUTPUT PRIORITY

Each PORTE pin is multiplexed with other functions.

The pins, their combined functions and their output

priorities are briefly described here. For additional

informat ion, refe r to the ap propria te sec tion in t his dat a

sheet.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the higher priority.

Table 10-4 lists the PORTE pin functions from the

highest to the lowest priority.

Anal og input funct ions, su ch as ADC , compara tor and

SR latch inputs , are not shown in the priority lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx registers. Digital

output functions may control th e pin when it is in Analog

mode with the priority shown below.

Note: On a Power-on Reset, RE<2:0> are

configured as analog inputs.

Note: On a Power-on Reset, RE3 is enabled as

a digital input only if Master Clear

functionality is disabled.

CLRF PORTE ; Initialize PORTE by

; clearing output

; data latches

CLRF LATE ; Alternate method

; to clear output

; data latches

CLRF ANSELE ; Configure analog pins

; for digital only

MOVLW 05h ; Value used to

; initialize data

; direction

MOVWF TRISE ; Set RE<0> as input

; RE<1> as output

; RE<2> as input

PIC18(L)F2X/4XK22

DS41412F-page 152  2010-2012 Microchip Technology Inc.

TABLE 10-14: PORTE I/O SUMMARY

Pin Function TRIS

Setting ANS EL

Setting Pin

Type Buffer

Type Description

RE0/P3A/CCP3/AN5 RE0 00O DIG LATE<0> data output; not affected by analog input.

10I ST PORTE<0> data input; disabled when analog input

enabled.

P3A(1) 00O DIG Enhanced CCP3 PW M output.

CCP3(1) 00

ODIG

Compare 3 output/PWM 3 output.

IST

Capture 3 input.

AN5 11I AN Analog input 5.

RE1/P3B/AN6 RE1 00O DIG LATE<1> data output; not affected by analog input.

10I ST PORTE<1> data input; disabled when analog input

enabled.

P3B 00O DIG E nhanced CCP3 PWM output.

AN6 11I AN Analog input 6.

RE2/CCP5/AN7 RE2 00O DIG LATE<2> data output; not affected by analog input.

10I ST PORTE<2> data input; disabled when analog input

enabled.

CCP5 00O DIG Compare 5 output/PWM 5 output.

10I ST Capture 5 input.

AN7 11I AN Analog input 7.

RE3/VPP/MCLR RE3 — — I ST PORTE<3> data input; enabled when Configuration bit

MCLRE = 0.

VPP — — P AN Programming voltage input; always available

MCLR ——I ST Active-low Master Clear (device Reset) input; enabled

when configuration bit MCLRE = 1.

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS

= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.

Note 1: Alternate pin assignment for P3A/CCP3 when Configuration bit CCP3MX is clear.

TABLE 10-15: REGISTERS ASSOCIATED WITH PORTE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 156

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP 117

LATE(1) — — — — — LATE2 LATE1 LATE0 157

PORTE — — — —RE3

RE2(1) RE1(1) RE0(1) 154

SLRCON — — —SLRE

(1) SLRD(1) SLRC SLRB SLRA 158

TRISE WPUE3 ———— TRISE2(1) TRISE1(1) TRISE0(1) 156

Legend: — = unimp lemented locations , read as ‘0’. Shaded bits are not used for PORTE.

Note 1: Available on PIC18(L)F4XK22 devices.

 2010-2012 Microchip Technology Inc. DS41412F- page 153

PIC18(L)F2X/4XK22

10.7 Port Analog Control

Most port pins are multiplexed with analog functions

such as the Analog-to-Digital Converter and

comparators. When these I/O pins are to be used as

analog in puts it is necess ary to disabl e the digit al inp ut

buffer to avoid excessive current caused by improper

biasing of the digital input. Individual control of the

digital input buffers on pins which share analog

functions is provided by the ANSELA, ANSELB,

ANSELC, ANSELD and ANSELE registers. Setting an

ANSx bit high will disable the associated digital input

buffer and cause all reads of that pin to return ‘0’ whi le

allowing analog functions of that pin to operate

correctly.

The state of the ANSx bits has no affect on digital

output functions. A pin with the associated TRISx bit

clear and ANSx bit set will still operate as a digital

output but the input mode will be analog. This can

cause unexpected behavior when performing read-

modify-write operations on the affected port.

All ANSEL register bits default to ‘1’ upon POR and

BOR, disabling digital inputs for their associated port

pins. All TRIS register bits default to ‘1’ upon POR or

BOR, disabling digital outputs for their associated port

pins. As a result, all port pins that have an ANSEL

10.8 Port Slew Rate Control

The output slew rate of each port is program mable to

select either the standard transition rate or a reduced

transition rate of approximately 0.1 times the standard

to minimize EMI. The reduced transition time is the

default slew rate for all ports.

10.9 Register Defin itions – Port Control

TABLE 10-16: CONFIGURATION REGISTERS ASSOCIATED WITH PORTE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

CONFIG3H MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360

CONFIG4L DEBUG XINST — — — LVP(1) —STRVEN 361

Legend: — = unimp lemented locations , read as ‘0’. Shaded bits are not used for Interrupts.

Note 1: Can only be changed when in high voltage programming mode.

R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x

Rx7 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0 Rx<7:0>: PORTx I/O bit values(2)

Note 1: Register Description for P ORTA, PORTB, PORTC and PORTD.

2: Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O

pin values.

PIC18(L)F2X/4XK22

DS41412F-page 154  2010-2012 Microchip Technology Inc.

U-0 U-0 U-0 U-0 R/W-u/x R/W-u/x R/W-u/x R/W-u/x

— — — —RE3

(1) RE2(2), (3) RE1(2), (3) RE0(2), (3)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4 Unimplemented: Read as ‘0’

bit 3 RE3: PORTE Input bit value(1)

bit 2-0 RE<2:0>: PORTE I/O bit values(2), (3)

Note 1: Port is available as input only when MCLRE = 0.

2: Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O

pin values.

3: Available on PIC18(L)F4XK22 devices.

U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1

—— ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 ANSA5: RA5 Analog Select bit

1 = Digital input buffer disabled

0 = Digital input buffer enabled

bit 4 Unimplemented: Read as ‘0’

bit 3-0 ANSA<3:0>: RA<3:0> Analog Select bit

1 = Digital input buffer disabled

0 = Digital input buffer enabled

 2010-2012 Microchip Technology Inc. DS41412F- page 155

PIC18(L)F2X/4XK22

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

—— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 ANSB<5:0>: RB<5:0> Analog Select bit

1 = Digital input buffer disabled

0 = Digital input buffer enabled

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0

ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 ANSC<7:2>: RC<7:2> Analog Select bit

1 = Digital input buffer disabled

0 = Digital input buffer enabled

bit 1-0 Unimplemented: Read as ‘0’

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ANSD<7:0>: RD<7:0> Analog Select bit

1 = Digital input buffer disabled

0 = Digital input buffer enabled

PIC18(L)F2X/4XK22

DS41412F-page 156  2010-2012 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1

— — — — — ANSE2(1) ANSE1(1) ANSE0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 ANSE<2:0>: RE<2:0> Analog Select bit(1)

1 = Digital input buffer disabled

0 = Digital input buffer enabled

Note 1: Available on PIC18(L)F4XK22 devices only.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISx7 TRISx6 TRISx5 TRISx4 TRISx3 TRISx2 TRISx1 TRISx0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISx<7:0>: PORTx Tri-State Control bit

1 = PORTx pin configured as an input (tri-stated)

0 = PORTx pin configured as an output

Note 1: Register description for TRISA, TRISB, TRISC and TRISD.

R/W-1 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1

WPUE3 — — — —TRISE2

(1) TRISE1(1) TRISE0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WPUE3: Weak Pull-up Register bits

1 = Pull-up enabled on PORT pin

0 = Pull-up disabled on PORT pin

bit 6-3 Unimplemented: Read as ‘0’

bit 2-0 TRISE<7:0>: PORTE Tri-State Control bit(1)

1 = PORTE pin configured as an input (tri-stated)

0 = PORTE pin configured as an output

Note 1: Available on PIC18(L)F4XK22 devices only.

 2010-2012 Microchip Technology Inc. DS41412F- page 157

PIC18(L)F2X/4XK22

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

LATx7 LATx6 LATx5 LATx4 LATx3 LATx2 LATx1 LATx0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 LATx<7:0>: POR T x Out put Latc h bit va lue (2)

Note 1: Register Description for LATA, LATB, LATC and LATD.

2: Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O

pin values.

U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u

— — — — — LATE2 LATE1 LATE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 LATE<2:0>: PORTE Output Latch bit value(2)

Note 1: Available on PIC18(L)F4XK22 devices only.

2: Wr ite s to PORTE are written to correspon din g LATE register. Reads from POR TE reg is ter is return of I/O

pin values.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 WPUB<7:0>: Weak Pull-up Register bits

1 = Pull-up enabled on PORT pin

0 = Pull-up disabled on PORT pin

PIC18(L)F2X/4XK22

DS41412F-page 158  2010-2012 Microchip Technology Inc.

R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0

IOCB7 IOCB6 IOCB5 IOCB4 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 IOCB<7:4>: Interrupt-on-Change PORTB control bits

1 = Interrupt-on-c han ge ena ble d(1)

0 = Interrupt-on-c han ge dis ab led

Note 1: Interrupt-on-change requires that the RBIE bit (INTCON<3>) is set.

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — —SLRE

(1)SLRD(1)SLRC SLRB SLRA

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 SLRE: PORTE Slew Rate Control bit(1)

1 = All outputs on PORTE slew at a limited rate

0 = All outputs on PORTE slew at the standard rate

bit 3 SLRD: PORTD Slew Rate Control bit(1)

1 = All outputs on PORTD slew at a limited rate

0 = All outputs on PORTD slew at the standard rate

bit 2 SLRC: PORTC Slew Rate Control bit

1 = All outputs on PORTC slew at a limited rate

0 = All outputs on PORTC slew at the standard rate

bit 1 SLRB: PORTB Slew Rate Control bit

1 = All outputs on PORTB slew at a limited rate

0 = All outputs on PORTB slew at the standard rate

bit 0 SLRA: PORTA Slew Rate Control bit

1 = All outputs on PORTA slew at a limited rate(2)

0 = All outputs on PORTA slew at the stand ard rate

Note 1: These bits are available on PIC18(L)F4XK22 devices.

2: The slew rate of RA6 defaults to standard rate when the pin is used as CLKOUT.

 2010-2012 Microchip Technology Inc. DS41412F- page 159

PIC18(L)F2X/4XK22

11.0 TIMER0 MODULE

The Timer0 module incorporates the following

features:

• Software selectable operation as a timer or

counter in both 8-bit or 16-bit modes

• Readable and writable registers

• Dedicated 8-bit, software programmable

prescaler

• Selectable clock source (internal or e x ternal)

• Edge select for external clock

• Interrupt-on-overflow

The T0CON register (Register 11-1) controls all

aspects of the module’s operation, including the

prescale selection. It is both readable and writable.

A simplified block diagram of the Timer0 module in 8-bit

mode is shown in Figure 11-1. Figure 11-2 shows a

simplified block diagram of the Timer0 module in 16-bit

mode.

11.1 Register Definitions: Timer0 Control

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TMR0ON T08BIT T0CS T0SE PSA TOPS<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR0ON: Timer0 On/Off Control bit

1 = Enables Timer0

0 = Stops Timer0

bit 6 T08BIT: Timer0 8-bit/16-bit Control bit

1 = Timer0 is configured as an 8-bit timer/counter

0 = Timer0 is configured as a 16-bit timer/counter

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transit ion on T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Timer0 Prescaler Assignment bit

1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.

0 = Timer0 prescaler is assigned. Timer0 clo c k input comes from pre s caler output.

bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits

111 = 1:256 prescale value

110 = 1:128 prescale value

101 = 1:64 prescale value

100 = 1:32 prescale value

011 = 1:16 prescale value

010 = 1:8 prescale value

001 = 1:4 prescale value

000 = 1:2 prescale value

PIC18(L)F2X/4XK22

DS41412F-page 160  2010-2012 Microchip Technology Inc.

11.2 Timer0 Operation

Timer0 can operate as either a timer or a counter; the

mode is selected with the T0CS bit of the T0CON

increments on every clock by default unless a different

prescaler value is selected (see Section 11.4

“Prescaler”). Timer0 incrementing is inhibited for two

instruction cycles following a TMR0 register write. The

user can work around this by adjusting the value written

to the T MR0 reg is ter to co mpensate for the a nti ci p ate d

missi ng inc rem en t s.

The Counter mode is selected by setting the T0CS bit

(= 1). In this mode, Timer0 increments either on every

rising or fal ling edge of pi n RA4/T0CKI . The increme nt-

ing edge is determined by the Timer0 Source Edge

Select bit , T0SE of the T0CON regi ster; clearing th is bit

selects the rising edge. Restrictions on the external

clock input are dis cuss ed below.

An external clock source can be used to drive Timer0;

however, it must meet certain requirements (see

Table 27-12) to ensure that the external clock can be

synchronized with the internal phase clock (TOSC).

There is a delay between synchronization and the

ons et of incrementing the timer/counter.

11.3 Timer0 Reads and Writes in

16-Bit Mode

TMR0H is not the actual high byte of Timer0 in 16-bit

mode; it is actually a buffered version of the real high

byte of Timer0 which is neither directly readable nor

writable (refer to Figure 11-2). TMR0H is updated with

the conte nts of the h igh by te of Timer0 durin g a read of

TMR0L. This provides the ability to read all 16 bits of

Timer0 without the need to verify that the read of the

high and low byte were valid. Invalid reads could

otherwise occur due to a rollover between successive

reads of the high and low byte.

Similarly, a write to the high byte of Timer0 must also

take place through the TMR0H Buffer register. Writing

to TMR0H does not directly affect Timer0. Instead, the

high byte of Timer0 is updated with the contents of

TMR0H when a write occurs to TMR0L. This allow s all

16 bits of Timer0 to be updated at once.

FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

T0CKI pin

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

Clocks TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS<2:0>

Set

TMR0IF

on Overflow

 2010-2012 Microchip Technology Inc. DS41412F- page 161

PIC18(L)F2X/4XK22

FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)

11.4 Prescaler

An 8-bi t counter i s availabl e as a presc aler for the T imer0

module. The prescaler is not directly readable or writable;

its value is set by the PSA and T0PS<2:0> bits of the

T0CON register which determine the prescaler

assi gn me nt and presca le ratio.

Clearing the PSA bit assigns the prescaler to the

Timer0 module. When the prescaler is assigned,

prescale values from 1:2 through 1:256 in integer

power-of-2 increments are selectable.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF TMR0, MOVWF

TMR0, BSF TMR0, etc.) clear the prescaler count.

11.4 .1 SWITCHI NG PRESC ALER

ASSIGNMENT

The prescaler assignment is fully under software

control and can be changed “on-the-fly” during program

execution.

11.5 Ti me r 0 Interr up t

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h in 8-bit mode, or from

FFFFh to 0000h in 16-bit mode. This overflow sets the

TMR0IF flag bit. The inte rrupt can be masked by cle ar-

ing the TMR0IE bit of the INTCON register. Before

re-enabling the interrupt, the TMR0IF bit must be

cleared by software in the Interrupt Service Routine.

Since Timer0 is shut down in Sleep mode, the TMR0

interrupt cannot awaken the processor from Sleep.

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

T0CKI pin

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

Clocks TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS<2:0>

Set

TMR0IF

on Overflow

TMR0

TMR0H

High Byte

Read TMR0L

Write TMR0L

Note: Writing to TMR0 when the prescaler is

assign ed to Tim er0 will clear the presca ler

count but will not change the prescaler

assignment.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on pag e

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP 117

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS<2:0> 159

TMR0H Timer0 Register, High Byte —

TMR0L Timer0 Register, Low Byte —

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 156

Legend: — = unimplemented locations, read as ‘ 0’. Shaded bits are not used by Timer0.

PIC18(L)F2X/4XK22

DS41412F-page 162  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 163

PIC18(L)F2X/4XK22

12.0 TIMER1/3/5 MODULE WITH

GATE CONTROL

The Timer1/3/5 module is a 16-bit timer/counter with

the following features:

• 16-bit timer/counter register pair (TMRxH:TMRxL)

• Programmable internal or external clock source

• 2-bit prescaler

• Dedicated Secondary 32 kHz oscillator circuit

• Op tionally synchronized comparator out

• Multiple Timer1/3/5 gate (count enable) sources

• Inter rupt on ov erflow

• Wake-up on overflow (external c lock,

Asynchronous mode only)

• 16-Bit Read/Write Operation

• Time base for the Capture/Compare function

• Special Event Trigger (with CCP/ECCP)

• Selectable Gate Source Polarity

• Gate Toggle mode

• Gate Singl e-pulse mode

• Gate Value Status

• Gate Event Interrupt

Figure 12-1 is a block diagram of the Timer1/3/5

module.

FIGURE 12-1: TIMER1/3/5 BLOCK DIAGRAM

TMRxH TMRxL

TxSYNC

TxCKPS<1:0>

Prescaler

1, 2, 4, 8

Synchronized

clock input

Set flag bit

TMRxIF on

Overflow TMRx(2),(4)

TMRxON

Note 1: ST Buffer is high speed type when using TxCKI.

2: Timer1/3/5 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

4: See Figure 12-2 for 16-Bit Read/Write Mode Block Diagram.

5: T1CKI is not available when the secondary oscillator is enabled. (SOSCGO = 1 or TXSOSCEN = 1)

6: T3CKI is not available when the secondary oscillator is enabled, unless T3CMX = 1.

7: Synchronized comparator output should not be used in conjunction with synchronized TxCKI.

TxG

FOSC/4

Internal

Clock

SOSCOUT

TxCKI

TMRxCS<1:0>

(5)

Synchronize(3),(7)

det

Sleep input

TMRxGE

TxGPOL

TxGVAL

TxGTM

Single Pulse

Acq. Control

TxGSPM

TxGGO/DONE

TxGSS<1:0>

FOSC

Internal

Clock

Reserved

Q1 RD

TXGCON

Data Bus

det

Interrupt TMRxGIF

Set

TxCLK

FOSC/2

Internal

Clock

TxG_IN

TMRxON

Timer2/4/6 Match

PR2/4/6

sync_C2OUT(7)

sync_C1OUT(7)

To Comparator Module

,(6)

TxSOSCEN

Secondary

Oscillator

Module

See Figure 2-4

TxCLK_EXT_SRC

(1)

PIC18(L)F2X/4XK22

DS41412F-page 164  2010-2012 Microchip Technology Inc.

12.1 Timer1/3/5 Operation

The Timer1/3/5 module is a 16-bit incrementing

counter w hic h is acce ssed th rough th e TMR xH:TMRx L

update the counter.

When us ed with an interna l clock source, t he modul e is

a timer and increments on every instruction cycle.

When used with an external clock source, the module

can be used as either a timer or counter and

increments on every selected edge of the external

source.

Timer1/3/5 is enabled by config uri ng the TMRxON an d

TMRxGE bits in the TxCON and TxGCON registers,

respectively. Table 12-1 display s the T imer1/3/5 en able

selections.

12.2 Clock Source Selection

The TMRxCS<1:0> and TxSOSCEN bits of the TxCON

Timer1/3/5. The dedicated Secondary Oscillator circuit

can be use d as the cloc k source for T imer1 , Timer3 and

Timer5, simultaneously. Any of the TxSOSCEN bits will

enable the Secondary Oscillator circuit and select it as

the clock source for that particular timer. Table 12-2

displays the cloc k source s elections.

12.2.1 INTERNAL CLOCK SOURCE

When the internal clock source is selected the

TMRxH:TMRxL register pair will increment on multiples

of FOSC as determined by the Timer1/3/5 prescaler.

When the FOSC internal clock source is selected, the

Timer1/3/5 register value will increment by four counts

every instruction clock cycle. Due to this condition, a

2 LSB error in resolution will occur when reading the

Timer1/3/5 value. To utilize the full resolution of

Timer1/3/5, an asynchronous input signal must be used

to gate the Timer1/3/5 clock input.

The following async hronous s ources m ay be use d:

• Asynch ronous eve nt on the TxG pin to Timer1/3 /5

Gate

• C1 or C2 comp arator input to Timer1/3/5 Gate

12.2.2 EXTERNAL CLOCK SOURCE

When the external clock source is selected, the

Timer1/3/5 module may work as a timer or a counter.

When enabled to count, Timer1/3/5 is incremented on

the rising edge of the external clock input of the TxCKI

pin. This external clock source can be synchronized to

the microcontroller system clock or it can run

asynchronously.

When used as a timer with a clock oscillator, an

external 32.768 kHz c rys t al can be use d in conjunction

with the d edi cated secondary i nte rnal osc il lator circuit.

TABLE 12-1: TIMER1/3/5 ENABLE

SELECTIONS

TMRxON TMRxGE Timer1/3/5

Operation

00Off

01Off

10Always On

11Count Enab led

Note: In Counter mode, a falling edge must be

registered by the counter prior to the first

inc rement ing ri sing ed ge after any one o r

more of the following conditions:

• Timer1/3 /5 e nabled af ter POR

• Write to TMRxH or TMRxL

• Timer1/3 /5 is disabled

• Timer1/3 /5 is dis abled (TMRxO N = 0)

when TxCKI is high then Timer1/3/5

is enab led (TMRxON=1) whe n TxCKI

is low.

TABLE 12-2: CLOCK SOURCE SELECTIONS

TMRxCS1 TMRxCS0 TxSOSCEN Clock Source

01xSyste m Cloc k (F OSC)

00xInstruction Clock (FOSC/4)

100External C locki ng on TxC KI Pin

101Osc.Circuit On SOSCI/SOSCO Pins

 2010-2012 Microchip Technology Inc. DS41412F- page 165

PIC18(L)F2X/4XK22

12.3 Timer1/3/5 Prescaler

T ime r1/3/5 has four prescaler options allowing 1, 2, 4 or

8 divisions of the clock input. The TxCKPS bits of the

TxCON register control the prescale counter. The

prescale counter is not directly readable or writable;

however , the prescaler counter is cleared upon a write to

TMRxH or TMRxL .

12.4 Secondary Oscillator

A dedicated secondary low-power 32.768 kHz

oscillator circuit is built-in between pins SOSCI (input)

and SOSCO (amplifier ou tput). This internal circ uit is to

be used in conjunction with an external 32.768 kHz

crystal.

The oscillator circuit is enabled by setting the

TxSOSCEN bit of the TxCON register , the SOSCGO bit

of the OSCCON2 register or by selecting the

secondary oscillator as the system clock by setting

SCS<1:0> = 01 in the OSC CON register . Th e oscillator

will continue to run during Sleep.

12.5 Timer1/3/5 Operation in

Asynchronous Counter Mode

If control bit TxSYNC of the TxCON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 12.5.1 “Reading and Wri ting Timer 1/3/5 in

Asynchronous Counter Mode”).

12.5.1 RE ADIN G AND WRITING

TIMER1/3/5 IN ASYNCHRONOUS

COUNTER MODE

Reading TMRxH or TMRxL while the timer is running

from an e xternal asyn chronous cl ock will ens ure a valid

read (taken care of in hardware). However, the user

should keep i n mind that rea ding t he 16-bi t time r in tw o

8-bit values itself, poses certain problems, since the

tim er m ay ov er f l ow be t wee n th e r ea d s. F or wr i t es , i t is

recommended that the user simply stop the timer and

write the desired values. A write contention may occur

by writing to the timer registers, while the register is

incrementing. This may produce an unpredictable

value in the TMRxH:TMRxL register pair.

12.6 Timer1/3/5 16-Bit Read/Write Mode

Timer1/3/5 c an be configured to read and write all 16

bits of data, to and from, the 8-bit TMRxL and TMRxH

registers, simultaneously. The 16-bit read and write

operations are enabled by setting the RD16 bit of the

TxCON register.

To accomplish this function, the TM RxH register value

is ma pped to a buffer register called the TMRxH buffer

not directly readable or writable and all read and write

operations take place through the use of this TMRxH

buffer register.

When a read fro m the TMRxL register is request ed, the

value of the TMRxH register is simultaneously loaded

into the TMRxH buffer register. When a read from the

TMRxH register is requested, the value is provided

from the TMRxH buffer register instead. This provides

the user with the ability to accurately read all 16 bits of

the Timer1/3/5 value from a single instance in time.

In contrast, when not in 16-Bit mode, the user must

read each register separately and determine if the

values have become invalid due to a rollover that may

have occurred between the read operations.

When a write request of the TMRxL register is

requeste d, the TMR xH buffer r egister is s imultan eously

updated with the contents of the TMRxH register. The

value of TMRxH must be preloaded into the TMRxH

buffer register prior to the write request for the TMRxL

all 16 bits to the TMRxL:TMRxH register pair at the

same time.

Any requests to write to the TMRxH directly does not

clear the Timer1/3/5 prescaler value. The prescaler

value is only cleared through write requests to the

TMRxL register.

Note: The oscillator requires a start-up and

stabilization time before use. Thus,

TxSOSCEN should be set and a suitable

delay observed prior to enabling

Timer1/3/5.

Note: When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

PIC18(L)F2X/4XK22

DS41412F-page 166  2010-2012 Microchip Technology Inc.

FIGURE 12-2: TIMER1/3/5 16-BIT

READ/WRITE MODE

BLOCK DIAGRAM

12.7 Timer1/3/5 Gate

Timer1/3/5 can be configured to count freely or the

count can be enabled and disabled using Timer1/3/5

Gate circuitry. This is also referred to as Timer1/3/5

Gate Enable.

Timer1/3/5 Gate can also be driven by multiple

selectable sources.

12.7.1 TIMER1/3/5 GATE ENABLE

The Timer1/3/5 Gate Enable mode is enabled by

setting the TMRxGE bit of the TxGCON register. The

polarity of the Timer1/3/5 Gate Enable mode is

configured using the TxGPOL bit of the TxGCON

When Timer1/3/5 Gate Enable mode is enabled,

Timer1/3/5 will increment on the rising edge of the

Timer1/3/5 clock source. When Timer1/3/5 Gate

Enable mode is disabled, no incrementing will occur

and Timer1/3/5 will hold the current count. See

Figure 12-4 for timing details.

12.7.2 TIMER1/3/5 GATE SOURCE

SELECTION

The Timer1/3 / 5 Gat e so urc e ca n be se le ct ed f r om one

of four different sources. Source selection is controlled

by the TxGSS bit s of the T xGCON regis ter . The p olarity

for each available source is also selectable. Polarity

selection is controlled by the TxGPOL bit of the

TxGCON register.

The Gate resource, Timer2 Match to PR2, changes

between Timer2, Timer4 and Timer6 depending on

which of the three 16-bit Timers, Timer1, Timer3 or

T imer 5, is sele cted. See Table 12-5 to determi ne whic h

Timer2/4/6 Match to PR2/4/6 combination is available

for the 16-bit timer being used.

12.7.2.1 TxG Pin Gate Operation

The TxG pin is one sou rce for T im er1/3/5 G ate Co ntrol.

It can be used to supply an external source to the

Timer1/3/5 Gate circuitry.

12.7.2.2 Timer2/4/6 Match Gate Operation

The TMR2/4/6 register will increment until it matches

the value in the PR2/4/6 register. On the very next

incr ement cycle, TMR2/ 4/6 w ill be r eset to 00h. When

this Rese t occurs, a low-to-h igh pulse wil l automaticall y

be generated and internally supplied to the Timer1/3/5

Gate circuitry. See Section 12.7.2 “Timer1/3/5 Gate

Source Selection” for more information.

TABLE 12-3: TIMER1/3/5 GATE ENABLE

SELECTIONS

TxCLK TxGPOL TxG Timer1/3/5

Operation

00Counts

01Holds Count

10Holds Count

11Counts

TMR1L

Internal Data Bus

Set

TMR1IF

on Overflow

TMR1

TMR1H

High Byte

Read TMR1L

Write TMR1L

From

Timer1

Circuitry

Block Diagr am of Timer1 Example of TIM ER 1/3/ 5

TABLE 12-4: TIMER1/3/5 GATE SOURCES

TxGSS Timer1/3/5 Gate Source

00 Ti mer1/3/5 Gate Pin

01 Timer2/4/6 Match to PR2/4/6

(TMR2/4/6 increments to match PR2/4/6)

10 Comparator 1 Output sync_C1OUT

(optionally Timer1/3/5 synchronized out-

put)

11 Comparator 2 Output sync_C2OUT

(optionally Timer1/3/5 synchronized out-

put)

TABLE 12-5: GATE RESOURCES FOR

TIMER2/4/6 MATCH TO

PR2/4/6

Timer1/3/5 Resource Timer1/3/5 Gate Match

Selection

Timer1 TMR2 Match to PR2

Timer3 TMR4 Match to PR4

Timer5 TMR6 Match to PR6

 2010-2012 Microchip Technology Inc. DS41412F- page 167

PIC18(L)F2X/4XK22

12.7.2.3 Comparator C1 Gate Operation

The output resulting from a Comp arator 1 operation can

be selected as a source for Timer1/3/5 Gate Control.

The Comparator 1 output (sync_C1OUT) can be

synchronized to the Timer1/3/5 clock or left

asynchronous. For more information see Section 18.8.4

“Synchronizing Comp arator Output to Timer1”.

12.7.2.4 Comparator C2 Gate Operation

The output resulting from a Comparator 2 operation

can be selected as a source for Timer1/3/5 Gate

Control. The Comparator 2 output (sync_C2OUT) can

be synchronized to the Timer1/3/5 clock or left

asynchronous. For more information see

Section 18.8.4 “Synchronizing Comparator Output

to Timer1”.

12.7.3 TIMER1/3/5 GATE TOGGLE MODE

When Timer1/3/5 Gate Toggle mode is enabled, it is

possible to measure the full-cycle length of a

T i mer1/3 /5 gate sig nal, as op posed to the duratio n of a

single level pulse.

The Timer1/3/5 Gate source is routed through a

flip-flop that change s state on every inc rementin g edge

of the signal. See Figure 12-5 for timing details.

T ime r1/3/5 Gate Toggle mode is enabled by settin g the

TxGTM bit of the TxGCON register. When the TxGTM

bit is c leared, the fl ip-flop is c leared and held c lear . Thi s

is necessary in order to control which edge is

measured.

12.7.4 TIMER1/3/5 GATE SINGLE-PULSE

MODE

When Timer1/3/5 Gate Single-Pulse mode is enabled,

it is possible to capture a single-pulse gate event.

Timer1/3/5 Gate Single-Pulse mode is first enabled by

setting the TxGSPM bit in the TxGCON register. Next,

the TxGGO/DONE bit in the TxGCON regi ste r m us t b e

set. The Timer1/3/5 will be fully enabled on the next

incrementing edge. On the next trailing edge of the

pulse, the TxGGO/DONE bit will automatically be

cleared. No other gate events will be allowed to

increment Timer1/3/5 until the TxGGO/DONE bit is

once again set in software.

Clearing the TxGSPM bit of the TxGCON register will

also clear the TxGGO/DONE bit. See Figure 12-6 for

timing details.

Enabling the Toggle mode and the Single-Pulse mode

simultaneously will permit both sections to work

toget her. This allows the cy cl e tim es on the Timer1/3/5

Gate source to be measured. See Figure 12-7 for

timing details.

12.7.5 TIMER1/3/5 GATE VALUE STATUS

When Timer1/3/5 Gate Value Status is utilized, it is

possible to read the most current level of the gate

control value. The value is stored in the TxGVAL bit in

the TxGCON register. The TxGVAL bit is valid even

when the Timer1/3/5 G ate is not enab led (TMRx GE bit

is cl eare d).

12.7.6 TIMER1/3/5 GATE EVENT

INTERRUPT

When Timer1/3/5 Gate Event Interrupt is enabled, it is

possible to generate an interrupt upon the completion

of a gate event. When the falling edge of TxGVAL

occurs, the TMRxGIF flag bit in the PIR3 register will be

set. If the TMRxGIE bit in the PIE3 register is set, then

an interrupt will be recognized.

The TMRxGIF flag bit operates even when the

Timer1/3/5 Gate is not enabled (TMRxGE bit is

cleared).

For more information on selecting high or low priority

status for the Timer1/3/5 Gate Event Interrupt see

Section 9.0 “Interrupts”.

Note: Enabling Toggle mode at the same time

as chan ging the gate po larity may res ult in

indeterm in ate ope rati on.

PIC18(L)F2X/4XK22

DS41412F-page 168  2010-2012 Microchip Technology Inc.

12.8 Timer1/3/5 Interrupt

The Timer1/3/5 register pair (TMRxH:TMRxL)

increments to FFFFh and rolls over to 0000h. When

T imer1/3 /5 rolls ove r , the T imer1 /3/5 interrupt fla g bit of

the PIR1/2/5 register is set. To enable the interrupt on

rollover, you must set these bits:

• TMRxON bit of the TxCON register

• TMRxIE bits of the PIE1, PIE2 or PIE5 registers

• PEIE/GIEL bit of the INTCON register

• GIE/GIEH bit of the INTCON register

The interrupt is cleared by clearing the TMRxIF bit in

the Interrupt Service Routine.

For more information on selecting high or low priority

status for the Timer1/3/5 Overflow Interrupt, see

Section 9.0 “Interrupts”.

12.9 Timer1/3/5 Operation During Sleep

Timer1/3/5 can only operate during Sleep when set up

in Asynchronous Counter mode. In this mode, an

external crystal or clock source can be used to

increment the counter. To set up the timer to wake the

device:

• TMRxON bit of the TxCON regi ster must be set

• TMRxIE bit of the PIE1/2/5 register must be set

• PEIE/GI EL bi t of the INTCON registe r mu st b e s et

• TxSYNC bit of the TxCON register must be set

• TMRxCS bits of the TxCON register must be

configured

• TxSOSCEN bit of the TxCON register must be

configured

The device will wake-up on an overflow and execute

the next i ns truc tio n. If the GIE/GIEH b it of the IN T CON

Routine.

The secondary oscillator will continue to operate in

Sleep regardless of the TxSYNC bit setting.

12.10 ECCP/CCP Capture/Compare Time

Base

The CCP m odules use th e TMRxH:TMR xL register p air

as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMRxH:TMRxL

In Compare mo de, an event is triggered wh en the value

CCPRxH:CCPRxL register pair matches the value in

the TMRxH:TMRxL register pair. This event can be a

Special Event Trigger.

For more information, see Section 14.0

“Capture/Compare/PWM Modules”.

12.11 ECCP/CCP Special Event Trigger

When any of the CCP’s are configured to trigger a

special event, the trigger will clear the TMRxH:TMRxL

Timer1/3/5 interrupt. The CCP module may still be

configured to generate a CCP interrupt.

In this mode of operation, the CCPRxH:CCPRxL

Timer1/3/5.

T i mer1/3/ 5 shoul d be sync hroni zed and FOSC/4 shoul d

be selected as the clock source in order to utilize the

Special Event Trigger. Asynchronous operation of

Timer1/3/5 can cause a Special Event Trigger to be

missed.

In the ev ent that a writ e to TMRxH or TMRx L coinci des

with a Special Event T rigger from the CCP, the write will

take precedence.

For more information, see Section 17.2.8 “Special

Event Trigger”.

Note: The TMRxH:TMRxL register pair and the

TMRxIF bit should be cleared before

enabling interrupts.

 2010-2012 Microchip Technology Inc. DS41412F- page 169

PIC18(L)F2X/4XK22

FIGURE 12-3: TIMER1/3/5 INCREMENTING EDGE

FIGURE 12-4: TIMER1/3/5 GATE ENABLE MODE

TXCKI = 1

when TMRx

Enabled

TXCKI = 0

when TMRX

Enabled

Note 1: Arrows indica te counter incremen ts.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

TMRxGE

TxGPOL

TxG_IN

TxCKI

TxGVAL

Timer1/3/5 N N + 1 N + 2 N + 3 N + 4

PIC18(L)F2X/4XK22

DS41412F-page 170  2010-2012 Microchip Technology Inc.

FIGURE 12-5: TIMER1/3/5 GATE TOGGLE MODE

FIGURE 12-6: TIMER1/3/5 GATE SINGLE-PULSE MODE

TMRxGE

TxGPOL

TxGTM

TxTxG_IN

TxCKI

TxGVAL

TIMER1/3/5 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8

TMRxGE

TxGPOL

TxG_IN

TxCKI

TxGVAL

TIMER1/3/5 N N + 1 N + 2

TxGSPM

TxGGO/

DONE Set by software Cleared by hard ware on

falling edge of TxGVAL

Set by hardware on

falling edge of TxGVAL

Cleared by software Cleared by

software

TMRxGIF

Counting enabled on

rising edge of TxG

 2010-2012 Microchip Technology Inc. DS41412F- page 171

PIC18(L)F2X/4XK22

FIGURE 12-7: TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

12.12 Peripheral Module Disable

When a peripheral module is not used or inactive, the

module can be disabled by setting the Module Disable

bit in the PMD registers. This will reduce power con-

sumption to an absolute minimum. Setting the PMD

bits holds the module in Reset and disconnects the

module’s clock source. The Module Disable bits for

Timer1 (TMR1MD), Timer3 (TMR3MD) and Timer5

(TMR5M D) are in the PM D0 Registe r . See Section 3.0

“Power-M ana ged Modes” for more information.

TMRxGE

TxGPOL

TxG_IN

TxCKI

TxGVAL

TIMER1/3/5 NN + 1

N + 2

TxGSPM

TxGGO/

DONE Set by software Cleared by hardware on

falling edge of TxGVAL

Set by hardware on

falling edge of TxGVAL

Cleared by sof tware Cleared b y

software

TMRxGIF

TxGTM

Counting enabled on

rising edge of TxG

N + 4

N + 3

PIC18(L)F2X/4XK22

DS41412F-page 172  2010-2012 Microchip Technology Inc.

12.13 Register Definitions: Timer1/3/5 Control

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/0 R/W-0/u

TMRxCS<1:0> TxCKPS<1:0> TxSOSCEN TxSYNC TxRD16 TMRxON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 TMRxCS<1:0>: Ti mer1/3/5 Clock Source Select bits

11 =Reserved. Do not use.

10 =Timer1/3/5 clock source is pin or oscillator:

If TxSOSCEN = 0:

External clock from TxCKI pin (on the rising edge)

If TxSOSCEN = 1:

Crystal oscillator on SOSCI/SOSCO pins

01 =Timer1/3/5 clock source is system clock (FOSC)

00 =Timer1/3/5 clock source is instruction clock (FOSC/4)

bit 5-4 TxCKPS<1:0>: Timer1/3/5 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 TxSOSCEN: Secondary Oscillator Enable Control bit

1 = Dedicated Secondary oscillator circuit enabled

0 = Dedicated Secondary oscillator circuit disabled

bit 2 TxSYNC: Timer1/3/5 External Clock Input Synchronization Control bit

TMRxCS<1:0> = 1X

1 = Do not synchronize external clock input

0 = Synchronize external clock input with system clock (FOSC)

TMRxCS<1:0> = 0X

This bit is ignored. Timer1/3/5 uses the internal clock when TMRxCS<1:0> = 1X.

bit 1 TxRD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer1/3/5 in one 16-bit operation

0 = Enables register read/write of Timer1/3/5 in two 8-bit operation

bit 0 TMRxON: Timer1/3/5 On bit

1 = Enables Timer1/3/5

0 = Stops T im er1/ 3/5

Clears Timer1/3/5 Gate flip-flop

 2010-2012 Microchip Technology Inc. DS41412F- page 173

PIC18(L)F2X/4XK22

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u

TMRxGE TxGPOL TxGTM TxGSPM TxGGO/DONE TxGVAL TxGSS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7 TMRxGE: Timer1/3 /5 Gate Enabl e bit

If TMRx ON = 0:

This bit is ignored

If TMRx ON = 1:

1 = Timer1/3/5 counting is controlled by the Timer1/3/5 gate function

0 = Timer1/3/5 counts rega rdless of Timer1/3/5 gate function

bit 6 TxGPOL: Timer1/3/5 Gate Polarity bit

1 = Timer1/3/5 gate is active-high (Timer1/3/5 counts when gate is high)

0 = Timer1/3/5 gate is active-low (Timer1/3/5 counts when gate is low)

bit 5 TxGTM: Timer1/3/5 Gate Toggle Mode bit

1 = Timer1/3/5 Gate Toggle mode is enabled

0 = Timer1/3/5 Gate Toggle mode is disabled and toggle flip-flop is cleared

Timer1/3/5 gate flip-flop toggles on every rising edge.

bit 4 TxGSPM: Timer1/3/5 Gate Single-Pulse Mode bit

1 = T i me r1/3 /5 gate Single -Pul se mode is enable d and is co ntrol li ng Timer1/3/5 gate

0 = Timer1/3/5 gate Single-Pulse mode is disabled

bit 3 TxGGO/DONE: Timer1/3/5 Gate Single-Pulse A cquisition Status bit

1 = Timer1/3/5 gate single-pulse acquisition is ready, waiting for an edge

0 = Timer1/3/5 gate single-pulse acquisition has completed or has not been started

This bit is automatically cleared when TxGSPM is cleared.

bit 2 TxGVAL: Timer1/3/5 Gate Current State bit

Indicates the current state of the Timer1/3/5 gate that could be provided to TMRxH:TMRxL.

Unaffected by Timer1/3/5 Gate Enable (TMRxGE).

bit 1-0 TxGSS<1:0>: Timer1/3/5 Gate Source Select bits

00 = Timer1/3/ 5 Gate pin

01 = Timer2/4/6 Match PR 2/4/6 output (See Table 12-6 for proper timer match selection)

10 = Comparator 1 optionally synchronized output (sync_C1OUT)

11 = Comparator 2 optionally synchronized output (sync_C2OUT)

PIC18(L)F2X/4XK22

DS41412F-page 174  2010-2012 Microchip Technology Inc.

TABLE 12-6: REGISTERS ASSOCIATED WITH TIMER1/3/5 AS A TIMER/COUNTER

TABLE 12-7: CONFIGURATION REGISTERS ASSOCIATED WITH TIMER1/3/5

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

V al ues on

Page

ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 155

ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 155

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129

IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130

IPR5 — — — — — TMR6IP TMR5IP TMR4IP 131

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125

PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126

PIE5 — — — — — TMR6IE TMR5IE TMR4IE 127

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

PIR5 — — — — — TMR6IF TMR5IF TMR4IF 123

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSCEN T1SYNC T1RD16 TMR1ON 172

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 173

T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 172

T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 173

T5CON TMR5CS<1:0> T5CKPS<1:0> T5SOSCEN T5SYNC T5RD16 TMR5ON 172

T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL T5GSS<1:0> 173

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register —

TMR1L Least Significant Byte of the 16-bit TMR1 Register —

TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register —

TMR3L Least Significant Byte of the 16-bit TMR3 Register —

TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register —

TMR5L Least Significant Byte of the 16-bit TMR5 Register —

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 156

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on Page

CONFIG3H MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360

 2010-2012 Microchip Technology Inc. DS41412F- page 175

PIC18(L)F2X/4XK22

13.0 TIMER2/4/6 MODULE

There are three identical 8-bit Timer2-type modules

available. To maintain pre-existing naming conventions,

the Timers are called Timer2, Timer4 and Timer6 (also

Timer2/4/6).

The Timer2/4/6 module incorporates the following

features:

• 8-bit Timer and Period registers (TMRx and PRx,

respectively)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMRx match with PRx, respectively

• Optional use as the shift clock for the MSSPx

modules (Timer2 only)

See Figure 13-1 for a block diagram of Timer2/4/6.

FIGURE 13-1: TIMER2/4/6 BLOCK DIAGRAM

Note: The ‘x’ variable used in this section is

used to designate Timer2, Timer4, or

Timer6. For example, TxCON references

T2CON, T4CON, or T6CON. PRx refer-

ences PR2, PR4, or PR6.

Comparator

TMRx Sets Flag

TMRx

Output

Reset

Postscaler

Prescaler

PRx

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

bit T MR xIF

TxOUTPS<3:0>

TxCKPS<1:0>

PIC18(L)F2X/4XK22

DS41412F-page 176  2010-2012 Microchip Technology Inc.

13.1 Timer2/4/6 Operation

The cloc k input to the T i mer2/4 /6 modul e is the sys tem

instr uction cloc k (FOSC/4).

TMRx increments from 00h on each clock edge.

A 4-bit counter/prescale r on the clock input al lows direct

input, divide-by-4 and divide-by-16 prescale options.

These options are selected by the prescaler control bits,

TxCKPS<1:0> of the TxCON register. The value of

TMRx is comp ared to that of the Period regis ter , PRx, on

each clock cycle. When the two values match, the

comparator generates a match signal as the timer

output. This signa l als o rese t s the valu e of TMRx to 00h

on the next cycle and drives the output

counter/postscaler (see Section 13.2 “Timer2/4/6

Interrupt”).

The TMR x and PRx regi sters are b oth directly readable

and writable. The TMRx register is cleared on any

device Reset, whereas the PRx register initializes to

FFh. Both the prescaler and postscaler counters are

cleared on the following events:

• a write to the TMRx register

• a write to the TxCON register

• Power-on Reset (PO R)

• Brown-out Reset (BOR)

•MCLR

Reset

• Watchdog Ti mer (WDT) Reset

• Stack O v erflow R eset

• Stack Un derflow Reset

•RESET Inst ruction

13.2 Timer2/4/6 Interrupt

Timer2/4/6 can also generate an optional device

interrupt. The Timer2/4/6 output signal (TMRx-to-PRx

match) provides the input for the 4-bit

counter/postscaler. This counter generates the TMRx

match interrupt flag which is latched in TMRxIF of the

PIR1/PIR5 registers. The interrupt is enabled by setting

the TMRx Match Interrupt Enable bit, TMRxIE of the

PIE1/PIE5 registers. Interrupt Priority is selected with

the TMRxIP bit in the IPR1/IPR5 registers.

A rang e o f 16 po stscale optio ns (from 1 :1 through 1:16

inclusive) can be selected with the postscaler control

bits, TxOUTPS<3:0>, of the TxCON register.

13.3 Timer2/4/6 Output

The unscaled output of TMRx is available primarily to

the CCP modules, where it is used as a time base for

operations in PWM mode. The timer to be used with a

specific CCP module is selected using the

CxTSEL<1:0> bits in the CCPTMRS0 and CCPTMRS1

registers.

T i mer2 ca n be op tiona lly us ed as th e shif t cl ock so urce

for the MSSPx modules operating in SPI mode by

setting SSPM<3 :0> = 0011 in the SSPxCON1 regi ster .

Additional information is provided in Section 15.0

“Master Synchronous Serial Port (MSSP1 and

MSSP2) Module”.

13.4 Timer2/4/6 Operation During Sleep

The Timer2/4/6 timers cannot be operated while the

proce ssor i s in Sleep mo de. The contents of th e TM Rx

and PRx registers will remain unchanged while the

proce ssor is in Slee p mod e.

13.5 Peripheral Module Disable

When a peripheral module is not used or inactive, the

module can be disabled by setting the Module Disable

bit in the PMD registers. This will reduce power con-

sumption to an absolute minimum. Setting the PMD

bits holds the module in Reset and disconnects the

module’s clock source. The Module Disable bits for

Timer2 (TMR2MD), Timer4 (TMR4MD) and Timer6

(TMR6MD ) are in the PMD0 Register. See Section 3.0

“Power-M ana ged Modes” for more information.

Note: TMRx is not cleared when TxCON is

written.

 2010-2012 Microchip Technology Inc. DS41412F- page 177

PIC18(L)F2X/4XK22

13.6 Register Definitions: Timer2/4/6 Control

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TxOUTPS<3:0> TMRxON TxCKPS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-3 TxOUTPS<3:0>: TimerX Output Postscaler Select bits

0000 = 1:1 Postscaler

0001 = 1:2 Postscaler

0010 = 1:3 Postscaler

0011 = 1:4 Postscaler

0100 = 1:5 Postscaler

0101 = 1:6 Postscaler

0110 = 1:7 Postscaler

0111 = 1:8 Postscaler

1000 = 1:9 Postscaler

1001 = 1:10 Postscaler

1010 = 1:11 Postscaler

1011 = 1:12 Postscaler

1100 = 1:13 Postscaler

1101 = 1:14 Postscaler

1110 = 1:15 Postscaler

1111 = 1:16 Postscaler

bit 2 TMRxON: TimerX On bit

1 = TimerX is on

0 = TimerX is off

bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

PIC18(L)F2X/4XK22

DS41412F-page 178  2010-2012 Microchip Technology Inc.

TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CCPTMRS0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> 208

CCPTMRS1 — — — — C5TSEL<1:0> C4TSEL<1:0> 208

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR5 — — — — —TMR6IPTMR5IP TMR4IP 131

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE5 — — — — —TMR6IETMR5IE TMR4IE 127

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR5 — — — — —TMR6IFTMR5IF TMR4IF 123

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

PR2 Timer2 Peri od Register —

PR4 Timer4 Peri od Register —

PR6 Timer6 Peri od Register —

T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 172

T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> 172

T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> 172

TMR2 Timer2 Register —

TMR4 Timer4 Register —

TMR6 Timer6 Register —

Legend: — = unimplemented locations, read as ‘0’. S haded bits are not used by Timer2/4/6.

 2010-2012 Microchip Technology Inc. DS41412F- page 179

PIC18(L)F2X/4XK22

14.0 CAPTURE/COMPARE/PWM

MODULES

The Capture/Compare/PWM module is a peripheral

which allows the user to time and control different

events, and to generate Pulse-Width Modulation

(PWM) signa ls. In Capture mo de, the periphera l allows

the timing of the duration of an event. The Compare

mode a llows t he us er to tri gger a n exte rnal even t whe n

a predetermined amount of time has expired. The

PWM mode can generate Pulse-Width Modulated

signals of varying frequency and duty cycle.

This family of devices contains three Enhanced

Capture/Compare/PWM modules (ECCP1, ECCP2,

and ECCP3) and two standard Capture/Compare/PWM

modules (CCP4 and CCP5).

The Capture and Compare functions are identical f or all

CCP/ECCP modules. The difference between CCP

and ECCP modules are in the Pulse-Width Modulation

(PWM) function. In CCP modules, the standard PWM

function is identical. In ECCP modules, the Enhanced

PWM function has either full-bridge or half-bridge PWM

output. Full-bridge ECCP modules have four available

I/O pins while half-bridge ECCP mo dules only h ave two

available I/O pins. ECCP PWM modules are backward

compatible with CCP PWM modules and can be

configu red as st a ndard PWM m odules . See Table 14-1

to determine the CCP/ECCP functionality available on

each device in this family.

Note 1: In devices with more than one CCP

module, it is very important to pay close

attention to the register names used. A

number pl aced af ter the module acronym

is used to distinguish between separate

modules. For example, the CCP1CON

and CCP2CON control the same

operational aspects of two completely

different CCP modules.

2: Throughout this section, generic

references to a CCP module in any of its

operating modes may be interpreted as

being equally applicable to ECCP1,

ECCP2, ECCP3, CCP4 and CCP5.

and bit names may use the generic

designator ‘x’ to indicate the use of a

numeral to distinguish a particular module,

when required.

TABLE 14-1: PWM RESOURCES

Device Name ECCP1 ECCP2 ECCP3 CCP4 CCP5

PIC18(L)F23K22

PIC18(L)F24K22

PIC18(L)F25K22

PIC18(L)F26K22

Enhanced PWM

Full-Bridge Enha nc ed PWM

Half-Bridge Enhanced PWM

Half-Bridge Standard PWM Standard PWM

(Special Event Trigger)

PIC18(L)F43K22

PIC18(L)F44K22

PIC18(L)F45K22

PIC18(L)F46K22

Enhanced PWM

Full-Bridge Enha nc ed PWM

Full-Bridge Enhanced PWM

Half-Bridge Standard PWM Standard PWM

(Special Event Trigger)

PIC18(L)F2X/4XK22

DS41412F-page 180  2010-2012 Microchip Technology Inc.

14.1 Capture Mode

The Captu re mo de function described in this sect ion is

identical for all CCP and ECCP modules available on

this device family.

Capture mode makes use of the 16-bit Timer

resources, Timer1, Timer3 and Timer5. The timer

resources for each CCP capture function are

independent and are selected using the CCPTMRS0

and CCPTMRS1 registers. When an event occurs on

the CCPx pin, the 16-bit CCPRxH:CCPRxL register

pair captures and stores the 16-bit value of the

TMRxH:TMRxL register pair, respectively. An event is

defined as one o f the followi ng and is c onfigured b y the

CCPxM<3:0> bits of the CCPxCON register:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

When a capture is made, the corresponding Interrupt

Request Flag bit CCPxIF of the PIR1, PIR2 or PIR4

software. If another capture occurs before the value in

the CCPRxH:CCPRxL register pair is read, the old

captured value is overwritten by the new captured

value.

Figure 14-1 shows a simplified diagram of the Capture

operation.

FIGURE 14-1: CAPTURE MODE

OPERATION BLOCK

DIAGRAM

14.1.1 CCP PIN CONFIGURATION

In Capture mode, the CCPx pin should be configured

as an input by setting the associated TRIS control bit.

Some CCPx outputs are multiplexed on a couple of

pins. Table 14-2 shows the CCP output pin

multiplexing. Selection of the output pin is determined

by the CCPxMX bits in Configuration register 3H

(CONFIG3H). Refer to Register 24-4 for more details.

14.1.2 TIMER1 MODE RESOURCE

The 16-bit Timer resource must be running in Timer

mode or Synchronized Counter mode for the CCP

module to use the capture feature. In Asynchronous

Counter mode, the capture operation m ay not work.

See Section 12.0 “Timer1/3/5 Module with Gate

Control” for more information on configuring the 16-bit

Timers.

14.1.3 SOFTWARE INTERRUPT MODE

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit of the PIE1, PIE2 or PIE4

user should clear the CCPxIF interrupt flag bit of the

PIR1, PIR2 or PIR4 register following any change in

Operating mode.

Note: If the CCPx p in is c onfigured as an o utput,

a write to the port can cause a capture

condition.

CCPRxH CCPRxL

TMR1/3/5H TMR1/3/5L

Set Flag bit CCPx IF

(PIR1/2/4 register)

Capture

Enable

CCPxM<3:0>

Prescaler

 1, 4, 16

and

Edge Detect

CCPx

System Clock (FOSC)

TABLE 14-2: CCP PIN MULTIPLEXING

CCP OUTPUT CONFIG 3H Control Bit Bit Value PIC18(L)F2XK22 I/O pin PIC18(L)F4XK22 I/O pin

CCP2 CCP2MX 0RB3 RB3

1(*) RC1 RC1

CCP3 CCP3MX 0(*) RC6 RE0

1RB5 RB5

Legend: * = Default

Note: Clocking the 16-bit Timer resource from

the system clock (FOSC) should not be

used in Capture mode. In order for

Capture mode to recognize the trigger

event on the CCPx pin, the T imer resource

must be clocked from the instruction clock

(FOSC/4 ) or fro m an ext ernal clo ck sour ce .

 2010-2012 Microchip Technology Inc. DS41412F- page 181

PIC18(L)F2X/4XK22

14.1.4 CCP PRESCALER

There are four prescaler settings specified by the

CCPxM< 3:0> bits of the C CPxCON regis ter . When ever

the C CP module is tu rned of f, o r the C CP mo dule is not

in Captu re mode, the presca ler coun ter is clea red. Any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another does

not clear the prescaler and may generate a false

interrupt. To avoid this unexpected operation, turn the

module off by clearing the CCPxCON register before

changing the prescaler. Example 14-1 demonstrates

the code to perform this function.

EXAMPLE 14-1: CHANGING BETWEE N

CAPTURE PRESCALERS

14.1.5 CAPTURE DURING SLEEP

Capture mode r equires a 16-bi t Time rX modul e fo r use

as a time base. There are four options for driving the

16-bit TimerX module in Capture mode. It can be driven

by the sy stem clock (FOSC), the instruction clock (FOSC/

4), or by the external clock sources, the Secondary

Oscillator (SOSC), or the TxCKI clock input. When the

16-bit TimerX resource is clocked by FOSC or FOSC/4,

TimerX will not increment during Sleep. When the

device wakes from Sle ep, TimerX will co ntinue from it s

previ ous state. Capture m ode will operate durin g Sleep

when the 16-bit TimerX resource is clocked by one of

the external clock sources (SOSC or the TxCKI pin).

#define NEW_CAPT_PS 0x06 //Capture

// Prescale 4th

... // rising edg e

CCPxCON = 0; // Turn th e CCP

// Module Off

CCPxCON = NEW_CAPT_PS; // Turn CCP module

// on with new

// prescale valu e

TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 205

CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 205

CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 205

CCP4CON — — DC4B<1:0> CCP4M<3:0> 205

CCP5CON — — DC5B<1:0> CCP5M<3:0> 205

CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) —

CCPR1L Capture/Comp are/PWM Register 1 Low Byte (LSB) —

CCPR2H Capture/Compare/PWM Register 2 High Byte (MSB) —

CCPR2L Capture/Comp are/PWM Register 2 Low Byte (LSB) —

CCPR3H Capture/Compare/PWM Register 3 High Byte (MSB) —

CCPR3L Capture/Comp are/PWM Register 3 Low Byte (LSB) —

CCPR4H Capture/Compare/PWM Register 4 High Byte (MSB) —

CCPR4L Capture/Comp are/PWM Register 4 Low Byte (LSB) —

CCPR5H Capture/Compare/PWM Register 5 High Byte (MSB) —

CCPR5L Capture/Comp are/PWM Register 5 Low Byte (LSB) —

CCPTMRS0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> 208

CCPTMRS1 — — — — C5TSEL<1:0> C4TSEL<1:0> 208

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129

IPR4 — — — — —CCP5IPCCP4IP CCP3IP 131

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not use d by Capture mode.

Note 1: These registers/ bits are available on PIC18(L)F4XK22 de vices.

PIC18(L)F2X/4XK22

DS41412F-page 182  2010-2012 Microchip Technology Inc.

PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125

PIE4 — — — — — CCP5IE CCP4IE CCP3IE 127

PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120

PIR4 — — — — — CCP5IF CCP4IF CCP3IF 122

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

PMD1 MSSP2MD MSSP1MD —CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 56

T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSCEN T1SYNC T1RD16 TMR1ON 172

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 173

T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 172

T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 173

T5CON TMR5CS<1:0> T5CKPS<1:0> T5SOSCEN T5SYNC T5RD16 TMR5ON 172

T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL T5GSS<1:0> 173

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register —

TMR1L Least Significant Byte of the 16-bit TMR1 Register —

TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register —

TMR3L Least Significant Byte of the 16-bit TMR3 Register —

TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register —

TMR5L Least Significant Byte of the 16-bit TMR5 Register —

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 156

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 156

TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 156

TRISE WPUE3 — — — —TRISE2

(1) TRISE1(1) TRISE0(1) 156

TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE (CONTINUED)

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.

Note 1: These regis ters/bits are available on PIC18( L)F4XK22 devices.

TABLE 14-4: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE

Name Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Regi ster

on Page

CONFIG3H MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360

Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.

 2010-2012 Microchip Technology Inc. DS41412F- page 183

PIC18(L)F2X/4XK22

14.2 Compare Mode

The Compare mode function described in this section

is identi cal for all CCP and ECC P modules ava ilable on

this device family.

Compare mode makes use of the 16-bit TimerX

resources, Timer1, Timer3 and Timer5. The 16-bit

value of the CCPRxH:CCPRxL register pair is

constantly compared against the 16-bit value of the

TMRxH:TMRxL register pair. When a match occurs,

one of the following events can occur:

• Toggle the CCPx ou tput

• Set the CCPx output

• Clear the CCPx output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCPxM<3:0> control bits of the CCPxCON register. At

the same ti me, the interrupt flag CCPxIF bit is set.

All Compare modes can generate an interrupt.

Figure 14-2 shows a simplified diagram of the

Compare operation.

FIGUR E 1 4-2: COMPARE MODE

OPERATION BLOCK

DIAGRAM

14.2.1 CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the associated TRIS bit.

Some CCPx outputs are multiplexed on a couple of

pins. Table 14-2 shows the CCP output pin

Multiplexing. Selection of the output pin is determined

by the CCPxMX bits in Configuration register 3H

(CONFIG3H). Refer to Register 24-4 for more details.

14.2.2 TimerX MODE RESOURCE

In Compare mode, 16-bit TimerX resource must be

running in eith er Timer mode or Synchronized Counter

mode. The compare operation may not work in

Asynchronous Counter mode.

See Section 12.0 “Timer1/3/5 Module with Gate

Control” for more information on configuring the 16-bit

TimerX resources.

14.2.3 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen

(CCPxM<3:0> = 1010), the CCPx module does not

assert control of the CCPx pin (see the CCPxCON

CCPRxH CCPRxL

TMRxH TMRxL

Comparator

ROutput

Logic

Special Event Trigger

Set CCPxIF Interrupt Flag

(PIR1/2/4)

Match

TRIS

CCPxM<3:0>

Mode Select

Output Enable

Special Event Trigger function on

• ECCP1, ECCP2, ECCP3, CCP4 and CCP5 will:

- Reset TimerX – TMRxH:TMRxL = 0x0000

- TimerX Interrupt Flag, (TMRxIF) is not set

Additional Function on

• CCP5 will

- Set ADCON0<1>, GO/DONE bit to start an ADC

Conversion if ADCON<0>, ADON = 1.

CCPx

Note: Clearing the CCPxCON register wi ll force

the CCPx compare output latch to the

default lo w l ev el. Th is i s no t the PO R T I/O

data latch.

Note: Clocking TimerX from the system clock

(FOSC) should not be used in Compare

mode. In order for Compare mode to

recognize the trigger event on the CCPx

pin, TimerX must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

PIC18(L)F2X/4XK22

DS41412F-page 184  2010-2012 Microchip Technology Inc.

14.2.4 SPECIAL EVENT TRIGGER

When Special Event Trigger mode is selected

(CCPxM<3:0> = 1011), and a match of the

TMRxH:TMRxL and the CCPRxH:CCPRxL registers

occurs, all CCPx and ECCPx modules will immediately:

• Set the CCP interrupt flag bit – CCPxIF

• CCP5 will start an ADC conversion, if the ADC is

enabled

On the next TimerX rising clock edge:

• A Reset of Ti merX register pair occurs –

TMRxH: TMR xL = 0x00 00,

This Special Event Trigger mode does not:

• Assert control over the CCPx or ECCPx pins.

• Set the TMRxIF interrupt bit when the

TMRxH:TMRxL register pair is reset. (TMRxIF

gets set on a TimerX overflow.)

If the value of the CCPRxH:CCPRxL registers are

modified when a match occurs, the user should be

aware that the automatic reset of TimerX occurs on the

next rising edge of the clock. Therefore, modifying the

CCPRxH:CCPRxL registers before this reset occurs

will allow the TimerX to continue without being reset,

inadvertently resulting in the next event being

adva nc ed or dela ye d.

The Special Event Trigger mode allows the

CCPRxH:CCPRxL register pair to effectively provide a

16-bit programmable period register for TimerX.

14.2.5 COMPARE DURING SLEEP

The Compare mode is dependent upon the system

clock (FOSC) for proper operation. Since FOSC is shut

down during Sleep mode, the Compare mode will not

function properly during Sleep.

TABLE 14-5: REGISTERS ASSOCIATED WITH COMPARE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 205

CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 205

CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 205

CCP4CON — — DC4B<1:0> CCP4M<3:0> 205

CCP5CON — — DC5B<1:0> CCP5M<3:0> 205

CCPR1H Capture/Compare/PWM Register 1 High B yte (MSB) —

CCPR1L Captu re/Compare/PWM Register 1 Low Byte (LSB) —

CCPR2H Capture/Compare/PWM Register 2 High B yte (MSB) —

CCPR2L Captu re/Compare/PWM Register 2 Low Byte (LSB) —

CCPR3H Capture/Compare/PWM Register 3 High B yte (MSB) —

CCPR3L Captu re/Compare/PWM Register 3 Low Byte (LSB) —

CCPR4H Capture/Compare/PWM Register 4 High B yte (MSB) —

CCPR4L Captu re/Compare/PWM Register 4 Low Byte (LSB) —

CCPR5H Capture/Compare/PWM Register 5 High B yte (MSB) —

CCPR5L Captu re/Compare/PWM Register 5 Low Byte (LSB) —

CCPTMRS0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> 208

CCPTMRS1 — — — — C5TSEL<1:0> C4TSEL<1:0> 208

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not us ed by Compare mode.

Note 1: These regis ters/bits are available on PIC18( L)F4XK22 devices.

 2010-2012 Microchip Technology Inc. DS41412F- page 185

PIC18(L)F2X/4XK22

IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129

IPR4 — — — — — CCP5IP CCP4IP CCP3IP 131

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125

PIE4 — — — — — CCP5IE CCP4IE CCP3IE 127

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120

PIR4 — — — — — CCP5IF CCP4IF CCP3IF 122

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

PMD1 MSSP2MD MSSP1MD —CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 56

T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSCEN T1SYNC T1RD16 TMR1ON 172

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 173

T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 172

T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 173

T5CON TMR5CS<1:0> T5CKPS<1:0> T5SOSCEN T5SYNC T5RD16 TMR5ON 172

T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL T5GSS<1:0> 173

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register —

TMR1L Least Significant Byte of the 16-bit TMR1 Register —

TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register —

TMR3L Least Significant Byte of the 16-bit TMR3 Register —

TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register —

TMR5L Least Significant Byte of the 16-bit TMR5 Register —

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 156

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 156

TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 156

TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 156

TABLE 14-5: REGISTERS ASSOCIATED WITH COMPARE (CONTINUED)

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not use d by Compare mode.

Note 1: These registers/ bits are available on PIC18(L)F4XK22 de vices.

TABLE 14-6: CONFIGURATION REGISTERS ASSOCIATED WITH COMPARE

Name Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CONFIG3H MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360

Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Compare mode.

PIC18(L)F2X/4XK22

DS41412F-page 186  2010-2012 Microchip Technology Inc.

14.3 PWM Overview

Pulse-Width Modulation (PWM) is a scheme that

provid es p owe r to a l oad b y sw i tchin g q ui ckl y bet ween

fully on and fully off states. The PWM signal resembles

a square wave where the high portion of the signal is

considered the on state and the low portion of the signal

is considered the off state. The high portion, also known

as the pulse width, can vary in time and is defined in

steps. A larger number of steps applied, which

lengthens the pulse width, also supplies more power to

the loa d. L oweri ng t he nu mber of steps a ppli ed, wh ich

shortens the pulse width, supplies less power. The

PWM period is defined as the duration of one complete

cycle o r the total amount of on and off time combined.

PWM resolution defines the maximum number of steps

that c an be present in a single PWM period. A higher

resolu tion all ows for more preci se control of th e pulse

width time and in turn the power that is applied to the

load.

The ter m dut y cycle d escri bes t he propo rti on of th e on

time to the off time and is expressed in percentages,

where 0% is fully off and 100% is fully on. A lower duty

cycle corresponds to less power applied and a higher

duty cycle corresponds to more power applied.

Figure 14-3 shows a typical waveform of the PWM

signal.

14.3.1 STANDARD PWM OPERATION

The standard PWM func tio n des crib ed in th is sec tion is

available and identical for CCP and ECCP modules.

The standard PWM mode generates a Pulse-Width

modulation (PWM) signal on the CCPx pin with up to 10

bits of resolution. The period, duty cycle, and resolution

are controlled by the followi ng registers:

•PRx registers

•TxCON registers

• CCPRxL registers

• CCPxCON registers

Figure 14-4 shows a simplified block diagram of PWM

operation.

FIGURE 14-3: CCP PWM OUTPUT SIGNAL

FIGURE 14-4: SIMPLIFIED PWM BLOCK

DIAGRAM

14.3.2 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for standard PWM operation:

1. Disable the CCPx pin output driver by setting the

associated TRIS bit.

2. Select the 8-bit TimerX resource, (Timer2,

Timer4 or Timer6) to be used for PWM genera-

tion by setting the CxTSEL<1:0> bits in the

CCPTMRSx register .(1)

3. Load the PRx register for the selected TimerX

with the PWM period value.

4. Configure the CCP module for the PWM mode

by loading the CCPxCON register with the

appropriate values.

5. Load the CCPRxL register and the DCxB<1:0>

bits of the CCPxCON register, with the PWM

duty cycle value.

Note 1: The corresponding TRIS bit must be

cleared to enable the PWM output on the

CCP x pi n.

2: Clearing the CCPxCON register will

relinquish control of the CCPx pin.

Period

Pulse Width

TMRx = 0

TMRx = CCPRxH:CCPxCON<5:4>

TMRx = PRx

CCPRxL

CCPRxH(2) (Slave)

Comparator

TMRx

PRx

(1)

Duty Cycle Registers CCPxCON<5:4>

Clear Timer,

toggle CCPx pin and

latch duty cycle

Note 1: The 8-bit timer TMRx register is concatenated

with the 2-bit internal system clock (FOSC), or

2 bits of the prescaler , to create the 10-bit time

base.

2: In PWM mode, CCPRxH is a read-only register.

TRIS

CCPx

Comparator

 2010-2012 Microchip Technology Inc. DS41412F- page 187

PIC18(L)F2X/4XK22

6. Configure and start the 8-bit TimerX resource:

• Clear the TMRxIF interrupt flag bit of the

PIR2 or PIR4 register. See Note 1 bel ow.

• Configure the TxCKPS bits of the TxCON

• Enable the Timer by setting the TMRxON

bit of the TxCO N register.

7. Enable PWM output pin:

• Wait until the Timer overflows and the

TMRxIF bit of the PIR2 or PIR4 register is

set. See Note 1 below.

• Enable the CCPx pin output driver by

clearing the associated TRIS bit.

14.3.3 PW M TIMER RESOURCE

The PW M st andard mode makes use of one of the 8-bit

Timer2/4/6 timer resour ces to specify the PWM period.

Configuring the CxTSEL<1:0> bits in the CCPTMRS0

or CCP TMRS 1 re gi ste r s ele cts wh ic h Timer2/4 /6 t im er

is used.

14.3.4 PW M PE RIOD

The PWM period is specified by the PRx regis ter of 8-bit

TimerX. The PWM period can be calculated using the

formula of Equation 14-1.

EQUATION 14-1: PWM PERIOD

When TMRx is equ al to PRx, the followi ng three event s

occur on t he next inc rement cy cle:

• TMRx is cleared

• The CCPx pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

• The PWM dut y cycle is l atched from CCPRxL into

CCPRxH.

14.3.5 PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit

value to multiple registers: CCPRxL register and

DCxB<1:0> bits of the CCPxCON register. The

CCPRxL contains the eight MSbs and the DCxB<1:0>

bits of the CCPxCON register contain the two LSbs.

CCPRxL and DCxB<1:0> bits of the CCPxCON

value is not latched into CCPRxH until after the period

completes (i.e., a match between PRx and TMRx

registers occurs). While using the PWM, the CCPRxH

Equation 14-2 is used to calculate the PWM pulse

width.

Equation 14-3 is used t o calculate the PW M d uty cy cl e

ratio.

EQUATION 14-2: PULSE WIDTH

EQUATION 14-3: DUTY CYCLE RATIO

The CCPRxH register and a 2-bit internal latch are

used to dou ble buf fer th e PWM duty cycle. Thi s doubl e

buffering is essential for gl itchless PWM operation.

The 8-bit timer TMRx register is concatenated with either

the 2-bit internal system clock (FOSC), or two bits of the

prescaler, to create the 10-bit time base. The system

clock is used if the TimerX prescaler is set to 1:1.

When the 10-bit time base matches the CCPRxH and

2-bit latch, then the CCPx pin is cleared (see

Figure 14-4).

Note 1: In order to send a complete duty cycle

and period on the first PWM output, the

above steps must be included in the

setup sequence. If it is not critical to start

with a complete PWM signal on the first

output, then step 6 may be ignored.

Note: The Timer postscaler (see Section 13.0

“Timer2/4/6 Module”) is not used in the

determination of the PWM frequency.

PWM Period PRx1+4TOSC =

(TMRx Presca l e V a l ue )

Note 1: TOSC = 1/FOSC

Pulse Width CCPRxL:CCPxCON<5:4>



TOSC



(TMRx Prescale Va lue)

Duty Cycle Ratio CCPRxL:CCPxCON<5:4>

4 PRx 1+

-----------------------------------------------------------------------=

PIC18(L)F2X/4XK22

DS41412F-page 188  2010-2012 Microchip Technology Inc.

14.3.6 PW M RES OLUT ION

The res olution de termine s the nu mber of availa ble duty

cycles for a given period. For example, a 10-bit resolution

will r e sult in 10 24 di sc ret e d ut y c ycl es , wh er eas an 8- b it

resol uti on wi ll re su lt in 2 56 di s cre te du ty c ycl es .

The maximum PWM resolution is ten bits when PRx is

255. The resolution is a function of the PRx register

value as shown by Equation 14-4.

EQUATION 14-4: PWM RESOLUTION

14.3.7 OPERATION IN SLEEP MODE

In Sleep mode, the TMRx register will not increment

and the state of the mo dule will no t change . If the C CPx

pin is dri ving a value , it wi ll cont inue to d rive th at valu e.

When the devic e wakes up, TMRx will conti nue from it s

previous state.

14.3.8 CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency. Any changes in the system clock frequency

will result in changes to the PWM frequency. See

Section 2.0 “Oscillator Module (With Fail-Safe

Clock Monitor)” for addi tional d etails.

14.3.9 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

Note: If the pu ls e width value is gre ate r th an the

period the assigned PWM pin(s) will

remain unchanged.

Resolution 4PRx 1+log 2log

------------------------------------------ bits=

TABLE 14-7: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz)

PWM Frequency 1.95 kHz 7.81 kHz 31.25 kHz 125 kHz 250 kHz 333.3 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1

PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.6

TABLE 14-8: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1

PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.6

TABLE 14-9: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1

PRx Value 0x65 0x65 0x65 0x19 0x0C 0x09

Maximum Resolution (bits) 8 8 8 6 5 5

 2010-2012 Microchip Technology Inc. DS41412F- page 189

PIC18(L)F2X/4XK22

TABLE 14-11: CONFIGURATION REGISTERS ASSOCIATED WITH STANDARD PWM

TABLE 14-10: REGISTERS ASSOCIATED WITH STANDARD PWM

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 205

CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 205

CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 205

CCP4CON — — DC4B<1:0> CCP4M<3:0> 205

CCP5CON — — DC5B<1:0> CCP5M<3:0> 205

CCPTMRS0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> 208

CCPTMRS1 — — — — C5TSEL<1:0> C4TSEL<1:0> 208

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129

IPR4 — — — — —CCP5IPCCP4IP CCP3IP 131

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125

PIE4 — — — — — CCP5IE CCP4IE CCP3IE 127

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120

PIR4 — — — — — CCP5IF CCP4IF CCP3IF 122

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

PMD1 MSSP2MD MSSP1MD —CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 56

PR2 Timer2 Period Register —

PR4 Timer4 Period Register —

PR6 Timer6 Period Register —

T2CON —T2OUTPS<3:0>TMR2ONT2CKPS<1:0> 172

T4CON —T4OUTPS<3:0>TMR4ONT4CKPS<1:0> 172

T6CON —T6OUTPS<3:0>TMR6ONT6CKPS<1:0> 172

TMR2 Timer2 Register —

TMR4 Timer4 Register —

TMR6 Timer6 Register —

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 156

TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 156

TRISE WPUE3 — — — —TRISE2

(1) TRISE1(1) TRISE0(1) 156

Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not use d by Standard PWM mode.

Note 1: These registers/ bits are available on PIC18(L)F4XK22 de vices.

Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Regi ster

on Page

CONFIG3H MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360

Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by S tandard PWM mode.

PIC18(L)F2X/4XK22

DS41412F-page 190  2010-2012 Microchip Technology Inc.

14.4 PWM (Enhanced Mode)

The enhanced PWM function described in this section is

available for CCP modules ECCP1, ECCP2 and

ECCP3, with any dif ferences between modules noted.

The enhanced PWM mode generates a Pulse-Width

Modulation (PWM) signal on up to four different output

pins with up to ten bits of resolution. The period, duty

cycle, and resolution are controlled by the following

registers:

•PRx registers

•TxCON registers

• CCPRxL registers

• CCPxCON registers

The ECCP modules have the following additional PWM

registers which control Auto-shutdown, Auto-restart,

Dead-band Delay and PWM Steering modes :

• ECCPxAS registers

• PSTRxCON registers

• PWMxCON registers

The enhanced PWM module ca n generate the following

five PWM Output modes:

• Single PWM

• Half-Bridge PWM

• Full-Bridge PWM, Fo rward mode

• Full-Bridge PWM, Reverse mode

• Single PWM with PWM Steering mode

To select an Enhanced PWM Output mode, the

PxM<1:0> bits of the CCPxCON register must be

configured appropriately.

The PWM outputs are multiplexed with I/O pins and are

designated PxA, PxB, PxC and PxD. The polarity of the

PWM pins is configurable and is selected by setting the

CCPxM bits in the CCPxCON register appropriately.

Figure 14-5 shows an example of a simplified block

diagram of the Enhanced PWM module .

Table 14-12 shows the pin assignments for various

Enhanced PWM modes.

FIGURE 14-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE

Note 1: The corresponding TRIS bit must be

cleared to enable the PWM output on the

CCPx pin.

2: Clearing the CCPxCON register will

relinquish control of the CCPx pin.

3: Any pin not used in the enhanced PWM

mode is available for alternate pin

functions, if applicable.

4: To prevent the generation of an

incomplete waveform when the PWM is

first enabled, the ECCP module waits

until the start of a new PWM period

before generating a PWM signal.

CCPRxL

CCPRxH (Slave)

Comparator

TMRx

Comparator

PRx

(1)

Duty Cycle Registers DCxB<1:0>

Clear Timer,

toggle PWM pin and

latch duty cycle

Note 1: The 8- bi t t imer TM Rx r egist er is con cate nated wit h th e 2 -bit i nte rna l Q cl o ck, o r 2 bits of th e prescaler to create t he 10- bi t time

base.

2: PxC and PxD are not available on half-bridge ECCP modules.

TRISx

CCPx/PxA

TRISx

PxB

TRISx

PxC(2)

TRISx

PxD(2)

Output

Controller

PxM<1:0> 2CCPxM<3:0>

PWMxCON

CCPx/PxA

PxB

PxC

PxD

 2010-2012 Microchip Technology Inc. DS41412F- page 191

PIC18(L)F2X/4XK22

FIGURE 14-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH

STATE)

TABLE 14-12: EXAMP LE PIN ASS IGNME NTS FOR VARIOUS PWM ENHANCED MODES

ECCP Mode PxM<1:0> CCPx/PxA PxB PxC PxD

Single 00 Yes(1) Yes(1) Yes(1) Yes(1)

Half-Bridge 10 Yes Yes No No

Full-Bridg e, Forward 01 Yes Yes Yes Yes

Full-Bridg e, Reve rse 11 Yes Yes Yes Yes

Note 1: PWM Steering enables outputs in Single mode.

Period

Signal PRX+1

PxM<1:0>

PxA Modulated

PxB Modulated

PxA Active

PxB Inactiv e

PxC Inactive

PxD Modulated

PxA Inactiv e

PxB Modulated

PxC Active

PxD Inactive

Pulse

Width

(Single Output)

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

Delay(1) Delay(1)

Relationships:

• Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)

• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)

• Delay = 4 * TOSC * (PWMxCON<6:0>)

Note 1: Dead-band delay is programmed using the PWMxCON register (Section 14.4.5 “Programmable Dead-Band Delay

Mode”).

PIC18(L)F2X/4XK22

DS41412F-page 192  2010-2012 Microchip Technology Inc.

FIGURE 14-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

Period

Signal PRx+1

PxM<1:0>

PxA Modulated

PxB Modulated

PxA Active

PxB Inactiv e

PxC Inactive

PxD Modulated

PxA Inactiv e

PxB Modulated

PxC Active

PxD Inactive

Pulse

Width

(Single Output)

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

Delay(1) Delay(1)

Relationships:

• Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)

• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)

• Delay = 4 * TOSC * (PWMxCON<6:0>)

Note 1: Dead-band delay is programmed using the PWMxCON register (Section 14.4.5 “Programmable Dead-Band Delay

Mode”).

 2010-2012 Microchip Technology Inc. DS41412F- page 193

PIC18(L)F2X/4XK22

14.4.1 HALF-BRIDGE MODE

In Half-Bridge mode, two pins are used as outputs to

drive push-p ull loa ds. The PW M outp ut sign al is output

on the CCPx/PxA pin, while the complementary PWM

output signal is output on the PxB pin (see Figure 14-9).

This mod e can be us ed for ha lf-bridge applica tions, as

shown in Figure 14-9, or for full-bridge applications,

where four power switches are being modulated with

two PWM signals.

In Half-Bridge mode, the programmable dead-band delay

can be used to prevent shoot-through current in half-

bridge power devices. The value of the PDC<6:0> bits of

the PWMxCON register sets the number of instruction

cycles before the output is driven active. If the value is

greater than the duty cycle, the corresponding output

remains inactive during the entire cycle. See

Section 14.4.5 “Programmable Dead-Band Delay

Mode” for more details of the dead-band delay

operations.

Since the Px A and PxB out puts are multiplexed wi th the

PORT data latches, the associated TRIS bits must be

cleared to configure PxA and PxB as outputs.

FIGURE 14-8: EXAMPLE OF HALF-

BRIDGE PWM OUTPUT

FIGURE 14-9: EXAMP LE OF HALF-BRIDGE APPLICATIONS

Period

Pulse Width

(1)

PxA(2)

PxB(2)

td = Dead-Band Delay

Period

(1) (1)

Note 1: At this time, the TMRx register is equal to the

PRx register .

2: Output signals are shown as active-high.

PxA

PxB

FET

Driver

FET

Driver

Load

FET

Driver

FET

Driver

V+

Load

FET

Driver

FET

Driver

PxA

PxB

Standard Half-Bridge Circuit (“Push-Pull”)

Half-Bridge Output Driving a Full-Bridge Circuit

PIC18(L)F2X/4XK22

DS41412F-page 194  2010-2012 Microchip Technology Inc.

14.4.2 FULL-BRIDGE MODE

In Full-Bridge mode, all four pins are used as outputs.

An example of full-bridge application is shown in

Figure 14-10.

In the Forward mode, pin CCPx/PxA is dri ven to its active

state, p in PxD i s modula ted, while P xB and PxC will b e

driven to their inactive state as shown in Figure 14-11.

In the Reverse mode, PxC is driven to its active state, pin

PxB is modulated, while PxA and PxD will be driven to

their inactive state as shown Figure 14-11.

PxA, PxB, PxC and PxD outputs are multiplexed with

the POR T dat a latc hes. The a ssoc iated T RIS bit s mus t

be cleared to configure the PxA, PxB, PxC and PxD

pins as outputs.

FIGURE 14-10: EXAMPLE OF FULL-BRIDGE APPLICATION

PxA

PxC

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

PxB

PxD

QB QD

 2010-2012 Microchip Technology Inc. DS41412F- page 195

PIC18(L)F2X/4XK22

FIGURE 14-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT

Period

Pulse Width

PxA(2)

PxB(2)

PxC(2)

PxD(2)

Forw a r d M o de

(1)

Period

Pulse Width

PxA(2)

PxC(2)

PxD(2)

PxB(2)

Reverse Mode

(1)

Note 1: At this time, the TMRx register is equal to the PRx register.

2: Output signal is shown as active-high.

PIC18(L)F2X/4XK22

DS41412F-page 196  2010-2012 Microchip Technology Inc.

14.4.2.1 Direction Change in Full-Bridge

Mode

In the Full-Bridge mode, the PxM1 bit in the CCPxCON

direction. When the application firmware changes this

direction co ntrol bit, the modu le will change to the new

direction on the next PWM cycle.

A direction change is initiated in software by changing

the PxM1 bit of the CCPxCON register. The following

sequence occurs four Timer cycles prior to the end of

the current PWM period:

• The modulated outputs (PxB and PxD) are placed

in their inactive state.

• The associated unmodulated outputs (PxA and

PxC) are switched to drive in the opposite

direction.

• PWM mo dulati on resumes at the be ginnin g of the

next period.

See Figure 14-12 for an illustration of this sequence.

The Full-Bridge mode does not provide dead-band

delay. As one output is modulated at a time, dead-band

delay is generally not required. There is a situation

where dead-band delay is required. This situation

occurs when both of the following conditions are true:

1. The direction of the PWM output changes when

the duty cycle of the output is at or near 100%.

2. The turn off time of the power switch, including

the power device and driver circuit, is greater

than the turn on time.

Figure 14-13 show s an example of the PWM dire ction

chan gi ng from for w ar d to rev ers e , at a ne ar 100% duty

cycle. In this example, at time t1, the output PxA and

PxD become inactive, while output PxC becomes

active. Since the turn off time of the power devices is

longer than the turn on time, a shoot-through current

will flow through power devices QC and QD (see

Figure 14-10) for the duration of ‘t’. The same

phenomenon will occur to power devices QA and QB

for PWM di rec t io n ch an ge from reve rs e to forw a rd.

If changing PWM direction at high duty cycle is required

for an app lication, two possible solutions f or eliminatin g

the shoot-through current are:

1. Reduce PWM duty cycle for one PWM period

before changing directions.

2. Use switch drivers that can drive the switches off

faster than they can drive them on.

Other options to prevent shoot-through current may

exist.

FIGURE 14-12: EXAMPLE OF PWM DIRECTION CHANGE

Pulse Width

Period(1)

Signal

Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.

2: When changing directions, the PxA and P xC signals switch bef ore the end of the cu rrent PWM cycle. The

modulated PxB and PxD signals are inactive at this time. The length of this time is (TimerX Prescale)/FOSC,

whe re Ti merX is Timer 2, Timer 4 or Timer 6.

Period

(2)

PxA (Active-H igh)

PxB (Active-H igh)

PxC (Active-High)

PxD (Active-High)

Pulse Width

 2010-2012 Microchip Technology Inc. DS41412F- page 197

PIC18(L)F2X/4XK22

FIGURE 14-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

14.4.3 ENHANCED PWM AUTO-

SH UTDOWN MODE

The PWM mode supports an Auto-Shut dow n mode that

will disable the PWM outputs when an external

shutdown event occurs. Auto-Shutdown mode places

the PWM output pins into a predetermined state. This

mode is used to help prevent the PWM from damaging

the application.

The auto-shutdown sources are selected using the

CCPxAS<2:0> bits of the ECCPxAS register. A

shutdow n event ma y be generated by :

•A logic ‘0’ on the INT pin

• Comparator Cx (async_CxOUT)

• Setting the CCPxASE bit in firmware

A shutdown condition is indicated by the CCPxASE

(Auto-Shutdown Event Status) bit of the ECCPxAS

normally. If the bit is a ‘1’, the PWM outputs are in the

shutdown state.

When a shut down even t occurs, tw o things happen:

The CCPxASE bit is set to ‘1’. The CCPxASE will

remain set until cleared in firmware or an auto-restart

occurs (see Section 14.4.4 “Auto-Restart Mode” ).

The enabled PWM pins are asynchronously placed in

their shutdown states. The PWM output pins are

grouped into pairs [PxA/PxC] and [PxB/PxD]. The state

of each pin pair is determined by the PSSxAC<1:0> and

PSSxBD<1:0> bits of the ECCPxA S register. Each pin

pair may be plac ed into one of three s t ates:

• Drive logic ‘1’

• Drive logic ‘0’

• Tri-state (high-impedance)

Forward Period Reverse Period

PxA

TON

TOFF

T = TOFF – TON

PxB

PxC

PxD

External Switch D

Potential

Shoot-Through Current

Note 1: All signals are shown as active-high.

2: TON is the turn-on delay of power switch QC and its driver.

3: TOFF is the turn-off delay of power switch QD and its driver.

External Switch C

Note 1: The auto-shutdown condition is a level-

based signal, not an edge-based signal.

As long as the level is present, the auto-

shutdown will persist.

2: Writing to the CCPxASE bit is disabled

while an auto-shutdown condition

persists.

3: Once the auto-shutdown condition has

been removed and the PWM restarted

(either through firmware or auto-restart),

the PWM signal will always restart at the

beginning of the next PWM period.

PIC18(L)F2X/4XK22

DS41412F-page 198  2010-2012 Microchip Technology Inc.

FIGURE 14-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0)

14.4.4 AUTO-RESTAR T MODE

The Enhanced PWM can be configured to

automatically restart the PWM signal once the auto-

shutdown condition has been removed. Auto-restart is

enabled by setting the PxRSEN bit in the PWMxCON

If auto-restart is enabled, the CCPxASE bit will remain

set as long as the auto-shutdown condition is active.

When the auto-shutdown condition is removed, the

CCPxASE bit will be cleared via hardware and normal

operation will resume.

FIGURE 14-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1)

Shutdown

PWM

CCPxASE bit

Activity

Event

Shutdown

Event Occurs Shutdown

Event Clears

PWM

Resumes

PWM Period

Start of

PWM Perio d

CCPxASE

Cleared by

Firmware

Timer

Overflow Timer

Overflow

Missing Pulse

(Auto-Shutdown) Missing Pulse

(CCPxASE not clear)

Timer

Overflow

Shutdown

PWM

CCPxASE bit

Activity

Event

Shutdown

Event Occurs Shutdown

Event Clears

PWM Period

Start of

PWM Perio d

CCPxASE

Cleared by

Hardware

Timer

Overflow Timer

Overflow

Missing Pulse

(Auto-Shutdown) Missing Pulse

(CCPxASE not clear)

Timer

Overflow

PWM

Resumes

 2010-2012 Microchip Technology Inc. DS41412F- page 199

PIC18(L)F2X/4XK22

14.4.5 PROGRAMMABLE DEAD-BAND

DELAY MODE

In half-b ridge applications where all po wer switches are

modul ate d at t he P WM fr equ ency, the powe r swi tches

normall y require more tim e to turn of f than to turn on. If

both the upper and lower power switches are switched

at the same time (one turned on, and the other turned

off), both switc hes ma y be on for a sh ort period of time

until one switch completely turns off. During this brief

interval , a ve ry hig h curre nt (sh oot- through curren t) wil l

flow through both power switches, shorting the bridge

supply. To avoid this potentially destructive shoot-

through current from flowing during switching, turning

on either of the power switches is normally delayed to

allow the other switch to completely turn off.

In Half-Bridge mode, a digitally programmable dead-

band delay is available to avoid shoot-through current

from destroying the bridge power switches. The delay

occurs at the si gnal tra nsition fro m the no n-acti ve st ate

to the active state. See Figure 14-16 for illustration.

The lower seven bits of the associated PWMxCON

of microcontroller instruction cycles (TCY or 4 TOSC).

FIGURE 14-16: EXAMPLE OF HALF-

BRIDGE PWM OUTPUT

FIGURE 14-17 : EX AMP LE OF HALF-BRIDGE APPLICATIONS

Period

Pulse Width

(1)

PxA(2)

PxB(2)

td = Dead-Band Delay

Period

(1) (1)

Note 1: At this time, the TMRx register is equal to the

PRx register.

2: Output signals are shown as active-high.

PxA

PxB

FET

Driver

FET

Driver

V+

V-

Load

Standard Half-Bridge Circuit (“Push-Pull”)

PIC18(L)F2X/4XK22

DS41412F-page 200  2010-2012 Microchip Technology Inc.

14.4.6 PWM STEERING MODE

In Single Output mode, PWM steering allows any of the

PWM pins to be t he modulated signal. Addi tio nal ly, the

same PWM signal can be simultaneously available on

multiple pins.

Once the Single Output mode is selected

(CCPxM<3:2> = 11 and PxM<1:0> = 00 of the

CCPxCON register), the user firmware can bring out

the same PWM signal to one, two, three or four output

pins by setting the appropriate Steering Enable bits

(STRxA, STRxB, STRxC and/or STRxD) of the

PSTRxCO N register , as sh own in Table 14-13.

While the PWM Steeri ng mo de is act iv e, C CP xM <1: 0>

bits of the CCPxCON register select the PWM output

polarity for the PxD, PxC, PxB and PxA pins.

The PWM auto-shutdown operation also applies to

PWM Steering mode as described in Section 14.4.3

“Enhanced PWM Auto-shutdown Mode”. An auto-

shutdown event will only affect pins that have PWM

outputs enabled.

FIGURE 14-18: SIMPLIFIED STEERING

BLOCK DIAGRAM

14.4.6.1 Steering Synchronization

The STRxSYNC bit of the PSTRxCON register gives

the user two selections of when the steering event will

happen. When the STRxSYNC bit is ‘0’, the steering

event will happen at the end of the instruction that

writes to the PSTRxCON register. In this case, the

output signal at the PxA, PxB, PxC and PxD pins may

be an incomplete PWM waveform. This operation is

useful when the user firmware needs to immediately

remove a PWM signal from the pin.

When the STRxSYNC bit is ‘1’, the effective steering

update will happen at the beginning of the next PWM

period. In this case, s teering on/of f th e PWM output wil l

always produce a complete PWM waveform.

Figures 14-19 and 14-20 illustrate t he timing diagr ams

of the PWM steering depending on the STRxSYNC

setting.

Note: The associated TRIS bits must be set to

outp ut ( ‘0’) to enable the pin output driver

in or der to s ee the PWM si gnal o n the p in.

0TRIS

PxA pin

PORT Data

PxA Signal

STRxA

0TRIS

PxB pin

PORT Data

STRxB

0TRIS

PxC pin

PORT Data

STRxC

0TRIS

PxD pin

PORT Data

STRxD

Note 1: Port outputs are configured as shown when

the CCPxCON register bits PxM<1:0> = 00

and CCPxM<3:2> = 11.

2: Single PWM output requires setting at least

one of the STRx bits.

CCPxM1

CCPxM0

CCPxM1

CCPxM0

 2010-2012 Microchip Technology Inc. DS41412F- page 201

PIC18(L)F2X/4XK22

14.4.7 START-UP CONSIDERATIONS

When any PWM mode is used, the application

hardware must use the proper external pull-up and/or

pull-down resistors on the PWM output pins.

The CCPxM<1:0> bits of the CCPxCON register allow

the user to choose whether the P WM output signals are

active-high or active-low for each pair of PWM output

pins (PxA/PxC and PxB/PxD). The PWM output

polarities must be selected before the PWM pin output

drivers are enabled. Changing the polarity

configuration while the PWM pin output drivers are

enable is not recommended since it may result in

damage to the applic ati on circuit s .

The P xA, P xB, P xC an d Px D output l atches ma y not be

in the proper states when the PWM module is

initialized. Enabling the PWM pin output drivers at the

same time as the Enhanced PWM modes may cause

damage to the application circuit. T he En han ce d PW M

modes must be enabled in the proper Output mode and

complete a full PWM cycle before enabling the PWM

pin output drivers. The completion of a full PWM cycle

is indicated by the TMRxIF bit of the PIR1, PIR2 or

PIR5 register being set as the second PWM period

begins.

FIGURE 14-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0)

FIGURE 14-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION

(STRxSYNC = 1)

Note: When the mic rocon troller i s release d from

Reset, all of the I/O pins are in the high-

impedance state. The external circuits

must ke ep the power s witch de vices in the

Off state until the microcontroller drives

the I/O pins with the proper signal levels or

activates the PWM output(s).

PWM

P1n = PWM

STRx

P1<D:A> PO RT Da ta

PWM Period

PORT Data

PWM

PORT Data

P1n = PW M

STRx

P1<D:A> PORT Data

PIC18(L)F2X/4XK22

DS41412F-page 202  2010-2012 Microchip Technology Inc.

14.4.8 SET UP FOR ECCP PWM

OPERATION USING ECCP1 AND

TIMER2

The following steps should be taken when configuring

the ECCP1 module for PWM operation using Timer2:

1. Configure the PWM pins to be used (P1A, P1B,

P1C, and P1D):

• Configu re PWM o utp uts to be used as inp uts

by se tting the corresponding TRIS bits. This

prevents spurious outputs during setup.

• Set the PSTR1CON bits for each PWM

output to be used.

2. Select Timer2 as the p eriod time r by con figurin g

CCPTMR0 register bits C1TSEL<1:0> = ‘00’.

3. Set the PWM period by loading th e PR2 register .

4. Configure auto-shutdown as OFF or select the

source with the CCP1AS<2:0> bits of the

ECCP1AS register.

5. Configure the auto-shutdown sources as

needed:

• Configure each comparator used.

• Config ure the comparator inputs as ana log .

• Configure the FLT0 input pin and clear

ANSB0.

6. Force a shutdown condition (OFF included):

• Configure safe starting output levels by

setting the default shutdown drive states with

the PSS1AC<1:0> an d PSS1BD<1:0> bits of

the ECCP1AS register.

• Clear the P1RSEN bi t of the PWM1CON

• Set the CCP1AS bit of the ECCP1AS

7. Configure the ECCP1 module for the desired

PWM mode and configuration by loading the

CCP1CON register with the appropriate values:

• Select one of the available output configura-

tions and dire cti on with the P1M <1:0 > bit s .

• Select the polarities of the PWM output

signals with the CCP1M<3:0> bits.

8. Set the 10-bit PWM duty cycle:

• Load the e ight MSbs into the C CPR1L

• Load the two LSbs into the DC<1:0> bits of

the CCP1CON register.

9. For Half-Bridge Output mode, set the dead-

band delay by loading P1DC<6:0> bits of the

PWM1CON register with the appropriate value.

10. Configure and start TMR2:

• Set the TMR2 prescale value by loading the

T2CKPS bits of the T2CON register.

• Start Timer2 by setting the TMR2ON bit.

11. Enable the ECCP1/P1A, P1B, P1C and/or P1D

pin outputs by clearing the respec tive TRIS bit s.

12. Start the PWM:

• If shut dow n au to-rest art is us ed, t hen s et the

P1RSEN bit of the PWM1CON register.

• If shutdow n auto- res tart is not used, then

clear the CCP1ASE bit of the ECCP1AS

 2010-2012 Microchip Technology Inc. DS41412F- page 203

PIC18(L)F2X/4XK22

TABLE 14-13: REGISTERS ASSOCIATED WITH ENHANCED PWM

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ECCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 209

CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 205

ECCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 209

CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 205

ECCP3AS CCP3ASE CCP3AS<2:0> PSS3AC<1:0> PSS3BD<1:0> 209

CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 205

CCPTMRS0 C3TSEL<1:0> —C2TSEL<1:0> —C1TSEL<1:0> 208

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129

IPR4 — — — — — CCP5IP CCP4IP CCP3IP 131

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125

PIE4 — — — — — CCP5IE CCP4IE CCP3IE 127

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120

PIR4 — — — — — CCP5IF CCP4IF CCP3IF 122

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

PMD1 MSSP2MD MSSP1MD —CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 56

PR2 Timer2 Period Register —

PR4 Timer4 Period Register —

PR6 Timer6 Period Register —

PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A 210

PSTR2CON — — — STR2SYNC STR2D STR2C STR2B STR2A 210

PSTR3CON — — — STR3SYNC STR3D STR3C STR3B STR3A 210

PWM1CON P1RSEN P1DC<6:0> 210

PWM2CON P2RSEN P2DC<6:0> 210

PWM3CON P3RSEN P3DC<6:0> 210

T2CON —T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 172

T4CON —T4OUTPS<3:0> TMR4ON T4CKPS<1:0> 172

T6CON —T6OUTPS<3:0> TMR6ON T6CKPS<1:0> 172

TMR2 T i mer2 Register —

TMR4 T i mer4 Register —

TMR6 T i mer6 Register —

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 156

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 156

TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 156

TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 156

Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not use d by Enhanced PWM mode.

Note 1: These registers/ bits are available on PIC18(L)F4XK22 de vices.

PIC18(L)F2X/4XK22

DS41412F-page 204  2010-2012 Microchip Technology Inc.

TABLE 14-14: CONFIGURATION REGISTERS ASSOCIATED WITH ENHANCED PWM

Name Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CONFIG3H MCLRE —P2BMXT3CMX HFOFST CCP3MX PBADEN CCP2MX 360

Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Enhanced PWM mode.

 2010-2012 Microchip Technology Inc. DS41412F- page 205

PIC18(L)F2X/4XK22

14.5 Register Definitions: ECCP Control

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— DCxB<1:0> CCPxM<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unused

bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mo de:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0 CCPxM<3:0>: ECCPx Mode S elect bits

0000 = Capture/Compare/PWM off (resets the module)

0001 = Reserved

0010 = Compare mode: toggle output on match

0011 = Reserved

0100 = Capture mode: every falling edge

0101 = Capture mode: every rising edge

0110 = Capture mode: every 4th rising edge

0111 = Capture mode: every 16th rising edge

1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set)

1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set)

1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected,

CCPxIF is set)

1011 = Compare mode: Special Even t Trigger (CCPx pin is unaffected, CCPxIF is set)

TimerX (selected by CxTSEL bits) is reset

ADON is set, starting A/D conversion if A/D module is enabled(1)

11xx =: PWM mode

Note 1: This feature is available on CCP5 only.

PIC18(L)F2X/4XK22

DS41412F-page 206  2010-2012 Microchip Technology Inc.

R/x-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PxM<1:0> DCxB<1:0> CCPxM<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits

If CCPxM<3:2> = 00, 01, 10: (Capture/Co mpare modes)

xx = PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins

Half-Bridge ECCP Modules(1):

If CCPxM<3:2> = 11: (PWM modes)

0x = Single ou tput; PxA modulated; PxB assigned as port pin

1x = Half-Bridge output; PxA, PxB modulated with dead-band control

Full-Bridge ECCP Modules(1):

If CCPxM<3:2> = 11: (PWM modes)

00 = Single ou tput; PxA modulated; PxB, PxC, PxD assigned as port pins

01 = Full-Bridge output forward; PxD modulated; PxA active; PxB, PxC inactive

10 = Half-Bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port

pins

11 = Full-Bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive

bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits

Capture mo de:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

Note 1: See Table 14-1 to determine full-bridge and half-bridge ECCPs for the device being used.

 2010-2012 Microchip Technology Inc. DS41412F- page 207

PIC18(L)F2X/4XK22

bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits

0000 = Capture/Compare/PWM off (resets the module)

0001 = Reserved

0010 = Compare mode: toggle output on match

0011 = Reserved

0100 = Capture mode: eve r y fal lin g edge

0101 = Capture mode: eve r y ris ing edge

0110 = Capture mode: eve r y 4th rising edge

0111 = Capture mode: eve r y 16t h risin g edge

1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set)

1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set)

1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected,

CCPxIF is set)

1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set)

Tim erX is reset

Half-Bridge ECCP Modules(1):

1100 = PWM mode: PxA active-high; PxB active-high

1101 = PWM mode: PxA active-high; PxB active-low

1110 = PWM mode: Px A active-low; PxB active-high

1111 = PWM mode: Px A active-low; PxB active-low

Full-Bridge ECCP Modules(1):

1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high

1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low

1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high

1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low

Note 1: See Table 14-1 to determine full-bridge and half-bridge ECCPs for the device being used.

PIC18(L)F2X/4XK22

DS41412F-page 208  2010-2012 Microchip Technology Inc.

R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 C3TSEL<1:0>: CCP3 Timer Selection bits

00 = CCP3 – Capture/Compare modes use Timer1, PWM modes use Timer2

01 = CCP3 – Capture/Compare modes use Timer3, PWM modes use Timer4

10 = CCP3 – Capture/Compare modes use Timer5, PWM modes use Timer6

11 =Reserved

bit 5 Unused

bit 4-3 C2TSEL<1:0>: CCP2 Timer Selection bits

00 = CCP2 – Capture/Compare modes use Timer1, PWM modes use Timer2

01 = CCP2 – Capture/C o mpare modes use T i me r3, PWM modes use Timer4

10 = CCP2 – Capture/Compare modes use Timer5, PWM modes use Timer6

11 =Reserved

bit 2 Unused

bit 1-0 C1TSEL<1:0>: CCP1 Timer Selection bits

00 = CCP1 – Capture/Compare modes use Timer1, PWM modes use Timer2

01 = CCP1 – Capture/Compare modes use Timer3, PWM modes use Timer4

10 = CCP1 – Capture/Compare modes use Timer5, PWM modes use Timer6

11 =Reserved

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — C5TSEL<1:0> C4TSEL<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-2 C5TSEL<1:0>: CCP5 Timer Selection bits

00 = CCP5 – Capture/Compare modes use Timer1, PWM modes use Timer2

01 = CCP5 – Capture/Compare modes use Timer3, PWM modes use Timer4

10 = CCP5 – Capture/Compare modes use Timer5, PWM modes use Timer6

11 =Reserved

bit 1-0 C4TSEL<1:0>: CCP4 Timer Selection bits

00 = CCP4 – Capture/Compare modes use Timer1, PWM modes use Timer2

01 = CCP4 – Capture/Compare modes use Timer3, PWM modes use Timer4

10 = CCP4 – Capture/Compare modes use Timer5, PWM modes use Timer6

11 =Reserved

 2010-2012 Microchip Technology Inc. DS41412F- page 209

PIC18(L)F2X/4XK22

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CCPxASE CCPxAS<2:0> PSSxAC<1:0> PSSxBD<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CCPxASE: CCPx Auto-shutdown Event Status bit

if PxRSEN = 1;

1 = An Auto-shutdown event occurred; CCPxASE bit will automatically clear when event goes away;

CCPx outputs in shutdown state

0 = CCPx outputs are operating

if PxRSEN = 0;

1 = An Au to-shutdown event occurred; bit must be cle ared in software to restart PWM;

CCPx outpu t s in shu tdown state

0 = CCPx outputs are operating

bit 6-4 CCPxAS<2:0>: CCPx Auto-Shutdown Source Select bits (1)

000 = Auto-shutdown is disabled

001 = Com parat or C1 (async_C1OUT ) – output high will ca use s hutdown event

010 = Com parat or C2 (async_C2OUT ) – output high will ca use s hutdown event

011 = Either Comparator C1 or C2 – output high will cause shutdown event

100 = FLT0 pin - low level will cause shu tdown event

101 = FLT0 pin or Comparator C1 (async_C1OUT) – low level will cause shutdown event

110 = FLT0 pin or Comparator C2 (async_C2OUT) – low level will cause shutdown event

111 = FLT0 pin or Comparators C1 or C2 – low level will cause shutdown event

bit 3-2 PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits

00 = Drive pins PxA and PxC to ‘0’

01 = Drive pins PxA and PxC to ‘1’

1x = Pins PxA and PxC tri-state

bit 1-0 PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits

00 = Drive pins PxB and PxD to ‘0’

01 = Drive pins PxB and PxD to ‘1’

1x = Pins PxB and PxD tri-state

Note 1: If C1SYNC or C2SYNC bits in the CM2CON1 register are enabled, the shutdown will be delayed by

Timer1.

PIC18(L)F2X/4XK22

DS41412F-page 210  2010-2012 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PxRSEN PxDC<6:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 PxRSEN: PWM Restart Enable bit

1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes

away; the PWM restarts automatically

0 = Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM

bit 6-0 PxDC<6:0>: PWM Delay Count bits

PxDCx = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal

should transition active and the actual time it transitions active

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1

— — — STRxSYNC STRxD STRxC STRxB STRxA

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4 STRxSYNC: Steering Sync bit

1 = Output steering update occurs on next PWM period

0 = Output steering update occurs at the beginning of the instruction cycle boundary

bit 3 STRxD: Steering Enable bit D

1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxD pin is assigned to port pin

bit 2 STRxC: Steering Enable bit C

1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxC pin is assigned to port pin

bit 1 STRxB: Steering Enable bit B

1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxB pin is assigned to port pin

bit 0 STRxA: Steering Enable bit A

1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxA pin is assigned to port pin

Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and

PxM<1:0> = 00.

 2010-2012 Microchip Technology Inc. DS41412F- page 211

PIC18(L)F2X/4XK22

15.0 MASTER SYNCHRONOUS

SERIAL PORT (MS SP1 AND

MSSP2) MODULE

15.1 Master SSPx (MSSPx) Module

Overview

The Master Sy nchronous Serial Port (MSSPx) module

is a se rial interfa ce useful for communi cating with other

periphera l or m icroc ontroll er dev ices. Th ese p eriphera l

devices may be Serial EEPROMs, shift registers,

display drivers, A/D converters, etc. The MSSPx

module can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I2C™)

The SPI interface supports the following modes and

features:

•Master mode

• Slave mode

• Clock Parity

• Slave Select Synchronization (Slave mode only)

• Daisy chain connection of slave devices

Figure 15-1 is a block diagram of the SPI interface

module.

FIGURE 15-1: MSSPx BL O CK DIAGRAM (SPI MODE)

( )

Read Write

Data Bus

SSPxSR Re g

SSPxM<3:0>

bit 0 Shift

Clock

SSxControl

Enable

Edge

Select

Clock Select

TMR2 Output

TOSC

Prescaler

4, 16, 64

Edge

Select

2 (CKP, CKE)

TRIS bit

SDOx

SSPxBUF Reg

SDIx

SSx

SCKx

Baud Rate

Generator

(SSPxADD)

PIC18(L)F2X/4XK22

DS41412F-page 212  2010-2012 Microchip Technology Inc.

The I2C interface supports the following modes and

features:

•Master mode

• Slave mode

• Byte NACKi ng (Slave mode)

• Limited Multi-master support

• 7-bit and 10-bit addressing

• Start and Stop interrupts

• Interrupt masking

• Clock stretching

• Bus collision detection

• General call address matching

•Address masking

• Address Hold and Data Hold modes

• Selectable S DAx hold times

Figure 15-2 is a block diagram of the I2C interface

module in Mas ter mode. Figure 15-3 is a diagram of the

I2C interface module in Slave mode.

The PIC18(L)F2X/4XK22 has two MSSP modules,

MSSP1 and MSSP2, each module operating indepen-

dently from the other.

FIGURE 15-2: MSSPx BLOCK DIAGRAM (I2C™ MASTER MODE)

Note 1: In devices with more than one MSSP

module, it is very important to pay close

attention to SSPxCONx register names.

SSP1CON1 and SSP1CON2 registers

control different operational aspects of

the same module, while SSP1CON1 and

SSP2CON1 control the s ame features for

two different modules.

2: Throughout this section, generic

references to an MSSP module in any of

its operating modes may be interpreted

as being equally applicable to MSSP1 or

MSSP2. Register names, module I/O

signals, and bit names may use the

generic designator ‘x’ to indicate the use

of a numeral to distinguish a particular

module when required.

Read Write

SSPxSR

Start bit, Stop bit,

Start bit Detect,

SSPxBUF

Internal

Data Bus

Set/Reset: S, P, SSPxSTAT, WCOL, SSPxOV

Shift

Clock

MSb LSb

SDAx

Acknowledge

Generate (SSPxCON2)

Stop bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

end of XMIT/RCV

SCLx

SCLx in

Bus Collision

SDAx in

Receive Enable (RCEN)

Clock Cntl

Clock Arbitrate/BC OL Dete ct

(Hold off clock source)

[SSPxM 3:0]

Baud Rate

Reset SEN, PEN (SSPxCON2)

Generator

(SSPxADD)

Address Matc h Detect

Set SSPxIF, BCLxIF

 2010-2012 Microchip Technology Inc. DS41412F- page 213

PIC18(L)F2X/4XK22

FIGURE 15-3: MSSPx BLOCK DIAGRAM (I2C™ SLAVE MODE)

Read Write

SSPxSR Reg

Match Detect

SSPxADD Reg

Start and

Stop bit Detect

SSPxBUF Reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPxSTAT Reg)

SCLx

SDAx

Shift

Clock

MSb LSb

SSPxMSK Reg

PIC18(L)F2X/4XK22

DS41412F-page 214  2010-2012 Microchip Technology Inc.

15.2 SPI Mode Overview

The Serial Peripheral Interface (SPI) bus is a

synchronous serial data communication bus that

operates in Full-Duplex mode. Devices communicate

in a ma ster/slave environment where the master device

initiates the communication. A slave device is

controlled through a chip select known as Slave Select.

The SPI bus specifies four signal connections:

• Ser ial Clock (SCKx)

• Serial Data Out (SDOx)

• Serial Data In (SDIx)

• Slave Select (SSx)

Figure 15-1 shows the block diagram of the MSSPx

module when operating in SPI Mode .

The SPI bus operates with a single master device and

one or more slave devices. When multiple slave

devices are used, an independent Slave Select

connection is required from the master device to each

slave dev ic e.

Figure 15-4 shows a typical connection between a

master device and multiple slave devices.

The mas ter select s only one sla ve at a time. M ost slave

devices have tri-state outputs so their output signal

appears disconnected from the bus when they are not

selected.

Transmissions involve two shift registers, eight bits in

size, o ne in the ma ster and o ne in the sla ve. With eith er

the master or the slave device, data is always shifted

out one b it at a time , with the Mo st Signifi cant bit (M Sb)

shifted out first. At the same time, a new Least

Significant bit (LSb) is shifted into the same register.

Figure 15-5 shows a typical connection between two

processors configured as master and slave devices.

Data is shifted out of both shift registers on the

programmed clock edge and latched on the opposite

edge of the clock .

The master device transmits information out on its

SDOx output pin which is connected to, and received

by, th e slav e’s SDIx i nput pin. T he sla ve dev ice tra ns-

mits information out on its SDOx output pin, which is

connec ted to , a nd rec ei ve d by, the m aster’s SDIx inp ut

pin.

To begin communication, the master device first sends

out the clock signal. Both the master and the slave

devices should be configured for the same clock

polarity.

The mas ter device sta rts a trans mission by sending out

the MSb from its shift register. The slave device reads

this bit from that same line and saves it into the LSb

position of its shift register.

During each SPI clock cycle, a full-duplex data

transmi ssion occurs. This means that at the sam e time,

the slave device is sending out the MSb from its shift

that same line and saving it as the LSb of its shift

Aft er 8 bits have bee n shif ted out, the maste r and slav e

have exchanged register values.

If there is more data to exchan ge, the shif t registers are

loaded with new data and the process repeats itself.

Whether the data is meaningful or not (dummy data),

depends on the application software. This leads to

three scenarios for data transmission:

• Master sends use ful dat a and sl ave sends dummy

data.

• Master sends useful data and slave sends useful

data.

• Master sends dummy data and slave sends use ful

data.

Transmissions may involve any number of clock

cycles. When there is no more data to be transmitted,

the master stops sending the clock signal and it

deselects the slave.

Every slave device connected to the bus that has not

been selected through its slave select line must disre-

gard the clock and transmission signals and must not

transmit out any data of its own.

 2010-2012 Microchip Technology Inc. DS41412F- page 215

PIC18(L)F2X/4XK22

FIGURE 15-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION

15.2.1 SPI MODE REGISTERS

The MSSPx module has five registers for SPI mode

operation. These are:

• MSSPx STATUS register (SSPxSTAT)

• MSSPx Control register 1 (SSPxCON1)

• MSSPx Control register 3 (SSPxCON3)

• MSSPx Data Buffer register (SSPxBUF)

• MSSPx Address register (SSPxADD)

• MSSPx Shift register (SSPxSR)

(Not directly accessible)

SSPxCON1 and SSPxSTAT are the control and

STATUS registers in SPI mode operation. The

SSPxCON1 register is readable and writable. The

lower 6 bit s of the SSPxSTA T are read-on ly. The upper

two bits of the SSPxSTAT are read/write.

In one SPI Master mode, SSPxADD can be loaded

with a value used in the Baud Rate Generator. More

information on the Baud Rate Gen e rator is available in

Section 15.7 “Baud Rate Generator”.

SSPxSR is the shift register used for shifting data in

and out. SSPxBUF provides indirect access to the

SSPxSR register. SSPxBUF is the buffer register to

which data bytes are written, and from which data

bytes are read.

In receive operations, SSPxSR and SSPxBUF

together create a buffered receiver. When SSPxSR

receives a co mplete by te, i t is tran sf erred to SSPx BUF

and the SSPxIF interrupt is set.

During transmission, the SSPxBUF is not buffered. A

write to SSPxBUF will write to both SSPxBUF and

SSPxSR.

15.2.2 SPI MODE OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCKx is the clock output)

• Slave mode (SCKx is the clock input)

• Clock Pola rity (Idle state of SCKx)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCKx)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

To enable the serial port, SSPx Enab le bit, SSPxEN of

the SSPxCON1 register , must be set. To reset or recon-

figure SPI mode, clear the SSPxEN bit, re-initialize the

SSPxCONx registers and then set the SSPxEN bit.

This configures the SDIx, SDOx, SCKx and SSx pins

as serial port pins. For the pins to behave as the serial

port function, some must have their data direction bits

(in the TRIS register) appropriately programmed as fol-

lows:

• SDIx must have corresponding TRIS bit set

• SDOx mus t have correspondin g TRIS bit cleared

• SCKx (Master mode) must have corresponding

TRIS bit cleared

• SCKx (Slave mode) must have corresponding

TRIS bit set

• SSx must have corresponding TRIS bit set

SPI Master SCLK

SDOx

SDIx

General I/O

SCLK

SDIx

SDOx

SSx

SPI Slave

SCLK

SDIx

SDOx

SSx

SPI Slave

SCLK

SDIx

SDOx

SSx

SPI Slave

PIC18(L)F2X/4XK22

DS41412F-page 216  2010-2012 Microchip Technology Inc.

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

The MSSPx con sist s of a tran smit/ receiv e shif t reg ister

(SSPxSR) and a buffer register (SSPxBUF). The

SSPxSR shifts the data in and out of the device, MSb

first. The SSPxBUF holds the data that was written to

the SSPxSR until the received data is ready. Once the

8 bit s of dat a ha ve been received, that byte is mov ed to

the SSPxBUF regi st er. Then, the Buffe r Full Dete ct bi t,

BF of the SSPx STAT regi ster, and the inte rrupt fla g bi t,

SSPxIF, are set. This double-buffering of the received

data (SSPx BUF) al lows the nex t by te to st a rt re ce ptio n

before reading the data that was just received. Any

write to the SSPxBUF register during transmission/

reception of data will be ignored and the write collision

detect bit, WCOL of the SSPxCON1 register, will be

set. User sof tware must clear the WCOL bit to allow the

following write(s) to the SSPxBUF register to complete

successfully.

When the application software is expecting to receive

valid data, the SSPxBUF should be read before the

next byte of da ta to transfer is written to the SSPxBUF.

The Buffer Full bit, BF of the SSPxSTAT register,

indicates when SSPxBUF has been loaded with the

received data (transmission is complete). When the

SSPxBUF is read, the BF bit is cleared. This data may

be irrelevant if the SPI is only a transmitter. Generally,

the MSSPx interrupt is used to determine when the

transmission/reception has completed. If the interrupt

method is not going to be used, then software polling

can be done to ensure that a write collision does not

occur.

FIGURE 15-5: SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(BUF)

Shift Register

(SSPxSR)

MSb LSb

SDOx

SDIx

Processor 1

SCKx

SPI Master SSPxM<3:0> = 00xx

Serial Input Buf fe r

(SSPxBUF)

Shift Register

(SSPxSR)

LSb

MSb

SDIx

SDOx

Processor 2

SCKx

SPI Slave SSPxM<3:0> = 010x

Serial Clock

SSx

Slave Select

General I/O (optional)

= 1010

 2010-2012 Microchip Technology Inc. DS41412F- page 217

PIC18(L)F2X/4XK22

15.2.3 SPI MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCKx line. The master

determines when the slave (Processor 2, Figure 15-5)

is to broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPxBUF register is written to. If the SPI

is only goi ng to rec ei ve, the SDOx outpu t cou ld be di s-

abled (pro grammed as an input). The SSPxSR reg ister

will continue to shift in the signal present on the SDIx

pin at the programmed clock rate. As each byte is

received, it will be load ed into the SSPxBUF register a s

if a normal received byte (interrupts and Status bits

appropriately set).

The clock polarity is selected by appropriately

programming the CKP bit of the SSPxCON1 register

and the CKE bit of the SSPxSTAT register. This then,

would give waveforms for SPI communication as

shown in Figure 15-6, Figure 15-8, Figure 15-9 and

Figure 15-10, where the MSB is transmitted first. In

Master mode, the SPI clock rate (bit rate) is user

programmable to be one of the following:

•F

OSC/4 (or TCY)

•FOSC/16 (or 4 * TCY)

•FOSC/64 (or 16 * TCY)

• Timer2 output/2

•F

OSC/(4 * (SSPxADD + 1))

Figure 15-6 shows the waveforms for Master mode.

When the CKE bit is se t, the SDOx dat a is va lid befo re

there is a clock e dge on SC Kx. The cha nge of the i nput

sample is shown based on the state of the SMP bit. The

time when the SSPxBUF is loaded with the received

dat a is shown.

FIGURE 15-6: SPI MODE WAVEFORM (MASTER MODE)

SCKx

(CKP = 0

SCKx

(CKP = 1

SCKx

(CKP = 0

SCKx

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDIx bit 7 bit 0

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

bit 7

SDIx

SSPxIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPxBUF

SSPx SR to

SSPxBUF

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)

bit 0

PIC18(L)F2X/4XK22

DS41412F-page 218  2010-2012 Microchip Technology Inc.

15.2 .4 SPI SLAVE MODE

In Slave m ode , the data is transmitted and rece iv ed a s

external clock pulses appear on SCKx. When the last

bit is latched, the SSPxIF inte rrupt flag bit is set.

Before enabling the module in SPI Slave mode, the clock

line must match the proper Idle state. The clock line can

be observed by reading the SCKx pin. The Idle state is

determined by the CKP bit of the SSPxCON1 register.

While in Slave mode, the external clock is supplied by

the external clock source on the SCKx pin. This exter-

nal clock must meet the minimum high and low times

as specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. The shift register is clocked from the SCKx pin

input and when a byte is received, the device will gen-

erate an interrupt. If enabled, the device will wake-up

from Sleep.

15.2.4.1 Daisy-Chain Configuration

The SPI bus can sometimes be connected in a daisy-

chain c on fig uration. The first sla ve output is connected

to the second slave input, the second slave output is

connected to the third slave input, and so on. The final

slave output is connected to the master input. Each

slave sends out, during a second group of clock

pulses, an exact copy of what was received during the

first group of clock pulses. The whole chain acts as

one large communication shift register. The daisy-

chain feature only requires a single Slave Select line

from the master device.

Figure 15-7 shows the block diagram of a typical

daisy-c ha in co nne cti on w hen operati ng in SPI Mode.

In a daisy-chain configuration, only the most recent

byte on the bus is required by the slave. Setting the

BOEN bit of the SSPxCON3 regi ster will enable writes

to the SSPxBUF re gis te r, even if the previo us byt e ha s

not been read. This allows the software to ignore data

that may not apply to it.

15.2.5 SL AV E SELE CT

SYNCHRONIZATION

The Slave Select can also be used to synchronize

commu nication. The Slave Selec t l ine is hel d hi gh u ntil

the master device is ready to communicate. When the

Slave Select line is pulled low, the slave knows that a

new transmission is starting.

If the slave fai ls to receive the commu nication properl y,

it will be reset at the en d of the trans m is sion, w hen the

Slave Select line returns to a high state. The slave is

then ready to receive a new transmission when the

Slave Se lect line is pulled low again . If the Sl ave Selec t

line is not used, there is a risk that the slave will even-

tually become out of sync with the master. If the slave

misses a bit , it wi ll always be one bi t of f in future trans -

missions. Use of the Slave Select line allows the slave

and master to align themselves at the beginning of

each transmission (Figure 15-8).

The SSx pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SSx pin control

enabled (SSPxCON1<3:0> = 0100).

When the SSx pin is low, transmission and reception

are enabled and the SDOx pin is driven.

When t he SSx pin goes hi gh, the SDOx pin is no longer

driven, even if in the middle of a transmitted byte and

becomes a floating output. External pull-up/pull-down

resistors may be desirable depending on the applica-

tion.

When the SPI module resets, the bit counter is forced

to ‘0’. Th is can be don e by eith er forcin g the SSx pin to

a high level or clearing the SSPxEN bit.

Note 1: When the SPI is in Slave mode with SSx

pin control enabled (SSPxCON1<3:0> =

0100), the SPI module will reset if the SSx

pin is set to VDD.

2: When the SPI is us ed in Slav e mode with

CKE set; the user must enable SSx pin

control.

3: While operated in SPI Slave mode the

SMP bit of the SSPxSTAT register must

remain clear.

 2010-2012 Microchip Technology Inc. DS41412F- page 219

PIC18(L)F2X/4XK22

FIGURE 15-7: SPI DAISY-CHAIN CONNECTION

FIGURE 15-8: SLAVE SELECT SYNCHRONOUS WAVEFORM

SPI Master SCLK

SDOx

SDIx

General I/O

SCLK

SDIx

SDOx

SSx

SPI Slave

SCLK

SDIx

SDOx

SSx

SPI Slave

SCLK

SDIx

SDOx

SSx

SPI Slave

SCKx

(CKP = 1

SCKx

(CKP = 0

Input

Sample

SDIx bit 7

SDOx bit 7 bit 6 bit 7

SSPxIF

Interrupt

CKE = 0)

Write to

SSPxBUF

SSPx SR to

SSPxBUF

SSx

Flag

bit 0

bit 7 bit 0

bit 6

SSPxBU F to

SSPxSR

Shift register SSPxSR

and bit count are reset

PIC18(L)F2X/4XK22

DS41412F-page 220  2010-2012 Microchip Technology Inc.

FIGURE 15-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

FIGURE 15-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SCKx

(CKP = 1

SCKx

(CKP = 0

Input

Sample

SDIx bit 7

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPxIF

Interrupt

CKE = 0)

Write to

SSPxBUF

SSPxSR to

SSPxBUF

SSx

Flag

Optional

bit 0

detection active

Write Collision

Valid

SCKx

(CKP = 1

SCKx

(CKP = 0

Input

Sample

SDIx bit 7 bit 0

SDOx b i t 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPxIF

Interrupt

CKE = 1)

Wr i te to

SSPxBUF

SSPxS R to

SSPxBUF

SSx

Flag

Not Optional

Write Collision

detection active

Valid

 2010-2012 Microchip Technology Inc. DS41412F- page 221

PIC18(L)F2X/4XK22

15.2.6 SPI OPERATION IN SLEEP MODE

In SPI Master mo de, modu le clo cks may be op erati ng

at a different speed than when in Full-Power mode; in

the case of the Sleep mode, all clocks are halted.

Special care must be taken by the user when the

MSSPx clock is much faster than the system clock.

In Slave mode, when MSSPx interrupts are enabled,

after the master completes sending data, an MSSPx

interrupt will wake the controller from Sleep.

If an exit from Sleep mode is not desired, MSSPx

interrupts should be disabled.

In SPI Master mode, when the Sleep mode is selected,

all module clocks are halted and the transmission/

reception will remain in that state until the device

wakes. After the device returns to Run mode, the

module will resume transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

allow s th e d ev ice to be placed in Sleep mode and data

to be shifted into the SPI Transmit/Receive Shift

MSSPx interrupt flag bit will be set and if enabled, will

wake the devic e.

TABLE 15-1: REGISTERS ASSOCIATED WITH SPI OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELA — — ANSA5 —ANSA3 ANSA2 ANSA1 ANSA0 154

ANSELB — — ANSB5 ANSB4 ANSB3(1) ANSB2(1) ANSB1(1) ANSB0(1) 155

ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 155

ANSELD ANSD7 ANSD6 ANSD5 ANSD4(2) ANSD3(2) ANSD2 ANSD1(2) ANSD0(2) 155

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

PMD1 MSSP2MD MSSP1MD —CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 56

SSP1BUF SSP1 Receive Bu ffer/Transmit Register —

SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 260

SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 263

SSP1STAT SMP CKE D/A P S R/W UA BF 259

SSP2BUF SSP2 Receive Bu ffer/Transmit Register —

SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 260

SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 263

SSP2STAT SMP CKE D/A P S R/W UA BF 259

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 156

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3(1) TRISB2(1) TRISB1(1) TRISB0(1) 156

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 156

TRISD TRISD7 TRISD6 TRISD5 TRISD4(2) TRISD3(2) TRISD2 TRISD1(2) TRISD0(2) 156

Legend: Shaded bits are not used by the M SSPx in SPI mod e.

Note 1: PIC18(L)F2XK22 devices.

2: PIC18(L)F4XK2 2 devices.

PIC18(L)F2X/4XK22

DS41412F-page 222  2010-2012 Microchip Technology Inc.

15.3 I2C Mode Overview

The Inter-Integrated Circuit Bus (I2C) is a multi-master

serial data communication bus. Devices communicate

in a master/slave environment where the master

devices initiate the communication. A slave device is

controlled through addressing.

The I2C bus specifies two signal connections:

• Ser ial Clock (SCLx)

• Serial Data (SDAx)

Figure 15-2 shows the block diagram of the MSSPx

module when operating in I2C mode.

Both the SCL x and SDAx conn ectio ns are bid irecti onal

open-drain lines, eac h requiring pull-up resistors for the

supply vo ltage. Pulling the line to ground is con si dere d

a logical zero and letting the line float is cons idered a

logical one.

Figure 15-11 shows a typical connection between two

processors configured as master and slave devices.

The I2C bus can operate with one or more master

devices and one or more slave devices.

There are four potential mo des o f operation for a g ive n

device:

• Master Transmit mod e

(master is transmitting data to a slave)

• Master Receive mode

(master is rec eiv in g dat a from a slave )

•Slave Transmit mode

(slave is transmitting data to a master)

• Sla ve Rece ive mode

(slave is receiving data from the master)

To begin communication, a master device starts out in

Master T ransmit mode. The master device sends out a

Start bit followed by the address byte of the slave it

intends to communicate with. This is followed by a sin-

gle Rea d/Write bit, which determines w hether the ma s-

ter inten ds to transmit to or receive data from the s lav e

device.

If the requested slave exists on the bus, it will respond

with an Acknowledge bit, otherwis e kno wn as an ACK.

The master then continues in either Transmit mode or

Receive mode and the slave continues in the comple-

ment, either in Receive mode or Transmit mode,

respectively.

A Start bit is indicated by a high-to- lo w transi tio n of the

SDAx line while the SCLx line is held high. Address and

data bytes are se nt out, Most Signifi cant b it (MSb) firs t.

The Read/Write bit is sent out as a lo gical one when the

master in ten ds to read data from the slave, a nd is se nt

out as a logic al zero w hen it i ntends to write d at a to th e

slave.

FIGURE 15-11: I2C™ MASTER/

SLAVE CONNECTION

The Acknowledge bit (ACK) is an active-low signal,

which holds the SDAx line low to indicate to the

transmitter that the slave device has received the

transmitted data and is ready to receive more.

The transition of data bits is always performed while the

SCLx line is held low. Transitions that occur while the

SCLx line is held high are used to indicate Start and

Stop bits.

If the master intends to write to the slave, then it

repeatedly sends out a byte of data, with the slave

responding after each byte with an ACK bit. In this

example, the master device is in Master T ransmit mode

and the slave i s in Sl ave Receive mode.

If the master intends to read from the slave, then it

repeatedly receives a byte of data from the slave, and

responds after each byte with an ACK bit. In this

exampl e, the master de vice is in Ma ster Rece ive mod e

and the slave is Slave Transmit mode.

On the last byte of data communicated, the master

device may end the t ransmiss ion by sendi ng a S top bit.

If the master device is in Receive mode, it sends the

Stop bit in place of the last ACK bit. A Stop bit is

indicated by a low-to-high transition of the SDAx line

while the SCLx line is held high.

In some cases, the master may want to maintain con-

trol of the bus and re-initiate another transmission. If

so, the master device may send another Start bit in

place of th e S top bit or last ACK bit when it is in receiv e

mode.

The I2C bus specifies three me ssage protocols;

• Single message where a master writes data to a

slave.

• Single message where a master reads data from

a slave.

• Combined message where a master initiates a

minimum of two writes, or two reads, or a

combination of writes and reads, to one or more

slaves.

Master

SCLK

SDIx

SCLK

SDOx

Slave

VDD

 2010-2012 Microchip Technology Inc. DS41412F- page 223

PIC18(L)F2X/4XK22

When one devi ce is transmit ting a logical on e, or letting

the line float, and a second device is transmitting a

logical zero, or holdin g the lin e low , the first device can

detect that the line is not a logical one. This detection,

when us ed on the SCLx lin e, is call ed cl oc k stre tc hin g.

Clock stretching give slave devices a mechanism to

control th e flow of da ta. When this detectio n is used on

the SDAx line, it is called arbitration. Arbitration

ensures that there is only one master device

communicating at an y single time.

15.3.1 CLOCK STRETCHING

When a slave device has not completed processing

data, it can del ay th e tran sfe r of more data through the

process of clock stretching. An addressed slave device

may hold the SCLx clock line low after receiving or

sending a bit, indicating that it is not yet ready to

continue. The master that is communicating with the

slave will attempt to raise the SCLx line in order to

transfer the next bit, but will detect that the clock line

has not yet been released. Because the SCLx

connection is open-drain, the slave has the ability to

hold that line low until it is ready to continue

communicating.

Clock stretching allows receivers that cannot keep up

with a transmitter to control the flow of incoming data.

15.3.2 ARBITRATION

Each mas ter d ev ice mu st m on itor the bus fo r St art an d

Stop bits. If the device detects that the bus is busy, it

cannot b egin a new message u ntil the bus returns to a n

Idle st a te.

However, two master devices may try to initiate a

transmission on or about the same time. When this

occurs, the process of arbitration begins. Each

transmitter checks the level of the SDAx data line and

compares it to the level that it expects to find. The first

transmitter to observe that the two levels don’t match,

loses arbitration, and must stop transmitting on the

SDAx line.

For example, if one transmitter holds the SDAx line to

a logical one (lets it float) and a second transmitter

holds it to a logical zero (pulls it low), the result is that

the SDAx line will be low. The first transmitter then

observes that the level of the line is different than

expected and concludes that another transmitter is

communicating.

The first transmitter to notice this difference is the one

that loses arbitration and must stop driving the SDAx

line. If this transmitter is also a master device, it also

must st op driv ing th e SCLx line. It then c an mo nitor th e

lines for a Stop condition before trying to reissue its

transmission. In the meantime, the other device that

has not noticed any difference between the expected

and actual levels on the SDAx line continues with its

original transmission. It can do so without any compli-

cations, because so far, the transmission appears

exactl y as expecte d with no other t ransmitter dis turbing

the message.

Slave Transmit mode can also be arbitrated, when a

master addresses multiple slaves, but this is less

common.

If two master devices are sending a message to two

diff erent sla ve devices a t the address stage, the master

sending the lower slave address always wins

arbitration. When two master devices send messages

to the same slave address, and addresses can

sometimes refer to multiple slaves, the arbitration

process must continue into the data stage.

Arbitration usually occurs very rarely, but it is a

necessary process for proper multi-master support.

PIC18(L)F2X/4XK22

DS41412F-page 224  2010-2012 Microchip Technology Inc.

15.4 I2C Mode Operation

All MSSPx I2C communication is byte oriented and

shifted out MSb first. Six SFR registers and 2 interrupt

flags interface the module with the PIC® microcon-

troller and user software. Two pins, SDAx and SCLx,

are exercised by the module to communicate with

other external I2C devices.

15.4.1 BYTE FORMAT

All communication in I2C is done in 9-bit segments. A

byte is sent from a master to a slave or vice-versa,

followed by an Acknowledge bit sent back. After the

8th falling edge of the SCLx line, the device outputting

data on the SDAx changes that pin to an input and

reads in an acknowledge value on the next clock

pulse.

The clock signal, SCLx, is provided by the master.

Data is valid to change while the SCLx signal is low,

and sampled on the rising edge of the clock. Changes

on the SDAx line while the SCLx line is high define

special conditions on the bus, explained below.

15.4.2 DEFINITION OF I2C TERMINOLOGY

There is language and terminology in the description

of I2C communication that have definitions specific to

I2C. That word usage is defined below and may be

used in the rest of this document without explana-

tion. This table was adapted from the Phillips I2C

specification.

15.4.3 SDAx AND SCLx PINS

Selection of any I2C mode with the SSPxEN bit set,

forces the SCLx and SDAx pins to be open-drain.

These pins should be set by the user to inputs by

setting the appropriate TRIS bits.

15.4.4 SDAx HOLD TI ME

The hold time of the SDAx pin is selected by the

SDAHT bit of the SSPxCON3 register. Hold time is the

time SDAx is held valid after the falling edge of SCLx.

Setting the SDAHT bit selects a longer 300 ns mini-

mum hold time and may help on buses with large

capacitance.

TABLE 15-2: I2C™ BUS TERMS

Note: Data is tied to output zero when an I2C

mode is enabled.

TERM Description

Transmitter T he device w hich shifts data out

onto the bus.

Receiver The device which shifts data in

from the bus.

Master The devi ce that in itiates a tran sfer,

generates clock signals and termi-

nates a transfer.

Slave The device addressed by the mas-

ter.

Multi-master A bus with more than one device

that can initiate data transfers.

Arbitration Procedure to ensure t hat only one

master at a time controls the bus.

Winning arbitration ensures that

the messa ge is not co rrupt ed.

Synchronization Procedure to synchronize the

clocks of two or more devices on

the bus.

Idle No master is controlling the bus,

and both SDAx and SCLx lines are

high.

Active Any time one or more master

devices are controlling the bus.

Addressed

Slave Slave device that has received a

matching address and is actively

being clocked by a master.

Matching

Address Ad dress by te that is cloc ked into a

slave that matches the value

stored in SSPxADD.

Write Request S lave receives a matching

address with R/W bit clear, and is

ready to clock in data.

Read Request Mas ter sends an address byte with

the R/W bit set, indicating that it

wishes to clock data out of the

Slave. This data is the next and all

following bytes until a Restart or

Stop.

Clock Stretching When a device on the bus holds

SCLx low to stall communication.

Bus Collision Any time the SDAx lin e is sa mpled

low by the module while it is out-

putting and expected high state.

 2010-2012 Microchip Technology Inc. DS41412F- page 225

PIC18(L)F2X/4XK22

15.4.5 START CONDITION

The I2C specification defines a Start condition as a

transiti on of SDAx from a hi gh-to -lo w st ate while SCL x

line is high. A Start condition is always generated by

the master and signifies the transition of the bus from

an Idle to an active state. Figure 15-12 shows wave

forms for Start and Stop conditions.

A bus collision can occur on a Start condition if the

modul e samples the SDAx line low be fore asse rting i t

low. This does not conform to the I2C specification that

states no bus collision can occur on a Start.

15.4.6 STOP CONDITION

A Stop condition is a transition of the SDAx line from a

low-to-high state while the SCLx line is high.

15.4.7 RESTART CONDITION

A Restart is valid any time that a Stop would be valid.

A master can issue a Restart if it wishes to hold the

bus after terminating the current transfer. A Restart

has the same effect on the slave that a Start would,

resetting all slave logic and preparing it to cloc k in an

address . The mas te r may want to ad dress th e same or

another sl ave. Figure 15-13 shows the wave form for a

Restart condition.

In 10-bit Addressing Slave mode a Restart is required

for the master to clock data out of the addressed slave.

Once a slave h as b een fully add re ssed, ma tchi ng bot h

high and low address bytes, the master can issue a

Restart and the high address byt e with the R/W bit set.

The slave logic will then hold th e clock and prepare to

clock out data.

After a fu ll m atc h wi th R/W clear in 10-b it mode, a prior

match flag is set and maintained. Until a Stop

condition, a high address with R/W clear, or high

address match fails.

15.4.8 ST ART/STOP CONDITION INTERRUPT

MASKING

The SCIE and PCIE bits of the SSPxCON3 register

can enable the generation of an interrupt in Slave

modes t hat do not typically su ppo rt th is function. Slave

modes where interrupt on Start and Stop detect are

already enabled, these bits will have no effect.

FIGURE 15-12 : I2C™ STAR T AND STOP CONDITIONS

FIGURE 15-13 : I2C™ RESTART CONDITION

Note: At least one SCLx low time must appear

before a St op i s va lid , th eref ore, if the SDAx

line go es low then hig h again while the SCLx

line stays high, only the Start condition is

detected.

SDAx

SCLx P

Stop

Condition

Start

Condition

Change of

Data Allowed

Change of

Data Allowed

Restart

Condition

Change of

Data Allowed

Change of

Data Allowed

PIC18(L)F2X/4XK22

DS41412F-page 226  2010-2012 Microchip Technology Inc.

15.4.9 ACKNOWLEDGE SEQUENCE

The 9th SCLx pulse for any transferred byte in I2C is

dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling

the SDAx line low. The transmitter must release con-

trol of the line during this time to shift in the response.

The Acknowledge (ACK) is an active-low signal, pull-

ing the SDAx line low indicated to the transmitter that

the device has received the transmitted data and is

ready to receive more.

The result of an ACK is placed in the ACKSTAT bit of

the SSPxCON2 register.

Slave software, when the AHEN and DHEN bits are

set, allow the user to set the ACK value sent back to

the transmitter. The ACKDT bit of the SSPxCON2

Slave hardware will generate an ACK response if the

AHEN and DHEN bits of the SSPxCON3 register are

clear.

There are certain conditions where an ACK will not be

sent by the slave. If the BF bit of the SSPxSTAT

are set when a by te is received.

When the module is addressed, after the 8th falling

edge of SCLx on the bus, the ACKTIM bit of the

SSPxCON3 register is set. The ACKTIM bit indicates

the acknowledge time of the active bus.

The A CKTIM Sta tus bit is only ac tive wh en the AH EN

bit or DHEN bit is enabled.

15.5 I2C Slave M ode Operation

The MSSPx Slave mode operates in one of four

modes selected in the SSPxM bits of SSPxCON1

Addressing mode. 10-bit Addressing modes operate

the same as 7-bit with some additional overhead for

handling the larger addresses.

Modes with Start and Stop bit interrupts operated the

same as the other modes with SSPxIF additionally

getting set upon detection of a Start, Restart, or Stop

condition.

15.5.1 SLAVE MODE ADDR ES SE S

The SSPxADD register (Register 15-6) contains the

Slave mode address. The first byte received after a

Start or Restart condition is compared against the

value stored in this register. If the byte matches, the

value is loaded into the SSPxBUF register and an

interrupt is generated. If the value does not match, the

module goes Idle and no indication is given to the

softw a re that any thi ng hap pen ed.

The SSPx Mask register (Register 15-5) affects the

address matching process. See Section 15.5.9

“SSPx Mask Register” for more information.

15.5.1.1 I2C Slave 7-bit Addressing Mode

In 7-bit Address ing mode, the LSb of the rec eived dat a

byte is i gnored wh en determ ining if there i s an add ress

match.

15.5.1.2 I2C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is

comp are d t o th e b ina ry v al ue of ‘ 1 1 1 1 0 A9 A8 0’. A9

and A8 are the two MSb of the 10-bit address and

stored in bits 2 and 1 of the SSPxADD register.

After the acknowledge of the high byte the UA bit is set

and SCLx is held low until the user updates SSPxADD

with the low address. The low address byte is clocked

in and all eight bits are compared to the low address

value in SSPxADD. Even if there is not an address

match; SSPxIF and UA are set, and SCLx is held low

until SSPxADD is updated to receive a high byte

again. When SSPxADD is updated the UA bit is

cleared. This ensures the module is ready to receive

the high address byte on the next communication.

A high and low address match as a write request is

required at the start of all 10-bit addressing

communication. A transmission can be initiated by

issuing a Restart once the slave is addressed, and

clocking in the high address with the R/W bit set. The

slave hardware will then acknowledge the read

request and prepare to clock out data. This is only

valid for a slave after it has received a complete high

and low address byte match.

 2010-2012 Microchip Technology Inc. DS41412F- page 227

PIC18(L)F2X/4XK22

15.5.2 SLAVE RECEPTION

When the R/W bit of a m atc hin g re ce iv ed add res s by te

is clear, the R/W bit of the SSPxSTAT register is

cleared. The received address is loaded into the

SSPxBUF register and acknowledged.

When the overflow condition exists for a received

address, then not Acknowledge is given. An overflow

condition is defined as either bit BF of the SSPxSTAT

ter is set. The BOEN bit of the SSPxCON3 register

modifies this operation. For more information see

An MSSPx interrupt is generated for each transferred

data byte. Flag bit, SSPxIF, must be cleared by

software.

When the SEN bit of the SSPxCON2 register is set,

SCLx will be held low (clock stretch) following each

received byte. The clock must be released by setting

the CKP bit of the SSPxCON1 register, except

sometimes in 10-bit mode. See Section 15.2.3 “SPI

Master Mode” for more detail.

15.5.2.1 7-bit Addressing Reception

This section describes a standard sequence of events

for the MSSPx module configured as an I2C slave in

7-bit Addressing mode. All decisions made by hard-

ware or software and their effect on reception.

Figure 15-14 and Figure 15-15 are used as a visual

reference for this description.

This is a step by step process of what typically must

be done to accomplish I2C communication.

1. Start bit detected.

2. S bit of SSPxSTAT is set; SSPxIF is set if

interrupt on Start detect is enabled.

3. Matching a ddress with R/W bit clear i s received.

4. The slave pul ls SDAx low sending an ACK to the

master, and sets SSPxIF bit.

5. Software clears the SSPxIF bit.

6. Software reads received address from

SSPxBUF clearing the BF flag.

7. If SEN = 1; Slave software sets CKP bit to

release the SCLx line .

8. The master clocks out a data byte.

9. Slave drives SDAx low sending an ACK to the

master, and sets SSPxIF bit.

10. Software clears SSPxIF.

11. Software reads the received byte from

SSPxBUF clearing BF.

12. Steps 8-12 are repeated for all received bytes

from the master.

13. Master sends Stop condition, setting P bit of

SSPxSTAT, and the bus goes Idle.

15.5.2.2 7-bit Reception with AHEN and DHEN

Slave device reception with AHEN and DHEN set

operate the same as without these options with extra

interrupts and clock stretching added after the 8th fall-

ing edge of SCLx . These additi onal in terrupt s al low the

slave software to decide whether it wants to ACK the

receive address or data byte, rather than the hard-

ware. This fun cti ona li ty a dds support for PMBus™ that

was not present on previous versions of this module.

This list describes the steps that need to be taken by

slave software to use these options for I2C

communication. Figure 15-16 display s a m odule usi ng

both address and data holding. Figure 15-17 includes

the operation with the SEN bit of the SSPxCON2

1. S bit of SSPxSTAT is set; SSPxIF is set if

interrupt on Start detect is enabled.

2. Matching address with R/W bit clear is clocked

in. SSPxIF is set and CKP cleared after the 8th

falling edge of SCLx.

3. Slave clears the SSPxIF.

4. Slave can look at the ACKTIM bit of the

SSPxCON3 register to determine if the SSPxIF

was after or before the ACK.

5. Slave reads the address value from SSPxBUF,

clearing the BF flag.

6. Slave sets ACK va lue cloc ke d out to the mast er

by setting ACKDT.

7. Slave releases the clock by setting CKP.

8. SSPxIF is set after an ACK, not after a NACK.

9. If SEN = 1 the slave hardware will stretch the

clock after the ACK.

10. Slave clears SSPxIF.

11. SSPxIF set and CKP cleared after 8th falling

edge of SCLx for a received data byte.

12. Slave looks at ACKTIM bit of SSPxCON3 to

determine the source of the interrupt.

13. Slave reads the received data from SSPxBUF

clearing BF.

14. Steps 7-14 are the same for each received data

byte.

15. Communication is ended by either the slave

sending an ACK =1, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop detect is disabled, the slave will only know

by po lling th e P bit of the SST STAT reg ister.

Note: SSPxIF is still set after the 9th falling edge of

SCLx e ven if there is no clock s tretching an d

BF has been cleared. Only if NACK is sent

to master is SSPxIF not set.

PIC18(L)F2X/4XK22

DS41412F-page 228  2010-2012 Microchip Technology Inc.

FIGURE 15-14 : I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)

Receiving Address

ACK

Receiving Data

ACK

Receiving Data ACK =1

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDAx

SCLx

SSPxIF

SSPxOV

12345678 12345678 12345678

999

ACK is not sent.

SSPxOV set because

SSPxBUF is still full.

Cleared by software

First byte

of data is

available

in SSPxBUF

SSPxBUF is read

SSPxIF set on 9th

falling edge of

SCLx

Cleared by software

Bus Master sends

Stop condi tion

From Slave to Master

 2010-2012 Microchip Technology Inc. DS41412F- page 229

PIC18(L)F2X/4XK22

FIGURE 15-15 : I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

SEN SEN

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0SDAx

SCLx 123456789 123456789 123456789 P

SSPxIF set on 9th

SCLx is not held

CKP is written to 1 in software,

CKP is written to ‘ 1’ in software,

ACK

low because

falling edge of SCLx

releasing SCLx

ACK is not sent.

Bus Master sends

CKP

SSPxOV

SSPxIF

SSPxOV set because

SSPxBUF is still full.

Cleared by software

First byte

of data is

available

in SSPxBUF

ACK=1

Cleared by software

SSPxBUF is read

Clock is held low until CKP is set to ‘1’

relea sing S C Lx

Stop condition

ACK ACK

Receive Address Receive Data Receive Data

R/W=0

PIC18(L)F2X/4XK22

DS41412F-page 230  2010-2012 Microchip Technology Inc.

FIGURE 15-16 : I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)

Receiving Address Receiving Data Received Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDAx

SCLx

CKP

12345678 912345678 912345678

Master sends

Stop condition

Data is read from SSPxBUF

Cleared by software

SSPxIF is set on

9th falling edge of

SCLx, after ACK

CKP set by sof tware,

SCLx is released

Slave software

ACKTIM cleared by

hardware in 9th

rising edge of SCLx

sets ACKDT to

not ACK

When DHEN=1:

CKP is cleared by

hardware on 8th falling

edge of SCLx

Slave software

clears ACKDT to

ACK the received

byte

ACKTIM set by hardware

on 8th falling edge of SCLx

When AHEN=1:

CKP is cleared by hardware

and SCLx is stretched

Address is

read from

SSBUF

ACKTIM set by hardware

on 8th falling edge of SCLx

ACK

Master Releases SDAx

to slave for ACK sequence

No interrupt

after not ACK

from Slave

ACK=1

ACK

ACKDT

ACKTIM

SSPxIF If AHEN = 1:

SSPxIF is set

 2010-2012 Microchip Technology Inc. DS41412F- page 231

PIC18(L)F2X/4XK22

FIGURE 15-17 : I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)

Receiving Address Receive Data Receive Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDAx

SCLx

SSPxIF

ACKDT

CKP

ACK

S12345678 912345678 9 12345678 9

ACK ACK

Cleared by software

ACKTIM is cleared by hardware

SSPxBUF can be

Set by software,

read any time be fore

next byte is loaded

release SCLx

on 9th rising edge of SCLx

Received

address is loaded into

SSPxBUF

Slave software cle ars

ACKDT to ACK

R/W = 0Mast er rel e ases

SDAx to slave for ACK sequence

the received byte

When AHEN = 1;

on the 8th falling edge

of SCLx of an address

byte, CKP is cleared

ACKTIM is set by hardware

on 8th falling edge of SCLx

When DHEN = 1;

on the 8th falling edge

of SCLx of a received

data byte, CKP is cleared

Received data is

available on SSPxBUF

Slave sends

not ACK

CKP is not cleared

if not ACK

Master sends

Stop condition

No interrupt after

if not ACK

from Slave

ACKTIM

PIC18(L)F2X/4XK22

DS41412F-page 232  2010-2012 Microchip Technology Inc.

15.5.3 SLAVE TRANSMISSION

When the R/W bi t of the in coming add ress byt e is set

and an address match occurs, the R/W bit of the

SSPxSTAT register is set. The received address is

loaded into the SSPxBUF reg ister , and an ACK pulse is

sent by the slave on the ninth bit.

Following the ACK, slave hardware clears the CKP bit

and the SCLx pin is held low (see Section 15.5.6

“Clock Stretching” for more detail). By stretching the

clock , the master w ill b e unable to ass ert anoth er clock

pulse until the slave is done preparing the transmit

data.

The transmit data must be loaded into the SSPxBUF

the SCLx pin should be releas ed by setting the CKP bit

of the SSPxCON1 register. The eight data bits are

shifted out on the falling edge of the SCLx input. This

ensures that the SDAx signal is valid during the SCLx

high time.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCLx input pulse. This ACK

value is copied to the ACKSTAT bit of t he SSPxCON2

transfer is complete. In this case, w hen the not ACK is

latched by the slave, the slave goes Idle and waits for

another occurrence of the Start bit. If the SDAx line was

low (ACK), the next transmit data must be loaded into

the SSPxBUF register. Again, the SCLx pin must be

released by setting bit CKP.

An MSSPx in terrupt is genera ted for each da ta trans fer

byte. The SSPxIF bit must be cleared by software and

the SSPxSTAT register is us ed to de term in e the status

of the byte . The SSPx IF bi t is set on the fall ing edge of

the ninth clock pulse.

15.5.3.1 Slave Mode Bus Collision

A slave receives a Read request and begins shifting

data out on the SDAx line. If a bus collision is detected

and the SBCDE bit of the SSPxCON3 register is set,

the BCLxIF bit of the PIRx register is set. Once a bus

collis ion is detec ted, the slav e goes Idle a nd waits to b e

addressed again. User software can use the BCLxIF bit

to handle a slave bus collision.

15.5.3.2 7-bit Transmission

A master device can transmit a read request to a

slave, and then clock data out of the slave. The list

below outl ines what s oft war e for a sl ave wil l need to do

to accomplish a standard transmission. Figure 15-18

can be used as a reference to this list.

1. Master sends a Start condition on SDAx and

SCLx.

2. S bit of SSPxSTAT is set; SSPxIF is set if inter-

rupt on Start detect is enabled.

3. Matching address with R/W bit set is received by

the slave setting SSPxIF bit.

4. Slave hardware generates an ACK and sets

SSPxIF.

5. SSPxIF bit is cleared by user.

6. Software reads the received address from

SSPxBUF, clearing BF.

7. R/W is set so CKP was automatically cleared

after the ACK.

8. The slave software loads the transmit data into

SSPxBUF.

9. CKP bit is set rele asing SCLx, allowi ng the mas-

ter to clock the data out of the slave.

10. SSPxIF is set after the ACK response from the

master is loaded into the ACKSTAT register.

11. SSPxIF bit is cleared.

12. The slave software checks the ACKSTAT bit to

see if the master wants to clock out more data.

13. Steps 9-13 are repeated for each transmitted

byte.

14. If the master sends a not ACK; the clock is not

held, but SSPxIF is still set.

15. The ma ster send s a Res tart co nditio n or a Stop.

16. The slave is no longer add res se d.

Note 1: If the master ACKs the clock will be

stretched.

2: ACKSTAT is the only bit updated on the

rising edge of SCLx (9th) rather than the

falling.

 2010-2012 Microchip Technology Inc. DS41412F- page 233

PIC18(L)F2X/4XK22

FIGURE 15-18 : I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)

Receiving Address Automatic Transmitting Data Automatic Transmitting Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDAx

SCLx

SSPxIF

CKP

ACKSTAT

R/W

D/A

Received address

When R/W is set

R/W is copied from the

Indicates an address

is read from SSPxBUF

SCLx is always

held low after 9th SCLx

fall ing edge

matching address byte

has been received

Masters not ACK

is copied to

ACKSTAT

CKP is not

held for not

ACK

BF is automatically

cleared after 8th falling

edge of SCLx

Data to transmit is

loaded into SSPxBUF

Set by software

Cleared by software

ACK

R/W = 1

Master send s

Stop condition

PIC18(L)F2X/4XK22

DS41412F-page 234  2010-2012 Microchip Technology Inc.

15.5.3.3 7-bit Transmission with Address

Hold Enabled

Setting the AHEN bit of the SSPxCON3 register

enables additional clock stretching and interrupt

generation after the 8th falling edge of a received

matching address. Once a matching address has

been clocked in, CKP is cleared and the SSPxIF

interrupt is set.

Figure 15-19 displays a standard waveform of a 7-bit

Address Slave Transmission with AHEN enabled.

1. Bus starts Idl e.

2. Master sends Start condition; the S bit of

SSPxSTAT is set; SSPxIF is set if interrupt on

Start detect is enabled.

3. Master sends matching address with R/W bit

set. After the 8th falling edge of the SCLx line the

CKP bit is cleared and SSPxIF interrupt is

generated.

4. Slave software clears SSPxIF.

5. Slave sof tware reads ACKTIM bi t of SSPxCON3

6. Slave reads the address value from the SSPxBUF

regis ter clearing th e BF bit.

7. Slave software deci des from th is i nfo rma tio n i f it

wishes to ACK or not ACK and sets ACKDT bit

of the SSPxCON2 register accordingly.

8. Slave sets the CKP bi t releasing SCLx.

9. Master clock s in the ACK value from the slave.

10. Slav e hardware autom atically clea rs the CKP bit

and sets SSPxIF after the ACK if the R/W bit is

set.

11. Slave software clears SSPxIF.

12. Slave loads value to transmit to the master into

SSPxBUF setting the BF bit.

13. Slave sets CKP bit releasing the clock.

14. Master clocks out the data from the slave and

sends an A CK value on the 9th SCLx pulse.

15. Slave hardware copies the ACK value into the

ACKSTAT bit of the SSPxCON2 register.

16. Steps 10-15 are repeated for each byte

transmitted to th e master from the slave.

17. If the master sends a not ACK the slave

releases the bus allowing the master to send a

Stop and end the communication.

Note: SSPxBUF cannot be loaded until after the

ACK.

Note: Master must send a not ACK on the last byte

to ensure that the slave releases the SCLx

line to receive a Stop.

 2010-2012 Microchip Technology Inc. DS41412F- page 235

PIC18(L)F2X/4XK22

FIGURE 15-19 : I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)

Receiving Ad dr ess A ut oma ti c Transmitting Data Aut oma tic Transmittin g Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDAx

SCLx

SSPxIF

ACKDT

ACKSTAT

CKP

R/W

D/A

Received address

is read from SSPxBUF

BF is automatically

cleared after 8th falling

edge of SCLx

Data to transmit is

loaded into SSPxBUF

Cleared by software

Slave clears

ACKDT to ACK

address

Master’s ACK

response is copied

to SSPxSTAT

CKP not cleared

after not ACK

Set by software,

releases SCLx

ACKTIM is cleared

on 9th rising edge of SCLx

ACKTIM is set on 8th falling

edge of SCLx

When AHEN = 1;

CKP is cleared by hardware

after receiving matching

address.

When R/W = 1;

CKP is always

cleared after ACK

Master send s

Stop condi tion

ACK

R/W = 1

Master releases SDAx

to slave for ACK sequence

ACK ACK

ACKTIM

PIC18(L)F2X/4XK22

DS41412F-page 236  2010-2012 Microchip Technology Inc.

15.5.4 SLAVE MODE 10-BIT ADDRESS

RECEPTION

This section describes a standard sequence of events

for the MSSPx module configured as an I2C slave in

10-b it Ad d res si ng m od e (Figure 15-20) and is used as

a visual reference for this description.

This is a step by s tep proc ess o f wha t mus t be don e by

slave software to accomp lish I 2C communication.

1. Bus starts Idl e.

2. Master sends S tart condition; S bit of SSPxST AT

is set; SSPxIF is set if interru pt on S t art detect is

enabled.

3. Master sends matching high address with R/W

bit clear; UA bi t of the SSPx STAT register is set.

4. Slave sends ACK and SSPxIF is set.

5. Software clears the SSPxIF bit.

6. Software reads received address from SSPxBUF

clearing the BF flag.

7. Slave loads low address into SSPxADD,

releasi ng SCLx.

8. Master sends matching low address byte to the

slave; UA bit is set.

9. Slave sends ACK and SSPxIF is set.

10. Slave clears SSPxIF.

11. Slave reads the received matching address

from SSPxBUF clearing BF.

12. Slave loads high address into SSPxADD.

13. Master clocks a data byte to the slave and cloc ks

out the slaves ACK on the 9th SCLx pulse;

SSPxIF is set.

14. If SEN bit of SSPxCON2 is set, CKP is cleared

by hardware and the clock is stretched.

15. Slave clears SSPxIF.

16. Slave reads the received byte from SSPxBUF

clearing BF.

17. If SEN i s set the sl ave sets CKP t o releas e the

SCLx.

18. Steps 13-17 repeat for each received byte.

19. Master sen ds Stop to end the transm is si on.

15.5.5 10-BIT ADDRESSING WITH ADDRESS

OR DATA HOLD

Reception using 10-bit addressing with AHEN or

DHEN set is the same as with 7-bit modes. The only

diff eren ce is th e nee d to update the SSPxADD register

using the UA bit. All functionality, specifically when the

CKP bit is cleared and SCLx line is held low are the

same. Figure 15-21 can be used as a reference of a

slave in 10-bit addressing with AHEN set.

Figure 15-22 shows a standard waveform for a slave

transmitter in 10-bit Addressing mode.

Note: Updates to the SSPxADD register are not

all owed until after the ACK sequence.

Note: If the low address does not match, SSPxIF

and UA are still set so that the slave soft-

ware can set SSPxADD back to the high

address. BF is not set because there is no

match. CKP is unaffected.

 2010-2012 Microchip Technology Inc. DS41412F- page 237

PIC18(L)F2X/4XK22

FIGURE 15-20 : I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

SSPxIF

Receive First Address Byte

ACK

Receive Second Address Byte

ACK

Receive Data

ACK

Receive D at a

ACK

1 1 1 1 0

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDAx

SCLx

CKP

12345678912345678

912345678

9123456789P

Master sends

Stop condition

Cleared by software

Receive address is

Software updates SSPxADD

Data is read

SCLx is held low

Set by software,

while CKP =

from SSPxBUF

releasing SCLx

When SEN =

;

CKP is cleared after

9th falling edge of received byte

read from SSPxBUF

and releases SCLx

When UA =

;

If address matches

Set by hardware

on 9th falling edge

SSPxADD it is loaded into

SSPxBUF

SCLx is held low

PIC18(L)F2X/4XK22

DS41412F-page 238  2010-2012 Microchip Technology Inc.

FIGURE 15-21 : I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)

Receive First Address Byte

Receive Second Address Byte

Receive Data

ACK

Receive Data

1 1 1 1 0

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5SDAx

SCLx

SSPxIF

ACKDT

CKP

ACKTIM

12345678 9

ACK

12345678 91234567891

SSPxBUF

is read from

Received data

SSPxBUF can be

read any time before

the next received byte

Cleared by software

falling edge of SCLx

not allowed until 9th

Update to SSPxADD is

Set CKP with softw are

releases SCLx

SCLx

clears UA and releases

Update of SSPxADD,

Set by hardware

on 9th falling edge

Slave software clears

ACKDT to ACK

the rec eived byt e

If when AHEN = 1;

on the 8th falling edge

of SCLx of an address

byte, CKP is cleared

ACKTIM is set by hardware

on 8th falling edge of SCLx

Cleared by software

R/W = 0

 2010-2012 Microchip Technology Inc. DS41412F- page 239

PIC18(L)F2X/4XK22

FIGURE 15-22 : I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)

Receiving Address

ACK

Receiving Second Address Byte

Receive First Address Byte ACK

Transmitting Data Byte

1 1 1 1 0

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 1 1 1 0

A9 A8 D7 D6 D5 D4 D3 D2 D1 D0SDAx

SCLx

SSPxIF

CKP

R/W

D/A

123456789 123456789 123456789 123456789

ACK = 1

Master sends

Stop condition

Master sends

not ACK

Master sends

Restart event

ACK

R/W = 0

Cleared by software

After SSPxADD is

updated, UA is cleared

and SC Lx is released

High address is loaded

Received address is Data to transmit is

Set by software

Indicates an address

When R/W = 1;

R/W is copied from the

Set by hardware

UA indicates SSPxADD

SSPxBUF loaded

with receiv ed addre ss

must be updated

has been received

loaded into SSPxBUF

releases SCLx

Masters not ACK

is copied

matching address byte

CKP is cleared on

9th falling edge of SCLx

read from SSPxBUF

back into SSPxADD

ACKSTAT

Set by hardware

PIC18(L)F2X/4XK22

DS41412F-page 240  2010-2012 Microchip Technology Inc.

15.5.6 CLOCK STRETCHING

Clock stretching occurs when a device on the bus

holds the SCLx line low effectively pausing communi-

cation. The slave may stretch the clock to allow more

time to handle dat a or p repare a respon se for the mas-

ter device. A master device is not concerned with

stretching as anytime it is active on the bus and not

transferring data it is stretching. Any stretching done

by a slave is invisible to the master software and han-

dled by the hardware that generates SCLx.

The CKP bit of the SSPxCON1 register is used to

control stretching in software. Any time the CKP bit is

cleared, the module will wait for the SCLx line to go

low and then hold it. Setting CKP will release SCLx

and allow more communication.

15.5.6.1 Normal Clock Stretching

Following an ACK if the R/W bit of SSPxSTAT is set, a

read request, the slave hardware will clear CKP. This

allows the slave time to update SSPxBUF with data to

transfer to the master. If the SEN bit of SSPxCON2 is

set, the slave hardware will always stretch the clock

after th e ACK sequen ce . Once the slav e is read y; CKP

is set by software and communication resumes.

15.5.6.2 10-bit Addressing Mode

In 10-bit Addressing mode, when the UA bit is set, the

clock is always stretched. This is the only time the

SCLx is stretched without CKP being cleared. SCLx is

released immediately after a write to SSPxADD.

15.5.6.3 Byte NACKing

When the AHEN bit of SSPxCON3 is set; CKP is

cleared by hardware after the 8th falling edge of SCLx

for a received matching address byte. When the

DHEN bit of SSPxCON3 is set; CKP is cleared after

the 8th falling edge of SCLx for received data.

Stretching after the 8th falling edge of SCLx allows the

slave to look at the received address or data and

decide if it wants to ACK the received data.

15.5.7 CLOCK SYNCHRONIZATION AND

THE CKP BIT

Any time the CKP bit is cleared, the module will wait

for the SCLx line to go low and then hold it. However,

clearing the CKP bit will not assert the SCLx output

low until the SCLx output is already sampled low.

Therefore, the CKP bit will not assert the SCLx line

until an external I2C master device has already

asserted the SCLx line. The SCLx output will remain

low until the CKP bit is set and all other devices on the

I2C bus h ave released SCLx. This ensures that a write

to the CKP bit will not violate the minimum high time

requirem ent for SCLx (see Figure 15-23).

FIGURE 15-23: CLOCK SYNCHRONIZATION TIMING

Note 1: The BF bit has no effect on whether the

clock will be stretched or not. This is

different than previous versions of the

module that would not stretch the clock,

clear CKP, if SSPxBUF was read before

the 9th falling edge of SCLx.

2: Previous versions of the module did not

stretch the clock for a transmission if

SSPxBUF was loaded before the 9th fall-

ing edg e of SCLx. It is now always cleared

for read requests.

Note: Previous versions of the module did not

stretch the clock if the second address byte

did not match.

SDAx

SCLx

DX ‚ – 1DX

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPxCON1

CKP

Master device

releases clock

Master device

asse rts clock

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PIC18(L)F2X/4XK22

15.5.8 GENERAL CALL ADDRESS SUPPORT

The addressing procedure for the I2C bus is such that

the first byte after the Start condition usually

determines which device will be the slave addressed

by the ma ster device. The e xc ep tion is the general call

address which can address all devices. When this

address is used, all devices should, in theory, respond

with an acknowledge.

The general call address is a reserved address in the

I2C protocol, defined as address 0x00. When the

GCEN bit of the SSPxCON2 register is set, the slave

module will automatically ACK the reception of this

address regardless of the value stored in SSPxADD.

After the slave clocks in an address of all zeros with the

R/W bit clear, an i nterrupt is generate d and slave soft-

ware can read SSPxBUF and respond. Figure 15-24

shows a general call reception sequence.

In 10-bit Address mode, the UA bit will not be set on

the reception of the general call address. The slave

will prepare to receive the second byte as data, just as

it would in 7-bit mode.

If the AHEN bit of the SSPxCON3 register is set, just

as with any other address reception, the slave

hardware will stretch the clock after the 8th falling

edge of SCLx. The slave must then set its ACKDT

value and release the clock with communication

progressing as it would normally.

FIGURE 15-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

15.5.9 SSPx MASK REGISTER

An SSPx Mask (SSPxMSK) register (Register 15-5) is

available in I2C Slave mode as a mask for the value

held in the SSPxSR register during an address

comparison operation. A zero (‘0’) bit in the SSPxMSK

of the received address a “don’t care”.

This register is reset to all ‘1’s upon any Reset

condition and, therefore, has no effect on standard

SSPx operation until written with a mask value.

The SSPx Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10-bit Add ress mode: ad dress compa re of A<7:0>

only. The SSPx mask has no effect during the

reception of the first (high) byte of the address.

SDAx

SCLx S

SSPxIF

BF (SSPxSTAT<0>)

Cleared by software

SSPxBUF is read

R/W = 0ACK

General Call Address

Address is compared to General Call Address

Receiving Data ACK

123456789123456789

D7 D6 D5 D4 D3 D2 D1 D0

after ACK, set interrupt

GCEN (SSPxCON2<7>) ’1’

PIC18(L)F2X/4XK22

DS41412F-page 242  2010-2012 Microchip Technology Inc.

15.6 I2C Master Mode

Master mode is enabled by setting and clearing the

appropri ate SSPxM bit s in the SSPxCON1 register an d

by setting the SSPxEN bit. In Master mode, the SCLx

and SDAx lines are set as inputs and are manipulated

by the MSSPx hardware.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop con-

ditions . The S t op (P) and S t art (S) bit s are clea red fro m

a Reset or when the MSSPx module is disabled. Con-

trol of the I 2C bus may be taken when the P bit is set,

or the bus is Idle.

In Firmware Controlled Master mode, user code

conducts all I2C bus operations based on Start and

Stop bit condition detection. Start and Stop condition

detection is the only active circuitry in this mode. All

other communication is done by the user software

directly manipulating the SDAx and SCLx lines.

The followi ng events will caus e the SSPx Interrupt Flag

bit, SSPxIF, to be set (SSPx interrupt, if enabled):

• Start condition detected

• Stop condition detected

• Data transfer byte transmitted/received

• Acknowledge transmi tted/ rece ived

• Repea ted Start gene rate d

15.6.1 I2C MASTER MODE OPERATION

The master device generates all of the serial clock

pulses and the S t a rt and Stop conditions. A tra nsfer i s

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the begi nning of the ne xt seria l transfer, the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDAx, while SCLx output s the serial clock. Th e

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit wi ll be lo gic ‘0’. S erial data is

transmi tted eight bits at a time. Aft er each by te is trans -

mitted, an Acknowledge bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

In Master Rec eive mode, the firs t byte transmitte d con-

tains the slave address of the transmitting device

(7 bits) and th e R/W bit. In this c ase, the R/W bit w ill b e

logic ‘1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDAx, while SCLx outputs

the serial clock. Serial data is received eight bits at a

time. Af ter each byte is rece ived, an Acknowl edge bit is

transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

A Baud Rate Generator is used to set the clock

frequency output on SCLx. See Section 15.7 “Baud

Rate Generator” for more detail.

Note 1: The MSSPx module, when configured in

I2C Master mode, does not allow queue-

ing of eve nt s. Fo r instan ce , the user is not

allowed to initiate a Start condition and

immediately write the SSPxBUF register

to initiate transmission before the Start

condition is complete. In this case, the

SSPxBUF will not be written to and the

WCOL bit will be set, indicating that a

write to the SSPxBUF did not occur

2: When in Master mode, Start/Stop

detection is masked and an interrupt is

generated when the SEN/PEN bit is

cleared and the generation is complete.

 2010-2012 Microchip Technology Inc. DS41412F- page 243

PIC18(L)F2X/4XK22

15.6.2 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

releases the SCLx pin (SCLx allowed to float high).

When the SCLx pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting

unti l the SCLx pin is act ually sa mpled high . When t he

SCLx pin is sampled high, the Baud Rate Generator is

reloaded with the contents of SSPxADD<7:0> and

begins counting. This ensures that the SCLx high time

will always be at least one BRG rollover count in the

event that the clock is held low by an external device

(Figure 15-25).

FIGURE 15-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

15.6.3 WCOL STATUS FLAG

If the user writes the SSPxBUF when a Start, Restart,

Stop, Recei ve or T rans mit s equen ce is in p rogress , the

WCOL is set and the contents of the buffer are

unchanged (the write does not occur). Any time the

WCOL bit is set it indicates tha t an action on SSPxBUF

was attempted while the module was not Idle.

SDAx

SCLx

SCLx deasserted but slave holds

DX ‚ – 1DX

BRG

SCLx is sampled high, reload takes

place and BRG starts it s count

03h 02h 01h 00h (hold off) 03h 02h

Reload

BRG

Value

SCLx low (clock arbitration) SCLx allowed to transition high

BRG decrements on

Q2 and Q4 cycles

Note: Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPxCON2 is disabled until the Start

conditi on is co mp let e.

PIC18(L)F2X/4XK22

DS41412F-page 244  2010-2012 Microchip Technology Inc.

15.6.4 I2C MASTER MODE START

CONDITION TIMING

To initiate a Start condition (Figure 15-26), the user

sets the Start Enable bit, SEN, of the SSPxCON2 reg-

ister. If the SDAx and SCLx pi ns are s am ple d hi gh, th e

Baud Rate Generator is reloaded with the contents of

SSPxADD<7:0> and starts its count. If SCLx and

SDAx are both sampled high when the Baud Rate

Generator times out (TBRG), the SDAx pin is driven

low. The action of the SDAx being driven low while

SCLx is high is the Start co nditio n and causes the S bit

of the SSPxSTAT1 register to be set. Following this,

the Baud R ate Ge ne rator is reloaded w ith the c ont ents

of SSPxADD<7:0> and resumes its count. When the

Baud Rate Generator times out (TBRG), the SEN bit of

the SSPxCON2 register will be automatically cleared

by hardware; the Baud Rate Generator is suspended,

leaving the SDAx line held low and the Start condition

is complete.

FIGURE 15-26: FIRST START BIT TIMING

Note 1: If at the beginning of the Start condition,

the SDAx and SCLx pins are already sam-

pled low, or if during the Start condition,

the SCLx line is sampled low before the

SDAx line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCLxIF, is set, the Start condition is

aborted and the I2C module is reset into

its Idle state.

2: The Philips I2C Specific ati o n sta t es th a t a

bus collision cannot occur on a Start.

SDAx

SCLx S

TBRG

1st bit 2nd bit

TBRG

SDAx = 1, At completion of Start bit,

SCLx = 1

W rite to SSPx BUF occurs he re

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here Set S bit (SSPxSTAT<3>)

and sets SSPxIF bit

 2010-2012 Microchip Technology Inc. DS41412F- page 245

PIC18(L)F2X/4XK22

15.6.5 I2C MASTER MODE REP EA TED

START CONDITION TIMING

A Repeated S tart conditi on (Figure 15-27) occurs when

the RSEN bit of the SSPxCON2 register is pro-

gram me d h igh and the master state mach ine is no lon-

ger active. When the RSEN bit is set, the SCLx pin is

asserted low. When the SCLx pin is sampled low, the

Baud Rate Generator is loaded and begins counting.

The SDAx pin is released (brought high) for one Baud

Rate Generator count (TBRG). When the Baud Rate

Generator times out, if SDAx is sampled high, the SCLx

pin will be deasserted (brought high). When SCLx is

sampled high, the Baud Rate Generator is reloaded

and begins counting. SDAx and SCLx must be sam-

pled high for one TBRG. This action is then followed by

assertion of the SDAx pin (SDAx = 0) for one TBRG

while SCLx is high. SCLx is asserted low. Following

this, the RSEN bit of the SSPxCON2 register will be

automat ically cleared an d the Baud Rate Generator will

not be reloaded, leaving the SDAx pin held low. As

soon as a Start condition is detected on the SDAx and

SCLx pins, the S bit of the SSPxSTAT register will be

set. The SSPxIF bit will not be set until the Baud Rate

Generat or has tim ed out .

FIGURE 15-27: REPEAT START CONDITION WAVEFORM

Note 1: If RSEN is programmed while any other

event is in progre ss , it will not t ak e effect.

2: A bus collision during the Repeated Start

conditi on occ urs if:

• SDAx is sampled low when SCLx

goes from low-to-high.

• SCLx goes low before SDAx is

asserted low. This may indicate

that another maste r is attempting to

transmit a data ‘1’.

SDAx

SCLx

Repeated Start

Write to SSPxCON2

Writ e to SSPxBUF occurs here

At completion of Start bit,

hardware clears RSEN bit

1st bit

S bit set by hardware

TBRG

SDAx = 1,SDAx = 1,

SCLx (no change) SCLx = 1

occurs here

TBRG TBRG TBRG

and sets SSPxIF

PIC18(L)F2X/4XK22

DS41412F-page 246  2010-2012 Microchip Technology Inc.

15.6.6 I2C MASTER MODE TRANSMISSION

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accom plished by simply

writing a value to th e SSPxBUF register. This a ction will

set the Buffer Full fla g b it, BF, and allow t he Bau d Ra te

Generator to begin counting and start the next trans-

mission. Each bit of address/data will be shifted out

onto the SDAx pin after the falling edge of SCLx is

asserte d. SCLx is hel d lo w for o ne Ba ud R at e G ene ra-

tor rollover count (TBRG). Data should be valid before

SCLx is released high. When the SCLx pi n is released

high, it is he ld that way for TBRG. The data on the SDAx

pin must rem ain st abl e for that duratio n and some hol d

time af ter the next fa lling edge of SCL x. After the e ighth

bit is shifted out (the falling edge of the eighth clock),

the BF flag is cleared and the master releases SDAx.

This allows the slave device being addressed to

respond with an ACK bit d uring the n inth bi t time if an

addr es s m at c h oc cu r red , o r if d a ta wa s rec ei v ed p rop -

erly. The status of ACK is written into the ACKSTAT bit

on the rising edge of the ninth clock. If the master

receive s an Ac knowled ge, the Acknow ledg e S tatus bit,

ACKSTA T, is cleare d. If not, the bit is set. Af ter the nin th

clock, the SSPxIF bi t is set a nd the m aster clock (Bau d

Rate Generator) is suspended until the next data byte

is loaded into the SSPxBUF, leaving SCLx low and

SDAx unchanged (Figure 15-28).

After th e write to t he SSPxBUF, each b it of the addres s

will be shifted out on the falling edge of SCLx until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

release the SDAx pin, allowing the slave to respond

with an Acknowledge. On the falling edge of the ninth

clock, the master will sample the SDAx pin to see if the

address was recognized by a slave. The status of the

ACK bit is loaded into the ACKSTAT Status bit of the

SSPxCON2 register. Following the falling edge of the

ninth clock transmission of the address, the SSPxIF is

set, the BF flag is c leared and t he Baud Rate Generator

is turned off until another write to the SSPxBUF takes

place, holding SCLx low and allowing SDAx to float.

15.6.6.1 BF Status Flag

In Transmit mode, the BF b it o f th e SSPx STAT register

is set when the CPU writes t o SSPxBUF and i s cleared

when all 8 bits are shifted out.

15.6.6.2 WCOL Status Flag

If the user writes the SSPxBUF when a transmit is

already in progress (i.e., SSPxSR is still shifting out a

data byte), the WCOL is set and the contents of the

buffer are unchanged (the write does not occur).

WCOL must be cleared by software before the next

transmission.

15.6.6.3 ACKSTAT Status Flag

In Transmit mode, t he ACKSTAT bit of the SSPxCO N2

Acknowledge (ACK =0) and is set when the slave

does not Acknowledge (ACK =1). A slave sends an

Acknowledge when it has recognized its address

(including a general call), or when the slave has

properly received its data.

15.6.6.4 Typical Transmit Sequence:

1. The user generates a Start condition by setting

the SEN bit of the SSPxCON2 register.

2. SSPxIF is set by hardware on co mplet ion of the

Start.

3. SSPxIF is cleared by software.

4. The MSSPx module will wait the required start

time before any other ope rati on takes place.

5. The user loads the SSPxBUF with the slave

address to transmit.

6. Address is shifted out the SDAx pin until all eight

bits are transmitted. Transmission begins as

soon as SSPxBUF is written to.

7. The MSSPx module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

8. The MSSPx module generates an interrupt at

the end of the ninth clock cycle by setting the

SSPxIF bit.

9. The user loads the SSPxBUF with eight bits of

data.

10. Data is shifted out the SDAx pin until all eight

bits are transmitted.

11. The MSSPx module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

12. Steps 8-11 are repeated for all transmitted data

bytes.

13. The user generates a Stop or Restart condition

by setting the PEN or RSEN bits of the

SSPxCON2 register . Interrupt is generated once

the Stop/Restart condition is complete.

 2010-2012 Microchip Technology Inc. DS41412F- page 247

PIC18(L)F2X/4XK22

FIGURE 15-28 : I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

SDAx

SCLx

SSPxIF

BF (SSPxSTAT<0>)

SEN

A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0

ACK

Transmitting Data or Second Half

R/W = 0Transmit Address to Slave

123456789 123456789 P

Cleared by software service routine

SSPxBUF is written by software

from SSPx interrup t

After Start condition, SEN cleared by hardware

SSPxBUF written with 7-bit address and R/W

start transmit

SCLx held low

while CPU

responds to SSPxIF

SEN = 0

of 10-bit Address

Write SSPxCON2<0> SEN = 1

Start condition begins From slave, clear ACKSTAT bit SSPxCON2<6>

ACKSTAT in

SSPxCON2 = 1

Cleared by software

SSPxBUF writte n

PEN

R/W

Cleared by software

PIC18(L)F2X/4XK22

DS41412F-page 248  2010-2012 Microchip Technology Inc.

15.6.7 I2C MASTER MODE RECE PTI ON

Master mode reception (Figure 15-29) is enabled by

programming the Receive Enable bit, RCEN, of the

SSPxCON2 register.

The Baud Rate Generator begins counting and on each

rollove r, the st ate of the SCLx pin changes (high-to-low/

low-to-high) and data is shifted into the SSPxSR. After

the falling edge of the eighth clock, the receive enable

flag is automatically cleared, the contents of the

SSPxSR are loaded into the SSPxBUF, the BF flag bit

is set, the SSPxIF flag bit is set and the Baud Rate

Generator is suspended from counting, holding SCLx

low. The MSSPx is now in Idle state awaiting the next

command. When the buffer is read by the CPU, the BF

flag bit is automatically cleared. The user can then

send an Acknowledge bit at the end of receptio n by set-

ting the Acknowledge Se quence Enabl e bit, ACKEN, of

the SSPxCON2 register.

15.6.7.1 BF Status Flag

In receiv e op era tion , the BF bit is set whe n an add res s

or data byte is loaded into SSPxBUF from SSPxSR. It

is cleared when the SSPxBUF register is read.

15.6.7.2 SSPx O V Stat us Flag

In receive operation, the SSPxOV bit is set when eight

bits are receiv ed into the SS PxSR and the BF fl ag bit is

already set from a previous reception.

15.6.7.3 WCOL Status Flag

If the user writes the SSPxBUF when a receive is

already in progress (i.e., SSPxSR is still shifting in a

data byte), the WCOL bit is set and the contents of the

buffer are unchanged (the write does not occur).

15.6.7.4 Typical Receive Sequence:

1. The user generates a Start condition by setting

the SEN bit of the SSPxCON2 register.

2. SSPxIF is set by hardware on co mplet ion of the

Start.

3. SSPxIF is cleared by software.

4. User writes SSPxBUF with the slav e addr ess to

transmit and the R/W bit set.

5. Address is shifted out the SDAx pin until all eight

bits are transmitted. Transmission begins as

soon as SSPxBUF is written to.

6. The MSSPx module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

7. The MSSPx module generates an interrupt at

the end of the ninth clock cycle by setting the

SSPxIF bit.

8. User sets the RCEN bit of the SSPxCON2 regis-

ter and the Master clocks in a byte from the slave.

9. After the 8th falling edge of SCLx, SSPxIF and

BF are set.

10. Master clears SSPxIF and reads the received

byte from SSPxUF, clears BF.

11. M aster sets ACK value sent to slave in ACKDT

bit of the SSPxCON2 register and initiates the

ACK by setting the ACKEN bit.

12. Masters ACK is clocked out to the slave and

SSPxIF is set.

13. User clears SSPxIF.

14. Steps 8-13 are repeated for each received byte

from the slave .

15. Master sends a not ACK or Stop to end

communication.

Note: The MSSPx module must be in an Idle

state before the RCEN bit is set or the

RCEN bit will be disregarded.

 2010-2012 Microchip Technology Inc. DS41412F- page 249

PIC18(L)F2X/4XK22

FIGURE 15-29 : I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

D3D4

D6D7

A7 A6 A5 A4 A3 A2 A1

SDAx

SCLx 12345678912345678 9 1234

Bus master

terminates

transfer

ACK Receiving Data from Slave

Receiving Data from Slave D0

D3D4

D6D7

ACK

Transmit Address to Slave

SSPxIF

ACK is not sent

Write to SSPxCON2<0>(SEN = 1),

Write to SSPxBUF occurs here , ACK fr om Slave

Master configured as a receiver

by programming SSPxCON2<3> (RCEN = 1)PEN bit = 1

written here

Data shifted in on falling edge of CLK

Cleared by software

start XMIT

SEN = 0

SSPxOV

SDAx = 0, SCLx = 1

while CPU

(SSPxSTAT<0>)

ACK

Cleared by software

Clear ed by software

Set SSPxIF interrupt

at end of receive

Set P bit

(SSPxSTAT<4>)

and SSPxIF

Cleared in

software

ACK from Master

Set SSPxIF at end

Set SSPxIF interrupt

at end of Acknowledge

sequence

Set SSPxIF interrupt

at end of Acknow-

ledge sequence

of receive

Set ACKEN, start Acknowledge sequence

SSPxOV is set because

SSPxBUF is still full

SDAx = ACKDT = 1

RCEN cleared

automatically

RCEN = 1, start

next receive

Write to SSPxCON2<4>

to start Acknowledge sequence

SDAx = ACKDT (SSPxCON2<5> ) = 0

RCEN cleared

automatically

responds to SSPxIF

ACKEN

begin Start condition

Cleared by software

SDAx = ACKDT = 0

Last bit is shifted into SSPxSR and

contents are unloaded into SSPxBUF

RCEN

Master configured as a receiver

by programming S SPxCON2<3> (RCEN = 1)RCEN cleared

automatically ACK from Master

SDAx = ACKDT = 0 RCEN cleared

automatically

R/W

PIC18(L)F2X/4XK22

DS41412F-page 250  2010-2012 Microchip Technology Inc.

15.6.8 ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN, of the

SSPxCON2 register . When this bit is set, the SCLx pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDAx pin. If the user wishes to

generate an Acknowledge, then the ACKDT bit should

be cleared. If not, the user should set the ACKDT bit

before starting an Acknowledge sequence. The Baud

Rate Generator then counts for one rollover period

(TBRG) and the SCLx pin is deasserted (pulled high).

When the SCLx pin is sampled high (clock arbitration),

the Baud Rate Generator counts for TBRG. The SCLx pin

is then pulled low. Following this, the ACKEN bit i s auto-

matically c leared, the Baud Rate G enerator is turned of f

and the MSSPx module then goes into Idle mode

(Figure 15-30).

15.6.8.1 WCOL Status Flag

If the user writes the SSPxBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write does

not occur ).

15.6.9 STOP CONDITION TIMING

A Stop bit is asserted on the SDAx pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN, of the SSPxCON2 register. At the end of a

receive/transmit, the SCLx line is held low after the

falling edge of th e ninth clock . When t he PEN bi t is se t,

the master will assert the SDAx line low. When the

SDAx line is sampled low, the Baud Rate Generator is

reloaded and counts down to ‘0’. When the Baud Rate

Generator times out, the SCLx pin will be brought high

and one TBRG (Baud Rate Generator rollover count)

later, the SDAx pin will be de asse rted. Whe n the SDA x

pin is sampled high while SCLx is high, the P bit of the

SSPxSTAT register is set. A TBRG later, the PEN bit is

cleared and the SSPxIF bit is set (Figure 15-31).

15.6.9.1 WCOL Status Flag

If the user writes the SSPxBUF when a S t op sequenc e

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write does

not occur).

FIGURE 15-30: ACKNOWLEDGE SEQUEN CE WAVEFORM

Note: TBRG = one Baud Rate Generator period.

SDAx

SCLx

SSPxIF set at

Acknowledge sequence starts here,

write to SSPxCON2 ACKEN automatically cleared

Cleared in

TBRG TBRG

the end of receive

ACKEN = 1, ACK D T = 0

SSPxIF

software SS PxIF set at the end

of Acknowledge sequence

Cleared in

software

ACK

 2010-2012 Microchip Technology Inc. DS41412F- page 251

PIC18(L)F2X/4XK22

FIGURE 15-31: STOP CONDITION RECEIVE OR TRANSMIT MODE

15.6.10 SLEEP OPERATION

While i n Sleep mo de, the I2C slav e module can receiv e

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSPx interrupt is enabled).

15.6.11 EFFECTS OF A RESET

A Reset disables the MSSPx module and terminates

the current transfer.

15.6.12 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determin ation of when the bu s is free. The S top (P) an d

Start (S) bits are cleared from a Reset or when the

MSSPx modu le is dis abled. Control of th e I2C bus may

be taken when the P bit of the SSPxSTAT register is

set, or the bus is Idle, with both the S and P bits clear.

When the bus is busy, enabling the SSPx interrupt will

generate the interrupt when the Stop condition occurs.

In multi-master operation, the SDAx line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed by

hardware with the result placed in the BCLxIF bit.

The states where arbi tration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

• A Repeated Start Condition

• An A cknowledge C ondition

SCLx

SDAx

SDAx asserted low before rising edge of clock

Write to SSPxCON2,

set PEN

Falling edg e of

SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG

9th clock

SCLx brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG TBRG

after SDAx sampled high. P bit (SSPxSTAT<4>) is set.

TBRG

to set up Stop condition

ACK

TBRG

PEN bit (SSPxCON2<2>) is cleared by

hardware and the SSPxIF bit is set

PIC18(L)F2X/4XK22

DS41412F-page 252  2010-2012 Microchip Technology Inc.

15.6.13 MULTI - MA S TE R COMM UN IC ATI O N,

BUS COLL ISIO N AND BUS

ARBITRATION

Multi-Master mode support is achieved by bus

arbitration. When the master outputs address/data bits

onto the SDAx pin, arbitration takes place when the

master outputs a ‘1’ on SDAx, by letting SDAx float high

and another master asserts a ‘0’. When the SCLx pin

floats high, data should be stable. If the expected data

on SDAx is a ‘1’ and the dat a samp led on the SDAx pin

is ‘ 0’, then a bus collision has taken place. The master

will set the Bus Collision Interrupt Flag, BCLxIF, and

reset the I2C port to its Idle state (Figure 15-32).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDAx and SCLx lines are deasserted and

the SSPxBUF can be written to. When the user

servic es the bus collis ion Interr upt Servic e Routine and

if the I2C bus is free, the user can resume

communication by asserting a Start condition.

If a Start, Repeated Start, Stop or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDAx and SCLx

lines are deasserted and the respective control bits in

the SSPxCON2 register are cleared. When the user

services the bus collision Interrupt Service Routine and

if the I2C bus is free, the user can resume

communication by asserting a Start condition.

The master will contin ue to monitor the SDAx and SCLx

pins. If a S top condition occurs, the SSPxIF bit will be set.

A write to the SSPxBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the

determination of when the bus is free. Control of the I2C

bus can be taken when the P bit is set in the SSPxST AT

cleared.

FIGURE 15-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDAx

SCLx

BCLxIF

SDAx released

SDAx line pulled low

by another source

Sample SDAx. While SCLx is high,

data does not match what is driven

Bus collision has occurred.

Set bus collision

interrupt (BCLxIF)

by the master.

by master

Data changes

while SCLx = 0

 2010-2012 Microchip Technology Inc. DS41412F- page 253

PIC18(L)F2X/4XK22

15.6.13.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDAx or SCLx are sampled low at t he begin ning

of the Start condition (Figure 15-33).

b) SCLx is sampled low before SDAx is asserted

low ( Figure 15-34).

Duri ng a Sta rt condi tion, both the SDAx and the SCLx

pins are monitored.

If the SDAx pin is already low, or the SCLx pin is

already low, then all of the following occur:

• the Start condition is ab orted,

• the BCLxIF flag is set and

• the MSSPx module is reset to its Idle state

(Figure 15-33).

The Start condition begins with the SDAx and SCLx

pins deasserted. When the SDAx pin is sampled high,

the Baud R ate Genera tor is loa ded and coun ts dow n. If

the SCLx pin is sample d lo w while SDAx is high , a bu s

collision occurs because it is assumed that another

master is attempting to drive a data ‘1’ during the Start

condition.

If the SDAx pin is sampled low during this count, the

BRG is reset and the SDAx line is asserted early

(Figure 15-35). If, however, a ‘1’ is sampled on the

SDAx pin, the SDAx pin is asserted low at the end of

the BRG count. The Baud Rate Generator is then

reloaded and counts down to zero; if the SCLx pin is

sampled as ‘0’ during this t ime, a bu s collis ion does not

occur. At the end of the BRG count, the SCLx pin is

asserted low.

FIGURE 15-33: BUS COLLISION DURING START CONDITION (SDAx ONLY)

Note: The reason that bus collision is not a fac-

tor during a Start condition is that no two

bus masters can assert a Start condition

at the exact same time. Therefore, one

master wil l always asse rt SDAx before the

other. This conditi on does not ca use a bus

collision because the two masters must be

allowed to arbitrate the first address fol-

lowing the S tart condi tion. If the addre ss is

the same, arbitration must be allowed to

continue into the data portion, Repeated

Start or Stop conditions.

SDAx

SCLx

SEN SDAx sampled low before

SDAx goes low before the SEN bit is set.

S bit and SSPxIF set because

SSPx module reset into Idle state.

SEN cleared automatically because of bus collision.

S bit and SSPxIF set because

Set SEN, enable Start

condition if SDAx = 1, SCLx = 1

SDAx = 0, SCLx = 1.

BCLxIF

SSPxIF

SDAx = 0, SCLx = 1.

SSPxIF and BCLxIF are

cleared by software

SSPxIF and BCLxIF are

cleared by software

Set BCLxIF,

S tart condition. Set BCLxIF.

PIC18(L)F2X/4XK22

DS41412F-page 254  2010-2012 Microchip Technology Inc.

FIGURE 15-34: BUS COLLISION DURING START CONDITION (SCLx = 0)

FIGURE 15-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDAx

SCLx

SEN bus collision occurs. Set BCLxIF.

SCLx = 0 before SDAx = 0,

Set SEN, enable Start

sequence if SDAx = 1, SCLx = 1

TBRG TBRG

SDAx = 0, SCLx = 1

BCLxIF

SSPxIF

Interrupt cleared

by softw a r e

bus collision occurs. Set BCLxIF.

SCLx = 0 before BRG time-out,

’0’’0’

SDAx

SCLx

SEN

Set S

Less th an TBRG TBRG

SDAx = 0, SCLx = 1

BCLxIF

SSPxIF

Interrupts cleared

by software

set SS PxIF

SDAx = 0, SCLx = 1,

SCLx pulled low after BRG

time-out

Set SS PxIF

’0’

SDAx pulled low by other master.

Reset BRG and assert SDAx.

Set SEN, enable Start

sequence if SDAx = 1, SCLx = 1

 2010-2012 Microchip Technology Inc. DS41412F- page 255

PIC18(L)F2X/4XK22

15.6.13.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occu rs if:

a) A low level is sampled on SDAx when SCLx

goes from low level to high level (Case 1).

b) SCLx goes low before SDAx is asserted low,

indicating that another master is attempting to

transmit a data ‘1’ (Case 2).

When the u ser releas es SDAx and the pin is all owed to

float high, the BRG is loaded with SSPxADD and

counts down to zero. The SCLx pin is then deasserted

and when sa mp led high, the SD Ax pin is samp led .

If SDAx is low , a bus c ollision has occurred (i.e., another

master is attempting to transmit a data ‘0’, Figure 15-36).

If SDAx is sampled high, the BRG is reloaded and

begins counting. If SDAx goes from high-to-low before

the BRG times out, no bus collision occurs because no

two masters can as sert SDAx at exactly the sam e time.

If SCLx goes from high-to-low before the BRG times

out and SDAx has not already been asserted, a bus

collision occurs. In this case, another master is

attempting to transmit a data ‘1’ during the Repeated

Start condition, see Figure 15-37.

If, at the end of the BRG time-out, both SCLx and SDAx

are still high, the SDAx pin is driven low and the BRG

is reloaded and begins counting. At the end of the

count, regardless of the status of the SCLx pin, the

SCLx pin is driven low and the Repeated Start

conditi on is complete.

FIGURE 15-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

FIGURE 15-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

SDAx

SCLx

RSEN

BCLxIF

SSPxIF

Sample SDAx when SCLx goes high.

If SDAx = 0, set BCLxIF and release SDAx and SCLx.

Cleared by software

’0’

SDAx

SCLx

BCLxIF

RSEN

SSPxIF

Interrupt cleared

by software

SCLx goes low before SDAx,

set BCLxIF. Release SDAx and SCLx.

TBRG TBRG

’0’

PIC18(L)F2X/4XK22

DS41412F-page 256  2010-2012 Microchip Technology Inc.

15.6.13.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDAx pin has been deasserted and

allowed to float high, SDAx is sampled low after

the BRG ha s timed out (Case 1).

b) After the SCLx pin is deasserted, SCLx is

sampled low before SDAx goes high (Case 2).

The Stop condition begins with SDAx asserted low.

When SD Ax is sam pled l ow, the SCL x pin is a llowed to

floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),

the Baud Ra te Generator is load ed with SSPxADD an d

count s down to z ero. Af te r the BRG t imes o ut, SDAx is

sampled. If SDAx is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 15-38). If the SCLx pin is

sampled low before SDAx is allowed to float high, a bus

collis ion occ urs. Thi s is anoth er case of a nother m aster

attempting to drive a data ‘0’ (Figure 15-39).

FIGURE 15-38: BUS COLLISION DURING A STOP CONDITION (CASE 1)

FIGURE 15-39: BUS COLLISION DURING A STOP CONDITION (CASE 2)

SDAx

SCLx

BCLxIF

PEN

SSPxIF

TBRG TBRG TBRG

SDAx asserted low

SDAx sampled

low a fte r TBRG,

set BC L xIF

’0’

SDAx

SCLx

BCLxIF

PEN

SSPxIF

TBRG TBRG TBRG

Assert SDAx SCLx goes low before SDAx goes high,

set BC L xIF

’0’

 2010-2012 Microchip Technology Inc. DS41412F- page 257

PIC18(L)F2X/4XK22

TABLE 15-3: REGISTERS ASSOCIATED WITH I2C™ OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELA — — ANSA5 —ANSA3 ANSA2 ANSA1 ANSA0 154

ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1(1) ANSB0(1) 155

ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 155

ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1(2) ANSD0(2) 155

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129

IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125

PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

PMD1 MSSP2MD MSSP1MD —CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 56

SSP1ADD SSP1 Address Register in I2C Slave mode. SSP1 Baud Rate Reload Register in I2C Master mode. 265

SSP1BUF SSP1 Receive Buffer/Transmit Register —

SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 260

SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 262

SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 263

SSP1MSK SSP1 MAS K Register bits 264

SSP1STAT SMP CKE D/A PSR/WUA BF 259

SSP2ADD SSP2 Address Register in I2C Slave mode. SSP2 Baud Rate Reload Register in I2C Master mode. 265

SSP2BUF SSP2 Receive Buffer/Transmit Register —

SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 260

SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 262

SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 263

SSP2MSK SSP1 MAS K Register bits 264

SSP2STAT SMP CKE D/A PSR/WUA BF 259

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1(1) TRISB0(1) 156

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 156

TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1(2) TRISD0(2) 156

Legend: Shaded bits are not used by the M SSPx in I2C mode.

Note 1: PIC18(L)F2XK22 devices.

2: PIC18(L)F4XK2 2 devices.

PIC18(L)F2X/4XK22

DS41412F-page 258  2010-2012 Microchip Technology Inc.

15.7 Baud Rate Generator

The MSSPx module has a Baud Ra te Gene rato r avail-

able for clock generation in both I2C and SPI Master

modes. The Baud Rate Generator (BRG) reload value

is placed in the SSPxADD register (Register 15-6).

When a write occurs t o SSPxBUF, the Ba ud Rate Gen-

erator will automatically begin counting down.

Once the given operati on is complete, the i nternal clock

will automatically stop counting and the clock pin will

remain in its last state.

An internal signal “Reload” in Figure 15-40 triggers the

value from SSPxADD to be loaded into the BRG

counter. This occurs twice for each oscillation of the

module clock line. The logic dictating when the reload

signal is asserted depends on the mode the MSSPx is

being operated in.

Table 15-4 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPxADD.

EQUATION 15-1:

FIGURE 15-40: BAUD RATE GENERATOR BLOCK DIAGRAM

FCLOCK FOSC

SSPxADD 1+4

-------------------------------------------------=

Note: Values of 0 x00, 0x 01 and 0x02 are not vali d

for SSPxADD when used as a Baud Rate

Generator for I2C . This is an implement ation

limitation.

SSPxM<3:0>

BRG Down Counter

SSPxCLK FOSC/2

SSPxADD<7:0>

SSPxM<3:0>

SCLx

Reload

Control Reload

TABLE 15-4: MSSPx CLOCK RATE W/BRG

FOSC FCY BRG Value FCLOCK

(2 Rollovers of BRG)

32 MHz 8 MHz 13h 400 kHz(1)

32 MHz 8 MHz 19h 308 kHz

32 MHz 8 MHz 4Fh 100 kHz

16 MHz 4 MHz 09h 400 kHz(1)

16 MHz 4 MHz 0Ch 308 kHz

16 MHz 4 MHz 27h 100 kHz

4 MHz 1 MHz 09h 100 kHz

Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

 2010-2012 Microchip Technology Inc. DS41412F- page 259

PIC18(L)F2X/4XK22

15.8 Register Definitions: MSSP Control

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A PSR/WUA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SMP: SPI Data Input Sample bit

SPI Master mode:

1 = Input data sampled at end of data output time

0 = Input data s ampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

In I2 C Mas ter or Slave mode:

1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for high speed mode (400 kHz)

bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)

In SPI Master or Slave mode:

1 = Transmit occurs on transition from active to Idle clock state

0 = Transmit occurs on transition from Idle to active clock state

In I2 C mode only:

1 = Enable input logic so that thresholds are compliant with SMbus specification

0 = Disable SMbus specific inputs

bit 5 D/A: Data/Address bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

bit 4 P: Stop bit

(I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)

1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0 = Stop bit was not detected last

bit 3 S: Sta r t b i t

(I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)

1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0 = Start bit was not detected last

bit 2 R/W: Read/Write bit information (I2C m ode only)

This bit holds the R/W bit information following the l ast address match. This bit is only valid from the address match

to the next Start bit, Stop bit, or not ACK bit.

In I2 C Slave mode:

1 = R ead

0 = Write

In I2 C Master mode:

1 = Transmit is in progress

0 = Transmit is not in progress

OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode.

bit 1 UA: Update Address bit (10-bit I2C mode only)

1 = Indicates that the user needs to update the address in the SSPxADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

Receive (SPI and I2 C modes):

1 = Receive comp let e, SSPxBUF is full

0 = Receive not complete, SSPxBUF is empty

Transmit (I2 C mode only):

1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full

0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty

PIC18(L)F2X/4XK22

DS41412F-page 260  2010-2012 Microchip Technology Inc.

R/C/HS-0 R/C/HS-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPxOV SSPxEN CKP SSPxM<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared

bit 7 WCOL: Write Collision Detect bit

Master mode:

1 = A wr ite to the S SP xB UF register was attempted while t he I2C conditions were not valid for a transmission to

be started

0 = N o collision

Slave mode:

1 = The SSPxBUF register is written while i t is s till t ransmitting th e previous word (must be cleared in software)

0 = N o collision

bit 6 SSPxOV: Receive Overflow Indicator bit(1)

In SPI mode:

1 = A new byte is received while the SSPxBUF register is still ho lding the previous data. In case of overflow, the data

in SSPxSR is lost. Overflow can only occur in Sla ve mode. In Slave mode, the user must read the SSPxBUF, even

if only transmitting dat a, to avoid setti ng overflow . In Master mode, the overflow bi t is not se t since each new recep-

tion (and transmissi on) is init iated by writing to the SSPxBUF register (must be cleared in sof tware).

0 = N o overflow

In I2 C mode:

1 = A byt e is received while t he SS PxBUF register is s till holding the previous byte. SSPx OV is a “don’t care” in

Transmit mode (must be cleared in software).

0 = N o overflow

bit 5 SSPxEN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly configured as input or output

In SPI mode:

1 = Enables seri al port and conf igures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2)

0 = Disables serial port and configures these pins as I/O port pins

In I2 C mode:

1 = Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins(3)

0 = Disables serial port and configures these pins as I/O port pins

bit 4 CKP: Clock Polarity Select bit

In SPI mode:

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

In I2 C Slave mode:

SCLx release control

1 = Enable clock

0 = Holds clock low (clock stretch). (Used to ensure data setup time.)

In I2 C Master mode:

Unused in this mode

 2010-2012 Microchip Technology Inc. DS41412F- page 261

PIC18(L)F2X/4XK22

bit 3-0 SSPxM<3:0>: Synchronous Serial Port Mode Select bits

0000 = SPI Master mode, clock = FOSC/4

0001 = SPI Master mode, clock = FOSC/16

0010 = SPI Master mode, clock = FOSC/64

0011 = SPI Master mode, clock = TMR2 output/2

0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled

0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin

0110 = I2C Slave mode, 7-bit address

0111 = I2C Sl ave mode, 10-bit address

1000 = I2C Master mode, clock = FOSC / (4 * (SSPxADD+1))(4)

1001 = Reserved

1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))

1011 = I2C fi rmware controlled Master mode (slave idle)

1100 = Reserved

1101 = Reserved

1110 = I2C S lave mode, 7-bit address with Start and Stop bit interrupts enabled

1111 = I2C S lave mode, 10-bit address with Start and Stop bit interrupts enabled

Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the

SSPxBUF register.

2: When enabled, these pins must be properly configured as input or output.

3: When enabled, the SDAx and SCLx pins must be configured as inputs.

4: SSPxADD values of 0, 1 or 2 are not supported for I2C mode.

PIC18(L)F2X/4XK22

DS41412F-page 262  2010-2012 Microchip Technology Inc.

R/W-0 R-0 R/W-0 R/S/HC-0 R/S/HC-0 R/S/HC-0 R/S/HC-0 R/W/HC-0

GCEN ACKSTAT ACKDT ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set

bit 7 GCEN: General Call Enable bit (i n I 2C Slave mode only)

1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR

0 = General call address disabled

bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)

1 = Acknowledge was not received

0 = Acknowledge was received

bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)

In Receive mode:

Value transmitted when the user initiates an Acknowledge sequence at the end of a receive

1 = Not Acknowl edge

0 = Acknowledge

bit 4 ACKEN(1): Acknowledge Sequence Enable bit (in I2C Master mode on ly)

In Master Receive mode:

1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0 = Acknowledge sequence idle

bit 3 RCEN(1): Receive Enable bit (in I2C Master mode on ly)

1 = Enables Receive mode for I2C

0 = Receive idle

bit 2 PEN(1): Stop Condition Enable bit (in I2C Master mode only)

SCKx R elease Control:

1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.

0 = Stop condition Idle

bit 1 RSEN(1): Repeated Start Condition Enabled bit (in I2C Master mode only)

1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.

0 = Repeated Start condition Idle

bit 0 SEN(1): Start Condition Enabled bit (in I2C Master mode only)

In Master mode:

1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.

0 = Start condition Idle

In Slave mode:

1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0 = Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be

set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).

 2010-2012 Microchip Technology Inc. DS41412F- page 263

PIC18(L)F2X/4XK22

R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCLx clock

0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCLx clock

bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only)

1 = Enable interrupt on detection of Stop condition

0 = Stop detection interrupts are disabled(2)

bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mo de onl y)

1 = Enable interrupt on detection of Start or Restart condi tions

0 = Start detection interrupts are disabled(2)

bit 4 BOEN: Buffer Overwrite Enab le bit

In SPI Slave mode:(1)

1 = SSPxBUF updates every time that a ne w data byte is shifted in ignoring the BF bit

0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPxOV bit of the

SSPxCON1 register is set, and the buffer is not updated

In I2C Master mode:

This bit is ignored.

In I2C Slav e mode:

1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the

state of the SSPxOV bit only if the BF bit = 0.

0 = SSPxBUF is only updated when SSPxOV is clear

bit 3 SDAHT: SDAx Hold Time Selection bi t (I2C mode only)

1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx

0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx

bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)

If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the

BCLxIF bit of the PIR2 register is set, and bu s goes idle

1 = Enable slave bus collision interrupts

0 = Slave bus collision interrupts are disabled

bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)

1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the

SSPxCON1 register will be c l eared and the SCLx will be held low.

0 = Address holding is disabled

Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still

set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to

SSPxBUF.

2: This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as

enabled.

3: The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set.

PIC18(L)F2X/4XK22

DS41412F-page 264  2010-2012 Microchip Technology Inc.

bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)

1 = Foll ow in g the 8th falling edge of SC Lx f or a re ce ive d data byte; sla ve ha rdwa re c le ars th e C KP bi t

of the SSPxCON1 register and SCLx is held low.

0 = Data holding is disabled

Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still

set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to

SSPxBUF.

2: This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as

enabled.

3: The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-1 MSK<7:1>: Mask bits

1 = The received address bit n is compared to SSPxADD<n> to detect I2C address match

0 = The received address bit n is not used to detect I2C address match

bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address

I2C Slave mode, 10-bit address (SSPxM<3:0> = 0111 or 1111):

1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match

0 = The received address bit 0 is not used to detect I2C address match

I2C Slave mode, 7-bit address, the bit is ignored

 2010-2012 Microchip Technology Inc. DS41412F- page 265

PIC18(L)F2X/4XK22

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADD<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

Master mode:

bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits

SCLx pin clock per iod = ((ADD<7:0> + 1) *4)/FOSC

10-Bit Slave mode — Most Significant Address byte:

bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit

patt ern sen t by mast er is fixed by I2C sp ecificat ion and mu st be equa l to ‘11110’. Howeve r , those bits

are compared by hardware and are not affected by the value in this register.

bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.

10-Bit Slave mode — Least Significant Address byte:

bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bi t Slave mode:

bit 7-1 ADD<7:1>: 7-bit address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.

PIC18(L)F2X/4XK22

DS41412F-page 266  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 267

PIC18(L)F2X/4XK22

16.0 ENHANCED UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O

communications peripheral. It contains all the clock

generators, shift registers and data buffers necessary

to perform an input or output serial data transfer

independent of device program execution. The

EUSART, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous

system. Full-Duplex mode is useful for

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These device s typ icall y do n ot have inter nal cl ocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

The EUSART m odule includes the follow ing capabilities:

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

• One-ch arac ter out put buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

• Input buffer overrun error detection

• Received character framing error detection

• Half-du ple x sy nc hron ous master

• Half-du ple x sy nc hron ous slave

• Programmable clock and data polarity

The EUSART module implements the following

additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

• Automatic detection and cali bration of the baud rate

• Wake-up on Break reception

• 13-bit Break cha r ac ter transm it

Block diagrams of the EUSART transmitter and

receiver are shown in Figure 16-1 and Figure 16-2.

FIGURE 16-1: EUSART TRANS MIT BLOCK DIAGRAM

TXxIF

TXxIE

Interrupt

TXEN

TX9D

MSb LSb

Data Bus

TXREG x Regi s ter

Transmit Shift Register (TSR)

(8) 0

TX9

TRMT

TXx/CKx pin

Pin Buffer

and Control

SPBRGxSPBRGHx

BRG16

FOSC ÷ n

+ 1 Multiplier x4 x16 x64

SYNC 1X00 0

BRGH X110 0

BRG16 X101 0

Baud Rate Generator

•••

PIC18(L)F2X/4XK22

DS41412F-page 268  2010-2012 Microchip Technology Inc.

FIGURE 16-2: EUSART RECEIVE BLOCK DIAGRAM

The operation of the EUSART module is controlled

through three registers:

• Transmit Status and Control (TXSTAx)

• Receive Status and Control (RCSTAx)

• Baud Rate Control (BAUDCONx)

These registers are detailed in Register 16-1,

For all modes of EUSART operation, the TRIS control

bits corresponding to the RXx/DTx and TXx/CKx pins

should be set to ‘1’. The EUSART control will

autom ati c al ly re co nf ig ure the pin from i nput to output, as

needed.

When the receiv er or transmitter section is not enabled

then the corresp onding RXx /DTx or TXx /CKx pin ma y be

used for general purpose input and output.

RXx/DTx pin

Pin Buffer

and Control Data

Recovery

CREN OERR

FERR

RSR Register

MSb LSb

RX9D RCREGx Register FIFO

Interrupt

RCxIF

RCxIE

Data Bus

Stop START

(8) 7 1 0

RX9

• • •

SPBRGxSPBRGHx

BRG16

RCIDL

FOSC ÷ n

+ 1 Multiplier x4 x16 x64

SYNC 1X00 0

BRGH X110 0

BRG16 X101 0

Baud Rate Generato r

 2010-2012 Microchip Technology Inc. DS41412F- page 269

PIC18(L)F2X/4XK22

16.1 EUSART Asynchronous Mode

The EUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH mark state which

represents a ‘1’ data bit, and a VOL space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output l evel of that bit wi thout returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the mark state. Each character

transmission consists of one Start bit followed by eight

or nine data bits and is always terminated by one or

more Stop b its. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is eight bits. Each transmitted bit persists for a

period of 1/(Baud R ate). An on-chip dedicated 8-bit/16-

bit Baud Rate Generator is used to derive standard

baud rate frequencies from the system oscillator. See

Table 16-5 for examples of baud rate configurations.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

indepen dent, but share th e sa me dat a format and bau d

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data b it.

16.1.1 EUSART ASYNCHRONOUS

TRANSMITTER

The EUSART transmitter block diagram is shown in

Figure 16-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXREGx register.

16.1.1.1 Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

•TXEN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the TXEN bit of the TXST Ax register enables the

transmitter circuitry of the EUSART. Clearing the SYNC

bit of the TXSTAx register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTAx register enables the EUSART and

automatically configures the TXx/CKx I/O pin as an

output. If the TXx/CKx pin is shared with an analog

peripheral the analog I/O function must be disabled by

clearing the corresponding ANSEL bit.

16.1.1.2 Transmitting Data

A transmission is initiated by writing a character to the

TXREGx register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREGx is immediately

transferred to the TSR re gister. If the T SR still contains

all or part of a previous character, the new character

data is held in the TXREGx until the Stop bit of the

previous character has been transmitted. The pending

character in the TXREGx is then transferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXREGx.

16.1.1.3 Transmit Data Polarity

The polarity of the transmit data can be controlled with

the CKTXP bit of the BAUDCONx register. The default

state of this bit is ‘0’ which selects high true transmit

idle and data bits. Setting the CKTXP bit to ‘1’ will invert

the trans mit dat a resultin g in low t rue idle an d data b its.

The CKTXP bit controls transmit data polarity only in

Asynchronous mode. In Synchronous mode the

CKTXP bit has a dif ferent function.

16.1.1.4 Transmit Interrupt Flag

The TXxIF interr upt f lag bit of the PIR 1/P IR3 register is

set whenever the EUSART transmitter is enabled and

no character is being held for transmission in the

TXREGx. In other words, the TXxIF bit is only clear

when the TSR is busy with a character and a new

character has been queued for transmission in the

TXREGx. The TXxIF flag bit is not cleared immediately

upon writing TXREGx. TXxIF becomes valid in the

second instruction cycle following the write execution.

Polling TXxIF immediately followi ng the TXREGx write

will return invalid results. The TXxIF bit is read-only, it

cannot be set or cleared by software.

The TXxIF interrupt can be enabled by setting the

TXxIE interrupt enable bit of the PIE1/PIE3 register.

However, the TXxIF flag bit will be set whenever the

TXREGx is empty, regardless of the state of TXxIE

enable bi t.

To use interru pts when t ransm itting dat a, set the TXx IE

bit only when there is more data to send. Clear the

TXxIE interrupt enable bit upon writing the last

character of the transmission to the TXREGx.

Note: The TXxIF transmitter interrupt flag is set

when the TXEN enable bit is set.

PIC18(L)F2X/4XK22

DS41412F-page 270  2010-2012 Microchip Technology Inc.

16.1.1.5 TSR Status

The TRMT bit of the TXSTAx register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

until all bits have been shifted out of the TSR register.

No int errupt lo gic i s tied to this bi t, so th e user needs to

poll this bit to determine the TSR status.

16.1.1.6 Transmitting 9-Bit Characters

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTAx register is set the

EUSAR T will shift nine bits out for each character trans-

mitted. The TX9D bit of the TXSTAx register is the

ninth, and Most Sign ifican t, dat a bit. When transmi tting

9-bit data, the TX9D data bit must be written before

writing the eight Least Signi ficant bit s into th e TXREGx.

All ni ne b its of data wi ll be tran sfe rred to t he T SR sh ift

A special 9-bit Address mode is available for use with

multiple receivers. See Section 16.1.2.8 “Address

Detection” for more information on the Address mod e.

16.1.1.7 Asynchronous Transmission Setup:

1. Initialize the SPBRGHx:SPBRGx register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 16.4 “EUSART

Baud Rate Generator (BRG)”).

2. Set the RXx/DTx and TXx/CKx TRIS controls to

‘1’.

3. Enable the asy nch ron ous seri al port by clearin g

the SYNC bit and setting the SPEN bit.

4. If 9-bit tran sm ission is desired, s et th e TX9 co n-

trol bit. A set ninth data bit will indicate that the

eight Least Significant data bits are an address

when the receiver is set for address detection.

5. Set the CKTXP control bit if inverted transmit

data polarity is desired.

6. Enable the transmission by setting the TXEN

control bi t. This will cau se the TXxIF inte rrupt bit

to be set.

7. If interrupts are desired, set the TXxIE interrupt

enable bit. An interrupt will occur immediately

provided that the GIE/GIEH and PEIE/GIEL bits

of the INTCON register are also set.

8. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

9. Load 8-bit data into the TXREGx register. This

will start the transmission.

FIGURE 16-3: ASYNCHRONOUS TRANSMISSION

Note: The TSR register is not mapped in data

memory, so it is not available to the user.

Word 1 Stop bit

Word 1

Transmit Shift Reg

Start bit bit 0 bit 1 bit 7/8

Write to TXREGx Word 1

BRG Output

(Shift Clock)

TXx/CKx

TXxIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Trans mit Sh ift

Reg. Empty Flag)

1 TCY

 2010-2012 Microchip Technology Inc. DS41412F- page 271

PIC18(L)F2X/4XK22

FIGURE 16-4: ASYNCHRONOUS TRANSMIS SION (BACK-TO-BACK)

Transmit Shift Reg

Write to TXREGx

BRG Output

(Shift Clock)

TXx/CKx

TXxIF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1 Wor d 2

Word 1 Word 2

Start bit Stop bit Start bit

Transmit Shift Reg

Word 1 Word 2

bit 0 bit 1 bit 7/8 bit 0

Note: This timing diagram shows two consecutive transmissions.

1 TCY

TABLE 16-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

Page

BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

SPBRG1 EUSART1 Baud Rate Generator, Low Byte —

SPBRGH1 EUSART1 Baud Rate Generator, High Byte —

SPBRG2 EUSART2 Baud Rate Generator, Low Byte —

SPBRGH2 EUSART2 Baud Rate Generator, High Byte —

TXREG1 EUSART1 Transmit Register —

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

TXRE G2 EUSART 2 Transmit Regist er —

TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

Legend: — = unimplemented locations, read as ‘0’. S haded bits are not used fo r as ynchron ous transm issi on.

PIC18(L)F2X/4XK22

DS41412F-page 272  2010-2012 Microchip Technology Inc.

16.1.2 EUSART ASYNCHRONOUS

RECEIVER

The Asynchronous mode would typically be used in

RS-232 s y ste ms . Th e rec ei ve r bl ock di ag ram is sh ow n

in Figure 16-2. The data is received on the RXx/DTx

pin and drives the data recovery block. The data

recovery block is actually a high-speed shifter

operating at 16 times the baud rate, whereas the serial

Receive Shift Register (RSR) operates at the bit rate.

When all eight or nine bits of the character have been

shifted in, they are immediately transferred to a two

character First-In-First-Out (FIFO) memory. The FIFO

buffering allows reception of two complete characters

and the start of a third character before software must

start servicing the EUSART receiver. The FIFO and

RSR r egisters are not di rectly ac cessibl e by softwar e.

Access to the received data is via the RCREGx

16.1.2.1 Enabling the Receiver

The EUSART receiver is enabled for asynchronous

operatio n by configuring the fol lowing three control bits:

• CREN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTAx register enables

the receiver circuitry of the EUSART. Clearing the

SYNC bit of the TXSTAx register configures the

EUSART for asynchronous operation. Setting the

SPEN bit of the RCSTAx register enables the

EUSART. The RXx/DTx I/O pin must be configured as

an input by setting the corresponding TRIS control bit.

If the RXx/DTx pin is shared with an analog peripheral

the analog I/O function must be disabled by clearing

the corresponding ANSEL bit.

16.1.2.2 Receiving Data

The receiver data recovery circuit initiates character

receptio n on t he fallin g edge of the first bit. Th e f irst bit,

also known as the Start bit, is always a zero. The data

recovery circuit co unt s one-h alf bi t time to the c enter of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit c ounts a full bit time to the ce nter of the

next bit. The bit is then sampled by a majority detect

circuit and the resultin g ‘0’ or ‘1’ is sh ifted int o the RSR.

This repeats until all data bits have been sampled and

shif ted into the RSR. One final bit time is measured and

the le ve l samp le d . Thi s is th e Stop bi t, w hic h is alwa ys

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

charact er , otherwise th e framing error is c leared for thi s

character. See Section 16.1.2.5 “Receive Framing

Error” for more information on framing errors.

Immediately after all data bits and the Stop bit have

been received, the character in the R SR is transferred

to the EUSART receive FIFO and the RCxIF interrupt

flag bit of th e PIR1/PIR3 regist er is set. The top ch arac-

ter in t he FIFO i s transfe rred out o f the FIFO by readin g

the RCREGx register.

16.1.2.3 Receive Data Polarity

The polarity of the receive data can be controlled with

the DTRXP bit of the BAUDCONx register. The default

state of this b it is ‘0’ wh ich select s h igh true rece ive idle

and dat a bits. Setting the DTRXP bit to ‘1’ will invert the

receive data re sulting in low true idle and da ta bit s. The

DTRXP bit controls receive data polarity only in Asyn-

chro nous mode. In Sy nchr ono us mod e th e DTRX P bit

has a different function.

Note: If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition is cleared. See Section 16.1.2.6

“Receive Overrun Error” for more

information on overrun errors.

 2010-2012 Microchip Technology Inc. DS41412F- page 273

PIC18(L)F2X/4XK22

16.1.2.4 Receive Interrupts

The RCxIF i nterrupt flag b it of the PI R1/PIR3 regist er is

set whenever the EUSART receiver is enabled and

there is an unread character in the receive FIFO. The

RCxIF interrupt flag bit is read-only, it cannot be set or

clea red by software.

RCxIF interrupts are enabled by setting the following

bits:

• RCxIE interrupt enable bit of the PIE1/PIE3

• PEIE/GIEL peripheral interrupt enable bit of the

INTCON register

• GIE/GIEH global interrupt enable bit of the

INTCON register

The RCxI F interru pt flag bi t will be set when there is an

unread c haract er in the FIF O, regardless of the st ate of

inter rupt ena ble bit s .

16.1.2.5 Receive Framing Error

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indic ates t hat a Stop bit was not se en at t he expec ted

time. The framing error status is accessed via the

FERR bit of the RCSTAx register. The FERR bit

represen ts the s ta tus o f the top u nread charac ter in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCREG.x

The FERR bit is read-only and only applies to the top

unre ad char acter in the re ceive F IFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCSTAx register which resets the EUSART.

Cleari ng the CRE N bit of the RCSTAx regis ter does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

16.1.2.6 Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be genera ted if a th ird charac ter , in it s

entirety , is received before the FIFO is accessed. When

this happens the OERR bit of the RCSTAx register is

set. The characters already in the FIFO buffer can be

read but no additional characters will be received until

the error is c leared. The error mu st be cleared by eith er

clearing the CREN bit of the RCSTAx register or by

resetting the EUSART by clearing the SPEN bit of the

RCSTAx regist er.

16.1.2.7 Receiving 9-bit Characters

The EUSAR T support s 9-bit chara cter receptio n. When

the RX9 bit of the RCS TAx register is set, t he EUS AR T

will shift nine bits into the RSR for each character

received. The RX9D bit of the RCSTAx register is the

ninth and Most Significant data bit of the top unread

charact er i n t he rec eiv e FIFO . Whe n r ead ing 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREGx.

16.1.2. 8 Addres s Detecti on

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTAx

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffe r , thereby setti ng the RCxIF interru pt

bit. All other characters will be ignored.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit oc cu rs. When user sof tware detect s th e end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

Note: If all receive characters in the receive

FIFO hav e fram ing erro rs, repea ted rea ds

of the RCREGx will not clear the FERR

bit.

PIC18(L)F2X/4XK22

DS41412F-page 274  2010-2012 Microchip Technology Inc.

16.1.2.9 Asynchronous Reception Setup:

1. Initialize the SPBRGHx:SPBRGx register pair

and the BRGH and BRG16 bits to achieve the

des i red baud rate (see Section 16.4 “EUSART

Baud Rate Generator (BRG)”).

2. Set the RXx/DTx and TXx/CKx TRIS controls to

‘1’.

3. Enable the serial port by setting the SPEN bit

and the RXx/DTx pin TRIS bit. The SYNC bit

must be clear for asynchronous operation.

4. If interrupts are desired, set the RCxIE interrupt

enable bi t and set the GIE/GIEH and PEIE/G IEL

bits of the INTCON register.

5. If 9-bit reception is desired, set the RX9 bit.

6. Set the DTRXP if inverted receive polarity is

desired.

7. Enable reception by setting the CREN bit.

8. The RCxIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCxIE interrupt enable bit was also set.

9. Read the RCSTAx register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data b it.

10. Get the rece ived eight Least Signif icant data bit s

from the receive buffer by reading the RCREGx

11. If an overrun occurred, clear the OERR flag by

clearing the C REN r eceiver e nable bit.

16.1.2.10 9-bit Address Detection Mode Setup

This m ode w o uld ty pi cally be used in RS-485 syste ms .

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGHx, SPBRGx register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (s ee Section 16.4 “EUSART

Baud Rate Generator (BRG)”).

2. Set the RXx/DTx and TXx/CKx TRIS controls to

‘1’.

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

4. If interrupts are desired, set the RCxIE interrupt

enable bi t and set the GIE/GIEH and PEIE/GIEL

bits of the INTCO N register .

5. Enable 9-bit reception by setting the RX9 bit.

6. Enable a ddress d etection by setting the ADDEN

bit.

7. Set the DTRXP if inverted receive polarity is

desired.

8. Enable reception by setting the CREN bit.

9. The RCxIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will be generated if the RCxIE interrupt enable

bit was also set.

10. Read the RC STAx registe r to get the error flags.

The ninth data bit will always be set.

1 1. Get the received eight Least Significa nt data bits

from the receive buffer by reading the RCREGx

device’s address.

12. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

13. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

 2010-2012 Microchip Technology Inc. DS41412F- page 275

PIC18(L)F2X/4XK22

FIGURE 16-5: ASYNCHRONOUS RECEPTION

Start

bit bit 7/8

bit 1bit 0 bit 7/8 bit 0Stop

bit

Start

bit Start

bit

bit 7/8 Stop

bit

RXx/DTx pin

Reg

Rcv Buffer Reg

Rcv Shift

Read Rcv

Buffer Reg

RCREGx

RCxIF

(Interrupt Flag)

OERR bit

CREN

Word 1

RCREGx Word 2

RCREGx

Stop

bit

Note: This ti ming diagram shows three w ords a ppe ari n g o n th e RXx/ DTx i n pu t. T he RCREGx ( rec ei ve buffer) is r ead after the third

word, causing the OERR (overrun) bit to be set.

RCIDL

TABLE 16-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 279

BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 279

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

RCREG1 EUS ART1 Receive Register —

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

RCREG2 EUS ART2 Receive Register —

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

SPBRG1 EUSART1 Baud Rate Generator, Low Byte —

SPBRGH1 EUSART1 Baud Rate Generato r, High Byte —

SPBRG2 EUSART2 Baud Rate Generator, Low Byte —

SPBRGH2 EUSART2 Baud Rate Generato r, High Byte —

TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 156

TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 156

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

Legend: — = unimplem ented loca t io ns, read as ‘0’ . Sh ade d bi ts are not used for asynchronous rec ept ion.

Note 1: PIC18(L)F4XK 22 devices.

2: PIC1 8(L) F2XK 22 devices.

PIC18(L)F2X/4XK22

DS41412F-page 276  2010-2012 Microchip Technology Inc.

16.2 Clock Accuracy with

Asynchronous Operation

The factory calibrates the internal oscillator block

output (HFINTOSC). However, the HFINTOSC

frequency may drift as VDD or temperature changes,

and this directly affects the asynchronous baud rate.

Two methods may be used to adjust the baud rate

clock, but both require a reference clock source of

some kind.

The first (preferred) method uses the OSCTUNE

value in the OSCTUNE register allows for fine

resolution changes to the system clock source. See

Section 2.6 “Internal Clock Modes” for more

information.

The other method adjusts the value in the Baud Rate

Generator. This can be done automatically with the

Auto-Baud Detect feature (see Section 16.4.1 “Auto-

Baud Detect”). There may not be fine enough

resolution when adjusting the Baud Rate Generator to

compensate for a gradual change in the peripheral

clock frequency.

 2010-2012 Microchip Technology Inc. DS41412F- page 277

PIC18(L)F2X/4XK22

16.3 Reg is ter De finitions : E U S A R T C on t r ol

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1 = M aster mode (clock generated internally from BRG)

0 = Slav e mode (clock from external so urce)

bit 6 TX9: 9-bit Transmit Enable bit

1 = Selec ts 9-bit transmission

0 = Selec ts 8-bit transmission

bit 5 TXEN: Tr ansmit Enable bit(1)

1 = Transmit enabled

0 = Transmit disabled

bit 4 SYNC: EUSART Mode Select bit

1 = S ync hronous mode

0 = A sy nchronous mode

bit 3 SENDB: Send Break Character bit

Asynchronous mode:

1 = S end Sync Break on next transmission (cleared by hardware upon completion)

0 = S ync Break transmiss i on completed

Synchronous mode:

Don’t care

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = H igh speed

0 = L ow speed

Synchronous mode :

Unused in this mode

bit 1 TRMT: Trans mit Sh ift Register Status bit

1 = TS R empty

0 = TSR full

bit 0 TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC18(L)F2X/4XK22

DS41412F-page 278  2010-2012 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins)

0 = Serial port disabled (held in Reset)

bit 6 RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1 = En ables singl e receive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronou s mod e – Slave

Don’t care

bit 4 CREN: Continuous Receiv e Enab le bit

Asynchronous mode:

1 = Enables receiver

0 = Disables receiver

Synchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables continuous receiv e

bit 3 ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

bit 2 FERR: Framing Error bit

1 = Framing erro r (can be updated by reading RCREGx register and receive next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit CREN)

0 = No overrun error

bit 0 RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

 2010-2012 Microchip Technology Inc. DS41412F- page 279

PIC18(L)F2X/4XK22

R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unim pl em ented bit, rea d as ‘0 ’

-n = Value at POR ‘1’ = Bit is set ‘ 0’ = B it is clear ed x = Bit is unknown

bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asy nchronous mode:

1 = Auto-baud timer overflowed

0 = Auto - baud timer did not overflo w

Syn chr on ous mode:

Don’t care

bit 6 RCIDL: Receive Idle Fl ag bit

Asy nchronous mode:

1 = Receiver is Idle

0 = Start bit has been det ect ed and the re cei ver is activ e

Syn chr on ous mode:

Don’t care

bit 5 DTRXP: Data/Recei ve P o l a rity Selec t b it

Asy nchronous mode:

1 = Receive data (RXx) is inverted (active-low)

0 = Recei ve data (RXx) is not i nverted (a ctive-high)

Syn chr on ous mode:

1 = Data (DTx) is inverted (active-low)

0 = Data (DTx) is not in ve rt ed (ac tive-high)

bit 4 CKTXP: Clock/Transmit Polarity Select bit

Asy nchronous mode:

1 = Idle state for transmit (TXx) is low

0 = Idle state for transmit (TXx) is high

Syn chr on ous mode:

1 = Data changes on the fall in g edge of the clock and is sam pled on the risi ng edge of the cl ock

0 = Data changes on the risin g edge of the clock and i s sa mpled on th e fa lling edge of the clock

bit 3 BRG16: 16 -b it Bau d R at e Generator bi t

1 = 16-bit Baud Rate Generator is used (SPBRGHx:SPBRGx)

0 = 8-bit Baud Rate Generator is used (SPBRGx)

bit 2 Unimplemented: Re ad as ‘0’

bit 1 WUE: Wake-up Enable bit

Asy nchronous mode:

1 = Receiver is waiting for a falling edge. No character will be received but RCxIF will be set on the falling

edge. WUE will automatically clear on the rising edge.

0 = Receiver is operating normally

Syn chr on ous mode:

Don’t care

bit 0 ABDEN: Auto-Ba ud Detect Enable bit

Asy nchronous mode:

1 = Auto-Baud Detec t mo de is enabled (c le ar s w hen auto-b aud is complet e)

0 = Auto-Baud Detec t mo de is di sabled

Syn chr on ous mode:

Don’t care

PIC18(L)F2X/4XK22

DS41412F-page 280  2010-2012 Microchip Technology Inc.

16.4 EUSART Baud Rate Generator

(BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the

asynchronous and synchronous EUSART operation.

By defau lt, the BRG ope rates in 8-bit mode . Setting th e

BRG16 bit of the BAUDCONx register selects 16-bit

mode.

The SPBRGHx:SPBRGx register pair determines the

period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate

period is determined by both the BRGH bit of the

TXSTAx register and the BRG16 bit of the BAUDCONx

Table 16-3 contains the formulas for determining the

baud rate . Example 16-1 provides a sam ple calcul ation

for determining the baud rate and baud rate error.

Typical baud rates and error values for various

Asynchronous modes have been computed for your

convenience and are shown in Table 16-5. It may be

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG (BRG16 = 1) to reduce th e baud rate

error. The 16-bit BRG mode is used to achieve slow

baud rates for fast oscillator frequencies.

Writing a new value to the SPBRGHx, SPBRGx

cleared). This ensures that the BRG does not wait for a

timer overflow before outputting the new baud rate.

If the s ys tem c lo ck is changed during an active receiv e

operation, a receive error or data loss may result. To

avoid thi s problem , check the status of the RCID L bit to

make sure that the receive operation is Idle before

changing the system clock.

EXAMPLE 16-1: CALCULATIN G BAUD

RATE ERROR

For a devi ce w ith FOSC of 16 MHz, des ired baud rate

of 9600, Asynch rono us mode, 8-bit BRG:

Solving for SPBRGHx:SPBRGx:

FOSC

Desired Ba ud R at e

---------------------------------------------

--------------------------------------------- 1–=

Desired Baud Rate FOSC

64 [SPBRGHx:SPBRGx] 1+

--------------------------------------------------------------------------=

16000000

9600

------------------------

------------------------1–=

25.04225==

Calculated Baud Rate 16000000

64 25 1+

---------------------------=

9615=

Error Calc. Bau d Rate Desired Baud Rate –

Desired Baud Rate

--------------------------------------------------------------------------------------------=

9615 9600–

9600

---------------------------------- 0.16%==

TABLE 16-3: BAUD RATE FORMULAS

Configuration Bits BRG/EUSART Mode Baud Rate Form ula

SYNC BRG16 BRGH

000 8-bit/Asynchronous FOSC/[64 (n+1)]

001 8-bit/Asynchronous FOSC/[16 (n+1)]

010 16-bit/Asynchronous

011 16-bit/Asynchronous

FOSC/[4 (n+1)]10x 8-bit/Synchronous

11x 16-bit/Synchronous

Legend: x = Don’t care, n = value of SPBRGHx, SPBRGx register pair.

 2010-2012 Microchip Technology Inc. DS41412F- page 281

PIC18(L)F2X/4XK22

TABLE 16-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0 Reset

Values

on Page

BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

SPBRG1 EUSART1 Baud Rate Gener at or, Low Byte —

SPBRGH1 EUSART1 Baud Rate Gener ator, High Byte —

SPBRG2 EUSART2 Baud Rate Gener at or, Low Byte —

SPBRGH2 EUSART2 Baud Rate Gener ator, High Byte —

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

Legend: — = unimplement ed, read as ‘0’. Shaded bits are not used by t he BR G.

TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz

Actual

Rate %

Error

SPBRxG

value

(decimal)

Actual

Rate %

Error

SPBRGx

value

(decimal)

Actual

Rate %

Error

SPBRGx

value

(decimal)

Actual

Rate %

Error

SPBRGx

value

(decimal)

300 — — — — — — — — — — — —

1200 —— — 1200 0.00 239 1202 0.16 207 1200 0.00 143

2400 —— — 2400 0.00 119 2404 0.16 103 2400 0.00 71

9600 9615 0.16 103 9600 0.00 29 9615 0.16 25 9600 0.00 17

10417 10417 0.00 95 10286 -1.26 27 10417 0.00 23 10165 -2.42 16

19.2k 19.23k 0.16 51 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8

57.6k 58.82k 2.12 16 57.60k 0.00 7—— —

57.60k 0.00 2

115.2k 111.11k -3.55 8 — — — — — — — — —

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRGx

value

(decimal)

Actual

Rate %

Error

SPBRGx

value

(decimal)

Actual

Rate %

Error

SPBRGx

value

(decimal)

Actual

Rate %

Error

SPBRGx

value

(decimal)

300 — — — 300 0.16 207 300 0.00 191 300 0.16 51

1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12

2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —

9600 9615 0.16 12 — — — 9600 0.00 5 — — —

10417 10417 0.00 11 10417 0.00 5 — — — — — —

19.2k — — — — — — 19.20k 0.00 2 — — —

57.6k — — — — — — 57.60k 0.00 0 — — —

115.2k — — — — — — — — — — — —

PIC18(L)F2X/4XK22

DS41412F-page 282  2010-2012 Microchip Technology Inc.

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz

Actual

Rate %

Error

SPBRGx

value

(decimal)

Actual

Rate %

Error

SPBRGx

value

(decimal)

Actual

Rate %

Error

SPBRGx

value

(decimal)

Actual

Rate %

Error

SPBRGx

value

(decimal)

300 —— — —— — — — — — — —

1200 — — — — — — — — — — — —

2400 — — — — — — —— — —— —

9600 — — — 9600 0.00 119 9615 0.16 103 9600 0.00 71

10417 — — — 10378 -0.37 110 10417 0.00 95 10473 0.53 65

19.2k 19.23k 0.16 207 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35

57.6k 57.97k 0.64 68 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11

115.2k 114.29k -0.79 34 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRGx

value

(decimal)

Actual

Rate %

Error

SPBRGx

value

(decimal)

Actual

Rate %

Error

SxBRGx

value

(decimal)

Actual

Rate %

Error

SPBRGx

value

(decimal)

300 —— — — — — — — — 300 0.16 207

1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51

2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25

9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —

10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5

19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —

57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —

115.2k — — — — — — 115.2k 0.00 1 — — —

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz

Actual

Rate %

Error

SPBRGHx:

SPBRGx

(decimal)

Actual

Rate %

Error

SPBRGHx:

SPBRGx

(decimal)

Actual

Rate %

Error

SPBRGHx

:SPBRGx

(decimal)

Actual

Rate %

Error

SPBRGHx:

SPBRGx

(decimal)

300 300.0 0.00 13332 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303

1200 1200.1 0.01 3332 1200 0.00 959 1200.5 0.04 832 1200 0.00 575

2400 2399 -0.02 1666 2400 0.00 479 2398 -0.08 416 2400 0.00 287

9600 9592 -0.08 416 9600 0.00 119 9615 0.16 103 9600 0.00 71

10417 10417 0.00 383 10378 -0.37 110 10417 0.00 95 10473 0.53 65

19.2k 19.23k 0.16 207 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35

57.6k 57.97k 0.64 68 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11

115.2k 114.29k -0.79 34 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5

TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

 2010-2012 Microchip Technology Inc. DS41412F- page 283

PIC18(L)F2X/4XK22

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRGHx:

SPBRGx

(decimal)

Actual

Rate %

Error

SPBRGHx:

SPBRGx

(decimal)

Actual

Rate %

Error

SPBRGHx

:SPBRGx

(decimal)

Actual

Rate %

Error

SPBRGHx:

SPBRGx

(decimal)

300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207

1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51

2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25

9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —

10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5

19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —

57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —

115.2k — — — — — — 115.2k 0.00 1 — — —

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 64.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz

Actual

Rate %

Error

SPBRGHx:

SPBRGx

(decimal)

Actual

Rate %

Error

SPBRGHx:

SPBRGx

(decimal)

Actual

Rate %

Error

SPBRGHx

:SPBRGx

(decimal)

Actual

Rate %

Error

SPBRGHx:

SPBRGx

(decimal)

300 300 0.00 53332 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215

1200 1200 0.00 13332 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303

2400 2400 0.00 6666 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151

9600 9598.1 -0.02 1666 9600 0.00 479 9592 -0.08 416 9600 0.00 287

10417 10417 0.00 1535 10425 0.08 441 10417 0.00 383 10433 0.16 264

19.2k 19.21k 0.04 832 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143

57.6k 57.55k -0.08 277 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47

115.2k 115.11k -0.08 138 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRGHx:

SPBRGx

(decimal)

Actual

Rate %

Error

SPBRGHx:

SPBRGx

(decimal)

Actual

Rate %

Error

SPBRGHx

:SPBRGx

(decimal)

Actual

Rate %

Error

SPBRGHx:

SPBRGx

(decimal)

300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832

1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207

2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103

9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25

10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23

19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12

57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —

115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —

TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

PIC18(L)F2X/4XK22

DS41412F-page 284  2010-2012 Microchip Technology Inc.

16.4.1 AUTO-BAUD DETECT

The EUSART module supports automatic detection

and calibration of the baud rate.

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the

incomi ng R Xx si gna l, the RXx s ignal is t iming the BR G.

The Baud Rate Generator is used to time the pe riod of

a receiv ed 55h (ASCII “U ”) which is the Sync character

for the LIN bus. The unique feature of this character is

that it has five rising edges in cluding the S top bit ed ge.

Setting the ABDEN bit of the BAUDCONx register

starts the auto-baud calibration sequence

(Section 16.4.2 “Auto-baud Overflow”). While the

ABD sequence takes place, the EUSART state

machine is held in Idle. On the first rising edge of the

receive line, after the Start bit, the SPBRGx begins

counting up using the BRG counter clock as shown in

Table 16-6. The f i fth r i si ng e dg e wi ll oc cu r o n t h e RX x/

DTx p in at the e nd of the eighth bit pe riod . At that time,

an accumulated value totaling the proper BRG period

is left in the SPBRGHx:SPBRGx register pair, the

ABDEN bit is automatically cleared, and the RCxIF

interrupt flag is set. A read operation on the RCREGx

needs to be performed to clear the RCxIF interrupt.

RCREGx content should be discarded. When

calibrating for modes that do not use the SPBRGHx

did not overflow by checking for 00h in the SPBRGHx

The BRG au to-baud clock is d etermined by the BRG1 6

and BRGH bits as shown in Table 16-6. During ABD,

both the SPBRGHx and SPBRGx registers are used as

a 16-bit c ou nte r, independent of th e BR G 16 bit se ttin g.

While calibrating the baud rate period, the SPBRGHx

and SPBRGx registers are clocked at 1/8th the BRG

base clo ck rate. The resu lting byte meas urement is the

average bit time when clocked at full speed.

FIGURE 16-6: AUTOMATIC BAUD RATE CALIBRATION

Note 1: If the WUE bit is set with the ABDEN bit,

auto-bau d detection will occur on the byte

following the Break character (see

Section 16.4.3 “Auto-Wake-up on

Break”).

2: It is up to the user to determine that the

incoming character baud r ate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible.

3: During the auto-baud process, the auto-

baud counter starts counting at one. Upon

completion of the auto-baud sequence, to

achieve maximum accuracy, subtract one

from the SPBRGHx:SPBRGx register pair .

TABLE 16-6: BRG COUNTER CLOCK

RATES

BRG16 BRGH BRG Base

Clock BRG ABD

Clock

00FOSC/64 FOSC/512

01FOSC/16 FOSC/128

10FOSC/16 FOSC/128

11 FOSC/4 FOSC/32

Note: During the ABD sequence, SPBRGx and

SPBRGHx registers are both used as a

16-bit counter, independent of BRG16

setting.

BRG Value

RXx/DTx pin

ABDEN bit

RCxIF bit

bit 0 bit 1

(Interrupt)

Read

RCREGx

BRG Clock

Start

Auto Cleared

Set by User

XXXXh 0000h

Edge #1 bit 2 bit 3

Edge #2 bit 4 bit 5

Edge #3 bit 6 bit 7

Edge #4 Stop bit

Edge #5

001Ch

Note 1: The ABD seq uen ce requ ire s the EUSART mo dule to be confi gur ed in Asynchr ono us mod e.

SPBRGx XXh 1Ch

SPBRGHx XXh 00h

RCIDL

 2010-2012 Microchip Technology Inc. DS41412F- page 285

PIC18(L)F2X/4XK22

16.4.2 AUTO-BAUD OVERFLOW

During the course of automatic baud detection, the

ABDOVF bi t of the BAUDCONx re gister will be set if the

baud rate cou nte r ove rf lows bef or e the fifth risin g edg e

is detected on the RX pin. The ABDOVF bit indicates

that the counter has exceeded the maximum count that

can fit in th e 16 bits of the SPBRGHx:SPBR Gx regis ter

pair. After th e ABD OVF has been set , the co unt er con-

tinues to co unt until t he fifth rising ed ge is detect ed on

the RXx/DTx pin. Upon detecting the fifth RXx/DTx

edge, the hardware will set the RCxIF interrupt flag and

clear the ABDEN bit of the BAUDCONx register. The

RCxIF flag can be subsequently cleared by reading the

RCREGx. The ABDOVF flag can be cleared by soft-

ware directly.

To terminate the auto-baud process before the RCxIF

flag is set, clear the ABDEN bit then clear t he ABDOVF

bit. The ABDOVF bit will rem ain s et i f th e ABDEN b it is

not clear ed first.

16.4.3 AUTO-WAKE-UP ON BREAK

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be

performed. The Auto-Wake-up feature allows the

controller to wake-up due to activity on the RXx/DTx

line. This feature is available only in Asynchronous

mode.

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUDCONx register. Once set, the

normal rec ei ve s equ enc e on R Xx/ D Tx is dis abl ed, and

the EUSART remains in an Idle state, monitoring for a

wake-u p event indepen dent of the CPU mode. A wake-

up event consists of a high-to-low transition on the

RXx/DTx line. (This coincides with the start of a Sync

Break or a wake-up signal character for the LIN

protocol.)

The EUSART module generates an RCxIF interrupt

coincident with the wake-up event. The interrupt is

generated s ynchronously to the Q clocks in normal CPU

operating modes (Figure 16-7), and asynchronously if

the device is in Sleep mode (Figure 16-8). The interrupt

condition is cleared by read ing the R CREGx regi ster.

The WUE bit is automatically cleared by the low-to-high

transition on the RXx line at the end of the Break. This

signals to the user that the Break event is over. At this

point, the EUSART module is in Idle mode waiting to

receive the next character.

16.4.3.1 Special Considerations

Brea k Cha ract er

To avoid character errors or character fragments during

a wake-up event, the wake-up character must be all

zeros.

When the wake-up is enabled the function works

independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is

receive d, the low time from the S tart bit to the first ris ing

edge will be interpreted as the wake-up event. The

remaining bits in the character will be received as a

fragmented character and subsequent characters can

result in framing or overrun errors.

Therefore, the ini tial cha racter in the transmi ssion mus t

be all ‘0’s. This must be 10 or more bit times, 13-bit

times recommended for LIN bus, or any number of bit

times for standard RS-232 devices.

Oscillator Start-up Time

Oscillator start-up time must be considered, especially

in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS/PLL mode). The Sync

Break (or wake-up signal) character must be of

sufficient length, and be followed by a sufficient

interval , to allow eno ugh ti me fo r the se lecte d osc illat or

to start and provide proper initialization of the EUSART.

WUE Bit

The wake-up event causes a receive interrupt by

setting the RCxIF bit. The WUE bit is cleared by

hardware by a rising edge on RXx/DTx. The interrupt

condition is then cleared by software by reading the

RCREGx register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process

before set ting the WU E bit. If a recei ve opera tion is n ot

occurring, the WUE bit may then be set just prior to

entering the Sleep mode.

PIC18(L)F2X/4XK22

DS41412F-page 286  2010-2012 Microchip Technology Inc.

FIGURE 16-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

FIGURE 16-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1 Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4 Q1Q2 Q3Q4

OSC1

WUE bit

RXx/DTx Line

RCxIF

Bit set by user Auto Cleared

Cleared due to User Read of RCREGx

Note 1: The EUSART remains in Idle while the WUE bit is set.

Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4

OSC1

WUE bit

RXx/DTx Line

RCxIF

Bit Set by User Auto Clear ed

Cleared due to User Read of RCREGx

Sleep Command Executed

Note 1

Note 1: If the wake-u p event requ ires long oscillator warm-up time, the automa tic clearing of the WUE bi t can occur wh ile the stposc signal is

still active. This sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

Sleep Ends

 2010-2012 Microchip Technology Inc. DS41412F- page 287

PIC18(L)F2X/4XK22

16.4.4 BREAK CHARACTER SEQUENCE

The EUSART module ha s t he c apability of s en din g th e

special Break character sequen ces that are required by

the LIN bus standard. A Break character consists of a

Start bit, follo w ed by 12 ‘0’ bits and a Stop bit.

To send a Break character, set the SENDB and TXEN

bits of the TXSTAx register . The Break character trans-

mission is then initiate d b y a w ri te t o the TXREGx. The

value o f da ta written to TXRE Gx w i ll be i gn ored an d al l

‘0’s will be transmitted.

The SENDB bit is automatically reset by hardware af ter

the corresponding Stop bit is s ent . Th is al lo w s t he us er

to preloa d the trans mit FIFO with the n ext transm it byte

following the Break character (typically, the Sync

character in the LIN specification).

The TRMT bit of the TXST Ax register indic ates when the

transmit operation is active or Idle, jus t as it does during

normal transmission. See Figure 16-9 for the timing of

the Break character sequence.

16.4.4.1 Brea k and Sy nc Transmit Sequenc e

The following sequence will start a message frame

header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus

master.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to enable the

Break sequence.

3. Load the TXREGx with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREGx to load the Sync charac-

ter into the transmit FIFO buffer.

5. After the Break has been se nt, the SEND B bit is

reset by hardware and the Sync character is

then transm itte d.

When the TXREGx becomes empty, as indicated by

the TXxIF, the next data byte can be written to

TXREGx.

16.4.5 RECEIVING A BREAK CHARACTER

The Enhanced EUSART module can receive a Break

character in two ways.

The first method to detect a Break character uses the

FERR bit of the RCSTAx register and the Received

data as indicated by RCREGx. The Baud Rate

Generator is assumed to have been initialized to the

expected baud rate.

A Break charac ter has been received when;

• RCxIF bit is set

• FERR bit is set

• RCREGx = 00h

The second method uses the Auto-Wake-up feature

described in Section 16.4.3 “Auto-Wake-up on

Break”. By enabling this feature, the EUSART will

sample the next two transitions on RXx/DTx, cause an

RCxIF interrupt, and receive the next data byte

follow ed by ano the r interru pt.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of

the BAUDCONx register before placing the EUSART in

Sleep mode.

FIGURE 16-9: SEND BREAK CHARACTER SEQUENCE

Write to TXREGx Dummy Write

BRG Output

(Shift Clock)

S tart bit bit 0 bit 1 bit 11 Stop bit

Break

TXxIF b i t

(Transmit

interrupt Flag)

TXx/C Kx (pin )

TRMT bit

(Transmit Shift

Reg. Empty Flag)

SENDB

(send Break

control bit)

SENDB Sam ple d Here Auto Cleared

PIC18(L)F2X/4XK22

DS41412F-page 288  2010-2012 Microchip Technology Inc.

16.5 EUSART Synchronous Mode

Synchronous serial communications are typicall y used

in systems with a single master and one or more

slaves. The master device contains the necessary

circuit ry for b aud rate ge neration and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the

internal clock generation circuitry.

There are two signal lines in Synchronous mode: a

bidirectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and

transmit shift registers. Since the data line is

bidirectional, synchronous operation is half-duplex

only. Half-duplex refers to the fact that master and

slave devices can receive and transmit data but not

both simultaneously. The EUSART can operate as

either a master or slave device.

Start and Stop bits are not used in synchronous

transmissions.

16.5.1 SYNCHRONOUS MASTER MODE

The following bits are used to configure the EUSART

for Synchronous Master operation:

• SYNC = 1

• CSRC = 1

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TXSTAx register configures

the de vi c e f or sy n ch ronous operation. Setting t he C SRC

bit of the TXSTAx register configures the device as a

master. Clearing the SREN and CREN bits of the

RCSTAx register ensures that the device is in the

Transmit mode, otherwise the device will be configured

to receive. Setting the SPEN bit of the RCSTAx register

enables the EUSART. If the RXx/DTx or TXx/CKx pins

are shared with an analog peripheral the analog I/O

functi ons must be disabled b y clearing the correspo nding

ANSEL bi ts .

The TRIS bits corresponding to the RXx/DTx and

TXx/CKx pins should be set.

16.5.1.1 Master Clock

Synchronous data transfers use a separate clock line,

which is synchronous wi th the data. A device configured

as a master transmits the clock on the TXx/CKx line. The

TXx/CKx pin ou tput driver is automatically enabled when

the EUSART is configured for synchronous transmit or

receive operation. Serial dat a bits change on the leading

edge to ensure they are valid at the trailing edge of each

clock. One clock cycle is generated for each data bit.

Only as many clock cycles are generated as there are

da ta bits.

16.5.1.2 Clock Polarity

A clock polarity option is provided for Microwire

comp atibilit y. Clock polari ty is se lected with the CKTXP

bit of the BAUDCONx register. Setting the CKTXP bit

sets the clock Idle state as high. When the CKTXP bit

is set, the data changes on the falling edge of each

clock and is sampled on the rising edge of each cloc k.

Clearing th e CKTXP bit sets the Idle st ate as low . When

the CKTXP bit is cleared, the data changes on the

rising edge of each clock and is sampled on the falling

edge of each clock.

16.5.1.3 Synchronous Master Transmission

Data is transferred out of the device on the RXx/DTx

pin. The RXx/DTx and TXx/CKx pin output drivers are

automat ically e nabled w hen the EUSAR T is configure d

for synchronous master transmit operation.

A transmission is initiated by writing a character to the

TXREGx register. If the TSR still contains all or part of

a previous character the new character data is held in

the TXREGx until the last bit of the previous character

has been tran smitted. If this is the first ch aracter, or the

previous character has been completely flushed from

the TSR, the data in the TXREGx is immediately trans-

ferred to the TSR. The transmission of the character

commences immediately following the transfer of the

data to the TSR from the TXREGx.

Each data bit changes on the leading edge of the

master clock and remains valid until the subsequent

leading clock edge.

16.5.1.4 Data Polarity

The polarity of the transmit and receive data can be

controlled with the DTRXP bit of the BAUDCONx

high tru e transm it and re ceive d ata. Se tting the DTRXP

bit to ‘1’ will inv ert the dat a resul ting in l ow true t ransmit

and receive data.

Note: The TSR register is not mapped in data

memory, so it is not available to the user.

 2010-2012 Microchip Technology Inc. DS41412F- page 289

PIC18(L)F2X/4XK22

16.5.1.5 Synchronous Master Transmission

Setup:

1. Initialize the SPBRGHx, SPBRGx register pair

and the BRGH and BRG16 bits to achieve the

des i red baud rate (see Section 16.4 “EUSART

Baud Rate Generator (BRG)”).

2. Set the RXx/DTx and TXx/CKx TRIS controls to

‘1’.

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC. Set the

TRIS bits corresponding to the RXx/DTx and

TXx/CK x I/O pins.

4. Disable Receive mode by clearing bits SREN

and CREN.

5. Enable Transmit mode by setting the TXEN bit.

6. If 9-bit transmission is desired, set the TX9 bit.

7. If interrupts are desired, set the TXxIE, GIE/

GIEH and PEIE/GIEL interrupt enable bits.

8. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

9. Start transmission by loading data to the

TXREGx register.

FIGURE 16-10: SYNCHRONOUS TRANSMISSION

FIGURE 16-11: SYNCHRONOUS TRANSM ISSION (THROUGH TXEN)

bit 0 bit 1 bit 7

Word 1 bit 2 bit 0 bit 1 bit 7

RXx/DTx

Write to

TXREGx Reg

TXxIF bit

(Interrupt Flag)

TXEN bit ‘1’ ‘1’

Word 2

TRMT bi t

Write Word 1 Write Word 2

Note: Sync Master mode, SPBRGx = 0, continuous tran sm is sion of tw o 8-bit word s.

TXx/CKx pin

(SCKP = 0)

(SCKP = 1)

RXx/DTx pin

TXx/CKx pi n

Write to

TXREGx reg

TXxIF bit

TRMT bit

bit 0 bit 1 bit 2 bit 6 bit 7

TXEN bi t

PIC18(L)F2X/4XK22

DS41412F-page 290  2010-2012 Microchip Technology Inc.

TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

SPBRG1 EUS ART1 Baud Rate Gene rato r, Low Byte —

SPBRGH1 EUSART1 Baud Ra te G ene ra to r, H igh Byte —

SPBRG2 EUS ART2 Baud Rate Gene rato r, Low Byte —

SPBRGH2 EUSART2 Baud Ra te G ene ra to r, H igh Byte —

TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 156

TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 156

TXREG1 EUSART1 Transmit Register —

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

TXRE G2 EUSART2 Transmit Regi ster —

TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

Legend: — = unimplem ented loca t io ns, read as ‘0’ . Sh aded bits are not us ed for synch ro nous mas te r tra nsm i ssion.

Note 1: PIC18(L)F4XK22 devices.

2: PIC18(L)F2XK2 2 devices.

 2010-2012 Microchip Technology Inc. DS41412F- page 291

PIC18(L)F2X/4XK22

16.5.1.6 Synchronous Master Reception

Data is received at the RXx/DTx pin. The RXx/DTx pin

output driver must be disabled by setting the

corresponding TRIS bits when the EUSART is

configured for synchronous master receive operation.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTAx register) or the Continuous Receive Enable

bit (CREN of the RCSTAx register).

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the com pletio n of one c har acter. When CREN is se t,

clocks are continuously generated until CREN is

cleared . If CREN is cleared in the middle of a c haracter

the CK clo ck sto p s imm ed iat ely and t he p a rtia l charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cl eared at the co mpletion of the first cha racter

and CREN takes precedence.

To initiate reception, set either SREN or CREN. Data is

sampled at the RXx/DTx pin on the trailing edge of the

TXx/ CKx cl ock pin and is shifted int o the Recei v e Shift

received into the RSR, the RCxIF bit is set and the

character is automatically transferred to the two

charact er receive FIFO. Th e Least Signifi cant eight bit s

of the top character in the receive FIFO are available in

RCREGx. The RCxIF bit remains set as long as there

are un-read character s in the receive FIFO .

16.5.1.7 Slave Clock

Synchronous data transfers use a separate clock line,

which is synchronous wi th the data. A device configured

as a slave receives the clock on the TXx/CKx line. The

TXx/CKx pin output driver must be disabled by setting

the associated TRIS bit when the device is configured

for synchronous slave transmit or receive operation.

Serial data bits change on the leading edge to ensure

they are valid at the trailing edge of each clock. One data

bit is transferred for each clock cycle. Only as many

clock cycles should b e received as there are data bits.

16.5.1.8 Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be genera ted if a th ird charac ter , in it s

entirety, is received before RCREGx is read to access

the FIFO. When this happens the OERR bit of the

RCSTA x regis ter i s set. Previ ous data in t he FI FO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

will be recei ved until the erro r is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCREGx.

If the overrun occurred when the CREN bit is set then

the error condition is cleared by either clearing the

CREN bit of the RCSTAx register or by clearing the

SPEN bit which resets the EUSART.

16.5.1.9 Receiving 9-bit Characters

The EUSAR T support s 9-bit chara cter receptio n. When

the RX9 bit of the RCSTAx register is set the EUSART

will shift 9-bits into the RSR for each character

received. The RX9D bit of the RCSTAx register is the

ninth, and Most Significant, data bit of the top unread

charact er i n t he rec eiv e FIFO . Whe n r ead ing 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREGx.

16.5.1.10 Synchronous Master Reception

Setup:

1. Initialize the SPBRGHx, SPBRGx register pair

for the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

2. Set the RXx/DTx and TXx/CKx TRIS controls to

‘1’.

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC. Disable

RXx/DTx and TXx/CKx output drivers by setting

the corresponding TRIS bits.

4. Ensure bits CREN and SREN are clear.

5. If using interrupts, set the GIE/GIEH and PEIE/

GIEL bits of the INTCON register and set

RCxIE.

6. If 9-bit reception is desired, set bit RX9.

7. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

8. Interrupt flag bit RCxIF will be set when recep-

tion of a character is complete. An interrupt will

be generated if the enable bit RCxIE was set.

9. Read the RCSTAx regist er to ge t the nint h bit ( if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCREGx register.

11. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTAx

the EUSART.

PIC18(L)F2X/4XK22

DS41412F-page 292  2010-2012 Microchip Technology Inc.

FIGURE 16-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

CREN bit

RXx/DTx

Write to

bit SREN

SREN bit

RCxIF bit

(Interrupt)

Read

RCREGx

‘0’

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

‘0’

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

TXx/CKx pin

(SCKP = 0)

(SCKP = 1)

TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

RCREG1 EUSART1 Receive Register —

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

RCREG2 EUSART2 Receive Register —

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

SPBRG1 EUSART1 Baud Rate Generator, Low Byte —

SPBRGH1 EUSART1 Baud Rate Generator, High Byte —

SPBRG2 EUSART2 Baud Rate Generator, Low Byte —

SPBRGH2 EUSART2 Baud Rate Generator, High Byte —

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.

 2010-2012 Microchip Technology Inc. DS41412F- page 293

PIC18(L)F2X/4XK22

16.5.2 SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART

for Synchronous slave operation:

• SYNC = 1

• CSRC = 0

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bi t of the TX STAx r egister conf igures

the device for synchronous operation. Clearing the

CSRC bit of the TXST Ax register configures the device as

a slave. Clearing the SREN and CREN bits of the

RCSTAx register ensures that the device is in the

T ransmit mode, otherwise the device will be configured to

receive. Setting the SPEN bit of the RCSTAx register

enables the EUSART. If the RXx/DTx or TXx/CKx pins

are shared with an analog peripheral the analog I/O

functions must be disabled by clearing the corresponding

ANSE L bit s.

RXx/DTx and TXx/CKx pin output drivers must be

disabled by setting the corresponding TRIS bits.

16.5.2.1 EUSART Synchronous Slave

Transmit

The operation of the Synchronous Master and Slave

modes are identical (see Section 16.5.1.3

“Synchronous Master Transmission”), except in the

case of the Sleep mode.

If two words are written to the TXREGx and then the

SLEEP instruction is executed, the following will occur:

1. The first character will immediately transfer to

the TSR register and transmit.

2. The second word will remain in TXREGx

3. The TXxIF bit will not be set.

4. After the first character has been shifted out of

TSR, the TXREGx register will transfer the

second character to the TSR and the TXxIF bit

will now be set.

5. If the PEIE/GIEL and TXxIE bits are set, the

interrupt will wake the device from Sleep and

execute the next instruction. If the GIE/GIEH bit

is also set, the program will call the Interrupt

Service Routi ne.

16.5.2.2 Synchronous Slave Transmission

Setup:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Set the RXx/DTx and TXx/CKx TRIS controls to

‘1’.

3. Clear the CREN and SREN bits.

4. If using interrupts, ensure that the GIE/GIEH

and PEIE/GIEL bits of the INTCON register are

set and set the TXxIE bit.

5. If 9-bit transmission is desired, set the TX9 bit.

6. Enable transmission by setting the TXEN bit.

7. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

8. Start transmission by writing the Least

Significant eight bits to the TXREGx register.

PIC18(L)F2X/4XK22

DS41412F-page 294  2010-2012 Microchip Technology Inc.

TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0 Register

on Page

BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

SPBRG1 EUSART1 Baud Rate Generator, Low Byte —

SPBRGH1 EUSART1 Baud Rate Generator, High Byte —

SPBRG2 EUSART2 Baud Rate Generator, Low Byte —

SPBRGH2 EUSART2 Baud Rate Generator, High Byte —

TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 156

TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 156

TXREG1 EUSART1 Transmit Register —

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

TXREG2 EUSART2 Transmit Register —

TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

Legend: — = unimplem ented loca t io ns, read as ‘0’ . Sh aded bits are not us ed for synch ro nous slave tr an smission.

Note 1: PIC18(L)F4 XK2 2 devices.

2: PIC18(L)F2XK2 2 devices.

 2010-2012 Microchip Technology Inc. DS41412F- page 295

PIC18(L)F2X/4XK22

16.5.2.3 EUSART Synchronous Slave

Reception

The operation of the Synchronous Master and Slave

modes is identical (Section 16.5.1.6 “Synchronous

Master Reception”), with the following exceptions:

• Sleep

• CREN bit is always set, therefore the receiver is

nev er Idle

• SR EN bit, which is a “don't care” in Slave mode

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is rec eived, th e RSR regist er will tran sfer the da ta

to the RCREGx register. If the RCxIE enable bit is set,

the inter rupt gen erated wi ll wake the device f rom Sleep

and execute the next instruction. If the GIE/GIEH bit is

also set, the program will branch to the interrupt vector.

16.5.2.4 Synchronous Slave Reception

Setup:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Set the RXx/DTx and TXx/CKx TRIS controls to

‘1’.

3. If using interrupts, ensure that the GIE/GIEH

and PEIE/GIEL bits of the INTCON register are

set and set the RCxIE bit.

4. If 9-bit reception is desired, set the RX9 bit.

5. Set the CREN bit to enable reception.

6. The RCxIF bit will be set when reception is

complete. An interrupt will be generated if the

RCxIE bit was set.

7. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTAx

8. Retrieve t he eight L eas t Sign ifican t bit s from the

receive FIFO by reading the RCREGx register.

9. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTAx

the EUSART.

TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 Register

on Page

BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 —WUE ABDEN 279

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130

PIE1 —ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126

PIR1 —ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55

RCREG1 EUSART1 Receive Register —

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

RCREG2 EUSART2 Receive Register —

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278

SPBRG1 EUSART1 Baud R ate Generator, Low Byt e —

SPBRGH1 EUS ART1 Ba ud Rate Genera tor, High Byte —

SPBRG2 EUSART2 Baud R ate Generator, Low Byt e —

SPBRGH2 EUS ART2 Ba ud Rate Genera tor, High Byte —

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277

Legend: — = unimplem ented loca t io ns, read as ‘0’ . Sh aded bits are not us ed for synch ro nous slave receptio n.

PIC18(L)F2X/4XK22

DS41412F-page 296  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 297

PIC18(L)F2X/4XK22

17.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates a 10-bit binary result via successive

approximation and stores the conversion result into the

ADC result registers (ADRESL and ADRESH).

The ADC voltage reference is software selectable to

either VDD or a v olt age applied to the external re ference

pins.

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be us ed to wak e-up the

device from Sleep.

Figure 17-1 shows the block diagram of the AD C.

FIGURE 17-1: ADC BLOCK DIAGRAM

Note: Additional ADC channels AN5-AN7 and AN20-AN27 are only available on PIC18(L)F4XK22 devices.

11111

11110

11101

11100

11011

FVR BUF2

DAC

CTMU

AN28(1)

AN27(1)

00101

00100

AN5(1)

AN4

00011

00010

AN3

AN2

00001

00000

AN1

AN0

5CHS<4:0>

10-Bit ADC

ADCMD

ADON

GO/DONE

0 = Left Justify

1 = Right Justify

ADFM

ADRESH ADRESL

AVDD

FVR BUF2

Reserved

VREF+/AN3

2PVCFG<1:0>

AVSS

Reserved

VREF-/AN2

2NVCFG<1:0>

PIC18(L)F2X/4XK22

DS41412F-page 298  2010-2012 Microchip Technology Inc.

17.1 ADC Configuration

When configuring and using the ADC the following

functio ns must be considered:

• Port config uration

• Channel selection

• ADC voltage reference selection

• ADC co nversion cl ock source

• Interrupt control

• Results formatting

17.1.1 PORT CONFIGURATION

The ANSELx and TRISx registers configure the A/D

port pins. Any port pin needed as an analog input

should have its corresponding ANSx bit set to disable

the digital input buffer and TRISx bit set to disable the

digital output driver. If the TRISx bit is cleared, the

digital output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of the

ANSx bits and the TRIS bits.

17.1.2 CHANNEL SELECTION

The CHS bits of the ADCON0 r egister det ermine whic h

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 17.2

“ADC Operation” for more information.

17.1.3 ADC VOLTAGE REFERENCE

The PVCFG<1:0> and NVCFG<1:0> bits of the

ADCON1 register provide independent control of the

positive and negative voltage references.

The positive voltage reference can be:

•V

• the fixed voltage reference (FVR BUF2)

• an exter nal voltage sour ce (VREF+)

The negative voltage reference can be:

•V

• an external voltage source (VREF-)

17.1.4 SELECTING AND CONFIGURING

ACQUISITIO N TIME

The ADCON2 register allows the user to select an

acquisition time that occurs each time the GO/DONE

bit is set.

Acquisition time is set with the ACQT<2:0> bits of the

ADCON2 register. Acquisition delays cover a range of

2 to 20 TAD. When the GO/DONE bit is set, the A/D

module continues to sample the input for the selected

acquisition time, then automatically begins a

conversion. Since the acquisition time is programmed,

there is n o need to wait for an acqui sition tim e between

selecting a channel and setting the GO/DONE bit.

Manual acquisition is selected when

ACQT<2:0> = 000. When the GO/DONE bit is set,

sampli ng is stoppe d and a conv ersion begins. The user

is responsible for ensuring the required acquisition time

has passed between selecting the desired input

channel and setting the GO/DONE bit. This option is

also the defaul t Res et st ate o f the AC QT<2:0> b it s and

is compatible with devices that do not offer

progra mmable acquisition times .

In either case, when the conversion is completed, the

GO/DONE bit is cleared, the ADIF flag is set and the

A/D begins sampling the currently selected channel

again. When an acquisition time is programmed, there

is n o indic ation of wh en th e acqu isit ion ti me en ds and

the conversion begins.

Note 1: When re adi ng the PO RT register, all pins

with their corresponding ANSx bit set

read as cleared (a low level). However,

analog conversion of pins configured as

digital inputs (ANSx bit cleared and

TRISx bit set) will be accurately

converted.

2: Analog levels on any pin with the corre-

sponding ANSx bit cleared may cause

the digi tal input buffer to consume cur rent

out of the device’s specification limits.

3: The PBADEN bit in Configuration

reset as analog or digital pins by

controlling how the bits in ANSELB are

reset.

 2010-2012 Microchip Technology Inc. DS41412F- page 299

PIC18(L)F2X/4XK22

17.1.5 CONVERSION CLOCK

The source of the conversion clock is software

selectable via the ADCS bits of the ADCON2 register.

There are seven possible clock options:

•F

OSC/2

•FOSC/4

•FOSC/8

•F

OSC/16

•FOSC/32

•FOSC/64

•F

RC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11 TAD periods

as sh own i n Figure 17-3.

For correct conversion, the appropriate TAD specification

must be met. See A/D conversion requirements in

Table 27-23 for more information. Table 17-1 gives

examples of appropriate ADC clock selections.

17.1.6 INTERRUPTS

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

Conversion. The ADC interrupt enable is the ADIE bit

in the PIE1 register and the interr upt priority is the ADIP

bit in the IPR1 register. The ADC interrupt flag is the

ADIF bit in the PIR1 register. The ADIF bit must be

cleared by software.

This interrupt can be generated while the device is

operatin g or while in Slee p. If the device is in Slee p, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP

instruction is always executed. If the user is attempting

to wake-up from Sleep and resume in-line code

execution, the global interrupt must be disabled. If the

global interrupt is enabled, execution will switch to the

Interrupt Service Routine.

Note: Unless using th e FRC, any change s in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

Note: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

TABLE 17-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

ADC Clock Period (TAD) Device Frequency (FOSC)

ADC Clock Source ADCS<2:0> 64 MHz 16 MHz 4 MHz 1 MHz

FOSC/2 000 31.25 ns(2) 125 ns(2) 500 ns (2) 2.0 s

FOSC/4 100 62.5 ns(2) 250 ns(2) 1.0 s4.0 s(3)

FOSC/8 001 400 ns(2) 500 ns(2) 2.0 s8.0 s(3)

FOSC/16 101 250 ns(2) 1.0 s4.0 s(3) 16.0 s(3)

FOSC/32 010 500 ns(2) 2.0 s8.0 s(3) 32.0 s(3)

FOSC/64 110 1.0 s4.0 s(3) 16.0 s(3) 64.0 s(3)

FRC x11 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4) 1-4 s(1,4)

Legend: Shaded cells are outside of reco mmended range.

Note 1: The FRC source has a typical TAD time of 1.7 s.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is grea ter than 1 MHz, the FRC clock source is only recommended if the

conversion will be perf ormed during S leep.

PIC18(L)F2X/4XK22

DS41412F-page 300  2010-2012 Microchip Technology Inc.

17.1.7 RES ULT FORM ATTING

The 10-bit A/D conversion res ult can be supplied in two

formats, left justified or right justified. The ADFM bit of

the ADCON2 register controls the output format.

Figure 17-2 shows the two output formats.

FIGURE 17-2: 10-BIT A/D CONVERSION RESULT FORMAT

ADRESH ADRESL

(ADFM = 0)MSB LSB

bit 7 bit 0 bit 7 bit 0

10-bit A/D Result Unimplemented: Read as ‘0’

(ADFM = 1)MSB LSB

bit 7 bit 0 bit 7 bit 0

Unimplemented: Read as ‘0’ 10-bit A/D Result

 2010-2012 Microchip Technology Inc. DS41412F- page 301

PIC18(L)F2X/4XK22

17.2 ADC Operation

17.2.1 STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 regis ter to a ‘1’ wil l, depend-

ing on the ACQT bits of the ADCON2 register, either

immediately start the Analog-to-Digital conversion or

start an acquisition delay followed by the Analog-to-

Digital conversion.

Figure 17-3 shows the operation of the A/D converter

after the GO bit has been set and the ACQT<2:0> bits

are cleared. A conversion is started after the following

instruction to allow entry into SLEEP mode before the

conversion begins.

Figure 17-4 shows the operation of the A/D converter

after the GO bit has been set and the ACQT<2:0> bits

are set to ‘010’ which se lec ts a 4 TAD acquisition time

before the conversion starts.

FIGURE 17-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 17-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

Note: The G O/DONE bit s hould not b e set in the

same instruction that turns on the ADC.

Refer to Section 17.2.10 “A/D Conver-

sion Procedure”.

TAD1TAD2TAD3TAD4 TAD5TAD6 TAD7TAD8 TAD11

Set GO bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10

TCY - TAD

ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capa citor is connected to analog input.

Conve r si on starts

b9 b6 b5 b4 b3 b2 b1

b8 b7

On the follow i ng cy cl e:

2 TAD

Discharge

123 4 5 67811

Set GO bit

(Holding capacitor is disconnected from analog input)

910

Conversion starts

123 4

(Holding capacitor continues

acquiring input)

TACQT Cycles TAD Cycles

Automatic

Acquisition

Time

b0b9 b6 b5 b4 b3 b2 b1

b8 b7

ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

On the following cycle:

2 TAD

Discharge

PIC18(L)F2X/4XK22

DS41412F-page 302  2010-2012 Microchip Technology Inc.

17.2.2 COMPLETION OF A CONVERSION

When the conv ersion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF flag bit

• Update the ADRESH:A DRESL regis ters with new

conversion result

17.2.3 DISCHARGE

The discharge phase is used to initialize the value of

the cap acitor array. The array is dis charged af ter eve ry

sample. This feature helps to optimize the unity-gain

amplifier, as the circuit always needs to charge the

capacitor array , rather than charge/discharge based on

previous meas ure va lues.

17.2.4 TERMINATING A CONVERSION

If a co nver sion must b e term ina ted be fore comp leti on,

the GO/DONE bit can be cleared by software. The

ADRESH:ADRESL registers will not be updated with

the partially complete Analog-to-Digital conversion

sample. Instead, the ADRESH:ADRESL register pair

will retain the value of the previous conversion.

17.2.5 DELAY BETWEEN CONVERSIONS

After the A/D conversion is completed or aborted, a

AD wait is required before the next acquisition can

be started. After this wait, the currently selected

channel is reconnected to the charge holding capacitor

comm encing the next acquisition.

17.2.6 ADC OPERATION IN POWER-

MANAGED MODES

The selection of the automatic acquisition time and A/D

conversion clock is determined in part by the clock

source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in

a power-managed mode, the ACQT<2:0> and

ADCS<2:0> bits in ADCON2 should be updated in

accordance with the clock source to be used in that

mode. After entering the mode, an A/D acquisition or

conversion may be started. Once started, the device

should continue to be clocked by the same clock

sour ce unt il the con ve r si on has been co mpl ete d.

If desired, the device may be placed into the

corr espondi ng Idle m ode dur ing the convers ion. I f the

device clock frequ ency is les s than 1 MHz, the A/D F RC

clock source should be selected.

17.2.7 ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC wa its on e addition al instru ction bef ore sta rting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present

conversion to be aborted and the ADC module is

turned off, although the ADON bit remains set.

17.2.8 SPECIAL EVENT TRIGGER

Two S pecial Event Triggers are available to start an A/D

conversion: CTMU and CCP5. The Special Event

Trigger source is selected using the TRIGSEL bit in

ADCON1.

When TRIGSEL = 0, the CCP5 module is selected as

the S pecial Event T rigger source. To enable the S pecial

Event Trigger in the CCP module, set CCP5M<3:0> =

1011, in the CCP5CON register.

When TRIGSEL = 1, the CTMU module is selected.

The CTMU module requires that the CTTRIG bit in

CTMUCONH is set to enable the S pecial Event T rigger .

In addition to TRIGSEL bit, the following steps are

required to start an A/D conversion:

• The A/D module must be enabled (ADON = 1)

• The appropriate analog input channel selected

• The minimum acquisition period set one of these

ways:

- Timing provided by the user

- Selection made of an appropriate TACQ time

With these conditions met, the trigger sets the GO/DONE

bit and the A/D acquisition starts.

If the A/D module is not enabled (ADON = 0), the

module ignores the Special Event Trigger.

17.2.9 PERIPHERAL MODULE DISABLE

When a peripheral module is not used or inactive, the

module can be disabled by setting the Module Disable

bit in the PMD registers. This will reduce power

consum ption to an ab solute mini mum. Setting the PMD

bits holds the module in Reset and disconnects the

module’s clock source. The Module Disable bit for the

ADC module is ADCMD in the PMD2 Register. See

Section 3.0 “Power-Managed Modes” for more

information.

Note: A devi ce Rese t forces all registers to th eir

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

 2010-2012 Microchip Technology Inc. DS41412F- page 303

PIC18(L)F2X/4XK22

17.2.10 A/D CONVERSION PROCEDURE

This is an example procedure for using the ADC to

perform an Analog-to-Digit al conve rsion:

1. Configure Port :

• Disable pin output driver (See TRIS register)

• Configure pin as analog

2. Configure the ADC module :

• Select ADC co nversion clock

• Configure voltage reference

• Select ADC input channel

• Select result format

• Select ac quisition delay

• Turn on ADC module

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt(1)

4. Wait the required acquisition time(2).

5. Start conversion by setting the GO/DONE bit.

6. Wait fo r ADC co nvers i on to com ple te b y o ne o f

the following:

• Polling the GO/DONE bit

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result

8. Clear the ADC in terrupt flag (re quired if in terrupt

is enabled).

EXAMPLE 17-1: A/D CON VE RSI ON

Note 1: The g lobal in terrupt ca n be dis abled if the

user is at tempti ng to wake -up from Sle ep

and resume in-line code ex ecution.

2: Software delay required if ACQT bits are

set to z ero de lay. See Section 17.4 “A/D

Acquisition Re quire men ts”.

;This code block configures the ADC

;for polling, Vdd and Vss as reference, Frc

clock and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

MOVLW B’10101111’ ;right justify, Frc,

MOVWF ADCON2 ; & 12 TAD ACQ time

MOVLW B’00000000’ ;ADC ref = Vdd,Vss

MOVWF ADCON1 ;

BSF TRISA,0 ;Set RA0 to input

BSF ANSEL,0 ;Set RA0 to analog

MOVLW B’00000001’ ;AN0, ADC on

MOVWF ADCON0 ;

BSF ADCON0,GO ;Start conversion

ADCPoll:

BTFSC ADCON0,GO ;Is conversion done?

BRA ADCPoll ;No, test again

; Result is complete - store 2 MSbits in

; RESULTHI and 8 LSbits in RESULTLO

MOVFF ADRESH,RESULTHI

MOVFF ADRESL,RESULTLO

PIC18(L)F2X/4XK22

DS41412F-page 304  2010-2012 Microchip Technology Inc.

17.3 Register Definitions: ADC Control

Note: Analog pin control is determined by the

ANSELx registe r s (see Register 10-2)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— CHS<4:0> GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ‘1’ = Bit is set ‘0’ = B it is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-2 CHS<4:0>: Ana log Channel Sele c t bits

00000 = AN0

00001 = AN1

00010 = AN2

00011 = AN3

00100 = AN4

00101 = AN5(1)

00110 = AN6(1)

00111 = AN7(1)

01000 = AN8

01001 = AN9

01010 = AN10

01011 = AN11

01100 = AN12

01101 = AN13

01110 = AN14

01111 = AN15

10000 = AN16

10001 = AN17

10010 = AN18

10011 = AN19

10100 = AN20(1)

10101 = AN21(1)

10110 = AN22(1)

10111 = AN23(1)

11000 = AN24(1)

11001 = AN25(1)

11010 = AN26(1)

11011 = AN27(1)

11100 = Reserved

11101 = CTMU

11110 = DAC

11111 = FVR BUF2 (1.024V/2.048V/2.096V Volt Fixed Volt age Reference)(2)

bit 1 GO/DONE: A/D Conversion Status bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0 = A/D conversion completed/not in progress

bit 0 ADON: ADC Enable bit

1 = ADC is enabled

0 = ADC is disabled and consumes no operating current

Note 1: Available on PIC18(L)F4XK22 devices only.

2: Allow greater than 15 s acquisition time when measuring the Fixed Voltage Reference.

 2010-2012 Microchip Technology Inc. DS41412F- page 305

PIC18(L)F2X/4XK22

R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

TRIGSEL — — — PVCFG<1:0> NVCFG<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TRIGSEL: Special Trigger Select bit

1 = Selects the special trigger from CTMU

0 = Selects the special trigger from CCP5

bit 6-4 Unimplemented: Read as ‘0’

bit 3-2 PVCFG<1:0>: Positive Voltage Refere nce Configuration bits

00 = A/D VREF+ connected to internal signal, AVDD

01 = A/D VREF+ connected to external pin, VREF+

10 = A/D VREF+ connected to internal signal, FVR BUF2

11 = Reserved (by default, A/D VREF+ connected to internal signal, AVDD)

bit 1-0 NVCFG<1:0>: Negative Voltage Reference Configuration bits

00 = A/D VREF- connected to internal signal, AVSS

01 = A/D VREF- connected to external pin, VREF-

10 = Reserved (by default, A/D VREF- connected to internal signal, AVSS)

11 = Reserved (by default, A/D VREF- connected to internal signal, AVSS)

PIC18(L)F2X/4XK22

DS41412F-page 306  2010-2012 Microchip Technology Inc.

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM — ACQT<2:0> ADCS<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Conversion Result Format Select bit

1 = Right justif ied

0 = Left justi fied

bit 6 Unimplemented: Read as ‘0’

bit 5-3 ACQT<2:0>: A/D Acquisition time select bits. Acquisition time is the duration that the A/D charge

holding capacitor remains connected to A/D channel from the instant the GO/DONE bit is set until

conversions begins.

000 = 0(1)

001 = 2 TAD

010 = 4 TAD

011 = 6 TAD

100 = 8 TAD

101 = 12 TAD

110 = 16 TAD

111 = 20 TAD

bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits

000 = FOSC/2

001 = FOSC/8

010 = FOSC/32

011 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal)

100 = FOSC/4

101 = FOSC/16

110 = FOSC/64

111 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal)

Note 1: When the A/D clock source is selected as FRC then the start of conversion is delayed by one instruction

cycle after t he GO/DONE bit is set to allow the SLEEP inst ruction t o be executed.

 2010-2012 Microchip Technology Inc. DS41412F- page 307

PIC18(L)F2X/4XK22

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ADRES<9:2>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ‘1’ = Bit is set ‘0’ = B it is cleared x = Bit is unknown

bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ADRES<1:0> — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ‘1’ = Bit is set ‘0’ = B it is cleared x = Bit is unknown

bit 7-6 ADRES<1:0>: ADC Result Register bits

Lower two bits of 10-bit conversion result

bit 5-0 Reserved: Do not use.

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — — — — — ADRES<9:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ‘1’ = Bit is set ‘0’ = B it is cleared x = Bit is unknown

bit 7-2 Reserved: Do not use.

bit 1-0 ADRES<9:8>: ADC Result Register bits

Upper two bits of 10-bit conversion result

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ADRES<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ‘1’ = Bit is set ‘0’ = B it is cleared x = Bit is unknown

bit 7-0 ADRES<7:0>: ADC Result Register bits

Lower eight bits of 10-bit conversion result

PIC18(L)F2X/4XK22

DS41412F-page 308  2010-2012 Microchip Technology Inc.

17.4 A/D Acquisition Requirements

For the A DC t o meet its specif ied accuracy, the char ge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 17-5. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the

capacitor CHOLD. The sampling switch (RSS) impedance

varies over the device voltage (VDD), see Figure 17-5.

The maximum recommended impedance for analog

sources is 10 k. As the source impedance is

decreased, the acquisition time may be decreased.

After the analog input channel is selected (or changed),

an A/D acquisition must be done before the conversion

can be started. To calculate the minimum acquisition

time, Equation 17-1 may be used. This equation

assumes that 1/2 LSb error is used (1024 steps for the

ADC). The 1/2 LSb erro r is the maximum er ror allow ed

for the ADC to meet its specified resolution.

EQUATION 17-1: ACQUISITION TIME EXAMPLE

TACQ Amplifier Settling Time Hold Capacitor Chargin g T ime Temperature Coefficient++=

TAMP TCTCOFF++=

5µs TCTemperature - 25°C0.05µs/°C++=

TCCHOLD RIC RSS RS++ ln(1/2047)–=

13.5pF 1k



700



10k



++– ln(0.000 4885)=

1.20

=µs

TACQ 5µs 1.20µs 50°C- 25°C0.05



s/°C++=

7.45µs=

VAPPLIED 1e

Tc–

---------

–







VAPPLIED 11

2047

------------

–





VAPPLIED 11

2047

------------

–





VCHOLD=

VAPPLIED 1e

TC–

----------

–







VCHOLD=

;[1] V CHOLD charged to within 1/2 lsb

;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]

The value for TC can be approximated with the following eq uations:

Solving for TC:

Therefore:

Temperature 50°C and external impedance of 10k



3.0V VDD=

Assumptions:

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

 2010-2012 Microchip Technology Inc. DS41412F- page 309

PIC18(L)F2X/4XK22

FIGURE 17-5: ANALOG INPUT MODEL

FIGURE 17-6: ADC TRANSFER FUNCTION

CPIN

Rs ANx

5 pF

VDD

I LEAKAGE(1)

RIC  1k

Sampling

Switch

SS Rss

CHOLD = 13.5 pF

VSS/VREF-

2.5V

Rss (k)

2.0V

1.5V

.1 1 10

VDD

Legend: CPIN

I LEAKAGE

RIC

CHOLD

= Input Capacitanc e

= Leakage current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance

various junctions

Discharge

Switch

3.0V

3.5V

100

Note 1: See Section 27.0 “Electrical Characteristics”.

3FFh

3FEh

ADC Output Code

3FDh

3FCh

004h

003h

002h

001h

000h

Full-Scale

3FBh

1/2 LSB ideal

VSS/VREF-Zero-Scale

Transition VDD/VREF+

Transition

1/2 LSB ideal

Full-Scale Range

Analog Input Voltage

PIC18(L)F2X/4XK22

DS41412F-page 310  2010-2012 Microchip Technology Inc.

TABLE 17-3: CONFIGURATION REGISTERS ASSOCIATED WITH THE ADC MODULE

TABLE 17-2: REGISTERS ASSOCIATED WITH A/D OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ADCON0 — CHS<4:0> GO/DONE ADON 304

ADCON1 TRIGSEL — — — PVCFG<1:0> NVCFG<1:0> 305

ADCON2 ADFM — ACQT<2:0> ADCS<2:0> 306

ADRESH A/D Result, High Byte 307

ADRESL A/D Result, Low Byte 307

ANSELA ——ANSA5— ANSA3 ANSA2 ANSA1 ANSA0 154

ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 155

ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 155

ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 155

ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 156

CCP5CON — — DC5B<1:0> CCP5M<3:0> 205

CTMUCONH CTMUEN —CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 333

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR1 —ADIPRC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128

IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130

IPR4 — — — — — CCP5IP CCP4IP CCP3IP 131

PIE1 —ADIERC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124

PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126

PIE4 — — — — — CCP5IE CCP4IE CCP3IE 127

PIR1 —ADIFRC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

PIR4 — — — — —CCP5IFCCP4IF CCP3IF 122

PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 56

PMD2 — — — —CTMUMDCMP2MD CMP1MD ADCMD 57

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 156

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 156

TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 156

TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 156

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by this module.

Note 1: Available on PIC1 8(L)F4XK22 devices.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

CONFIG3H MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by the ADC module.

 2010-2012 Microchip Technology Inc. DS41412F- page 311

PIC18(L)F2X/4XK22

18.0 COMPARATOR MODULE

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

The comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of the program execution. The analog

comparator module includes the following features:

• Independent comparator control

• Programmable input selection

• Comparator ou tput is avail able internall y/externally

• Programmable output polarity

• Interrupt-on-change

• Wake-up from Sleep

• Programmable Speed/Power optimization

•PWM shutdown

• Programmable and fixed voltage reference

• Selectable Hysteresis

18.1 Comparator Overview

A singl e com pa rato r is shown i n Figure 18-1 along with

the relationship between the analog input levels and

the digital output. When the analog voltage at VIN+ is

less than the analog voltage at VIN-, the output of the

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the outp ut of the comp arat or is a digit al high le vel.

FIGURE 18-1: SINGLE COMP ARATOR

–

VIN+

VIN-Output

Output

VIN+

VIN-

Note: The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

PIC18(L)F2X/4XK22

DS41412F-page 312  2010-2012 Microchip Technology Inc.

FIGURE 18-2: COMPARATOR C1/C2 SIMPLIFIED BLOCK DIAGRAM

Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.

2: Q1 and Q3 are phases of the four-phase system clock (FOSC).

3: Q1 is held high during Sleep mode.

4: Synchronized comparator output should not be used to gate Timer1 in conjunction with synchronized T1CKI.

CxPOL to PWM Logic

CxON

(1)

CxCH<1:0>

CxR

CM2CON1 (MCxOUT)

To Interrupts

CxV

C12IN0-

C12IN1-

C12IN2-

C12IN3-

CxIN+

(2),(3)

Read or Write

Reset

DAC Output

CXRSEL

FVR BUF 1

CxSP

CXVREF CxOE

xOUT

Timer1 Clock

sync_C

xOUT

To CMxCON0 (CxOUT)

(CxIF)

of CMxCON0

(2)

CxSYNC

async_CXOUT

TRIS bit

to S R La t ch

to Tx G M U X

(4)

 2010-2012 Microchip Technology Inc. DS41412F- page 313

PIC18(L)F2X/4XK22

18.2 Comparator Control

Each comparator has a separate control and

Configuration register: CM1CON0 for Comparator C1

and CM2CON0 for Comparator C2. In addition,

Comparator C2 has a second control register,

CM2CON1, for controlling the interaction with Timer1 and

simultaneous reading of both comparator outputs.

The CM1CON0 and CM2CON0 registers (see

following:

• Enable

• Input selection

• Reference selection

•Output selection

• Output pol arit y

• Speed selection

18.2.1 COMPARATOR ENABLE

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator resulting in minimum current

consumption.

18.2.2 COMPARATOR INPUT SELECTION

The CxCH<1:0> bits of the CMxCON0 register direct

one of four analog input pins to the comparator

inverting input.

18.2.3 COMPARATOR REFERENCE

SELECTION

Setting the CxR bit of the CMxCON0 register directs an

internal voltage reference or an analog input pin to the

non-inverting input of the comparator. See

Section 21.0 “Fixed Voltage Reference (FVR)” for

more information on the Internal Voltage Reference

module.

18.2.4 COMPARATOR OUTPUT

SELECTION

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CM2CON1 register. In order

to make the output available for an external connection,

the following conditions must be true:

• CxOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

• CxON bit of the CMxCON0 register must be set

18.2.5 COMPARATOR OUTPUT POLARITY

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit result s in a non-inverted outpu t.

Table 18-1 shows the output state versus input

conditions, including polarity control.

18.2.6 COMPARATOR SPEED SELECTION

The trade-off between speed or power can be

optimized during program execution with the CxSP

control bit. The default state for this bit is ‘1’ which

selects the normal speed mode. Device power

consumption can be optimized at the cost of slower

comp arator p rop agatio n delay by cl earing the C xSP bit

to ‘0’.

18.3 Comparator Response Time

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new refe rence volta ge. This period is refer red to as

the response time. The response time of the

comparator differs from the settling time of the voltage

reference. Therefore, both of these times must be

considered when determining the total response time

to a comparator input change. See the Comparator and

Voltage Reference Specifications in Section 27.0

“Electri cal Characte ristics” for more details.

Note: To use CxIN + and C12IN x- pins as a nalog

inputs, the appropriate bits must be set in

the ANSEL register and the

corr esp on di n g TR IS b i ts mus t al so b e se t

to disable the output drivers.

Note 1: The CxOE bit overrides the PORT data

latch. Se tting the Cx ON has no impa ct on

the port overrid e.

2: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

TABLE 18-1: COMPARATOR OUTPUT

STATE VS. INPUT

CONDITIONS

Input Condition CxPOL CxOUT

CxVIN- > CxVIN+00

CxVIN- < CxVIN+01

CxVIN- > CxVIN+11

CxVIN- < CxVIN+10

PIC18(L)F2X/4XK22

DS41412F-page 314  2010-2012 Microchip Technology Inc.

18.4 Comparator Interrupt Operation

The comparator interrupt flag will be set whenever

there is a chang e in the o utput val ue of the compa rator.

Changes are recognized by means of a mismatch

circuit which consists of two latches and an exclusive-

or gate (see Figure 18-2). The first l atch is upda ted with

the comparator output value, when the CMxCON0

third cycle of the system clock, also known as Q3. This

first latch retains the comparator value until another

read or write of the CMxCON0 register occurs or a

Reset takes place. The second latch is updated with

the comparator ou tput value on every first cycle of the

system clock, also known as Q1. When the output

value of the comparator changes, the second latch is

updated and the output values of both latches no

longer match one another, resulting in a mismatch

condition. The latch outputs are fed directly into the

input s of an excl usive-or g ate. This mismatc h conditio n

is detected by the exclusive-or gate and sent to the

interrupt circuitry. The mismatch condition will persist

until the first latch value is updated by performing a

read of the CMxCON0 register or the comparator

output returns to the previous state.

When the mismatch condition occurs, the comparator

interr upt flag is set. The int errupt flag is trigg ered by the

edge of the chang ing val ue comi ng from the exclus ive-

or gate. This means that the interrupt flag can be reset

onc e it i s trig ger ed w ith out th e addi ti onal st ep o f r ead-

ing or writing the CMxCON0 register to clear the mis-

match latches. When the mismatch registers are

cleared, an interrupt will oc cur upon the comparator ’s

return to the previous state, otherwise no interrupt will

be generated.

Software will need to maintain information about the

status of the comparator output, as read from the

CMxCON0 register , or CM2CON1 register, to determine

the actual change that has occurred. See Figures 18-3

and 18-4.

The CxIF bit of the PIR2 register is the comparator

interrupt flag. This bit must be reset by software by

clearing it to ‘0’. Since i t i s also po ssib le t o writ e a ‘1’ to

this register, an interrupt can be generated.

In mid-range Compatibility mode the CxIE bit of the

PIE2 register an d the PEIE/GIEL a nd GIE/GIEH b it s of

the I NTC ON register must al l b e s et to enable compar-

ator inte rrupts. If any of thes e bits a re cleared, the inter-

rupt is not enabled, although the CxIF bit of the PIR2

18.4.1 PRESETTING THE MISMATCH

LATCHES

The comparator mismatch latches can be preset to the

desired state before the comparators are enabled.

When the comparator is off the CxPOL bit controls the

CxOUT level. Set the C xPOL bit to the desi red CxOU T

non-inte rrupt lev el w hile th e CxON bi t is clea red. The n,

configu re the de sired CxPO L leve l in the same ins truc-

tion that t he CxON bit is se t. Since all register writes are

performed as a read-modify-write, the mismatch

latches will be cleared during the instruction read

phase and the actual configuration of the CxON and

CxPOL bits will be occur in the final write phase.

FIGURE 18-3: COMPARATOR

INTERRUPT TIMING W/O

CMxCON0 READ

FIGURE 18-4: COMPARATOR

INTERRUPT TIMING WITH

CMxCON0 READ

Note 1: A write operation to the CMxCON0

condition because all writes include a read

operation at the beginning of the write

cycle.

2: Comparator interrupts will operate

correctly regardless of the state of CxOE.

Note 1: If a change in the CMxCON0 register

(CxOUT) sho uld occur when a re ad oper-

ation is being executed (start of the Q2

cycle), then the CxIF interrupt flag of the

PIR2 register may not get set.

2: When either comparator is first enabled,

bias circuitry in the comparator module

may cause an invalid output from the

comparator until the bias circuitry is

stable. Allow about 1 s for bias settling

then clear the mismatch condition and

interrupt flags before enabling comparator

interrupts.

CxIN+

CxIN

Set CxIF (edge)

CxIF

TRT

Reset by Software

CxIN+

CxOUT

Set CxIF (edge)

CxIF

TRT

Reset by Software

Cleared by CMxCON0 Read

 2010-2012 Microchip Technology Inc. DS41412F- page 315

PIC18(L)F2X/4XK22

18.5 Operation During Sleep

The compa rator , if enabled b efore entering Sleep mode,

remains active during Sleep. The additional current

consumed by the comparator is shown separately in

Section 27.0 “Electrical Characteristics”. If the

comparator is not used to wake the device, power

consumption can be minimized while in Sleep mode by

turning off the comp arator. Each comparator is turned off

by clearing the CxON bit of the CMxCON0 regis ter.

A change to the comparator output can wake-up the

device from Sleep. To enable the comparator to wake

the devic e from Sle ep, the CxIE bit of the PIE2 reg ister

and the PEIE/G IEL bit of th e IN TCO N regi ste r mu st be

set. The instruction following the SLEEP instruction

always executes following a wake from Sleep. If the

GIE/GIEH bit of the INTCON register is also set, the

device will then execute the Interrupt Service Routine.

18.6 Effects of a Reset

A device Reset forces the CMxCON0 and CM2CON1

registers to their Reset states. This forces both

comparators and the voltage references to their Off

states.Comparator Control Registers.

18.7 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 18-5. Since the analog input pins share their

connection with a digital input, they have reverse

biased ESD protection diodes to VDD and VSS. The

analog in put, therefore, must be betwee n VSS and VDD.

If the input voltage deviates from this range by more

than 0.6V in either direction, one of the diodes is

forward biased and a latch-up may occur.

A maximum source impedance of 10 k is recommended

for the analog sources. Also, any external component

connected to an ana log inp ut pin , such a s a capacitor or

a Zener diode, should have very little leakage cur rent to

minimize inaccuracies introduced.

FIGURE 18-5: ANALOG INPUT MODEL

Note 1: When reading a PORT register, all pins

configu red as analog in puts w ill read as a

‘0’. Pins configured as digital inputs will

convert as an analog input, according to

the input specification.

2: Analog levels on any pin defined as a

digit al input, may cause th e input buffer to

consume more current than is specified.

Rs < 10K

CPIN

5 pF

VDD

VT  0.6V

RIC

ILEAKAGE(1)

Vss

AIN

Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC = Interconnect Resistance

RS= Source I mpedance

VA= Analog Voltage

VT= Threshold Voltage

Note 1: See Section 27.0 “Electrical Characteristics”.

To Comparator

PIC18(L)F2X/4XK22

DS41412F-page 316  2010-2012 Microchip Technology Inc.

18.8 Additional Comparator Features

There are four additional comparator features:

• Simultaneous read of comparator outputs

• Internal refe renc e sel ec tio n

• Hys teresis selection

• Output Synchronization

18.8.1 SIMULTANEOUS COMPARATOR

OUTPUT READ

The MC1OUT and MC2OUT bits of the CM2CON1

The ability to read both outputs simultaneously from a

single register eliminates the timing skew of reading

separate registers.

18.8.2 INTERNAL REFERENCE

SELECTION

There are two internal voltage references available to

the non-inverting input of each comparator. One of

these is the Fixed Voltage Reference (FVR) and the

other is the varia ble Digit al-to-Analog Converter (D AC).

The CxRSEL bit of the CM2CON1 register determines

which of these referenc es is routed to the Comparator

Voltage reference output (CXVREF). Further routing to

the comparator is accomplished by the CxR bit of the

CMxCON0 register. See Section 21.0 “Fixed Voltage

Reference (FVR)” and Figure 18-2 for more detail.

18.8.3 COMPARATOR HYSTERESIS

Each Comparator has a selectable hysteres is feature.

The hysteresis can be enabled by setting the CxHYS

bit of th e C M 2CO N1 register. See Se ction 27.0 “Elec-

tri cal C haracteristics” for more details.

18.8.4 SYNCHRONIZING COMPARATOR

OUTPUT TO TIMER1

The Compar ator Cx outpu t can be sync hronize d with

Timer1 by setting the CxSYNC bit of the CM2CON1

the falling edge of the T imer1 source clock. To prevent

a race condition when gating Timer1 clock with the

comparator output, Timer1 increments on the rising

edge of its clock so urce, a nd the fal ling edg e latche s

the comparator output. See the Comparator Block

Diagram (Figure 18-2) and the Timer1 B l ock Diagram

(Figure 12-1) for more information.

Note 1: Obtaining the status of C1OUT or

C2OUT by reading CM2CON1 does not

affect the comparator interrupt mismatch

registers.

Note 1: The comparator synchronized output

should not be used to gate the external

Timer1 clock when the Timer1

synchronizer is enabled.

2: The Timer1 pr esc al e s ho uld be set to 1:1

when synchronizing the comparator

output as unexpected results may occur

with other prescale values.

 2010-2012 Microchip Technology Inc. DS41412F- page 317

PIC18(L)F2X/4XK22

18.9 Register Definitions: Comparator Control

R/W-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0

CxON CxOUT CxOE CxPOL CxSP CxR CxCH<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CxON: Comparator Cx Enable bit

1 = Comparator Cx is enabled

0 = Comparator Cx is disable d

bit 6 CxOUT: Comparator Cx Output b it

If CxPOL = 1 (inverted polarity):

CxOUT = 0 when CxVIN+ > CxVIN-

CxOUT = 1 when CxVIN+ < CxVIN-

If CxPOL = 0 (non-inverted polarity):

CxOUT = 1 when CxVIN+ > CxVIN-

CxOUT = 0 when CxVIN+ < CxVIN-

bit 5 CxOE: Comparator Cx Output Enab le bit

1 = CxOUT is present on the CxOUT pin(1)

0 = CxOUT is internal only

bit 4 CxPOL: Comparator Cx Output Polarity Select bit

1 = CxOUT logic is inverted

0 = CxOUT logic is not inverted

bit 3 CxSP: Comparator Cx Speed/Power Select bit

1 = Cx operates in Normal-Power, Higher Speed mode

0 = Cx operates in Low-Power, Low-Speed mode

bit 2 CxR: Comparator Cx Reference Select bit (non-inverting input)

1 = CxVIN+ connects to CXVREF output

0 = CxVIN+ connects to C12IN+ pin

bit 1-0 CxCH<1:0>: Comparator Cx Channel Select bit

00 = C12IN0- pin of Cx connects to CxVIN-

01 = C12IN1- pin of Cx connects to CXVIN-

10 = C12IN2- pin of Cx connects to CxVIN-

11 = C12IN3- pin of Cx connects to CxVIN-

Note 1: Comparator output requires the following three conditions: CxOE = 1, CxON = 1 and corresponding port

TRIS bit = 0.

PIC18(L)F2X/4XK22

DS41412F-page 318  2010-2012 Microchip Technology Inc.

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 MC1OUT: Mirror Copy of C1OUT bit

bit 6 MC2OUT: Mirror Copy of C2OUT bit

bit 5 C1RSEL: Comparator C1 Refe rence Select bit

1 = FVR BUF1 routed to C1VREF input

0 = DAC routed to C1VREF input

bit 4 C2RSEL: Comparator C2 Refe rence Select bit

1 = FVR BUF1 routed to C2VREF input

0 = DAC routed to C2VREF input

bit 3 C1HYS: Comparator C1 Hysteresis Enable bit

1 = Comparator C1 hysteresis enabled

0 = Comparator C1 hysteresis disabled

bit 2 C2HYS: Comparator C2 Hysteresis Enable bit

1 = Comparator C2 hysteresis enabled

0 = Comparator C2 hysteresis disabled

bit 1 C1SYNC: C1 Output Sync hronous Mode bit

1 = C1 output is synchronized to rising edge of TMR1 clock (T1CLK)

0 = C1 output is asynchronous

bit 0 C2SYNC: C2 Output Sync hronous Mode bit

1 = C2 output is synchronized to rising edge of TMR1 clock (T1CLK)

0 = C2 output is asynchronous

 2010-2012 Microchip Technology Inc. DS41412F- page 319

PIC18(L)F2X/4XK22

TABLE 18-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0 Register

on Page

ANSELA —— ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 154

ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 155

CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 318

CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH<1:0> 317

CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH<1:0> 317

VREFCON1 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 347

VREFCON2 — — — DACR<4:0> 348

VREFCON0 FVREN FVRST FVRS<1:0> — — — — 344

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129

PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125

PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120

PMD2 — — — — CTMUMD CMP2MD CMP1MD ADCMD 57

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 156

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156

Legend: — = unimp lemented locations , read as ‘0’. Shaded bits are not used by the comparator module.

PIC18(L)F2X/4XK22

DS41412F-page 320  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 321

PIC18(L)F2X/4XK22

19.0 CHARGE TIME

MEASUREMENT UNIT (CTMU)

The Charge Time Measurement Unit (CTMU) is a

flexible analog module that provides accurate

differential time measurement between pulse sources,

as well as asynchronous pulse generation. By working

with other on-chip analog modules, the CTMU can be

used to prec isel y meas ure time, measu re cap ac ita nce,

measure relative changes in capacitance or generate

output pulses with a specific time delay. The CTMU is

ideal for interfacing with capacitive-based sensors.

The module includes the following key features:

• Up to 28(1) channels available for capacitive or

time measurement input

• On-chip precision current source

• Four-edge input trigger sources

• Polarity control for each edge source

• Control of edge sequence

• Control of response to edges

• High precision time measurement

• Time delay of external or internal signal

asynchronous to system clock

• Accurate current source suitable for capacitive

measurement

The CTMU works in conjunction with the A/D Converter

to provide up to 28(1) channels for time or charge

measurement, depending on the specific device and

the number of A/D channels available. When config-

ured for time delay, the CTMU is connected to the

C12IN1- input of Comparator 2. The level-sensitive

input edge sources can be select ed from four sources:

two external input pins (CTED1/CTED2) or the ECCP1/

(E) CCP2 Specia l Event Triggers.

Figure 19-1 provides a block diagram of the CTMU.

FIGURE 19-1: CTMU BLOCK DIAGRAM

Note 1: PIC18(L)F2XK22 devices have up to 17

channel s available.

CTED1

CTED2

Current Source

Edge

Control

Logic

CTMUCONH/CTMUCONL

Pulse

Generator

ECCP2

ECCP1

Current

Control

ITRIM<5:0>

IRNG<1:0>

CTMUICON

CTMU

Control

Logic

EDGEN

EDGSEQEN

EDG1SELx

EDG1POL

EDG2SELx

EDG2POL EDG1STAT

EDG2STAT

TGEN

IDISSEN

CTPLS

Comparator 2 Output

CTTRIG

Comparator C1/C2 Input

A/D Converter

PIC18(L)F2X/4XK22

DS41412F-page 322  2010-2012 Microchip Technology Inc.

19.1 CTMU Operation

The CTMU works by using a fixed current source to

charge a circuit. The type of circui t depends on the type

of measurement being made. In the case of charge

measurement, the current is fixed, and the amount of

time the current is applied to the circuit is fixed. The

amou nt of vol tage re ad by the A/D is then a me asur e-

ment of the capacitance of the circuit. In the case of

time measurement, the current, as well as the capaci-

tance of the circuit, is fixed. In this case, the voltage

read by th e A/D is th en repre sent ativ e of the a mount of

time elapsed from the time the current source starts

and stops charging the circuit.

If the CTMU is being used as a time delay, both

cap acitance an d current source are fixed, as well as the

volt age s upplie d t o the comp arato r c ircuit . The d elay of

a signal is determined by the amount of time it takes the

voltage to charge to the comparator threshold voltage.

19.1.1 THEORY OF OPERATION

The operation of the CTMU is based on the equation

for charge:

More simply, the amount of charge measured in

coulombs in a circuit is defined as current in amperes

(I) multiplied by the amount of time in seconds that the

current flows (t). Charge is also defined as the

capacitance in farads (C) multiplied by the voltage of

the circuit (V). It follows that:

The CTM U modu le prov ides a const ant, know n curre nt

source. The A/D Converter is used to measure (V) in

the equation, leaving two unknowns: capacitance (C)

and time (t). The ab ove equ ation c an be use d to calc u-

late capacitance or time, by either the relationship

using the known fixed capac itance of the circuit:

or by:

using a fixed time that the current source is applied to

the circuit.

19.1.2 CURRENT SOURCE

At the hea rt of the CTMU is a pre cisi on current source,

designed to provide a constant reference for measure-

ments. The level of current is user-selectable across

three range s, with the ability to trim the output. The cur-

rent range is sele cted by the IRNG<1:0> bits (CTMUI-

CON<1:0>), with a value of ‘00’ representing the

lowest range.

Current trim is provided by the ITRIM<5:0> bits

(CTMUICO N<7:2>). N ote that ha lf of the range adjust s

the curre nt source p ositively and the oth er half r educes

the current source. A value of ‘000000’ is the neutral

position (no change). A value of ‘100000’ is the maxi-

mum negative adjustment, and ‘011111’ is the maxi-

mum positive adjustme nt.

19.1.3 EDGE SELECTION AND CONTROL

CTMU measurements are controlled by edge events

occurring on the module’s two input channels. Each

channel , referred to as Edge 1 and Ed ge 2, can be co n-

figured to receive input pulses from one of the edge

input pins (CTED1 and CTED2) or ECCPx Special

Event Triggers. The input channels are level-sensitive,

responding to the instantaneous level on the channel

rath er th an a t rans iti on be twee n le vels . The i npu ts are

selected using the EDG1SEL and EDG2SEL bit pairs

(CTMUCONL<3:2 and 6:5>).

In addition to source, each channel can be configured for

event polarity using the EDGE2POL and EDGE1POL

bits (CTMUCONL<7,4>). The input channels can also

be filtered for an edge event sequence (Edge 1 occur-

ring before Edge 2) by setting the EDGSEQEN bit

(CTMUCONH<2>).

19.1.4 EDGE STATUS

The C TMUCONL register also con tains two Status bit s:

EDG2STAT and EDG1STAT (CTMUCONL<1:0>).

Their primary function is to show if an edge response

has occurred on the corresponding channel. The

CTMU auto matic ally sets a p a rticul ar bit when a n edge

response is detected on its channel. The level-sensitive

nature of the in put chann els also means t hat the St atus

bit s b ecome set imm ediate ly if the cha nnel’ s conf igura-

tion is changed and is the same as the channel’s

current state.

-------=

ItCV.=

tCVI=

CItV=

 2010-2012 Microchip Technology Inc. DS41412F- page 323

PIC18(L)F2X/4XK22

The module uses the edge Status bits to control the

current source output to externa l analog modules (such

as the A/D Converter). Current is only supplied to

external modules when only one (but not both) of the

Status bits is set, and shuts current off when both bits

are either set or cleared. This allows the CTMU to

measure current only during the interval between

edges. After both Status bits are set, it is necessary to

clear t hem befo re another measu rem ent is t ak en. Both

bits should be cleared simultaneously, if possible, to

avoid re-enabling the CTMU current source.

In addition to being set by the CTMU hardware, the

edge Status bits can also be set by software. This is

also the user’s application to manually enable or

disable the current source. Setting either one (but not

both ) of t he bi ts enabl es th e cur rent sour ce. Sett ing or

clearing both bits at onc e disables the source.

19.1.5 INTERRUPTS

The CTMU sets its interrupt flag (PIR3<2>) whenever

the current source is enabled, then disabled. An

interrupt is generated only if the corresponding

interrupt enable bit (PIE3<2>) is also set. If edge

sequencing is not enabled (i.e., Edge 1 must occur

before Edge 2), it is necessary to monitor the edge

S tatus bits and determine whi ch edge occurred last and

caused the interrupt.

19.2 CTMU Module Initialization

The following sequence is a general guideline used to

initiali ze the CTMU mo dule:

1. Select the current source range using the IRNG

bits (CTMUICON<1:0>).

2. Adjust the current source trim using the ITRIM

bits (CTMUICON<7:2>).

3. Configure the edge input sources for Edge 1 and

Edge 2 by s etti ng the ED G1 SEL a nd EDG2SEL

bits (CTMUCONL<3:2 and 6:5>).

4. Configure th e input pola rities for the edge input s

using the EDG1POL and EDG2POL bits

(CTMUCONL<4,7>). The default configuration

is for negative edge polarity (high-to-low

transitions).

5. Enable ed ge sequencing using the ED GSEQEN

bit (CTMUCONH<2>). By default, edge

sequencing is disabled.

6. Select the operating mode (Measurement or

Time Delay) with the TGEN bit. The default

mode is Time/Capacitance Measurement.

7. Discharge the connected circuit by setting the

IDISSEN bit (CTMUCONH<1>); after waiting a

sufficient time for the circuit to discharge, clear

IDISSEN.

8. Disable the m odule by cl earing the CTM UEN b it

(CTMUCONH<7>).

9. Enable the module by setting the CTMUEN bit.

10. Clear the Edge Status bits: EDG2STAT and

EDG1STAT (CTMUCONL<1:0>).

11. Enable both edge inputs by setting the EDGEN

bit (CTMUCONH<3>).

Depending on the type of measurement or pulse

generation being performed, one or more additional

module s may al so need to be initial ized and confi gured

with the CTMU module:

• Edge Source Generation: In addition to the

external edge input pins, both Timer1 and the

Output Compare/PWM1 module can be used as

edge sources for the CTMU.

• Capacit ance or Time Measurement: The CTMU

module uses the A/D Converter to meas ure the

volt age across a capacitor that is connected to one

of the analog input channels.

• Pulse Gene ration: W hen ge neratin g sys tem cl ock

independent output pulses, the CTMU module

uses Comparator 2 and the associated

comp ara tor vo lt age reference.

PIC18(L)F2X/4XK22

DS41412F-page 324  2010-2012 Microchip Technology Inc.

19.3 Calibrating the CTMU Module

The CTMU requires calibration for precise

measurements of capacitance and time, as well as for

accurate time delay. If the application only requires

measurement of a relative change in capacitance or

time, calibration is usually not neces sary. An example of

this type of application would incl ude a capacitive touch

switch, in which the touch circuit has a baseline

capacitance, and the added capacitance of the human

body changes the overall capacitance of a ci rcuit.

If actual capac itance or ti me measurement is required,

two hardware calibrations must take place: the current

source needs calibration to set it to a precise current,

and the circuit being measured needs calibration to

measure and/or nullify all other capacitance other than

that to be measured .

19.3.1 CURRENT SOURCE CALIBRATION

The current source on the CTMU module is trimable.

Therefore, for precise measurements, it is possible to

measure and adjust this current source by placing a

high precision resistor, RCAL, onto an unused analog

channel. An example circuit is shown in Figure 19-2.

The current source measurement is performed using

the following steps:

1. Initialize the A/D Converter.

2. Initialize the CTMU.

3. Enable the current source by setti ng EDG1ST A T

(CTMUCONL<0>).

4. Issue settling time delay.

5. Perform A /D conversion.

6. Calculate the current source current using

I=V/RCAL, where RCAL is a high precision

resistance and V is meas ured by perfor min g an

A/D conversion.

The CTMU current source may be trimmed with the

trim bit s in CTMUICON using an i terative process to get

an exact desired current. Alternatively, the nominal

value without adjustment may be used; it may be

stored by the software for use in all subsequent

capacitive or time measurements .

To calculate the value for RCAL, the nominal current

must be chosen, and then the resistance can be

calculated. For example, if the A/D Converter reference

voltage is 3.3V, use 70% of full scale, or 2.31V as the

desired approximate voltage to be read by the A/D

Converter. If the range of the CTMU current source is

select ed to be 0.55 A, the resistor value needed is cal-

culated as RCAL = 2.31V/0.55 A, for a value o f 4.2 MΩ.

Similarly, if the current source is chosen to be 5.5 A,

RCAL would be 420,000Ω, and 42,000Ω if the current

source is set to 55 A.

FIGURE 19-2: CTMU CURRENT SOURCE

CALIBRATION CIRCUIT

A value of 70% of full-scale voltage is chosen to make

sure that the A/D Converter was in a range that is well

above the noise floor. Keep in mind that if an exact cur-

rent is chosen, that is to incorporate the trimming bits

from CTMUICON, th e resisto r value of RCAL ma y need

to be adjusted accordingly. RCAL may also be a djusted

to allow for av ailable re sistor val ues. RCAL shou ld be of

the highest precision available, keeping in mind the

amount of precision needed for the circuit that the

CTMU will be used to measure. A recommended

minimum would be 0.1% tolerance.

The following examples show one typical method for

performing a CTMU current calibration. Example 19-1

demonstrates how to initialize the A/D Converter and

the CTMU; this routine is typical for applications using

both modules. Example 19-2 demonstrates one

method for the actual calibration routine.

PIC18(L)FXXK22 Device

A/D Converter

CTMU

ANx

RCAL

Current Source

MUX

A/D

 2010-2012 Microchip Technology Inc. DS41412F- page 325

PIC18(L)F2X/4XK22

EXAMPLE 19-1: SE TUP FOR CTMU CALIBRATION ROUTINES

#include "p18cxxx.h"

/**************************************************************************/

/*Set up CTMU *****************************************************************/

/**************************************************************************/

void setup(void)

{ //CTMUCONH/1 - CTMU Control registers

CTMUCONH = 0x00; //make sure CTMU is disabled

CTMUCONL = 0x90;

//CTMU continues to run when emulator is stopped,CTMU continues

//to run in idle mode,Time Generation mode disabled, Edges are blocked

//No edge sequence order, Analog current source not grounded, trigger

//output disabled, Edge2 polarity = positive level, Edge2 source =

//source 0, Edge1 polarity = positive level, Edge1 source = source 0,

//CTMUICON - CTMU Current Control Register

CTMUICON = 0x01; //0.55uA, Nominal - No Adjustment

/**************************************************************************/

//Set up AD converter;

/**************************************************************************/

TRISA=0x04; //set channel 2 as an input

// Configure AN2 as an analog channel

ANSELAbits.ANSA2=1;

TRISAbits.TRISA2=1;

// ADCON2

ADCON2bits.ADFM=1; // Results format 1= Right justified

ADCON2bits.ACQT=1; // Acquition time 7 = 20TAD 2 = 4TAD 1=2TAD

ADCON2bits.ADCS=2; // Clock conversion bits 6= FOSC/64 2=FOSC/32

// ADCON1

ADCON1bits.PVCFG0 =0; // Vref+ = AVdd

ADCON1bits.NVCFG1 =0; // Vref- = AVss

// ADCON0

ADCON0bits.CHS=2; // Select ADC channel

ADCON0bits.ADON=1; // Turn on ADC

}

PIC18(L)F2X/4XK22

DS41412F-page 326  2010-2012 Microchip Technology Inc.

EXAMPLE 19-2: CURRE NT CALIBRATION ROUTINE

#include "p18cxxx.h"

#define COUNT 500 //@ 8MHz = 125uS.

#define DELAY for(i=0;i<COUNT;i++)

#define RCAL .027 //R value is 4200000 (4.2M)

//scaled so that result is in

//1/100th of uA

#define ADSCALE 1023 //for unsigned conversion 10 sig bits

#define ADREF 3.3 //Vdd connected to A/D Vr+

int main(void)

{

int i;

int j = 0; //index for loop

unsigned int Vread = 0;

double VTot = 0;

float Vavg=0, Vcal=0, CTMUISrc = 0; //float values stored for calcs

//assume CTMU and A/D have been set up correctly

//see Example 25-1 for CTMU & A/D setup

setup();

CTMUCONHbits.CTMUEN = 1; //Enable the CTMU

CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero

CTMUCONLbits.EDG2STAT = 0;

for(j=0;j<10;j++)

{

CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit

DELAY; //wait 125us

CTMUCONHbits.IDISSEN = 0; //end drain of circuit

CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit

//using CTMU current source

DELAY; //wait for 125us

CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit

PIR1bits.ADIF = 0; //make sure A/D Int not set

ADCON0bits.GO=1; //and begin A/D conv.

while(!PIR1bits.ADIF); //Wait for A/D convert complete

Vread = ADRES; //Get the value from the A/D

PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag

VTot += Vread; //Add the reading to the total

}

Vavg = (float)(VTot/10.000); //Average of 10 readings

Vcal = (float)(Vavg/ADSCALE*ADREF);

CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA

}

 2010-2012 Microchip Technology Inc. DS41412F- page 327

PIC18(L)F2X/4XK22

19.3.2 CAPACITANCE CALIBRATION

There is a small amount of capacitance from the

internal A/D Converter sample capacitor as well as

stray capacitance from the circuit board traces and

pads that affect the precision of capacitance

measurements. A measurement of the stray

capacitance can be taken by making sure the desired

capacitance to be measured has been removed. The

measurement is then performed using the following

steps:

1. Initialize the A/D Converter and the CTMU.

2. Set EDG1STAT (= 1).

3. Wait for a fixed delay of time t.

4. Clear EDG1STAT.

5. Perform an A/D conversion.

6. Calculate the stray and A/D sample capacitances:

where I is known from the current source measure ment

step, t is a fixed de lay and V is me asured by perform ing

an A/D convers ion.

This measured value is then stored and used for

calculations of time measurement or subtracted for

capacitance measurement. For calibration, it is

expected that the capacitance of CSTRAY +CAD is

approximately known. CAD is approximately 4 pF.

An iterat ive process may need to be use d to a dju st th e

time, t, that the cir cuit is charg ed to obtai n a reasonable

voltage reading from the A/D Converter. The value of t

may be determined by setting COFFSET to a theoretical

value, then solving for t. For example, if CSTRAY is

theoretically calculated to be 11 pF, and V is expected

to be 70% of VDD, or 2.31V, then t would be:

or 63 s.

See Example 19-3 for a typical routine for CTMU

capac itance calibra tion.

COFFSET CSTRAY CAD

+ItV==

(4 pF + 11 pF) • 2.31V/0.55 A

PIC18(L)F2X/4XK22

DS41412F-page 328  2010-2012 Microchip Technology Inc.

EXAMPLE 19-3: CAPACITANCE CALIBRATION ROUTINE

#include "p18cxxx.h"

#define COUNT 25 //@ 8MHz INTFRC = 62.5 us.

#define ETIME COUNT*2.5 //time in uS

#define DELAY for(i=0;i<COUNT;i++)

#define ADSCALE 1023 //for unsigned conversion 10 sig

bits

#define ADREF 3.3 //Vdd connected to A/D Vr+

#define RCAL .027 //R value is 4200000 (4.2M)

//scaled so that result is in

//1/100th of uA

int main(void)

{

int i;

int j = 0; //index for loop

unsigned int Vread = 0;

float CTMUISrc, CTMUCap, Vavg, VTot, Vcal;

//assume CTMU and A/D have been set up correctly

//see Example 25-1 for CTMU & A/D setup

setup();

CTMUCONHbits.CTMUEN = 1; //Enable the CTMU

CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero

CTMUCONLbits.EDG2STAT = 0;

for(j=0;j<10;j++)

{

CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit

DELAY; //wait 125us

CTMUCONHbits.IDISSEN = 0; //end drain of circuit

CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit

//using CTMU current source

DELAY; //wait for 125us

CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit

PIR1bits.ADIF = 0; //make sure A/D Int not set

ADCON0bits.GO=1; //and begin A/D conv.

while(!PIR1bits.ADIF); //Wait for A/D convert complete

Vread = ADRES; //Get the value from the A/D

PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag

VTot += Vread; //Add the reading to the total

}

Vavg = (float)(VTot/10.000); //Average of 10 readings

Vcal = (float)(Vavg/ADSCALE*ADREF);

CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA

CTMUCap = (CTMUISrc*ETIME/Vcal)/100;

}

 2010-2012 Microchip Technology Inc. DS41412F- page 329

PIC18(L)F2X/4XK22

19.4 Measuring Capacitance with the

CTMU

There are two separate methods of measuring

capacitance with the CTMU. The first is the absolute

method, in which the actual capacitance value is

desired. The second is the relative method, in which

the actual capacitance is not needed, rather an

indication of a change in capacitance is required.

19.4.1 ABSOLUTE CAPACITANCE

MEASUREMENT

For absolute capacitance measurements, both the

current and capacitance calibration steps found in

Section 19.3 “Calibrating the CTMU Module”

should be followed. Capacitance measurements are

then performed using the following steps:

1. Initialize the A/D Converter.

2. Initialize the CTMU.

3. Set EDG1STAT.

4. Wait for a fixed delay, T.

5. Clear EDG1STAT.

6. Perform an A/D conversion.

7. Calculate the total capacitance, CTOTAL = (I * T)/V,

where I is known from the current source

measurement step ( s ee Section 19.3.1 “Current

Sourc e Calibrat ion”), T is a fixed delay and V is

measured by performing an A/D conversion.

8. Subtract the stray and A/D capacitance

(COFFSET from Section 19.3.2 “Capacitance

Calibration”) from CTOTAL to determine the

measured capacitance.

19.4.2 RELATIVE CHARGE

MEASUREMENT

An application may not require precise capacitance

measurements. For example, when detecting a valid

press of a capacitance-based switch, detecting a rela-

tive change o f capacitance is of interest. In this typ e of

application, when the switch is open (or not touched),

the tot al capacit ance is the capacitan ce of the combina-

tion of the board traces, the A/D Converter , etc. A larger

voltag e will be measu red by the A/D Conver ter. When

the switch is closed (or is touched), the total

capacitance is larger due to the addition of the

capacitance of the human body to the above listed

capacitances, and a smaller voltage will be measured

by the A/D Converter.

Detecting capacitance changes is easily accomplished

with the CTMU using these steps:

1. Initialize the A/D Converter and the CTMU.

2. Set EDG1STAT.

3. Wait for a fixed delay.

4. Clear EDG1STAT.

5. Perform an A/D conversion.

The voltage measured by performing the A/D

conversion is an indication of the relative capacitance.

Note that in this case, no calibration of the current

source or circuit capacitance measurem ent is needed.

See Example 19-4 for a sample software routine for a

capacitive touch switch.

PIC18(L)F2X/4XK22

DS41412F-page 330  2010-2012 Microchip Technology Inc.

EXAMPLE 19-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH

#include "p18cxxx.h"

#define COUNT 500 //@ 8MHz = 125uS.

#define DELAY for(i=0;i<COUNT;i++)

#define OPENSW 1000 //Un-pressed switch value

#define TRIP 300 //Difference between pressed

//and un-pressed switch

#define HYST 65 //amount to change

//from pressed to un-pressed

#define PRESSED 1

#define UNPRESSED 0

int main(void)

{

unsigned int Vread; //storage for reading

unsigned int switchState;

int i;

//assume CTMU and A/D have been set up correctly

//see Example 25-1 for CTMU & A/D setup

setup();

CTMUCONHbits.CTMUEN = 1; // Enable the CTMU

CTMUCONLbits.EDG1STAT = 0; // Set Edge status bits to zero

CTMUCONLbits.EDG2STAT = 0;

CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit

DELAY; //wait 125us

CTMUCONHbits.IDISSEN = 0; //end drain of circuit

CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit

//using CTMU current source

DELAY; //wait for 125us

CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit

PIR1bits.ADIF = 0; //make sure A/D Int not set

ADCON0bits.GO=1; //and begin A/D conv.

while(!PIR1bits.ADIF); //Wait for A/D convert complete

Vread = ADRES; //Get the value from the A/D

if(Vread < OPENSW - TRIP)

{

switchState = PRESSED;

}

else if(Vread > OPENSW - TRIP + HYST)

{

switchState = UNPRESSED;

}

 2010-2012 Microchip Technology Inc. DS41412F- page 331

PIC18(L)F2X/4XK22

19.5 Measuring T ime with the CTMU

Module

Time can be prec isely measured after the ratio (C/I) is

measur ed from the current and capac ita nce cal ibratio n

step by following these steps:

1. Initialize the A/D Converter and the CTMU.

2. Set EDG1STAT.

3. Set EDG2STAT.

4. Perform an A/D conversion.

5. Calcul ate the time betwe en edge s as T = (C/I) * V ,

where I is ca lculated in the current c alibration step

(Section 19.3.1 “Current Source Calibration”),

C is calculated in the capacitance calibration step

(S ection 19.3.2 “Cap acit ance Calib ration”) and

V is measured by performing the A/D conversion.

It is assumed that the time measured is small enough

that the capacitance, COFFSET, provides a valid voltage

to the A/D Converter. For the smallest time measure-

ment, always set the A/D Channel Select register

(AD1CHS) to an unused A/D channel; the correspond-

ing pin for which is not connected to any circuit board

trace. This minimizes added stray capacitance, keep-

ing the total circuit capacitance close to that of the A/D

Converter itself (4-5 pF). To measure longer time

intervals, an external capacitor may be connected to an

A/D channel and this channel selected when making a

time measurement.

FIGU RE 19-3: TYPICAL C O NN ECT I ON S AN D IN T ERN AL CONF I G UR ATIO N F OR TIME

MEASUREMENT

A/D Converter

CTMU

CTED1

CTED2

ANX

Output

Pulse

EDG1

EDG2

CAD

RPR

Current Source

PIC18(L)FXXK22 Device

PIC18(L)F2X/4XK22

DS41412F-page 332  2010-2012 Microchip Technology Inc.

19.6 Creating a Delay with the CTMU

Module

A unique feature on board the CTMU module is its

ability to generate system clock independent output

pulses based on an external capacitor value. This is

accomplished using the internal comparator voltage

reference module, Comparator 2 input pin and an

external cap acit or. The puls e is ou tput onto the CT PLS

pin. To enable this mode, set the TGEN bit.

See Figure 19-4 for an example circuit. CPULSE is

chosen by th e user to dete rmine the out put pulse wid th

on CTPLS. The pulse width is calculated by

T=(CPULSE/I)*V, where I is known from the current

source measurement step (Section 19.3.1 “Current

Source Calibration”) and V is the internal reference

voltage (CVREF).

An example use of this feature is for interfacing with

variable capacitive-based sensors, such as a humidity

senso r. A s the humi dity va ries, the puls e width ou tput

on CTPL S will vary. The CT PLS outp ut pin can be co n-

nected to an input capture pin and the varying pulse

width is measured to determine the humidity in the

application.

Follow these steps to use this feature:

1. Initialize Comparator 2.

2. Initialize the comparator voltage reference.

3. Initialize the CTMU and enable time delay

generation by setting the TGEN bi t.

4. Set EDG1STAT.

5. When CPULSE charges to the value of the voltage

reference trip point, an output pulse is generated

on CTPLS.

FIGURE 19-4: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE

DELAY GENERATION

19.7 Operation During Sleep/Idle

Modes

19.7.1 SLEEP MODE AND DEEP SLEEP

MODES

When the device enters any Sleep mode, the CTMU

module cu rrent sou rce is alwa ys di sable d. If the CTMU

is perfor mi ng an operation tha t de pen ds on t he c urre nt

source when Sleep mode is invoked, the operati on may

not terminate correctly. Capacitance and time

measurements may return erroneous values.

19.7.2 IDLE MODE

The behavior of the CTMU in Idle mode is determined

by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL

is cleared, the module will continue to operate in Idle

mode. I f CTMUSIDL is set, the mod ule’s c urrent source

is disabled when the device enters Idle mode. If the

module is performing an operation when Idle mode is

invoke d, in this cas e, the res ul ts will be si mi lar to those

with Sleep mode.

19.8 CTMU Peripheral Module Disable

(PMD)

When this peripheral is not used, the Peripheral

Module Disable bit can be set to disconnect all clock

sources to the module, reduci ng power cons umption to

an absolute minimum. See Section 3.6 “Selective

Peripheral Module Control”.

CVREF

CTPLS

PIC18(L)FXXK22 Device

Current Source

Comparator

CTMU

CTED1

C12IN1-

CPULSE

EDG1

 2010-2012 Microchip Technology Inc. DS41412F- page 333

PIC18(L)F2X/4XK22

19.9 Effects of a Reset on CTMU

Upon Re set, all registers of the CTMU are cleared. This

leaves the CTMU module disabled, it s current source is

turned off and all configuration options return to their

default settings. The module needs to be re-initialized

following any Reset.

If the CTMU is in the process of taking a measurement at

the t ime of R ese t, the meas urem ent wi ll be lo st. A p art ial

charge may exist on the circuit that was being measured,

and should be properly discharged before the CTMU

makes subsequent attempts to make a measurement.

The cir cuit is dis cha rged by sett ing an d then clea ring th e

IDISSEN bit (CTMUCONH<1>) while the A/D Converter

is connected to the appropriate channel.

19.10 Registers

There are three control registers for the CTMU:

• CTMUCONH

• CTMUCONL

• CTMUICON

The CTMUCONH and CTMUCONL registers

(Register 19-1 and Register 19-2) contain control bits

for configuring the CTMU module edge source selec-

tion, edge source polarity selection, edge sequencing,

A/D trigger, analog circuit capacitor discharge and

enables. The CTMUICON register (Register 19-3) has

bits for selecting the current source range and current

source trim.

19.11 Register Definitions: CTMU Control

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CTMUEN: CTMU Enable bit

1 = Module is enabled

0 = Module is disabled

bit 6 Unimplemented: Read as ‘0’

bit 5 CTMUSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 4 TGEN: Time Generation Enable bit

1 = Enables edge del ay genera t io n

0 = Disables ed ge delay ge neration

bit 3 EDGEN: Edge Enable bit

1 = Edges are not blocked

0 = Edges are bl ock ed

bit 2 EDGSEQEN: Edge Sequence Enable bit

1 = Edge 1 ev ent must occur befor e Edge 2 event can occur

0 = No edge sequence is needed

bit 1 IDISSEN: Analog Current Source Control bit

1 = Analog current source output is grounded

0 = Analog current source output is not grounded

bit 0 CTTRIG: CTMU Special Event Trigger Control Bit

1 = CTMU Special Event Trigger is enabled

0 = CTMU Special Event Trigger is disabled

PIC18(L)F2X/4XK22

DS41412F-page 334  2010-2012 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EDG2POL EDG2SEL<1:0> EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EDG2POL: Edge 2 Polarity Select bit

1 = Edge 2 progr ammed for a positive edge response

0 = Edge 2 programmed for a negat ive edge response

bit 6-5 EDG2SEL<1:0>: Edge 2 Source Select bits

11 = CTED1 pin

10 = CTED2 pin

01 = ECCP1 Special Event Trigger

00 = ECCP2 Special Event Trigger

bit 4 EDG1POL: Edge 1 Polarity Select bit

1 = Edge 1 progr ammed for a positive edge response

0 = Edge 1 programmed for a negat ive edge response

bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits

11 = CTED1 pin

10 = CTED2 pin

01 = ECCP1 Special Event Trigger

00 = ECCP2 Special Event Trigger

bit 1 EDG2STAT: Edge 2 Status bit

1 = Edge 2 event has occurred

0 = Edge 2 event has not occurr ed

bit 0 EDG1STAT: Edge 1 Status bit

1 = Edge 1 event has occurred

0 = Edge 1 event has not occurr ed

 2010-2012 Microchip Technology Inc. DS41412F- page 335

PIC18(L)F2X/4XK22

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ITRIM<5:0> IRNG<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 ITRIM<5:0>: Current Source Trim bits

011111 = Maximum positive change from nominal current

011110

000001 = Minimum positive change from nominal current

000000 = Nominal current output specified by IRNG<1:0>

111111 = Minimum negative change from nominal current

100010

100001 = Maximum negative change from nominal current

bit 1-0 IRNG<1:0>: Current Source Range Select bits (see Table 27-4)

11 = 100  Bas e current

10 = 10  Base current

01 = Base current level

00 = Current source disabled

TABLE 19-1: REGISTERS ASSOCIATED WITH CTMU MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on Page

CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 333

CTMUCONL EDG2POL EDG2SEL<1:0> EDG1POL EDG1SEL<1:0> EDG2STAT EDG1STAT 334

CTMUICON ITRIM<5:0> IRNG<1:0> 335

IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130

PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126

PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121

PMD2 — — — — CTMUMD CMP2MD CMP1MD ADCMD 57

Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during CTMU operation.

PIC18(L)F2X/4XK22

DS41412F-page 336  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 337

PIC18(L)F2X/4XK22

20.0 SR LATCH

The module consists of a single SR latch with multiple

Set and Reset input s a s well as sep arat e l atch output s.

The SR latch module includes the following features:

• Programmable input selection

• SR latch output is available internally/externally

• Selectable Q and Q output

• Firmware Set and Reset

The SR latch can be used in a variety of analog

applications, including oscillator circuits, one-shot

circuit, hysteretic controllers, and analog timing

applications.

20.1 Latch Operation

The latch is a Set-Reset latch that does not depend o n a

clock source. Each of the Set and Reset inputs are

active-high. The latch can be s et or reset by:

• Software control (SRPS and SRPR bits )

• Comparator C1 output (sync_C1OUT)

• Comparator C2 output (sync_C2OUT)

•SRI Pin

• Programmable clock (DIVSRCLK)

The SRPS and the SRPR bits of the SRCON0 register

may be used to set or reset the SR latch, respectively.

The latc h is Reset -dominant . Therefore, i f both Set an d

Reset inputs are high, the latch will go to the Reset

state. Both the SRPS and SRPR bits are self resetting

which means that a single write to either of the bits is

all that is necessary to complete a latch Set or Reset

operation.

The output from Comparator C1 or C2 can be used as

the Set or Reset inputs of the SR latch. The output of

either Comparator can be synchronized to the Timer1

clock source. See Section 18.0 “Comparator

Module” and Section 12.0 “Timer1/3/5 Module with

Gate Control” for more information.

An external source on the SRI pin can be used as the

Set or Reset inputs of the SR latch.

An inter nal cloc k sour ce, DIVSRCL K, is av ailable and it

can periodically set or reset the SR latch. The

SRCLK<2:0> bits in the SRCON0 register are used to

select the clock source period. The SRSCKE and

SRRCKE bi ts of th e SRCON1 regist er enable the clock

source to set or reset the SR latch, respectively.

20.2 Latch Output

The SRQEN and SRNQEN bits of the SRCON0

SR latch outputs may be directly output to I/O pins at

the same time. Control is determined by the st ate of bits

SRQEN and SRNQEN in the SRCON0 register.

The applicable TRIS bit of the corresponding port must

be cleared to enable the port pin output driver.

20.3 DIVSRCLK Clock Generation

The DIVSRCLK clock signal is generated from the

peripheral clock which is pre-scaled by a value

determined by the SRCLK<2:0> bits. See Figure 20-2

and Table 20-1 for additional detail.

20.4 Effects of a Reset

Upon any device Reset, the SR latch is not initialized,

and the SRQ and SRNQ outputs are unknown. The

user’s firmware is responsible to initialize the latch

output before enabling it to the output pins.

PIC18(L)F2X/4XK22

DS41412F-page 338  2010-2012 Microchip Technology Inc.

FIGURE 20-1: DIVSRCLK BLOCK DIAGRAM

FIGURE 20-2: SR LATCH SIMP LIFIED BLOCK DIAGRAM

SRCLK<2:0>

Peripheral

Clock DIVSRCLK

Programmable

SRCLK divider

1:4 to 1:512

Tosc

4-512 cycles

...

SRCLK<2:0> = "001"

1:8

t0+4t0 t0+8 t0+12

SRPS

Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q =1

2: Pulse generator causes a pulse width of 2 TOSC clock cycles.

3: Name denotes the connection point at the comparator output.

Pulse

Gen(2)

Latch(1)

SRQEN

SRSPE

SRSC2E

SRSCKE

DIVSRCLK

sync_C2OUT(3)

SRSC1E

sync_C1OUT(3)

SRPR Pulse

Gen(2)

SRRPE

SRRC2E

SRRCKE

DIVSRCLK

sync_C2OUT(3)

SRRC1E

sync_C1OUT(3)

SRLEN

SRNQEN

SRLEN

SRQ

SRNQ

SRI

 2010-2012 Microchip Technology Inc. DS41412F- page 339

PIC18(L)F2X/4XK22

TABLE 20-1: DIVSRCLK FREQUENCY TABLE

SRCLK<2:0> Divider FOSC = 20 MHz FOSC = 16 MHz FOSC = 8 MHz FOSC = 4 MHz FOSC = 1 MHz

111 512 25.6 s32 s64 s 128 s 512 s

110 256 12.8 s16 s32 s64 s 256 s

101 128 6.4 s8 s16 s32 s 128 s

100 64 3.2 s4 s8 s16 s64 s

011 32 1.6 s2 s4 s8 s32 s

010 16 0.8 s1 s2 s4 s16 s

001 80.4 s0.5 s1 s2 s8 s

000 40.2 s0.25 s0.5 s1 s4 s

PIC18(L)F2X/4XK22

DS41412F-page 340  2010-2012 Microchip Technology Inc.

20.5 Register Defini tions: SR Latch Control

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SRLEN: SR Latch Enable bit(1)

1 = SR latch is enabled

0 = SR latch is disabled

bit 6-4 SRCLK<2:0>: SR Latch Clock Divider Bits

000 = Generates a 2 TOSC wide pulse on DIVSRCLK every 4 peripheral clock cycles

001 = Generates a 2 TOSC wide pulse on DIVSRCLK every 8 peripheral clock cycles

010 = Generates a 2 TOSC wide pulse on DIVSRCLK every 16 peripheral clock cycles

011 = Generates a 2 TOSC wide pulse on DIVSRCLK every 32 peripheral clock cycles

100 = Generates a 2 TOSC wide pulse on DIVSRCLK every 64 peripheral clock cycles

101 = Generates a 2 TOSC wide pulse on DIVSRCLK every 128 peripheral clock cycles

110 = Generates a 2 TOSC wide pulse on DIVSRCLK every 256 peripheral clock cycles

111 = Generates a 2 TOSC wide pulse on DIVSRCLK every 512 peripheral clock cycles

bit 3 SRQEN: SR Latch Q Output Enable bit

1 = Q is present on the SRQ pin

0 = Q is internal only

bit 2 SRNQEN: SR Latch Q Output Enable bit

1 =Q is present on the SRNQ pin

0 =Q

is internal only

bit 1 SRPS: Pulse Set Input of the SR Latch bit(2)

1 = Pulse set input for two TOSC clock cycles

0 = No effect on set input

bit 0 SRPR: Pulse Reset Input of the SR Latch bit(2)

1 = Pulse reset input for two TOSC clock cycles

0 = No effect on Reset input

Note 1: Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset

inputs of the latch.

2: Set only, always reads bac k ‘0’.

 2010-2012 Microchip Technology Inc. DS41412F- page 341

PIC18(L)F2X/4XK22

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SRSPE: SR Latch Peripheral Set Enable bit

1 = SRI pin status sets SR latch

0 = SRI pin status has no effect on SR latch

bit 6 SRSCKE: SR Latch Set Clock Enable bit

1 = Set input of SR latch is pulsed with DIVSRCLK

0 = Set input of SR latch is not pulsed with DIVSRCLK

bit 5 SRSC2E: SR Latch C2 Set Enable bit

1 = C2 Compa rator output set s SR latch

0 = C2 Comparator output has no effect on SR latch

bit 4 SRSC1E: SR Latch C1 Set Enable bit

1 = C1 Compa rator output set s SR latch

0 = C1 Comparator output has no effect on SR latch

bit 3 SRRPE: SR Latch Peripheral Reset Enable bit

1 = SRI pin resets SR latch

0 = SRI pin has no effect on SR latch

bit 2 SRRCKE: SR Latch Reset Clock Enable bit

1 = Reset input of SR latch is pulsed with DIVSRCLK

0 = Reset input of SR latch is not pulsed with DIVSRCLK

bit 1 SRRC2E: SR Latch C2 Reset Enable bit

1 = C2 Comparator output resets SR latch

0 = C2 Comparator output has no effect on SR latch

bit 0 SRRC1E: SR Latch C1 Reset Enable bit

1 = C1 Comparator output resets SR latch

0 = C1 Comparator output has no effect on SR latch

TABLE 20-2: REGISTERS ASSOCIATED WITH THE SR LATCH

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 340

SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 341

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 156

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 156

WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 157

Legend: Shaded bits are not used with this module.

PIC18(L)F2X/4XK22

DS41412F-page 342  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 343

PIC18(L)F2X/4XK22

21.0 FIXED VOLTAGE REFERENCE

(FVR)

The Fixed Voltage Reference, or FVR, is a stable

voltage reference, independent of VDD, with 1.024V,

2.048V or 4.096V selectable output levels. The output

of the FVR can be configured to supply a reference

voltage to the following:

• ADC input channel

• ADC positive reference

• Comparator positive input

• Digital-to-Analog C onverter (D AC)

The FVR can be enabled by setting the FVREN bit of

the VREFCON0 register.

21.1 Independent Gain Amplifiers

The output of the FVR supplied to the ADC,

Comparators and DAC is routed through an

independent programmable gain amplifier. The

amplifier can be configured to amplify the 1.024V

reference voltage by 1x, 2x or 4x, to produce the three

possible voltage lev els .

The FVRS<1:0> bits of the VREFCON0 register are

used to enable and configure the gain amplifier settings

for the reference supplied to the DAC and Comparator

modules. When the ADC module is configured to use

the FVR output, (FVR BUF2) the reference is buffered

through an additional unity gain a mp lif ier. This bu f fe r i s

disabled if the ADC is not configured to use the FVR.

For spe cific use of the FVR, refer to the specific mo dule

sections: Section 17.0 “Analog-to-Digital Converter

(ADC) Module”, Section 22.0 “Digital-to-Analog

Converter (DAC) Module” and Section 18.0 “Com-

parator Module”.

21.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it

requires time for the reference and amplifier circuits to

stabilize. Once the circuits stabilize and are ready for use,

the FVRST bit of the VREFCON0 register will be set. See

Table 27-3 for the minimum delay requirement.

FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM

to Comparators, DAC

FVREN

FVRST

FVRS<1:0>

to ADC module

FVR BUF1

FVR BUF2

1.024V

Fixed

Voltage

Reference

Note 1: FVR_b uf2_enable = ‘1’ when (ADON = ‘1’)AND [(PVCFG<1:0> = ‘10’) OR ( CHS<4:0> = ‘11111’)]

FVR_buf2_enable(1)

PIC18(L)F2X/4XK22

DS41412F-page 344  2010-2012 Microchip Technology Inc.

21.3 Register Definitions: FVR Control

R/W-0 R/W-0 R/W-0 R/W-1 U-0 U-0 U-0 U-0

FVREN FVRST FVRS<1:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 FVREN: Fixed Voltage Reference Enable bit

0 = Fixed Voltage Reference is disabled

1 = Fixed Voltage Reference is enabled

bit 6 FVRST: Fixed Voltage Reference Read y F lag bit

0 = Fixed Voltage Reference output is not ready or not enabled

1 = Fixed Voltage Referen ce out put is ready for use

bit 5-4 FVRS<1:0>: Fixed Voltage Reference Selection bits

00 = Fixed Voltage Reference Peripheral output is off

01 = Fixed Voltage Reference Peripheral output is 1x (1.024V)

10 = Fixed Voltage Reference Peripheral output is 2x (2.048V)(1)

11 = Fix ed Voltage R eferenc e Per ipheral output is 4x (4.096V) (1)

bit 3-2 Reserved: Read as ‘0’. Maintain these bits clear.

bit 1-0 Unimplemented: Read as ‘0’.

Note 1: Fixed Voltage Reference output cannot exceed VDD.

TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

VREFCON0 FVREN FVRST FVRS<1:0> — — — — 344

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by the FVR module.

 2010-2012 Microchip Technology Inc. DS41412F- page 345

PIC18(L)F2X/4XK22

22.0 DIGITAL-TO-ANALOG

CONVERTER (DAC) MODULE

The Digital-to-Analog Converter supplies a variable

voltage reference, ratiometric with the input source,

with 32 selectable output levels.

The input of the DAC can be connected to:

•External V

REF pins

•VDD supply voltage

• FVR (Fixed Voltage Reference)

The output of the DAC can be configured to supply a

reference voltage to the following:

• Comparator positive input

• ADC input channel

•DACOUT pin

The Digit al-to-An alog Converte r (DAC) can be enabled

by setting the DACEN bit of the VREFCON1 register.

22.1 Output Voltage Selection

The DAC has 32 voltage level ranges. The 32 levels

are set with the DACR<4:0> bits of the VREFCON2

The DAC ou tput vol t ag e is determined by the foll owing

equations:

EQUATION 22-1: DAC OUTPUT VOLTAGE

22.2 Ratiometric Output Level

The DAC output value is derived using a resistor ladder

with each end of the ladder tied to a positive and

negative voltage reference input source. If the voltage

of either input source fluctuates, a similar fluctuation will

result in the DAC output value.

The value of the individual resistors within the ladder

can be found in Section 27.0 “Electrical

Characteristics”.

22.3 Low-Power Voltage State

In order for the DAC module to consume the least

amount of power, one of the two voltage reference input

sources to the resistor ladder must be disconnected.

Either the positive voltage source, (VSRC+), or the

negative voltage source, (VSRC-) can be disabled.

The negative voltage source is disabled by setting the

DACLPS bit in the VREFCON1 register. Clearing the

DACLPS bit in the VREFCON1 register disables the

positive voltage source.

22.4 Output Clamped to Positive

Voltage Source

The DAC output voltage can be set to VSRC+ with the

least a mount of power co nsumption by perfor ming the

following:

• Clearing the DACEN bit in the V REFCON1

• Setting the DACLPS bit in the VREFCON1

• Configuring the DACPSS bits to the proper

positive source.

• Configuring the DACRx bits to ‘11111’ in the

VREFCON2 register.

This is also the method used to output the voltage level

from the FVR to an output pin. See Section 22.6 “DAC

Voltage Reference Output” for more information.

22.5 Output Clamped to Negative

Voltage Source

The DAC output voltage can be set to VSRC- with the

least a mount of power co nsumption by perfor ming the

following:

• Clearing the DACEN bit in the V REFCON1

• Clearing the DACLPS bit in th e VREFCON1

• Configuring the DACPSS bits to the proper

negative source.

• Configuring the DACRx bits to ‘00000’ in the

VREFCON2 register.

This allows the comparator to detect a zero-crossing

while not consuming additional current through the DAC

module.

22.6 DAC Voltage Reference Output

The DAC can be output to the DACOUT pin by setting

the DACOE bit of the VREFCON1 register to ‘1’.

Selecting the DAC reference voltage for output on the

DACOUT pin automatically overrides the digital output

buffer and digital input threshold detector functions of

that pin. Reading the DACOUT pin when it has been

configured for DAC reference voltage output will always

return a ‘0’.

Due to the limited curren t drive cap abilit y, a buf fer must

be used on the DAC voltage reference output for

external connections to DACOUT. Figure 22-2 shows

an example buffering technique.

VOUT VSRC+VSRC-–

DACR<4:0>

-------------------------------





=+ VSRC-

VSRC+ = VDD, VREF+ or FVR1

VSRC- = VSS or VREF-

PIC18(L)F2X/4XK22

DS41412F-page 346  2010-2012 Microchip Technology Inc.

FIGURE 22-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

FIGURE 22-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

32-to-1 MUX

DACR<4:0>

VREF-

DACNSS

32 DAC Output

DACOUT

(to Comparators and

ADC Modules)

DACOE

VDD

VREF+

DACPSS<1:0>

DACEN

Steps

Digital-to-Ana log Converter (DAC)

FVR BUF1

VSRC-

VSRC+

VSS

DACLPS

11111

11110

00001

00000

Reserved 11

DACOUT Buffered DAC Output

–

DAC

Module

Voltage

Reference

Output

Impedance

PIC® MCU

 2010-2012 Microchip Technology Inc. DS41412F- page 347

PIC18(L)F2X/4XK22

22.7 Operation During Sleep

When the device wakes up from Sleep through an

inter rupt or a Watchdog Timer time-out, the co ntent s of

the VREFCON1 register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

22.8 Effects of a Reset

A device Reset af fec t s the follow ing:

• DAC is disabled

• DAC output voltage is removed from the

DACOUT pin

• The DACR<4:0> range select bits are cleared

22.9 Register Definitions: DAC Control

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0

DACEN DACLPS DACOE —DACPSS<1:0> —DACNSS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 DACEN: DAC Enable bit

1 = DAC is enabled

0 = DAC is disabled

bit 6 DACLPS: DAC Low-Power Voltage Source Select bit

1 = DAC Positive reference source sel ecte d

0 = DAC Negative reference source selected

bit 5 DACOE: DAC Voltag e Output E nable bit

1 = DAC voltage level is also an output on the DACOUT pin

0 = DAC voltage level is disconnected from the DACOUT pin

bit 4 Unimplemented: Read as ‘0’

bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits

00 =V

01 =VREF+

10 = FVR BUF1 output

11 = R eserved, do no t use

bit 1 Unimplemented: Read as ‘0’

bit 0 DACNSS: DAC Negat ive Source Select bits

1 =V

REF-

0 =V

PIC18(L)F2X/4XK22

DS41412F-page 348  2010-2012 Microchip Technology Inc.

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — DACR<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 DACR<4:0>: DAC Voltage Output Select bits

VOUT = ((VSRC+) - (VSRC-))*(DACR<4:0>/(25)) + VSRC-

TABLE 22-1: REGISTERS ASSOCIATED WITH DAC MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

VREFCON0 FVREN FVRST FVRS<1:0> ————344

VREFCON1 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 347

VREFCON2 — — — DACR<4:0> 348

Legend: — = Unimplemented locations, read as ‘0’. Shaded bits are not used by the DAC module.

 2010-2012 Microchip Technology Inc. DS41412F- page 349

PIC18(L)F2X/4XK22

23.0 HIGH/LOW-VOLTAGE DETECT

(HLVD)

The PIC18(L)F2X/4XK22 devices hav e a High/Low-Volt-

age Detect mo dule (H LVD). This is a programma ble ci r-

cuit that sets both a device voltage trip point and the

direction of change from that point. If the device experi-

ences an excursion past the trip point in that direction, an

interrupt flag is set. If the interrupt is enabled, the pro-

gram execution branch es to the interrupt vector addre ss

and the soft ware responds to the in terrupt.

The High/Low-Voltage Detect Control register

(Register 23-1) completely controls the operation of the

HLVD module. This allows the circuitry to be “turned

off” by the user under software control, which

minimizes the current consumption for the device.

The modul e’s block diag ram is shown in Figure 23-1.

23.1 Register - HLVD Control

R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1

VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 VDIRMAG: Voltage Direction Magnitude Select bit

1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>)

0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>)

bit 6 BGVST: Band Gap Reference Voltages Stable Status Flag bit

1 = Internal band gap voltage references are stable

0 = Internal band gap voltage reference is not stable

bit 5 IRVST: Internal Refer ence Voltage Stable Flag bi t

1 = Indicates that the volt age detect l ogic will genera te the interrup t flag at the spec ified volt age range

0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage

range and the HLVD interrupt should not be enabled

bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit

1 = HLVD enabled

0 = HLVD disabled

bit 3-0 HLVDL<3:0>: Voltage Detection Level bits(1)

1111 = External analog input is used (input comes from the HLVDIN pin)

1110 = Maximu m setting

0000 = Minimum setting

Note 1: See Table 27-5 for speci fic ati ons .

PIC18(L)F2X/4XK22

DS41412F-page 350  2010-2012 Microchip Technology Inc.

The module is enabled by setting the HLVDEN bit

(HLVDCON<4>). Each time the HLVD module is

enabled, the circuitry requires some time to stabilize.

The IRVST bit (HLVDCON<5>) is a read-only bit used

to indicate when the circuit is stable. The module can

only gen erat e an in terrupt after the circui t is s t ab le an d

IRVST is set.

The VDIRMAG bit (HLVDCON<7>) determines the

overall operation of the module. When VDIRMAG is

cleared, the module monitors for drops in VDD below a

predetermined set point. When the bit is set, the

module monitors for rises in VDD above the set point.

23.2 Operation

When the HLVD module is enab led, a co mparat or uses

an internally generated reference voltage as the set

point. The set point is compared with the trip point,

where each node in the resistor divider represents a

trip point voltage. The “trip point” voltage is the voltage

level at which the device detects a high or low-voltage

event, depending on the configuration of the module.

When the supply voltage is equal to the trip point, the

voltage tapped off of the resistor array is equal to the

internal reference voltage generated by the voltage

refe rence mod ule. T he comparat or then ge nerates an

interrupt signal by setting the HLVDIF bit.

The trip point voltage is software programmable to any of

16 values. The trip point is selected by programming the

HLVDL<3:0> b i ts (HLVD C O N < 3 :0> ).

The HLVD mo dule has an add itional f eature tha t allow s

the user to supply the trip voltage to the module from

an external source. This mode is enabled when bits,

HLVDL<3:0>, are set to ‘1111’. In this state, the

comparator input is multiplexed from the external input

pin, H LVDIN. This gi ves users the fl exibi lity of con figur-

ing the High/Low-Voltage Detect interrupt to occur at

any voltage in the valid operating range.

FIGURE 23-1: HLVD MO DULE BLOCK DIAGRAM (WITH EXTERNA L INPUT)

Set

VDD

16-to -1 MUX

HLVDEN

HLVDCON

HLVDL<3:0> Register

HLVDIN

VDD

External ly Gener at ed

Trip Point

HLVDIF

HLVDEN

BOREN Internal Voltage

Reference

VDIRMAG

1.024V Typical

 2010-2012 Microchip Technology Inc. DS41412F- page 351

PIC18(L)F2X/4XK22

23.3 HLVD Setup

To set up the HLVD module:

1. Select the desired HLVD trip point by w ri tin g th e

value to the HLVDL<3:0> bits.

2. Set the VDIRMAG bit to detect high voltage

(VDIRMAG = 1) or low voltage (VDIRMAG = 0).

3. Enable the HLVD module by setting the

HLVDEN bit.

4. Cle ar th e HLVD i nter rupt flag (PIR 2<2> ), whi ch

may have been set from a previous interrupt.

5. If interrupts are desired, enable the HLVD

interrupt by setting the HLVDIE and GIE/GIEH

bits (PIE2<2> and INTCON<7>, respectively).

An interrupt will not be generated until the

IRVST bit is set.

23.4 Current Consumption

When the module is enabled, the HLVD comparator

and voltage divider are enabled and consume static

current. The total current consumption, when enabled,

is specified in Section 27.0 “Electrical Characteris-

tics”. Depe ndi ng on th e application, the H LVD module

does no t n eed to operate const an t ly. To reduce curre nt

requirements, the HLVD circuitry may only need to be

enabled for short periods where the voltage is checked.

After such a check, the module could be disabled.

23.5 HLVD Start-up Time

The internal reference voltage of the HLVD module,

specified in Section 27.0 “Electrical

Characteristics”, may be used by other internal

circuitry, such as the programmable Brown-out Reset.

If the H L VD or othe r circuit s using the vo ltage refere nce

are di sabled to lower th e device’ s current con sumption,

the referen ce voltag e circuit will require time to become

stable before a low or high-voltage condition can be

reliably detected. This start-up time, TIRVST, is an

interval that is independent of device clock speed.

The HLVD interrupt flag is not enabl ed u nti l TIRVST has

expired and a stable reference voltage is reached. For

this reason, brief excursions beyond the set point may

not be detec ted du ring this inter val (see Figure 23-2 or

Figure 23-3).

FIGURE 23-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)

Note: Before changing any module settings

(VDIRMAG, HLVDL<3:0>), first disable the

module (HLVDEN = 0), m ake the chang es

and re-enable the module. This prevents

the generation of false HLVD events.

VHLVD

VDD

HLVDIF

VHLVD

VDD

Enable HLVD

TIRVST

HLVDI F m ay n ot b e se t

Enable HLVD

HLVDIF

HLVDIF cleared in software

HLVDIF cleared in software,

CASE 1:

CASE 2:

HLVDIF remains set since HLVD condition still exists

TIRVST

Internal Reference is stable

IRVST

PIC18(L)F2X/4XK22

DS41412F-page 352  2010-2012 Microchip Technology Inc.

FIGURE 23-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)

23.6 Applications

In many applications, it is desirable to detect a drop

below, or rise above, a p articular v oltage threshold . For

example, the HLVD module could be periodically

enabled to de tec t U nivers al Seria l Bus (USB) attach or

det ach. This a ssumes the dev ice is powered by a lower

voltage source than the USB when detached. An att ach

would indicate a h igh-volt a ge dete ct from, fo r exam ple,

3.3V to 5V (the voltage on USB) and vice versa for a

detach. This feature could save a design a few extra

components and an attach signal (input pin).

For general battery applications, Figure 23-4 shows a

possible voltage curve. Over time, the device voltage

decreases. When the device voltage reaches voltage

VA, the HLVD logic generates an interrupt at time, TA.

The interrupt could cause the execution of an ISR,

which would allow the application to perform “house-

keeping tasks” and a controlled shutdown before the

device voltage exits the valid operating range at TB.

This would give the application a time window,

represented by the difference between TA and TB, to

safely exit.

FIGURE 23-4: TYPICAL LOW-VOLTAGE

DETECT APPLICATION

VHLVD

VDD

HLVDIF

VHLVD

VDD

Enable HLVD

TIRVST

HLVDIF may not be set

Enable HLVD

HLVDIF

HLVDIF cleared in software

HLVDIF cleared in software,

CASE 1:

CASE 2:

HLVDIF remains set since HLVD condition still exists

TIRVST

IRVST

Internal Reference is stable

IRVST

Time

Voltage

TATB

VA = HLVD trip point

VB = Minimum valid device

operating voltage

Legend:

 2010-2012 Microchip Technology Inc. DS41412F- page 353

PIC18(L)F2X/4XK22

23.7 Operation During Sleep

When en abled, the HLVD circuit ry contin ues to op erate

during Sleep. If the device voltage crosses the trip

point, the HLVDIF bit will be set and the device will

wake-up from Sleep. Device execution will continue

from the interrupt vector address if interrupts have

been globally enabled.

23.8 Effects of a Reset

A device Reset forces all registers to their Reset state.

This forces the HLVD module to be turned off.

TABLE 23-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0> 349

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116

IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129

PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125

PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 156

Legend: — = unimp lemented locations , read as ‘0’. Shaded bits are unused by the HLVD module.

PIC18(L)F2X/4XK22

DS41412F-page 354  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 355

PIC18(L)F2X/4XK22

24.0 SPECIAL FEATURES OF

THE CPU

PIC18(L)F2X/4XK22 devices include several features

intended to maximize reliability and minimize cost through

elimination of external components. These are:

• Oscillator Selection

• Resets:

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Code Protection

• ID Locations

• In-Circuit Serial Programming™

The oscillator can be configured for the application

dependi ng on frequ ency, power, accuracy and cost . All

of the options are discussed in detail in Section 2.0

“Oscillator M odule (W ith Fai l-Safe Clock Monitor)” .

A complete discussion of device Resets and interrupts

is avail able in previous sections of this data sheet.

In addition to their Power-up and Oscillator Start-up

Timers provided for Resets, PIC18(L)F2X/4XK22

devices have a Watchdog Timer, which is either

permanently enabled via the Configuration bits or

software co ntrolled (if configured a s disabl ed).

The inclu si on of an in tern al R C osc ill ato r also prov ide s

the additional benefits of a Fail-Safe Clock Monitor

(FSCM) and Two-Speed Start-up. FSCM provides for

background monitoring of the peripheral clock and

automatic switchover in the event of its failure. Two-

Speed Start-up enables code to be executed almost

immed iately on s tart-up, while t he primary c lock sourc e

completes its start-up delays.

All of these features are enabled and configured by

setting the appropriate Configuration register bits.

24.1 Configurati on Bits

The Configuration bits can be programmed (read as

‘0’) or lef t unprog rammed ( read as ‘ 1’) to se lect various

device configurations. These bits are mapped starting

at program memory location 300000h.

The user will note that address 300000h is beyond the

user program memory space. In fact, it belongs to the

configuration memory space (300000h-3FFFFFh), which

can only be accessed using table reads and table writes.

Programming the Configuration registers is done in a

manner s imilar t o programmin g the Flas h memo ry. The

WR bit in the EECON1 register starts a self-timed write

to the Configuration register. In Normal operation

mode, a TBLWT instr uction with the TBLPTR pointi ng to

the Configuration register sets up the address and the

data f or the Configuration register write . Setting the WR

bit starts a long write to the Configuration register. The

Conf igu rati on regis ter s a re writ ten a by te a t a ti me. To

write or erase a configuration cell, a TBLWT instru cti on

can writ e a ‘1’ or a ‘0’ i nto the cell. For addi tional d etail s

on Flash programming, refer to Section 6.6 “Writing

to Flash Program Memory”.

PIC18(L)F2X/4XK22

DS41412F-page 356  2010-2012 Microchip Technology Inc.

TABLE 24-1: CONFIGURATION BITS AND DEVICE IDs

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/

Unprogramme d

Value

300000h CONFIG1L — — — — — — — — 0000 0000

300001h CONFIG1H IESO FCMEN PRICLKEN PLLCFG FOSC<3:0> 0010 0101

300002h CONFIG2L — — — BORV<1:0> BOREN<1:0> PWRTEN 0001 1111

300003h CONFIG2H —— WDPS<3:0> WDTEN<1:0> 0011 1111

300004h CONFIG3L — — — — — — — — 0000 0000

300005h CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 1011 1111

300006h CONFIG4L DEBUG XINST — — —LVP

(1) — STRVEN 1000 0101

300007h CONFIG4H — — — — — — — — 1111 1111

300008h CONFIG5L — — — —CP3

(2) CP2(2) CP1 CP0 0000 1111

300009h CONFIG5H CPD CPB — — — — — — 1100 0000

30000Ah CONFIG6L — — — —WRT3

(2) WRT2(2) WRT1 WRT0 0000 1111

30000Bh CONFIG6H WRTD WRTB WRTC(3) — — — — — 1110 0000

30000Ch CONFIG7L — — — —EBTR3

(2) EBTR2(2) EBTR1 EBTR0 0000 1111

30000Dh CONFIG7H —EBTRB — — — — — — 0100 0000

3FFFFEh DEVID1(4) DEV<2:0> REV<4:0> qqqq qqqq

3FFFFFh DEVID2(4) DEV<10:3> 0101 qqqq

Legend: – = unimplemented, q = value depends on condit ion. Shaded bits are unimplemented, read as '0'.

Note 1: Can only be changed when in high voltage programming mode.

2: Ava ilable on PIC18(L)FX5K22 an d PIC18(L)FX6K22 devices only.

3: In user mode, this bit is rea d-only and cannot be self-programmed.

4: See Register 24-12 and Register 24-13 for DEVID values . DEVID registers are read-only and cannot be programmed by the

user.

 2010-2012 Microchip Technology Inc. DS41412F- page 357

PIC18(L)F2X/4XK22

24.2 Register Defini tions: Configuration Word

R/P-0 R/P-0 R/P-1 R/P-0 R/P-0 R/P-1 R/P-0 R/P-1

IESO FCMEN PRICLKEN PLLCFG FOSC<3:0>

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed x = Bit is unknown

bit 7 IESO(1): Internal/External Oscillator Switchover bit

1 = Oscill ator Switchover mode enabled

0 = Oscillator Switchover mode disabled

bit 6 FCMEN(1): Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Cloc k Mo nito r enabl ed

0 = Fail-Safe Cloc k Mo nito r disa bled

bit 5 PRICLKEN: Pr imary Clock E nable bit

1 = Primary Clock is always enabled

0 = Primary Clock can be disabled by software

bit 4 PLLCFG: 4 x PLL Enable bit

1 = 4 x PLL always enabled, Oscillator multiplied by 4

0 = 4 x PLL is under software control, PLLEN (OSCTUNE<6>)

bit 3-0 FOSC<3:0>: Oscillator Selection bits

1111 = External RC oscillator, CLKOUT function on RA6

1110 = External RC oscillator, CLKOUT function on RA6

1101 = EC oscillator (low power, <500 kHz)

1100 = EC oscilla tor, CLKOUT function on OSC2 (low power, <500 kHz)

1011 = EC oscillator (medium power, 500 kHz-16 MHz)

1010 = EC oscillator, CLKOUT function on OSC2 (medium power, 500 kHz-16 MHz)

1001 = Internal oscillator block, CLKOUT function on OSC2

1000 = Internal oscillator block

0111 = External RC oscillator

0110 = External RC oscillator, CLKOUT function on OSC2

0101 = EC oscillator (high power, >16 MHz)

0100 = EC oscilla tor, CLKOUT function on OSC2 (high power, >16 MHz)

0011= HS oscillator (medium power, 4 MHz-16 MHz)

0010= HS oscillator (high power, >16 MHz)

0001= XT oscillator

0000= LP oscillator

Note 1: When FOSC<3:0> is configured for HS, XT, or LP oscillator and FCMEN bit is set, then the IESO bit

should also be set to pr event a fa lse failed clo ck indica tion and to en able autom atic cloc k switch over from

the internal oscillator block to the external oscillator when the OST times out.

PIC18(L)F2X/4XK22

DS41412F-page 358  2010-2012 Microchip Technology Inc.

U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

— — —BORV<1:0>

(1) BOREN<1:0>(2) PWRTEN(2)

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1)

11 = VBOR set to 1.9V nominal

10 = VBOR set to 2.2V nominal

01 = VBOR set to 2.5V nominal

00 = VBOR set to 2.85V nominal

bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits(2)

11 = Brown-out Reset enabled in hardware only (SBOREN is disabled)

10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode

(SBOREN is disabled)

01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled)

00 = Brown-out Reset disabled in hardware and software

bit 0 PWRTEN: Power-up Timer Enable bit(2)

1 = PWRT disabled

0 = PWRT enabled

Note 1: See Section 27.1 “DC Characteristics: Supply Voltage, PIC18(L)F2X/4XK22” for specifications.

2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled.

 2010-2012 Microchip Technology Inc. DS41412F- page 359

PIC18(L)F2X/4XK22

U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

— — WDTPS<3:0> WDTEN<1:0>

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-2 WDTPS<3:0>: Watchdog Timer Postscale Select bits

1111 = 1:32,768

1110 = 1:16,384

1101 = 1:8,192

1100 = 1:4,096

1011 = 1:2,048

1010 = 1:1,024

1001 = 1:512

1000 = 1:256

0111 = 1:128

0110 = 1:64

0101 = 1:32

0100 = 1:16

0011 = 1:8

0010 = 1:4

0001 = 1:2

0000 = 1:1

bit 1-0 WDTEN<1:0>: Watchdog Timer Enable bits

11 = WDT enabled in hardware; SWDTEN bit disabled

10 = WDT controlled by the SWD TEN bit

01 = WDT enabled when device is active, disabled when device is in Sleep; SWDTEN bit disabled

00 = WDT disabled in hardware; SWDTEN bit disabled

PIC18(L)F2X/4XK22

DS41412F-page 360  2010-2012 Microchip Technology Inc.

R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

MCLRE —P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed x = Bit is unknown

bit 7 MCLRE: MCLR Pin Enable bit

1 = MCLR pin enabled; RE3 inpu t pin disabled

0 = RE3 input pin enable d; MCLR dis ab led

bit 6 Unimplemented: Read as ‘0’

bit 5 P2BMX: P2B Input MUX bit

1 = P2B is on RB5(1)

P2B is on RD2(2)

0 = P2B is on RC0

bit 4 T3CMX: Timer3 Clock Input MUX bit

1 = T3CKI is on RC0

0 = T3CKI is on RB5

bit 3 HFOFST: HFINTOSC Fast Start-up bit

1 = HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize

0 = The system clock is held off until the HFINTOSC is stable

bit 2 CCP3MX: CCP3 MUX bit

1 = CCP3 inpu t/output is multiplexed with RB5

0 = CCP3 inpu t/output is multiplexed with RC6(1)

CCP3 input/output is multiplexed with RE0(2)

bit 1 PBADEN: PORTB A/D Enable bit

1 = ANSELB<5:0> resets to 1, PORTB<5:0> pins are configured as analog inputs on Reset

0 = ANSELB<5:0> resets to 0, PORTB<4:0> pins are configured as digital I/O on Reset

bit 0 CCP2MX: CCP2 MUX bit

1 = CCP2 inpu t/output is multiplexed with RC1

0 = CCP2 inpu t/output is multiplexed with RB3

Note 1: PIC18(L)F2XK22 devices only.

2: PIC18(L)F4XK22 devices only.

 2010-2012 Microchip Technology Inc. DS41412F- page 361

PIC18(L)F2X/4XK22

R/P-1 R/P-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1

DEBUG(2) XINST — — —LVP

(1) —STVREN

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Va lue when device is unprogrammed x = Bit is unknown

bit 7 DEBUG: Background Debugger Enable bit(2)

1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins

0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug

bit 6 XINST: Extended Instruction Set Enable bit

1 = Instruction set extension and Indexed Addressing mode enabled

0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)

bit 5-3 Unimplemented: Read as ‘0’

bit 2 LVP: Single-S upply ICS P Enable bit

1 = Single-Supply ICSP enabled

0 = Single-Supply ICSP disabled

bit 1 Unimplemented: Read as ‘0’

bit 0 STVREN: Stack Full/Underflow Reset Enable bit

1 = Stack full/underflow will cause Reset

0 = Stack full/underflow will not cause Reset

Note 1: Can only be changed by a programmer in high-voltage programming mode.

2: The DEBUG bit is managed automatically by device development tools including debuggers and programmers. For

normal device operations, this bit should be maintained as a ‘1’.

U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1

— — — —CP3

(1) CP2(1) CP1 CP0

bit 7 bit 0

Legend:

R = Readable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed C = Clearable only bit

bit 7-4 Unimplemented: Read as ‘0’

bit 3 CP3: Code Protection bit(1)

1 = Block 3 not code-protected

0 = Block 3 code-protected

bit 2 CP2: Code Protection bit(1)

1 = Block 2 not code-protected

0 = Block 2 code-protected

bit 1 CP1: Code Protection bit

1 = Block 1 not code-protected

0 = Block 1 code-protected

bit 0 CP0: Code Protection bit

1 = Block 0 not code-protected

0 = Block 0 code-protected

Note 1: Available on PIC18(L)FX5K22 and PIC18(L)FX6K22 devices.

PIC18(L)F2X/4XK22

DS41412F-page 362  2010-2012 Microchip Technology Inc.

R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0

CPD CPB — — — — — —

bit 7 bit 0

Legend:

R = Readable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed C = Clearable only bit

bit 7 CPD: Data EEPROM Code Protection bit

1 = Data EEPROM not code-protected

0 = Data EEPROM code-protected

bit 6 CPB: Boot Block Code Protection bit

1 = Boot Block not code-protected

0 = Boot Block code-protected

bit 5-0 Unimplemented: Read as ‘0’

U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1

— — — —WRT3

(1) WRT2(1) WRT1 WRT0

bit 7 bit 0

Legend:

R = Readable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed C = Clearable only bit

bit 7-4 Unimplemented: Read as ‘0’

bit 3 WRT3: Write Protection bit(1)

1 = Block 3 not write-protected

0 = Block 3 write-protected

bit 2 WRT2: Write Protection bit(1)

1 = Block 2 not write-protected

0 = Block 2 write-protected

bit 1 WRT1: Write Protection bit

1 = Block 1 not write-protected

0 = Block 1 write-protected

bit 0 WRT0: Write Protection bit

1 = Block 0 not write-protected

0 = Block 0 write-protected

Note 1: Available on PIC18(L)FX5K22 and PIC18(L)FX6K22 devices.

 2010-2012 Microchip Technology Inc. DS41412F- page 363

PIC18(L)F2X/4XK22

R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0

WRTD WRTB WRTC(1) — — — — —

bit 7 bit 0

Legend:

R = Readable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed C = Clearable only bit

bit 7 WRTD: Data EEPROM Write Protection bit

1 = Data EEPROM not write-protected

0 = Data EEPROM write-protected

bit 6 WRTB: Boot Block Write Protection bit

1 = Boot Bloc k not write-protect ed

0 = Boot Block write-protected

bit 5 WRTC: Configuration Register Write Protection bit(1)

1 = Configuration registers not write-protected

0 = Conf iguration registers wr ite- prot ected

bit 4-0 Unimplemented: Read as ‘0’

Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.

U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1

— — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0

bit 7 bit 0

Legend:

R = Readable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed C = Clearable only bit

bit 7-4 Unimplemented: Read as ‘0’

bit 3 EBTR3: Table Read Protection bit(1)

1 = Block 3 not protected from table reads executed in other blocks

0 = Block 3 protected from table reads executed in other blocks

bit 2 EBTR2: Table Read Protection bit(1)

1 = Block 2 not protected from table reads executed in other blocks

0 = Block 2 protected from table reads executed in other blocks

bit 1 EBTR1: Table Read Protection bit

1 = Block 1 not protected from table reads executed in other blocks

0 = Block 1 protected from table reads executed in other blocks

bit 0 EBTR0: Table Read Protection bit

1 = Block 0 not protected from table reads executed in other blocks

0 = Block 0 protected from table reads executed in other blocks

Note 1: Available on PIC18(L)FX5K22 and PIC18(L)FX6K22 devices.

PIC18(L)F2X/4XK22

DS41412F-page 364  2010-2012 Microchip Technology Inc.

U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0

— EBTRB — — — — — —

bit 7 bit 0

Legend:

R = Readable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed C = Clearable only bit

bit 7 Unimplemented: Read as ‘0’

bit 6 EBTRB: Boot Block Table Read Protection bit

1 = Boot Block not protected from table reads executed in other blocks

0 = Boot Block protected from table reads executed in other blocks

bit 5-0 Unimplemented: Read as ‘0’

RRRRRRRR

DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0

bit 7 bit 0

Legend:

R = Readable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed C = Clearable only bit

bit 7-5 DEV<2:0>: Device ID bits

These bits, together with DEV<10:3> in DEVID2, determine the device ID.

See Table 24-2 for complete Device ID list.

bit 4-0 REV<4:0>: Revision ID bits

These bi ts indicate the device revision.

RRRRRRRR

DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3

bit 7 bit 0

Legend:

R = Readable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed C = Clearable only bit

bit 7-0 DEV<10:3>: Device ID bits

These bits, together with DEV<2:0> in DEVID1, determine the device ID.

See Table 24-2 for complete Device ID list.

 2010-2012 Microchip Technology Inc. DS41412F- page 365

PIC18(L)F2X/4XK22

TABLE 24-2: DEVICE ID TABLE FOR THE PIC18(L)F2X/4XK22 FAMILY

DEV<10:3> DEV<2:0> Part Number

0101 0100

000 PIC18F46K22

001 PIC18LF46K22

010 PIC18F26K22

011 PIC18LF26K22

0101 0101

000 PIC18F45K22

001 PIC18LF45K22

010 PIC18F25K22

011 PIC18LF25K22

0101 0110

000 PIC18F44K22

001 PIC18LF44K22

010 PIC18F24K22

011 PIC18LF24K22

0101 0111

000 PIC18F43K22

001 PIC18LF43K22

010 PIC18F23K22

011 PIC18LF23K22

PIC18(L)F2X/4XK22

DS41412F-page 366  2010-2012 Microchip Technology Inc.

24.3 Watchdog Timer (WDT)

For PIC18(L)F2X/4XK22 devices, the WDT is driven by

the LFINTOSC source. When the WDT is enabled, the

clock s ourc e is a ls o e nab le d. The nominal WD T p erio d

is 4 ms and has the same stability as the LFINTOSC

oscillator.

The 4 ms period of the WDT is multiplied by a 16-bit

postscaler. Any output of the WDT postscaler is

selected by a multiplexer , controlled by bits in Configu-

ration Register 2H. Av ailable periods range from 4 ms

to 131.072 seconds (2.18 minutes). The WDT and

post scaler are cleare d when any of the following events

occur: a SLEEP or CLRWDT instruction is executed, the

IRCF bits of the OSCCON register are changed or a

clock failure has occurr ed.

FIGURE 24-1: WDT BLOCK DIAGRAM

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and postscaler counts

when execute d.

2: Changing the setting of the IRCF bits of

the OSCCON register clears the WDT

and postscaler counts.

3: When a CLRWDT instruction is executed,

the postscaler count will be cleared.

LFINTOSC Source

WDT

Wake-up

Reset

WDT Counter

Progra mmable P ostscaler

1:1 to 1:32,768

Enable WDT

WDTPS<3:0>

SWDTEN

WDTEN

CLRWDT

from Power

Reset

All Device Resets

Sleep

128

Change on IRCF bits Managed Modes

 2010-2012 Microchip Technology Inc. DS41412F- page 367

PIC18(L)F2X/4XK22

24.3.1 CONTROL REGISTER

readable and writable regis te r whic h co nt ains a control

bit that allows software to override the WDT enable

Configuration bit, but only if the Configuration bit has

disabled the WDT.

24.4 Regist e r D e finition s : WDT C o nt rol

TABLE 24-4: CONFIGURATION REGISTERS ASSOCIATED WITH WATCHDOG TIMER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —SWDTEN

(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 Unimplemented: Read as ‘0’

bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer bit(1)

1 = WDT is turned on

0 = WDT is turned off (Reset value)

Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.

TABLE 24-3: REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on Page

RCON IPEN SBOREN —RI TO PD POR BOR 60

WDTCON ———————SWDTEN367

Legend: — = unimplemented, read as ‘0’. Shaded bits are not used by the Watchdog Timer.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on Page

CONFIG2H — — WDPS<3:0> WDTEN<1:0> 359

Legend: — = unimplemented, read as ‘0’. Shaded bits are not used by the Watchdog Timer.

PIC18(L)F2X/4XK22

DS41412F-page 368  2010-2012 Microchip Technology Inc.

24.5 Program Verification and

Code Protection

The overall structure of the code protection on the

PIC18 Flash devices differs significantly from other

PIC® microcontroller device s.

The user program memory is divided into three or five

blocks, depending on the device. One of these is a

Boot Block of 0.5K or 2K bytes, depending on the

device. The remainder of the memory is divided into

individual blocks on binary boundaries.

Each of t he b locks h as three c ode p rotecti on bit s a sso-

ciated with them. They are:

• Code-Protect bit (CPn)

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 24-2 shows the program memory organization

for 8, 16 and 32-Kbyte devices and the specific code

protection bit associated with each block. The actual

locations of the bits are summarized in Table 24-5.

FIGURE 24-2: CODE-P ROTECTE D PROGRAM MEMORY FOR PIC18(L)F2X/4XK22

MEMORY SIZE/DEVICE Bloc k Code Protection

Controlled By:

8Kbytes

(PIC18(L)FX3K22) 16 Kbytes

(PIC18(L)FX4K22) 32 Kbytes

(PIC18(L)FX5K22) 64 Kbytes

(PIC18(L)FX6K22)

Boot Block

(000h-1FFh) Boot Bloc k

(000h-7FFh) Boot Bloc k

(000h-7FFh) Boot Block

(000h-7FFh) CPB, WRTB, EBTRB

Block 0

(200h-FFFh) Block 0

(800h-1FFFh) Block 0

(800h-3FFFh) CP0, WRT0, EBTR0

Block 1

(1000h-1FFFh) Block 1

(2000h-3FFFh) Block 1

(4000h-7FFFh) CP1, WRT1, EBTR1

Unimplemented

Read ‘0’s

(2000h-1FFFFFh)

Unimplemented

Read ‘0’s

(4000h-1FFFFFh)

Block 2

(4000h-5FFFh) Block 2

(8000h-BFFFh) CP2, WRT2, EBTR2

Block 3

(6000h-7FFFh) Block 3

(C000h-FFFFh) CP3, WRT3, EBTR3

Unimplemented

Read ‘0’s

(8000h-1FFFFFh)

Unimplemented

Read ‘0’s

(10000h-1FFFFFh)

(Unimplemented

Memory Space)

TABLE 24-5: CONFIGURATION REGISTERS ASSOCIATED WITH CODE PROTECTION

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

300008h CONFIG5L — — — —CP3

(1) CP2(1) CP1 CP0

300009h CONFIG5H CPD CPB — — — — — —

30000Ah CONFIG6L — — — —WRT3

(1) WRT2(1) WRT1 WRT0

30000Bh CONFIG6H WRTD WRTB WRTC(2) — — — — —

30000Ch CONFIG7L — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0

30000Dh CONFIG7H — EBTRB — — — — — —

Legend: Shaded bits are unimplemented.

Note 1: Av ailable on PIC18(L)FX5K22 and PIC18(L)FX6K22 devices only.

2: In user mode, this bit is read-only and cannot be self-programmed.

 2010-2012 Microchip Technology Inc. DS41412F- page 369

PIC18(L)F2X/4XK22

24.5.1 PROGRAM MEMORY

CODE PROTECTION

The program memory may be read to or written from

any location using the table read and table write

instructions. The device ID may be read with table

reads. The Configuration registers may be read and

written with the table read and table write instructions.

In Normal execution mode, the CPn bits have no direct

ef fect. CPn bits inhi bit external reads and writes. A block

of user memory may be protected fro m table writes if the

WRTn Configuration bit is ‘0’. The EBTRn bits control

table reads. Fo r a block of u ser memory with the EBTRn

bit cleared to ‘0’, a table READ instruction that executes

from within that block is allowed to read. A table read

instruction that executes from a location outside of that

block is not allowed to read and will res ult in reading ‘0’s.

Figures 24-3 through 24-5 illustrate table write and t able

read protection.

FIGURE 24-3: TABLE WRITE (WRTn) DISALLOWED

Note: Code protection bits may only be written

to a ‘0’ from a ‘1’ s tate . It is not p ossib le to

write a ‘1’ to a bit in the ‘0’ state. Code pro-

tection b its are only set to ‘1’ b y a full chip

erase or block erase function. The full chip

erase and block erase functions can only

be initiated via ICSP™ or an external

programmer.

000000h

0007FFh

000800h

001FFFh

002000h

003FFFh

004000h

005FFFh

006000h

007FFFh

WRTB, EBTRB = 11

WRT0, EBTR0 = 01

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLWT*

TBLPTR = 0008FFh

PC = 001FFEh

TBLWT*

PC = 005FFEh

Results: All table writes disabled to Blockn whenever WRTn = 0.

PIC18(L)F2X/4XK22

DS41412F-page 370  2010-2012 Microchip Technology Inc.

FIGURE 24-4: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED

FIGURE 24-5: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED

WRTB, EBTRB = 11

WRT0, EBTR0 = 10

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLRD*

TBLPTR = 0008FFh

PC = 003FFEh

Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.

TABLAT register returns a value of ‘0’.

000000h

0007FFh

000800h

001FFFh

002000h

003FFFh

004000h

005FFFh

006000h

007FFFh

WR TB, EBTRB = 11

WRT0, EBTR0 = 10

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLRD*

TBLPTR = 0008FFh

PC = 001FFEh

Results: Table reads permitt ed wi thi n Bloc kn, even when EBTRBn = 0.

TABLAT register returns the value of the data at the location TBLPTR.

000000h

0007FFh

000800h

001FFFh

002000h

003FFFh

004000h

005FFFh

006000h

007FFFh

 2010-2012 Microchip Technology Inc. DS41412F- page 371

PIC18(L)F2X/4XK22

24.5.2 DATA EEPROM

CODE PROTECTION

The entire data EEPROM is protected from external

reads and writes by two bits: CPD and WRTD. CPD

inhibits external reads and writes of data EEPROM.

WRTD inhibits internal and external writes to data

EEPROM. The CPU can always read data EEPROM

under n ormal op eration, re gardless o f the prot ection bit

settings.

24.5.3 CONFIGURATION REGISTER

PROTECTION

The Configuration registers can be write-protected.

The WRTC bit controls protection of the Configuration

registers. In Normal execution mode, the WRTC bit is

readable only. WRTC can only be written via ICSP or

an external programmer.

24.6 ID Locations

Eight memory locations (200000h-200007h) are

designated as ID locations, where the user can store

checksum or other code identification numbers. These

locatio ns are b oth read abl e and writable d urin g no rmal

execution through the TBLRD and TBLWT instructions

or du r ing p r ogr am / ver if y. Th e I D lo ca tio n s c a n b e re ad

when the device is code-protected.

24.7 In-Circuit Serial Progra mming

PIC18(L)F2X/4XK22 devices can be serially

progra mmed w hile in t he en d app licati on c ircuit. This is

simply done with tw o lines for cl ock and dat a and thre e

other lines for power, ground and the programming

voltage. This allow s customers to manufacture boards

with unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

24.8 In-Circuit Debugger

When the DEBUG Configuration bit is programmed to

a ‘0’, the In-Circuit Debugger functionality is enabled.

This funct ion al lows s imple debug ging f unct ions wh en

use d wi t h M PLA B® IDE. When the microcontroller has

this featu r e ena ble d, so me reso urc es are not available

for gene ral us e. Table 24-6 shows which resources are

required by the background debugger.

TABLE 24-6: DEBUGGER RESOURCES

To use the In-Circuit Debugger function of the

microcontroller, the design must implement In-Circuit

Serial Programming co nnections to the following p ins:

•MCLR

/VPP/RE3

•V

•VSS

•RB7

•RB6

This will interface to the In-Circuit Debugger module

available from Microchip or one of the third party

development tool compan ies .

24.9 Single-Supply ICSP Programming

The LV P Configuration bit enables Single-Supply ICSP

Programming (formerly known as Low-Voltage ICSP

Programming or LVP). When Single-Supply Program-

ming is enabled, the microcontroller can be programmed

without requiring high voltage being applied to the

MCLR/VPP/RE3 pin. See “PIC18(L)F2XK22/4XK22

Flash Memory Programming” (DS41398) for more

details about low vol t age programm ing.

The LVP bit may be set or cleared only when using

standard high-voltage programming (VIHH applied to

the MC LR/VPP/RE3 pin). Once L VP has been disabled,

only the standard high-voltage programming is

available and must be used to program the device.

Memory tha t is not code -protected ca n be erased usin g

either a b lock erase, or erased ro w by row, then writte n

at any s pecified VDD. If co de-protected m emory is to be

erased, a block erase is required.

I/O pins: RB6 , RB7

Note 1: High-voltage programming is always

available, regardless of the state of the

LVP bit, by applying VIHH to the MCLR

pin.

2: By default, Single-Supply ICSP is

enabled in unprogrammed devices (as

supplied from Microchip) and erased

devices.

3: While in Low -Voltage ICSP mo de, MCLR

is always enabled, regardless of the

MCLRE bit, and the RE3 pin can no

longer be used as a general purpose

input.

PIC18(L)F2X/4XK22

DS41412F-page 372  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 373

PIC18(L)F2X/4XK22

25.0 INSTRUCTION SET SUMMARY

PIC18(L)F2X/4XK22 devices incorporate the standard

set of 75 PIC18 core instructions, as well as an extended

set of eight new instructions, for the optimiz ation of code

that is recursive or that utilizes a software stack. The

extended set is discu ssed la te r in this sec tion.

25.1 Standard Instruction Set

The standard PIC18 instruction set adds many

enhancements to the previous PIC® MCU instruction

sets, while maintaining an easy migration from these

PIC® MCU instruction sets. Most instructions are a

single program memory word (16 bits), but there are

four instructions that require two program memory

locations.

Each single-word instruction is a 16-bit word divided

into an o pcode, whi ch specifies the instructi on type and

one or more operands, which further specify the

operation of the instruction.

The instruction set is highly orthogonal and is grouped

into four basic categories:

•Byte-oriented operations

•Bit-oriented operations

•Literal operati ons

•Control operations

The PIC18 instruction set summary in Table 25-2 lists

byte-oriented, bit-oriented, literal and control

operations. Table 25-1 shows the opcode field

descriptions.

Most byte-oriented in str uct ions have three operands:

1. The file register (specified by ‘f’)

2. The destination of the result (specified by ‘d’)

3. The accessed memory ( specified by ‘a’)

The file register designator ‘f’ specifies which file

designator ‘d’ specifies where the result of the opera-

tion is to be placed. If ‘d’ is zero, the result is placed in

the WREG register. If ‘d’ is one, the result is placed in

the file register specified in the instruction.

All bit-oriented instructions have three operands:

1. The file register (specified by ‘f’)

2. The bit in the file register (specified by ‘b’)

3. The accessed memory ( specified by ‘a’)

The bit field design ator ‘b’ sele cts the numb er of the bit

affected by the operation, while the file register

design ator ‘f’ represent s the numbe r of the fil e in w hich

the bit is located.

The literal ins truc tions may use so me of the follo wing

operands:

• A literal value to be loaded into a file register

(specified by ‘k’)

• The desired FSR register to load the literal value

into (specified by ‘f’)

• No operand requir ed

(specified by ‘—’)

The control ins tructions may use so me of the f ollowing

operands:

• A program memory address (specified by ‘n’)

• The mode of the CALL or RETURN instructions

(specified by ‘s’)

• The mode of the table read and table write

ins tructions (specified by ‘m’)

• No operand requir ed

(specified by ‘—’)

All instructions are a single word, except for four

double-word instructions. These instructions were

made double-word to contain the required information

in 32 bit s. In the secon d word, the four MSbs are ‘1’s. If

this second word is executed as an instruction (by

it se lf), it will exe cu te as a NOP.

All single-word instructions are executed in a single

inst ruct ion c yc le , un le ss a conditional test is true or th e

program counter is changed as a result of the instruc-

tion. In th ese cases, the execution takes tw o instruction

cycle s, with the addit ional instru ction cyc le(s) exec uted

as a NOP.

The double-word instructions execute in two instruction

cycles.

One in struction cycle consist s of f our oscil lator p eriods.

Thus, for an oscillator frequency of 4 MHz, the normal

inst ruction ex ecution ti me is 1 s. If a cond itional tes t is

true, or the program counter is changed as a result of

an instruction, the instruction execution time is 2 s.

Two-word branch instructions (if true) would take 3 s.

Figure 25-1 show s the gener al format s that the instruc-

tion s can hav e. All exampl es use the conv ention ‘nnh’

to represent a hexadecimal number.

The Instruction Set Summary, shown in Table 25-2,

lists the standard instructions recognized by the

Microchip Assembler (MPASMTM).

Section 25.1.1 “Standard Instruction Set” provides

a description of each instruction.

PIC18(L)F2X/4XK22

DS41412F-page 374  2010-2012 Microchip Technology Inc.

TABLE 25-1: OPCODE FIELD DESCRIPTIONS

Field Description

aRAM access bit

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb Bit address within an 8-bit file register (0 to 7).

BSR Bank Select Register. Used to select the current RAM bank.

C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.

dDestination select bit

d = 0: store result in WREG

d = 1: store result in file register f

dest Destination: either the WREG register or the specified register file location.

f8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).

fs12-bit Register file address (000h to FFFh). This is the source address.

fd12-bit Register file address (000h to FFFh). This is the destination address.

GIE Global Interrupt Enable bit.

kLiteral field, constant data or lab el (may be either an 8-bit, 12-bit or a 20-bit value).

label Label name.

mm The mode of the TBLPTR register for the table read and table write instructions.

Only used with table read and table write instructions:

*No change to register (such as TBLPTR with table reads and writes)

*+ Post-Increment register (suc h as TBLPTR with table reads and writes)

*- Post-Decremen t register (such as TBLPTR with table reads and writes)

+* Pre-Increment register (such as TBLPTR with table reads and writes)

nThe relative address (2’s complement number) for relative branch instructions or the direct address for

CALL/BRANCH and RETURN instructions.

PC Program Counter.

PCL Program Counter Low Byte.

PCH Program Counter High Byte.

PCLATH Program Counter High Byte Latch.

PCLATU Program Counter Upper Byte Latch.

PD Power-down bit.

PRODH Product of Multiply High Byte.

PRODL Product of Multiply Low Byte.

sFast Call/Return mode select bit

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

TBLPTR 21-bit Table Pointer (points to a Program Memory location).

TABLAT 8-bit Table Latch.

TO Time-out bit.

TOS Top-of-Stack.

uUnused or unchanged.

WDT Watchdog Tim er.

WREG Working register (accumulator).

xDon’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for

compatibility with all Microchip software tools.

zs7-bit offset value for indirect addressing of register files (source).

zd7-bit offset value for indirect addressing of register files (destination).

{ } O ptional argumen t.

[text] Indicates an indexed address.

(text) The contents of text.

[expr]<n> Spec ifies bit n of the register indicated by the pointer expr.

Assigned to.

< > Register bit field.

In the set of.

italics User defined term (font is Courier).

 2010-2012 Microchip Technology Inc. DS41412F- page 375

PIC18(L)F2X/4XK22

FIGURE 25-1: GENE RAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

15 10 9 8 7 0

d = 0 for result destination to be WREG register

OPCODE d a f (FILE #)

d = 1 for result destina tion to be file register (f)

a = 0 to force Access Bank

Bit-oriented file register operations

15 12 11 9 8 7 0

OPCODE b (BIT #) a f (FILE #)

b = 3-bit position of bit in file register (f)

Literal operations

15 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Byte to Byte move operations (2-word)

15 12 11 0

OPCODE f (Source FILE #)

CALL, GOTO and Branch operations

15 8 7 0

OPCODE n<7:0> (literal)

n = 20-bit immediate value

a = 1 for BSR to select bank

f = 8-bit file register address

a = 0 to force Acce ss Bank

a = 1 for BSR to select bank

f = 8-bit file register address

15 12 11 0

1111 n<19:8> (literal)

15 12 11 0

1111 f (Destin a tion FILE #)

f = 12-bit file register address

Control operations

Example Instruction

ADDWF MYREG, W, B

MOVFF MYREG1, MYREG2

BSF MYREG, bit, B

MOVLW 7Fh

GOTO Label

15 8 7 0

OPCODE n<7:0> (literal)

15 12 11 0

1111 n<19:8> (literal)

CALL MYFUNC

15 11 10 0

OPCODE n<10:0> (literal)

S = Fast bit

BRA MYFUNC

15 8 7 0

OPCODE n<7:0> (literal) BC MYFUNC

PIC18(L)F2X/4XK22

DS41412F-page 376  2010-2012 Microchip Technology Inc.

TABLE 25-2: PIC18(L)F2X/4XK22 INSTRUCTION SET

Mnemonic,

Operands Description Cycles 16- Bit Instruction Word Status

Affected Notes

MSb LSb

BYTE-ORIENTED OPERATIONS

ADDWF

ADDWFC

ANDWF

CLRF

COMF

CPFSEQ

CPFSGT

CPFSLT

DECF

DECFSZ

DCFSNZ

INCF

INCFSZ

INFSNZ

IORWF

MOVF

MOVFF

MOVWF

MULWF

NEGF

RLCF

RLNCF

RRCF

RRNCF

SETF

SUBFWB

SUBWF

SUBWFB

SWAPF

TSTFSZ

XORWF

f, d, a

f, a

f, d, a

f, a

f, d, a

fs, fd

f, a

f, d, a

f, a

f, d, a

f, a

f, d, a

Add WREG and f

Add WREG and CARRY bit to f

AND WREG with f

Clear f

Complement f

Compare f with WREG, skip =

Compare f with WREG, skip >

Compare f with WREG, skip <

Decrement f

Decrement f, Skip if 0

Decrement f, Skip if Not 0

Increment f

Increment f, Skip if 0

Increment f, Skip if Not 0

Inclusive OR WREG with f

Move f

Move fs (sour ce) to 1st word

fd (destination) 2nd word

Move WREG to f

Multiply WREG with f

Negate f

Rotate Left f through Carry

Rotate Left f (N o C a r ry)

Rotate Right f through Carry

Rotate Right f (No Carry)

Set f

Subtract f from WREG with

bo rrow

Subtract WREG fro m f

Subtract WREG from f with

bo rrow

Swap nibbles in f

Test f, skip if 0

Exclusive OR WREG with f

1 (2 or 3)

0010

0001

0110

0001

0110

0000

0010

0100

0010

0011

0100

0001

0101

1100

1111

0110

0000

0110

0011

0100

0011

0100

0110

0101

0011

0110

0001

01da

00da

01da

101a

11da

001a

010a

000a

01da

11da

10da

11da

10da

00da

ffff

111a

001a

110a

01da

00da

100a

01da

11da

10da

011a

10da

ffff

C, D C , Z , OV, N

Z, N

None

C, D C , Z , OV, N

None

C, D C , Z , OV, N

None

Z, N

None

C, D C , Z , OV, N

C, Z, N

Z, N

C, Z, N

Z, N

None

C, D C , Z , OV, N

None

Z, N

1, 2

1,2

1, 2

1, 2, 3, 4

1, 2

1, 2, 3, 4

1, 2

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensur es that all program memory

locations have a valid instruction.

 2010-2012 Microchip Technology Inc. DS41412F- page 377

PIC18(L)F2X/4XK22

BIT-ORIENTED OPERATIONS

BCF

BSF

BTFSC

BTFSS

BTG

f, b, a

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

Bit Toggle f

1 (2 or 3)

1001

1000

1011

1010

0111

bbba

ffff

None

1, 2

3, 4

1, 2

CONTROL OPERATIONS

BNC

BNN

BNOV

BNZ

BOV

BRA

CALL

CLRWDT

DAW

GOTO

NOP

POP

PUSH

RCALL

RESET

RETFIE

RETLW

RETURN

SLEEP

k, s

—

Branch if Carry

Branch if Negative

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

Branch if Overflow

Branch Unconditionally

Branch if Zero

Call subroutine 1 st word

2nd word

Clear Watchdog Ti m er

Decimal Adjust WREG

Go to address 1st word

2nd word

No Operation

Pop top of return stack (TOS)

Push top of return stack (TOS)

Relative Call

Software device Reset

Return from interrupt enable

Return with literal in WREG

Return from Subroutine

Go into Standby mode

1 (2)

1110

1101

1110

1111

0000

1110

1111

0000

1111

0000

1101

0000

0010

0110

0011

0111

0101

0001

0100

0nnn

0000

110s

kkkk

0000

1111

kkkk

0000

xxxx

0000

1nnn

0000

1100

0000

nnnn

kkkk

0000

kkkk

0000

xxxx

0000

nnnn

1111

0001

kkkk

0001

0000

nnnn

kkkk

0100

0111

kkkk

0000

xxxx

0110

0101

nnnn

1111

000s

kkkk

001s

0011

None

TO, PD

None

All

GIE/GIEH,

PEIE/GIEL

None

TO, PD

TABLE 25-2: PIC18(L)F2X/4XK22 INSTRUCTI ON SE T (CONTINUED )

Mnemonic,

Operands Description Cycles 16- Bit Instruction Word Status

Affected Notes

MSb LSb

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unl ess the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

PIC18(L)F2X/4XK22

DS41412F-page 378  2010-2012 Microchip Technology Inc.

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

LFSR

MOVLB

MOVLW

MULLW

RETLW

SUBLW

XORLW

f, k

Add literal and WREG

AND literal with WREG

Inclusive OR literal with WREG

Move literal (12-bit) 2nd word

to FSR(f) 1s t word

Move literal to BSR<3:0>

Move literal to WREG

Multiply literal with WREG

Return with literal in WREG

Subtract WREG from literal

Exclusive OR literal with WREG

0000

1110

1111

0000

1111

1011

1001

1110

0000

0001

1110

1101

1100

1000

1010

kkkk

00ff

kkkk

0000

kkkk

C, D C , Z , OV, N

Z, N

None

C, D C , Z , OV, N

Z, N

DATA MEMO RY  PROGRAM MEMORY OPERATIONS

TBLRD*

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Read

Table Read with post-increment

Table Read with post-decrement

Table Read with pre-increment

Table Write

Table Write with post-increment

Table Write with post-decrement

Table Write with pre-increment

0000

1000

1001

1010

1011

1100

1101

1110

1111

None

TABLE 25-2: PIC18(L)F2X/4XK22 INSTRUCTI ON SE T (CONTINUED )

Mnemonic,

Operands Description Cycles 16- Bit Instruction Word Status

Affected Notes

MSb LSb

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensur es that all program memory

locations have a valid instruction.

 2010-2012 Microchip Technology Inc. DS41412F- page 379

PIC18(L)F2X/4XK22

25.1.1 STANDARD INSTRUCTION SET

ADDLW ADD literal to W

Syntax: ADDLW k

Operands: 0  k  255

Operation: (W) + k  W

Status Affected: N, OV, C, DC, Z

Encoding: 0000 1111 kkkk kkkk

Description: The contents of W are added to the

8-bit literal ‘k’ and the result is placed in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Wri te to W

Example:ADDLW 15h

Before Instruction

W = 10h

After Instruction

W = 25h

ADDWF ADD W to f

Syntax: ADDWF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (W) + (f)  dest

Status Affected: N, OV, C, DC, Z

Encoding: 0010 01da ffff ffff

Description: Add W to register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:ADDWF REG, 0, 0

Before Instruction

W = 17h

REG = 0C2h

After Instruction

W = 0D9h

REG = 0C2h

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, th e instruction format then becomes: {label} instruction argument(s).

PIC18(L)F2X/4XK22

DS41412F-page 380  2010-2012 Microchip Technology Inc.

ADDWFC ADD W and CARRY bit to f

Syntax: ADDWFC f {,d {,a}}

Operands: 0  f  255

d [0,1]

a [0,1]

Operation: (W) + (f) + (C)  dest

Status Affected: N,OV, C, DC, Z

Encoding: 0010 00da ffff ffff

Description: Add W, the CARRY flag and data mem-

ory location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e ra l Offset Ad d r e ssin g

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:ADDWFC REG, 0, 1

Before Instruction

CARRY bit = 1

REG = 02h

W=4Dh

After Instruction

CARRY bit = 0

REG = 02h

W = 50h

ANDLW AND literal with W

Syntax: ANDLW k

Operands: 0  k  255

Operation: (W) .AND. k  W

Status Affected: N, Z

Encoding: 0000 1011 kkkk kkkk

Description: The contents of W are AND’ed with the

8-bit literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’ Proces s

Data Write to W

Example:ANDLW 05Fh

Before Instruction

W=A3h

After Instruction

W = 03h

 2010-2012 Microchip Technology Inc. DS41412F- page 381

PIC18(L)F2X/4XK22

ANDWF AND W with f

Syntax: ANDWF f {,d {,a}}

Operands: 0  f  255

d [0,1]

a [0,1]

Operation: (W) .AND. (f)  dest

Status Affected: N, Z

Encoding: 0001 01da ffff ffff

Description: The contents of W are AND’ed with

in W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e ra l Offset Ad d r e ssin g

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:ANDWF REG, 0, 0

Before Instruction

W = 17h

REG = C2h

After Instruction

W = 02h

REG = C2h

BC Branch if Carry

Syntax: BC n

Operands: -128  n  127

Operation: if CARRY bit is ‘1’

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0010 nnnn nnnn

Description: If the CARRY bit is ‘1’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example:HERE BC 5

Before Instruction

PC = address (HERE)

After Instruction

If CARRY = 1;

PC = address (HERE + 12)

If CARRY = 0;

PC = address (HERE + 2)

PIC18(L)F2X/4XK22

DS41412F-page 382  2010-2012 Microchip Technology Inc.

BCF Bit Clear f

Syntax: BCF f, b {,a}

Operands: 0  f  255

0  b  7

a [0,1]

Operation: 0  f

Status Affected: None

Encoding: 1001 bbba ffff ffff

Description: Bit ‘b’ in register ‘f’ is cleared.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e ra l Offset Ad d r e ssin g

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example:BCF FLAG_REG, 7, 0

Before Instruction

FLAG_R EG = C7h

After Instruction

FLAG_REG = 47h

BN Branch if Negative

Syntax: BN n

Operands: -128  n  127

Operation: if NEGATIVE bit is ‘1’

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0110 nnnn nnnn

Description: If the NEGATIVE bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example:HERE BN Jump

Before Instruction

PC = address (HERE)

After Instruction

If NEGATIVE = 1;

PC = address (Jump)

If NEGATIVE = 0;

PC = address (HERE + 2)

 2010-2012 Microchip Technology Inc. DS41412F- page 383

PIC18(L)F2X/4XK22

BNC Branch if Not Carry

Syntax: BNC n

Operands: -128  n  127

Operation: if CARRY bit is ‘0’

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0011 nnnn nnnn

Description: If the CARRY bit is ‘0’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example:HERE BNC Jump

Before Instruction

PC = address (HERE)

After Instruction

If CARRY = 0;

PC = address (Jump)

If CARRY = 1;

PC = address (HERE + 2)

BNN Branch if Not Negative

Syntax: BNN n

Operands: -128  n  127

Operation: if NEGATIVE bit is ‘0’

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0111 nnnn nnnn

Description: If the NEGATIVE bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example:HERE BNN Jump

Before Instruction

PC = address (HERE)

After Instruction

If NEGATIVE = 0;

PC = address (Jump)

If NEGATIVE = 1;

PC = address (HERE + 2)

PIC18(L)F2X/4XK22

DS41412F-page 384  2010-2012 Microchip Technology Inc.

BNOV Branch if Not Overflow

Syntax: BNO V n

Operands: -128  n  127

Operation: if OVERFLOW bit is ‘0’

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0101 nnnn nnnn

Description: If the OVERFLOW bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example:HERE BNOV Jump

Before Instruction

PC = address (HERE)

After Instruction

If OVERFL OW= 0;

PC = address (Jump)

If OVERFL OW= 1;

PC = address (HERE + 2)

BNZ Branch if Not Zero

Syntax: BNZ n

Operands: -128  n  127

Operation: if ZERO bit is ‘0’

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0001 nnnn nnnn

Description: If the ZERO bit is ‘0’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example:HERE BNZ Jump

Before Instruction

PC = address (HERE)

After Instruction

If ZERO = 0;

PC = address (Jump)

If ZERO = 1;

PC = address (HERE + 2)

 2010-2012 Microchip Technology Inc. DS41412F- page 385

PIC18(L)F2X/4XK22

BRA Unconditional Branch

Syntax: BRA n

Operands: -1024  n  1023

Operation: (PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1101 0nnn nnnn nnnn

Description: Add the 2’s complement number ‘2n’ to

the PC. Since the PC will have incre-

mented to fetch the next instruction, the

new address will be PC + 2 + 2n. This

instruction is a two-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

Example:HERE BRA Jump

Before Instruction

PC = address (HERE)

After Instruction

PC = address (Jump)

BSF Bit Set f

Syntax: BS F f, b {,a}

Operands: 0  f  255

0  b  7

a [0,1]

Operation: 1  f

Status Affected: None

Encoding: 1000 bbba ffff ffff

Description: Bit ‘b’ in register ‘f’ is set.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example:BSF FLAG_REG, 7, 1

Before Instruction

FLAG_REG = 0Ah

After Instruction

FLAG_REG = 8Ah

PIC18(L)F2X/4XK22

DS41412F-page 386  2010-2012 Microchip Technology Inc.

BTFSC Bit Test File, Skip if Clear

Syntax: BTFS C f, b {,a}

Operands: 0  f  255

0  b  7

a [0,1]

Operation: skip if (f) = 0

Status Affected: None

Encoding: 1011 bbba ffff ffff

Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next

instruction is skipped. If bit ‘b’ is ‘0’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOP is executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates in

Indexed Literal Offset Addressing

mode whenever f 95 (5Fh).

See Section 25.2.3 “Byte-Ori ented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example:HERE

FALSE

TRUE

BTFSC

FLAG, 1, 0

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0;

PC = address (TRUE)

If FLAG<1> = 1;

PC = address (FALSE)

BTFSS Bit Test File, Skip if Set

Syntax: BTFSS f, b {,a}

Operands: 0  f  255

0  b < 7

a [0,1]

Operation: skip if (f) = 1

Status Affected: None

Encoding: 1010 bbba ffff ffff

Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next

instruction is skipped. If bit ‘b’ is ‘1’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOP is executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh).

See Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructi o ns in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example:HERE

FALSE

TRUE

BTFSS

FLAG, 1, 0

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0;

PC = address (FALSE)

If FLAG<1> = 1;

PC = address (TRUE)

 2010-2012 Microchip Technology Inc. DS41412F- page 387

PIC18(L)F2X/4XK22

BTG Bit Toggle f

Syntax: BTG f, b {,a}

Operands: 0  f  255

0  b < 7

a [0,1]

Operation: (f)  f

Status Affected: None

Encoding: 0111 bbba ffff ffff

Description: Bit ‘b’ in data mem ory location ‘f’ is

inverted.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Liter a l Offset Mod e ” for det ails .

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example:BTG PORTC, 4, 0

Before Instruction:

PORTC = 0111 0101 [75h]

After Instruction:

PORTC = 0110 0101 [65h]

BOV Branch if Ov erf low

Syntax: BOV n

Operands: -128  n  127

Operation: if OVERFLOW bit is ‘1’

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0100 nnnn nnnn

Description: If the OVERFLOW bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example:HERE BOV Jump

Before Instruction

PC = address (HERE)

After Instruction

If OVERFL OW= 1;

PC = address (Jump)

If OVERFL OW= 0;

PC = address (HERE + 2)

PIC18(L)F2X/4XK22

DS41412F-page 388  2010-2012 Microchip Technology Inc.

BZ Branch if Zero

Syntax: BZ n

Operands: -128  n  127

Operation: if ZERO bit is ‘1’

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0000 nnnn nnnn

Description: If the ZERO bit is ‘1’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example:HERE BZ Jump

Before Instruction

PC = address (HERE)

After Instruction

If ZERO = 1;

PC = address (Jump)

If ZERO = 0;

PC = address (HERE + 2)

CALL Subroutine Call

Syntax: C ALL k {,s}

Operands: 0  k  1048575

s [0,1]

Operation: (PC) + 4  TOS,

k  PC<20:1>,

if s = 1

(W)  WS,

(S tatus)  STAT USS,

(BSR)  BSRS

Status Affected: None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>) 1110

1111 110s

k19kkk k7kkk

kkkk kkkk0

kkkk8

Description: Subroutine call of entire 2-Mbyte

memory range. First, return address

(PC + 4) is pushed onto the return

stack. If ‘s’ = 1, the W, Status and BSR

registers are also pushed into their

respective shadow registers, WS,

STATUSS and BSRS. If ‘s’ = 0, no

update occurs (default). Then, the

20-bit value ‘k’ is loaded into PC<20:1>.

CALL is a two-cycle instruction.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’<7:0>, PUSH PC to

stack Read literal

‘k’<19:8>,

Write to PC

operation No

operation

Example:HERE CALL THERE, 1

Before Instruction

PC = address (HERE)

After Instruction

PC = address (THERE)

TOS = address (HERE + 4)

WS = W

BSRS = BSR

STATUSS= Status

 2010-2012 Microchip Technology Inc. DS41412F- page 389

PIC18(L)F2X/4XK22

CLRF Clear f

Syntax: CLRF f {,a}

Operands: 0  f  255

a [0,1]

Operation: 000h  f

1  Z

Status Affected: Z

Encoding: 0110 101a ffff ffff

Description: Clears the contents of the specified

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e ra l Offset Ad d r e ssin g

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example:CLRF FLAG_REG, 1

Before Instruction

FLAG_REG = 5Ah

After Instruction

FLAG_REG = 00h

CLRWDT Clear Watchdog Timer

Syntax: CLRWDT

Operands: None

Operation: 000h  WDT,

000h  WDT postscaler,

1  TO,

1  PD

Status Affected: TO, PD

Encoding: 0000 0000 0000 0100

Description: CLRWDT instruction resets the

Watchdog Timer. It also resets the post-

scaler of the WDT. Stat us bits, TO and

PD, are set.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation Process

Data No

operation

Example:CLRWDT

Before Instruction

WDT Counter = ?

After Instruction

WDT Counter = 00h

WDT Postscaler = 0

TO =1

PD =1

PIC18(L)F2X/4XK22

DS41412F-page 390  2010-2012 Microchip Technology Inc.

COMF Complement f

Syntax: COMF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f)  dest

Status Affected: N, Z

Encoding: 0001 11da ffff ffff

Description: The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e ra l Offset Ad d r e ssin g

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:COMF REG, 0, 0

Before Instruction

REG = 13h

After Instruction

REG = 13h

W=ECh

CPFSEQ Compare f with W, skip if f = W

Syntax: CPFSE Q f {,a}

Operands: 0  f  255

a  [0,1]

Operation: (f) – (W),

skip if (f) = (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 001a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If ‘f’ = W, then the fetched instruction is

discarded and a NOP is executed

instead, making this a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example:HERE CPFSEQ REG, 0

NEQUAL :

EQUAL :

Before Instruction

PC Address = HERE

W=?

REG = ?

After Instruction

If REG = W;

PC = Address (EQUAL)

If REG  W;

PC = Address (NEQUAL)

 2010-2012 Microchip Technology Inc. DS41412F- page 391

PIC18(L)F2X/4XK22

CPFSGT Compare f with W, skip if f > W

Syntax: CPFSGT f {,a}

Operands: 0  f  255

a  [0,1]

Operation: (f) –W),

skip if (f) > (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 010a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of the W by

performing an unsigned subtraction.

If the contents of ‘f’ are greater than the

contents of WREG, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruct ion.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e ra l Offset Ad d r e ssin g

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example:HERE CPFSGT REG, 0

NGREATER :

GREATER :

Before Instruction

PC = Address (HERE)

W= ?

After Instruction

If REG  W;

PC = Address (GREATER)

If REG  W;

PC = Address (NGREATER)

CPFSLT Compare f with W, skip if f < W

Syntax: CPFSLT f {,a}

Operands: 0  f  255

a  [0,1]

Operation: (f) –W),

skip if (f) < (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 000a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If the contents of ‘f’ are less than the

contents of W, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruct ion.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example:HERE CPFSLT REG, 1

NLESS :

LESS :

Before Instruction

PC = Address (HERE)

W= ?

After Instruction

If REG < W;

PC = Address (LESS)

If REG  W;

PC = Address (NLESS)

PIC18(L)F2X/4XK22

DS41412F-page 392  2010-2012 Microchip Technology Inc.

DAW Decimal Adjust W Register

Syntax: DAW

Operands: None

Operation: If [W<3:0> > 9] or [DC = 1] then

(W<3:0>) + 6  W<3:0>;

else

(W<3:0>)  W<3:0>;

If [W<7:4> + DC > 9] or [C = 1] then

(W<7:4>) + 6 + DC  W<7:4>;

else

(W<7:4>) + DC  W<7:4>

Status Affected: C

Encoding: 0000 0000 0000 0111

Description: DAW adjusts the eight-bit value in W,

resulting from the earlier addition of two

variables (each in packed BCD format)

and produces a correct packed BCD

result.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example1:

DAW

Before Instruction

W=A5h

C=0

DC = 0

After Instruction

W = 05h

C=1

DC = 0

Example 2:

Before Instruction

W=CEh

C=0

DC = 0

After Instruction

W = 34h

C=1

DC = 0

DECF Decrement f

Syntax: DECF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) – 1  dest

Status Affected: C, DC, N, OV, Z

Encoding: 0000 01da ffff ffff

Description: Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:DECF CNT, 1, 0

Before Instruction

CNT = 01h

Z=0

After Instruction

CNT = 00h

Z=1

 2010-2012 Microchip Technology Inc. DS41412F- page 393

PIC18(L)F2X/4XK22

DECFSZ Decrement f, skip if 0

Syntax: DECF SZ f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) – 1  dest,

skip if result = 0

Status Affected: None

Encoding: 0010 11da ffff ffff

Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e ra l Offset Ad d r e ssin g

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example:HERE DECFSZ CNT, 1, 1

GOTO LOOP

CONTINUE

Before Instruction

PC = Address (HERE)

After Instruction

CNT = CNT - 1

If CNT = 0;

PC = Address (CONTINUE)

If CNT 0;

PC = Address (HERE + 2)

DCFSNZ Decrement f, skip if not 0

Syntax: DCFSNZ f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) – 1  dest,

skip if result  0

Status Affected: None

Encoding: 0100 11da ffff ffff

Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOP is execut ed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example:HERE DCFSNZ TEMP, 1, 0

ZERO :

NZERO :

Before Instruction

TEMP = ?

After Instruction

TEMP = TEM P – 1,

If TEMP = 0;

PC = Address (ZERO)

If TEMP 0;

PC = Address (NZERO)

PIC18(L)F2X/4XK22

DS41412F-page 394  2010-2012 Microchip Technology Inc.

GOTO Unconditional Branch

Syntax: GOTO k

Operands: 0  k  1048575

Operation: k  PC<20:1>

Status Affected: None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>) 1110

1111 1111

k19kkk k7kkk

kkkk kkkk0

kkkk8

Description: GOTO allows an unconditional branch

anywhere within entire

2-Mbyte memory range. The 20-bit

value ‘k’ is loaded into PC<20:1>.

GOTO is always a two-cycle

instruction.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’<7:0>, No

operation Read literal

‘k’<19:8>,

Write to PC

operation No

operation

Example:GOTO THERE

After Instruction

PC = Address (THERE)

INCF Increment f

Syntax: INCF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) + 1  dest

Status Affected: C, DC, N, OV, Z

Encoding: 0010 10da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:INCF CNT, 1, 0

Before Instruction

CNT = FFh

Z=0

C=?

DC = ?

After Instruction

CNT = 00h

Z=1

C=1

DC = 1

 2010-2012 Microchip Technology Inc. DS41412F- page 395

PIC18(L)F2X/4XK22

INCFSZ Increment f, skip if 0

Syntax: INCFSZ f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) + 1  dest,

skip if result = 0

Status Affected: None

Encoding: 0011 11da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e ra l Offset Ad d r e ssin g

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example:HERE INCFSZ CNT, 1, 0

NZERO :

ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

CNT = CNT + 1

If CNT = 0;

PC = Address (ZERO)

If CNT 0;

PC = Address (NZERO)

INFSNZ Increment f, skip if not 0

Syntax: INFSNZ f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) + 1  dest,

skip if result  0

Status Affected: None

Encoding: 0100 10da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOP is execut ed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example:HERE INFSNZ REG, 1, 0

ZERO

NZERO

Before Instruction

PC = Address (HERE)

After Instruction

REG = REG + 1

If REG 0;

PC = Address (NZERO)

If REG = 0;

PC = Address (ZERO)

PIC18(L)F2X/4XK22

DS41412F-page 396  2010-2012 Microchip Technology Inc.

IORLW Inclusive OR literal with W

Syntax: IORLW k

Operands: 0  k  255

Operation: (W) .OR. k  W

Status Affected: N, Z

Encoding: 0000 1001 kkkk kkkk

Description: The contents of W are ORed with the

eight-bit literal ‘k’. The result is placed in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Proces s

Data Write to W

Example:IORLW 35h

Before Instruction

W=9Ah

After Instruction

W=BFh

IORWF Inclusive OR W with f

Syntax: IORWF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (W) .OR. (f)  dest

Status Affected: N, Z

Encoding: 0001 00da ffff ffff

Description: Inclusive OR W with register ‘f’. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is placed back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:IORWF RESULT, 0, 1

Before Instruction

RESULT = 13h

W = 91h

After Instruction

RESULT = 13h

W = 93h

 2010-2012 Microchip Technology Inc. DS41412F- page 397

PIC18(L)F2X/4XK22

LFSR Load FSR

Syntax: LFSR f, k

Operands: 0  f  2

0  k  4095

Operation: k  FSRf

Status Affected: None

Encoding: 1110

1111 1110

0000 00ff

k7kkk k11kkk

kkkk

Description: The 12-bit literal ‘k’ is loaded into the

File Select Register pointed to by ‘f’.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’ MSB Process

Data Write

literal ‘k’

MSB to

FSRfH

Decode Read literal

‘k’ L S B Process

Data Write literal

‘k’ to FSRfL

Example:LFSR 2, 3ABh

After Instruction

FSR2H = 03h

FSR2L = ABh

MOVF Move f

Syntax: MOVF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: f  dest

Status Affected: N, Z

Encoding: 0101 00da ffff ffff

Description: The contents of register ‘f’ are moved to

a destination dependent upon the

status of ‘d’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write W

Example:MOVF REG, 0, 0

Before Instruction

REG = 22h

W=FFh

After Instruction

REG = 22h

W = 22h

PIC18(L)F2X/4XK22

DS41412F-page 398  2010-2012 Microchip Technology Inc.

MOVFF Move f to f

Syntax: MOVFF fs,fd

Operands: 0  fs  4095

0  fd  4095

Operation: (fs)  fd

Status Affected: None

Encoding:

1st word (source)

2nd word (destin.) 1100

1111 ffff

ffff ffff

ffff ffffs

ffffd

Description: The contents of source register ‘fs’ are

moved to destination register ‘fd’.

Location of source ‘f s’ can be anywhere

in the 4096-byte data space (000h to

FFFh) and location of destination ‘fd’

can also be anywhere from 000h to

FFFh.

Either source or destination can be W

(a useful special situation).

MOVFF is particularly useful for

transferring a data memory location t o a

peripheral register (such as the transmit

buffer or an I/O port).

The MOVFF instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

Words: 2

Cycles: 2 (3)

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

(src)

Process

Data No

operation

Decode No

operation

No dummy

read

operation Write

(dest)

Example:MOVFF REG1, REG2

Before Instruction

REG1 = 33h

REG2 = 11h

After Instruction

REG1 = 33h

REG2 = 33h

MOVLB Move litera l to low nibbl e in BSR

Syntax: MOVLW k

Operands: 0  k  255

Operation: k  BSR

Status Affected: None

Encoding: 0000 0001 kkkk kkkk

Description: The eight-bit literal ‘k’ is loaded into the

Bank Select Register (BSR). The value

of BSR<7:4> always remains ‘0’,

regardless of the value of k7:k4.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Proces s

Data W rite literal

‘k’ to BSR

Example:MOVLB 5

Before Instruction

BSR Register = 02h

After Instruction

BSR Register = 05h

 2010-2012 Microchip Technology Inc. DS41412F- page 399

PIC18(L)F2X/4XK22

MOVLW Move literal to W

Syntax: MOVLW k

Operands: 0  k  255

Operation: k  W

Status Affected: None

Encoding: 0000 1110 kkkk kkkk

Description: T he eight-bit literal ‘k’ is loaded into W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Write to W

Example:MOVLW 5Ah

After Instruction

W=5Ah

MOVWF M ove W to f

Syntax: MOVWF f {,a}

Operands: 0  f  255

a  [0,1 ]

Operation: (W)  f

Status Affected: None

Encoding: 0110 111a ffff ffff

Description: Move data from W to register ‘f’.

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, t he BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index ed

Literal Offset Mod e” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example:MOVWF REG, 0

Before Instruction

W=4Fh

REG = FFh

After Instruction

W=4Fh

REG = 4Fh

PIC18(L)F2X/4XK22

DS41412F-page 400  2010-2012 Microchip Technology Inc.

MULLW Multiply literal with W

Syntax: MULLW k

Operands: 0  k  255

Operation: (W ) x k  PRO D H: PR O DL

Status Affected: None

Encoding: 0000 1101 kkkk kkkk

Description: An unsigned multiplication is carried

out between the contents of W and the

8-bit literal ‘k’. The 16-bit result is

placed in the PRODH:PRODL register

pair. PRODH contains the high byte.

W is unchanged.

None of the Status flags are affected.

Note that neither overflow nor carry is

possible in this operation. A zero result

is possible but not detected.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Write

registers

PRODH:

PRODL

Example:MULLW 0C4h

Before Instruction

W=E2h

PRODH = ?

PRODL = ?

After Instruction

W=E2h

PRODH = ADh

PRODL = 08h

MULWF Multiply W with f

Syntax : MULWF f {,a}

Operands: 0  f  255

a  [0,1]

Operation: (W) x (f)  PRODH:PRODL

Status Affected: None

Encoding: 0000 001a ffff ffff

Description: An unsigned multiplication is carried

out between the contents of W and the

result is stored in the PRODH:PRODL

high byte. Both W and ‘f’ are

unchanged.

None of the Status flags are affected.

Note that neither overflow nor carry is

possible in this operation. A zero

result is possible but not detected.

If ‘a’ is ‘0’, the Access Ban k is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f 95 (5Fh). See Section 25.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

registers

PRODH:

PRODL

Example:MULWF REG, 1

Before Instruction

W=C4h

REG = B5h

PRODH = ?

PRODL = ?

After Instruction

W=C4h

REG = B5h

PRODH = 8Ah

PRODL = 94h

 2010-2012 Microchip Technology Inc. DS41412F- page 401

PIC18(L)F2X/4XK22

NEGF Negate f

Syntax: NEGF f {,a}

Operands: 0  f  255

a  [0,1]

Operation: ( f ) + 1  f

Status Affected: N, OV, C, DC, Z

Encoding: 0110 110a ffff ffff

Description: Location ‘f’ is negated using two’s

complement. The result is placed in the

data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Liter a l Offset Mod e” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example:NEGF REG, 1

Before Instruction

REG = 0011 1010 [3Ah]

After Instruction

REG = 1100 0110 [C6h]

NOP No Operation

Syntax: NOP

Operands: None

Operation: No operation

Status Affected: None

Encoding: 0000

1111 0000

xxxx 0000

xxxx

Description: No operation.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation No

operation

Example:

None.

PIC18(L)F2X/4XK22

DS41412F-page 402  2010-2012 Microchip Technology Inc.

POP Pop Top of Return Stack

Syntax: POP

Operands: None

Operation: (TOS)  bit bucket

Status Affected: None

Encoding: 0000 0000 0000 0110

Description: The TOS value is pulled off the return

stack and is discarded. The TOS value

then becomes the previous value that

was pushed onto the return stack.

This instruction is provided to enable

the user to properly manage the return

stack to incorporate a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation POP TOS

value No

operation

Example:POP

GOTO NEW

Before Instruction

TOS = 0031A2h

Stack (1 level down) = 014332h

After Instruction

TOS = 014332h

PC = NEW

PUSH Push Top of Return Stack

Syntax: PUSH

Operands: None

Operation: (PC + 2)  TOS

Status Affected: None

Encoding: 0000 0000 0000 0101

Description: The PC + 2 is pushed onto the top of

the return stack. The previous TOS

value is pushed down on the stack.

This instruction allows implementing a

software stack by modifying TOS and

then pushing it onto the return stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode PUSH

PC + 2 onto

return stack

operation No

operation

Example:PUSH

Before Instruction

TOS = 345Ah

PC = 0124h

After Instruction

PC = 0126h

TOS = 0126h

Stack (1 level down) = 345Ah

 2010-2012 Microchip Technology Inc. DS41412F- page 403

PIC18(L)F2X/4XK22

RCALL Relative Call

Syntax: RCALL n

Operands: -1024  n  1023

Operation: (PC) + 2  TOS,

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1101 1nnn nnnn nnnn

Description: Subroutine call with a jump up to 1K

from the current location. First, return

address (PC + 2) is pushed onto the

stack. Then, add the 2’s complement

number ‘2n’ to the PC. S ince the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is a

two-cycle instruct ion.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

PUSH PC to

stack

Process

Data Write to PC

operation No

operation

Example:HERE RCALL Jump

Before Instruction

PC = Address (HERE)

After Instruction

PC = Address (Jump)

TOS = Address (HERE + 2)

RESET Reset

Syntax: RESET

Operands: None

Operation: Reset all registers and flags that are

affected by a MCLR Reset.

Status Affected: All

Encoding: 0000 0000 1111 1111

Description: This instruction provides a way to

execute a MCLR Rese t b y so ftw a re.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Start

Reset No

operation No

operation

Example:RESET

After Instruction

Registers = Reset Value

Flags* = Reset Value

PIC18(L)F2X/4XK22

DS41412F-page 404  2010-2012 Microchip Technology Inc.

RETFIE Return from Interrupt

Syntax: RETFIE {s}

Operands: s  [0,1]

Operation: (TOS)  PC,

1  GIE/GI EH o r PEIE/GIE L ,

if s = 1

(WS)  W,

(STATUSS)  Status,

(BSRS)  BSR,

PCLATU, PCLATH are unchanged.

Status Affected: GIE/GIEH, PEIE/GIEL.

Encoding: 0000 0000 0001 000s

Description: Return from interrupt. Stack is popped

and Top-of-Stack (TOS) is loaded into

the PC. Interrupts are enabled by

setting either the high or low priority

global interrupt enable bit. If ‘s’ = 1, the

contents of the shadow registers, WS,

STATUSS and BSRS, are loaded into

their corresponding registers, W,

Status and BSR. If ‘s’ = 0, no update of

these registers occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation No

operation POP PC

from stack

Set GIEH or

GIEL

operation No

operation

Example:RETFIE 1

After Interrupt

PC = TOS

W=WS

BSR = BSRS

Status = STATUSS

GIE/ GIEH, PEIE/GIEL = 1

RETLW Return literal to W

Syntax: RETLW k

Operands: 0  k  255

Operation: k  W,

(TOS)  PC,

PCLATU, PCLATH are unchanged

Status Affected: None

Encoding: 0000 1100 kkkk kkkk

Description: W is loaded with the eight-bit literal ‘k’.

The program counter is loaded from the

top of the stack (the return address).

The high address latch (PCLATH)

remains unchanged.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Proces s

Data POP PC

from stack,

Write to W

operation No

operation

Example:

CALL TABLE ; W contains table

; offset value

; W now has

; table value

TABLE

ADDWF PCL ; W = offset

RETLW k0 ; Begin table

RETLW k1 ;

:RETLW kn ; End of table

Before Instruction

W = 07h

After Instruction

W = value of kn

 2010-2012 Microchip Technology Inc. DS41412F- page 405

PIC18(L)F2X/4XK22

RETURN Return from Subroutine

Syntax: RETURN {s}

Operands: s  [0,1]

Operation: (TOS)  PC,

if s = 1

(WS)  W,

(STATUSS)  Status,

(BSRS)  BSR ,

PCLATU, PCLATH are unchanged

Status Affected: None

Encoding: 0000 0000 0001 001s

Description: Return from subroutine. The stack is

popped and the top of the stack (TOS)

is loaded into the program counter. If

‘s’= 1, the contents of the shadow

registers, WS, STATUS S and BSRS,

are loaded into their corresponding

registers, W, Status and BSR. If

‘s’ = 0, no update of these registers

occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation Process

Data POP PC

from stack

operation No

operation

Example:RETURN

After Instruction:

PC = TOS

RLCF Rotate Lef t f through Carry

Syntax: RLCF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f<n>)  dest<n + 1>,

(f<7>)  C,

Status Affected: C, N, Z

Encoding: 0011 01da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the left through the CARRY

flag. If ‘d’ is ‘0’, the result is placed in

W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used to

select the GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f 95 (5F h). See Section 25.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:RLCF REG, 0, 0

Before Instruction

REG = 1110 0110

C=0

After Instruction

REG = 1110 0110

W=1100 1100

C=1

Cregister f

PIC18(L)F2X/4XK22

DS41412F-page 406  2010-2012 Microchip Technology Inc.

RLNCF Rotate Left f (No Carry)

Syntax: RLNCF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f<n>)  dest<n + 1>,

(f<7>)  dest<0>

Status Affected: N, Z

Encoding: 0100 01da ffff ffff

Description: The conte nts of register ‘f’ are rotated

one bit to the left. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, th e re sult is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh ). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructi ons in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:RLNCF REG, 1, 0

Before Instruction

REG = 1010 1011

After Instruction

REG = 0101 0111

RRCF Rotate Right f through Carry

Syntax: RRCF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f<n>)  dest<n – 1>,

(f<0>)  C,

Status Affected: C, N, Z

Encoding: 0011 00da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the right through the CARRY

flag. If ‘d’ is ‘0’, the result is placed in W.

If ‘d’ is ‘1’, the result is placed back in

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:RRCF REG, 0, 0

Before Instruction

REG = 1110 0110

C=0

After Instruction

REG = 1110 0110

W=0111 0011

C=0

Cregister f

 2010-2012 Microchip Technology Inc. DS41412F- page 407

PIC18(L)F2X/4XK22

RRNCF Rotate Right f (No Carry)

Syntax: RRNCF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f<n>)  dest<n – 1>,

(f<0>)  dest<7>

Status Affected: N, Z

Encoding: 0100 00da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the right. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank will be

selected (default), overriding the BSR

value. If ‘a’ is ‘1’, then the bank will be

selected as per the BSR value.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e ra l Offset Ad d r e ssin g

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example 1:RRNCF REG, 1, 0

Before Instruction

REG = 1101 0111

After Instruction

REG = 1110 1011

Example 2:RRNCF REG, 0, 0

Before Instruction

W=?

REG = 1101 0111

After Instruction

W=1110 1011

REG = 1101 0111

SETF Set f

Syntax: SETF f {,a}

Operands: 0  f  255

a [0,1]

Operation: FFh  f

Status Affected: None

Encoding: 0110 100a ffff ffff

Description: The contents of the specified register

are set to FFh.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example:SETF REG, 1

Before Instruction

REG = 5Ah

After Instruction

REG = FFh

PIC18(L)F2X/4XK22

DS41412F-page 408  2010-2012 Microchip Technology Inc.

SLEEP Enter Sleep mode

Syntax: SLEEP

Operands: None

Operation: 00h  WDT,

0  WDT postscaler,

1  TO ,

0  PD

Status Affected: TO, PD

Encoding: 0000 0000 0000 0011

Description: The Power-down Status bit (PD) is

cleared. The Time-out Status bit (TO)

is set. Watchdog Timer and its post-

scaler are cleared.

The processor is put into Sleep mode

with the oscillator stopped.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation Process

Data Go to

Sleep

Example:SLEEP

Before Instruction

TO =?

PD =?

After Instruction

TO =1 †

PD =0

† If WDT causes wake-up, this bit is cleared.

SUBFWB Subtract f from W with borrow

Syntax: SUBF WB f {,d {,a}}

Operands: 0 f 255

d  [0,1]

a  [0,1]

Operation: (W) – (f) – (C) dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 01da ffff ffff

Description: Subtract register ‘f’ and CARRY flag

(borrow) from W (2’s complement

method). If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored in

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank.

If ‘a’ is ‘0’ and t he extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f 95 (5Fh). See Section 25.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” f or details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example 1:SUBFWB REG, 1, 0

Before Instruction

REG = 3

W=2

C=1

After Instruction

REG = FF

W=2

C=0

Z=0

N = 1 ; result is negative

Example 2:SUBFWB REG, 0, 0

Before Instruction

REG = 2

W=5

C=1

After Instruction

REG = 2

W=3

C=1

Z=0

N = 0 ; result is positive

Example 3:SUBFWB REG, 1, 0

Before Instruction

REG = 1

W=2

C=0

After Instruction

REG = 0

W=2

C=1

Z = 1 ; result is ze r o

N=0

 2010-2012 Microchip Technology Inc. DS41412F- page 409

PIC18(L)F2X/4XK22

SUBLW Subtract W from literal

Syntax: SUBLW k

Operands: 0 k 255

Operation: k – (W) W

Status Affected: N, OV, C, DC, Z

Encoding: 0000 1000 kkkk kkkk

Description W is subtracted from the eight-bit

literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Proces s

Data Write to W

Example 1: SUBLW 02h

Before Instruction

W = 01h

C=?

After Instruction

W = 01h

C = 1 ; result is posi tiv e

Z=0

N=0

Example 2:SUBLW 02h

Before Instruction

W = 02h

C=?

After Instruction

W = 00h

C = 1 ; result is zero

Z=1

N=0

Example 3:SUBLW 02h

Before Instruction

W = 03h

C=?

After Instruction

W = FFh ; (2’s comple ment)

C = 0 ; result is negative

Z=0

N=1

SUBWF Subtract W from f

Syntax: SUBW F f {,d {,a}}

Operands: 0 f 255

d  [0,1]

a  [0,1]

Operation: (f) – (W) dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 11da ffff ffff

Description: Subtract W f rom register ‘f ’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank.

If ‘a’ is ‘0’ and t he extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f 95 (5Fh). See Section 25.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” f or details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example 1:SUBWF REG, 1, 0

Before Instruction

REG = 3

W=2

C=?

After Instruction

REG = 1

W=2

C = 1 ; result is positive

Z=0

N=0

Example 2:SUBWF REG, 0, 0

Before Instruction

REG = 2

W=2

C=?

After Instruction

REG = 2

W=0

C=1; result is zero

Z=1

N=0

Example 3:SUBWF REG, 1, 0

Before Instruction

REG = 1

W=2

C=?

After Instruction

REG = FF h ;(2’s complement)

W=2

C = 0 ; result is negative

Z=0

N=1

PIC18(L)F2X/4XK22

DS41412F-page 410  2010-2012 Microchip Technology Inc.

SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) – (W) – (C) dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 10da ffff ffff

Description: Subtract W and the CARRY flag

(borrow) from register ‘f’ (2’s comple-

ment method). If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example 1:SUBWFB REG, 1, 0

Before Instruction

REG = 19h (0001 1001)

W=0Dh (0000 1101)

C=1

After Instruction

REG = 0Ch (0000 1100)

W=0Dh (0000 1101)

C=1

Z=0

N = 0 ; result is positive

Example 2: SUBWFB REG, 0, 0

Before Instruction

REG = 1Bh (0001 1011)

W=1Ah (0001 1010)

C=0

After Instruction

REG = 1Bh (0001 1011)

W = 00h

C=1

Z = 1 ; result is z e ro

N=0

Example 3: SUBWFB REG, 1, 0

Before Instruction

REG = 03h (0000 0011)

W=0Eh (0000 1110)

C=1

After Instruction

REG = F5h (1111 0101)

; [2’s co mp]

W=0Eh (0000 1110)

C=0

Z=0

N = 1 ; result is negative

SWAPF Swap f

Syntax: SWAPF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f<3:0>)  dest<7:4>,

(f<7:4>)  dest<3:0>

Status Affected: None

Encoding: 0011 10da ffff ffff

Description: The upper and lower nibbles of register

‘f’ are exchanged. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:SWAPF REG, 1, 0

Before Instruction

REG = 53h

After Instruction

REG = 35h

 2010-2012 Microchip Technology Inc. DS41412F- page 411

PIC18(L)F2X/4XK22

TBLRD Table Read

Syntax: TBLRD ( *; *+; *-; +*)

Operands: None

Operation: if TBLRD *,

(Prog Mem (TBLPTR))  TABLAT;

TBLPTR – No Change;

if TBLRD *+,

(Prog Mem (TBLPTR))  TABLAT;

(TBLPTR) + 1  TBLPT R ;

if TBLRD *-,

(Prog Mem (TBLPTR))  TABLAT;

(TBLPTR) – 1  TBLPTR;

if TBLRD +*,

(TBLPTR) + 1  TBLPT R ;

(Prog Mem (TBLPTR))  TABLAT;

S t at us Af fected : None

Encoding: 0000 0000 0000 10nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description: This instruction is used to read the contents

of Program Memory (P.M.). To address the

program memory, a pointer called Table

Pointer (TBLPT R ) is used.

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory. TBLPTR

has a 2-Mbyte address range.

TBLPTR[0] = 0: Least Significant Byte

of Program Memor y

Word

TBLPTR[0] = 1: Most Signifi cant Byte

of Program Memor y

Word

The TBLRD instruction can modify the value

of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation No

operation

operation No operatio n

(Read Program

Memory)

operation No operation

(Write TAB-

LAT)

TBLRD Table Read (Continued)

Example1:TBLRD *+ ;

Before Instruction

TABLAT = 55h

TBLPTR = 00A356h

MEMORY (00A356h) = 34h

After Instruction

TABLAT = 34h

TBLPTR = 00A357h

Example2:TBLRD +* ;

Before Instruction

TABLAT = AAh

TBLPTR = 01A357h

MEMORY (01A357h) = 12h

MEMORY (01A358h) = 34h

After Instruction

TABLAT = 34h

TBLPTR = 01A358h

PIC18(L)F2X/4XK22

DS41412F-page 412  2010-2012 Microchip Technology Inc.

TBLWT Table Write

Syntax: TBLWT ( *; *+; *-; +*)

Operands: None

Operation: if TBLWT*,

(TABLAT)  Holding Register;

TBLPTR – No Change;

if TBLWT*+,

(TABLAT)  Holding Register;

(TBLPT R) + 1  TBLPTR;

if TBLWT*-,

(TABLAT)  Holding Register;

(TBLPTR) – 1  TBLPTR;

if TBLWT+*,

(TBLPT R) + 1  TBLPTR;

(TABLAT)  Holding Register;

Status Affected: None

Encoding: 0000 0000 0000 11nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description: T his instr uction uses the three LSBs of

TBLPTR to determine which of the eight

holding registers the TABLA T is written to.

The holding registers are used to program

the contents of Program Memory (P.M.).

(Refer to Section 6.0 “Flash Program

Memory” for additional details on pr o-

gramming Flash memo ry.)

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory.

TBLPTR has a 2-MByte address range.

The LSb of the TBLPTR selects which

byte of the program memory location to

access.

TBLPTR[0 ] = 0: Least Significant

Byte of Program

Memory Word

TBLPTR[0 ] = 1: Most Significant

Byte of Program

Memory Word

The TBLWT instruction can modify the

value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity: Q1 Q2 Q3 Q4

Decode No

operation No

operation

operation No

operation

(Read

TABLAT)

operation No

operation

(Write to

Holding

TBLWT Table Write (Continued)

Example1:TBLWT *+;

Before Instruction

TABLAT = 55h

TBLPTR = 00A356h

HOLD ING REGIST ER

(00A356h) = FFh

After Instructions (table write completion)

TABLAT = 55h

TBLPTR = 00A357h

HOLD ING REGIST ER

(00A356h) = 55h

Example 2:TBLWT +*;

Before Instruction

TABLAT = 34h

TBLPTR = 01389Ah

HOLD ING REGIST ER

(01389Ah) = FFh

HOLD ING REGIST ER

(01389Bh) = FFh

After Instruction (table write completion)

TABLAT = 34h

TBLPTR = 01389Bh

HOLD ING REGIST ER

(01389Ah) = FFh

HOLD ING REGIST ER

(01389Bh) = 34h

 2010-2012 Microchip Technology Inc. DS41412F- page 413

PIC18(L)F2X/4XK22

TSTFSZ Test f, skip if 0

Syntax: TSTFS Z f {,a}

Operands: 0  f  255

a  [0,1]

Operation: skip if f = 0

Status Affected: None

Encoding: 0110 011a ffff ffff

Description: If ‘f’ = 0, the next instruction fetched

during the current instruction execution

is discarded and a NOP is executed,

making this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e ra l Offset Ad d r e ssin g

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example:HERE TSTFSZ CNT, 1

NZERO :

ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

If CNT = 00h,

PC = Address (ZERO)

If CNT 00h,

PC = Address (NZERO)

XORLW Exclusive OR literal with W

Syntax: XORLW k

Operands: 0 k 255

Operation: (W) .XOR. k W

Status Affected: N, Z

Encoding: 0000 1010 kkkk kkkk

Description: The contents of W are XORed with

the 8-bit literal ‘k’. The result is placed

in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Proces s

Data Write to W

Example:XORLW 0AFh

Before Instruction

W=B5h

After Instruction

W=1Ah

PIC18(L)F2X/4XK22

DS41412F-page 414  2010-2012 Microchip Technology Inc.

XORWF Exclusive OR W with f

Syntax: XORWF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (W) .XOR. (f) dest

Status Affected: N, Z

Encoding: 0001 10da ffff ffff

Description: Exclusive OR the contents of W with

in W. If ‘d’ is ‘1’, the result is stored back

in the register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR i s used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e ra l Offset Ad d r e ssin g

mode whenever f 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:XORWF REG, 1, 0

Before Instruction

REG = AFh

W=B5h

After Instruction

REG = 1Ah

W=B5h

 2010-2012 Microchip Technology Inc. DS41412F- page 415

PIC18(L)F2X/4XK22

25.2 Extended Instruct ion Set

In additi on to the st an dard 75 i nst ruc tion s o f the PIC18

instruction set, PIC18(L)F2X/4XK22 devices also

provide an optional extension to the core CPU

functionality. The added features include eight

additional instructions that augment indirect and

indexe d addressing o perations and th e implement ation

of Indexed Literal Offset Addressing mode for many of

the standard PIC18 instructions.

The additional features of the extended instruction set

are d isabled by defa ult. To enable t hem, users mus t set

the XINST Configuration bit.

The instructions in the extended set can all be

class ified as literal operation s, which eith er manip ulate

the File Select Registers, or use them for indexed

addressing. Two of the instructions, ADDFSR and

SUBFSR, each have an additional special instantiation

for using FSR2. These versions (ADDULNK and

SUBULNK) allow for automatic return after execution.

The exte nded instr uctions are s pecifically im plemented

to optimize re-entrant program code (that is, code that

is recursive or that uses a software stack) written in

high-level languages, particularly C. Among other

things, they allow users working in high-level

languages to perform certain operations on data

structures more efficiently. These include:

• dynamic allocation and deallocation of software

stack space when entering and leaving

subroutines

• function poi nter invoca tion

• software Stack Pointer manipulation

• manipulation of variables located in a software

stack

A summary of the instructions in the extended instruc-

tion set is provide d in Table 25-3. Deta iled des cripti ons

are pro vided in Section 25.2.2 “Extended Instruction

Set”. The op code fiel d descript ions in Table 25-1 apply

to both the standard and extended PIC18 instruction

sets.

25.2.1 EX TEN DED INSTRU CTION SYNTAX

Most of the extended instructions use indexed

arguments, using one of the File Select Registers and

some offset to specify a source or destination register.

When an argument for an instruction serves as part of

indexed addressing, it is enclosed in square brackets

(“[ ]”). This is done to in dicate that the argument is used

as an index or of f set . MPASM™ Assembler will flag an

error if it de termines that an index or offset valu e is not

bracketed.

When the ex tended ins truction s et is enabled, bra cket s

are also used to indicate index arguments in byte-

oriented and bit-oriented in structions. This is in addition

to other changes in their syntax. For more details, see

Section 25.2.3.1 “Extended Instruction Syntax with

Standard PIC18 Commands”.

TABLE 25-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET

Note: The instruction set extension and the

Indexed Literal Offset Addressing mode

were designed for optimizing applic ations

written in C; the user m ay l ike ly ne ver use

these instructions directly in assembler.

The syntax for these commands is pro-

vided as a reference for users who may be

reviewing code that has been generated

by a compiler.

Note: In the past, square brackets have been

used to denote optional arguments in the

PIC18 and earlier instruction sets. In this

text and going forward, optional

arguments are denoted by braces (“{ }”).

Mnemonic,

Operands Description Cycles 16-Bit Instruction Word Status

Affected

MSb LSb

ADDFSR

ADDULNK

CALLW

MOVSF

MOVSS

PUSHL

SUBFSR

SUBULNK

f, k

zs, fd

zs, zd

f, k

Add literal to FSR

Add literal to FSR2 and return

Call subrou tine using WREG

Move zs (source) to 1st word

fd (destination) 2nd word

Move zs (source) to 1st word

zd (destination) 2nd word

Store literal at FSR2,

decrement FSR2

Subtract literal from FSR

Subtract literal from FSR2 and

return

1110

0000

1110

1111

1110

1111

1110

1000

0000

1011

ffff

1011

xxxx

1010

1001

ffkk

11kk

0001

0zzz

ffff

1zzz

xzzz

kkkk

ffkk

11kk

kkkk

0100

zzzz

ffff

zzzz

kkkk

None

PIC18(L)F2X/4XK22

DS41412F-page 416  2010-2012 Microchip Technology Inc.

25.2.2 EXTENDED INSTRUCTION SET

ADDFSR Add Literal to FSR

Syntax: ADDFSR f, k

Operands: 0  k  63

f  [ 0, 1, 2 ]

Operation: FSR(f) + k  FSR(f)

Status Affected: None

Encoding: 1110 1000 ffkk kkkk

Description: The 6-bit literal ‘k’ is added t o the

contents of the FSR specified by ‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Write to

FSR

Example: ADDFSR 2, 23h

Before Instruction

FSR2 = 03FFh

After Instruction

FSR2 = 0422h

ADDULNK A d d L it eral t o FSR2 and Re turn

Syntax: ADDULNK k

Operands: 0  k  63

Operation: FSR2 + k  FSR2,

(TOS) PC

Status Affected: None

Encoding: 1110 1000 11kk kkkk

Description: The 6-bit literal ‘k’ is added to the

contents of FSR2. A RETURN is then

executed by loading the PC with the

TOS.

The instruction takes two cycles to

execute; a NOP is performed during

the second cycle.

This may be thought of as a special

case of the ADDFSR instruction,

where f = 3 (binary ‘11’); it operates

only on FSR2.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Write to

FSR

Operation No

Operation

Example: ADDULNK 23h

Before Instruction

FSR2 = 03FFh

PC = 0100h

After Instruction

FSR2 = 0422h

PC = (TOS)

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).

 2010-2012 Microchip Technology Inc. DS41412F- page 417

PIC18(L)F2X/4XK22

CALLW Subroutine Call Using WREG

Syntax: CALLW

Operands: None

Operation: (PC + 2)  TOS,

(W)  PCL,

(PCLATH)  PCH,

(PCLATU)  PCU

Status Affected: None

Encoding: 0000 0000 0001 0100

Description First, the return address (PC + 2) is

pushed onto the return stack. Next, the

contents of W are written to PCL; the

existing value is discarded. Then, the

contents of PCLATH and PCLATU are

latched into PCH and PCU,

respectively. The second cycle is

executed as a NOP instruction while the

new next instruction is fetched.

Unlike CALL, there is no option to

update W, Status or BSR.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

WREG PUSH PC to

stack No

operation

operation No

operation

Example:HERE CALLW

Before Instruction

PC = address (HERE)

PCLATH = 10h

PCLATU = 00h

W = 06h

After Instruction

PC = 001006h

TOS = address (HERE + 2)

PCLATH = 10h

PCLATU = 00h

W = 06h

MOVSF Move Indexed to f

Syntax: MOVSF [zs], fd

Operands: 0  zs  127

0  fd  4095

Operation: ((FSR2) + zs)  fd

Status Affected: None

Encoding:

1st word (source)

2nd word (destin.) 1110

1111 1011

ffff 0zzz

ffff zzzzs

ffffd

Description: The contents of the source register are

moved to destination register ‘fd’. The

actual address of the source register is

determined by adding the 7-bit literal

offset ‘zs’ in the first word to the value of

FSR2. The address of the destination

‘fd’ in the second word. Both addresses

can be anywhere in the 4096-byte data

space (000h to FFFh).

The MOVSF instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Determine

source addr Determine

source addr Read

source reg

Decode No

operation

No dummy

read

operation Write

(dest)

Example:MOVSF [05h], REG2

Before Instruction

FSR2 = 80h

Contents

of 85h = 33h

REG2 = 11h

After Instruction

FSR2 = 80h

Contents

of 85h = 33h

REG2 = 33h

PIC18(L)F2X/4XK22

DS41412F-page 418  2010-2012 Microchip Technology Inc.

MOVSS Move Indexed to Indexed

Syntax: MO VSS [zs], [zd]

Operands: 0  zs  127

0  zd  127

Operation: ((FSR2) + zs)  ((FSR2) + zd)

Status Affected: None

Encoding:

1st word (source)

2nd word (dest.) 1110

1111 1011

xxxx 1zzz

xzzz zzzzs

zzzzd

Description The contents of the source register are

moved to the destination register . The

addresses of the source and destination

registers are determined by adding the

7-bit literal offset s ‘zs’ or ‘zd’,

respectively, to the value of FSR2. Both

registers can be located anywhere in

the 4096-byte data memory space

(000h to FFFh).

The MOVSS instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h. If the

resultant destination address points to

an indirect addressing register, the

instruction will execute as a NOP.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Det ermine

source addr Determine

source addr Read

source reg

Decode Determine

dest addr Determine

dest addr Write

to dest reg

Example:MOVSS [05h], [06h]

Before Instruction

FSR2 = 80h

Contents

of 85h = 33h

Contents

of 86h = 11h

After Instruction

FSR2 = 80h

Contents

of 85h = 33h

Contents

of 86h = 33h

PUSHL

Store Literal at FSR2, Decrement FSR2

Syntax: PUSHL k

Operands: 0k  255

Operation: k  (F SR2),

FSR2 – 1  FSR2

S t at us Af fected : None

Encoding: 1111 1010 kkkk kkkk

Description: The 8-bit literal ‘k’ is written to the data

memory address specified by FSR2. FSR2

is decremented by 1 after the operation.

This instruction allows users to push values

onto a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

data Write to

destination

Example:PUSHL 08h

Before Instruction

FSR2H:FSR2L = 01ECh

Memory (01ECh) = 00h

After Instruction

FSR2H:FSR2L = 01EBh

Memory (01ECh) = 08h

 2010-2012 Microchip Technology Inc. DS41412F- page 419

PIC18(L)F2X/4XK22

SUBFSR Subtract Literal from FSR

Syntax: SU BFSR f, k

Operands: 0  k  63

f  [ 0, 1, 2 ]

Operation: F SR(f) – k  FSRf

Status Affected: None

Encoding: 1110 1001 ffkk kkkk

Description: The 6-bit literal ‘k’ is subtracted from

the contents of the FSR specified by

‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:SUBFSR 2, 23h

Before Instruction

FSR2 = 03FFh

After Instruction

FSR2 = 03DCh

SUBULNK

Subtract Literal from FSR2 and Return

Syntax: SUBULNK k

Operands: 0  k  63

Operation: FSR2 – k  FSR2

(TOS) PC

S t at us Af fected : None

Encoding: 1110 1001 11kk kkkk

Description: The 6-bit literal ‘k’ is subtracted from the

contents of the FSR2. A RETURN is then

executed by loading the PC with the TOS.

The instruction takes two cycles to

execute; a NOP is performed during the

second cycle.

This may be thought of as a special case of

the SUBFSR instruction, where f = 3 (binary

‘11’); it operates only on FSR2.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Operation No

Operation

Example:SUBULNK 23h

Before Instruction

FSR2 = 03FFh

PC = 0100h

After Instruction

FSR2 = 03DCh

PC = (TOS)

PIC18(L)F2X/4XK22

DS41412F-page 420  2010-2012 Microchip Technology Inc.

25.2.3 BY TE- ORIE NT ED AND

BIT-ORIENTED INSTRUCTIONS IN

INDEXED LITERAL OFFSET MODE

In additio n to eight new comm ands in the extende d set,

enabling the extended instruction set also enables

Indexed Literal Offset Addre ssing mode (Section 5.7.1

“Indexed Addressing with Literal Offset”). This has

a sign ificant im pact on the way t hat many com mands of

the standard PIC18 instruction set are interpreted.

When the extended set is disabled, addresses

embedded in opcodes are treated as literal memory

locatio ns : ei the r as a lo ca tio n in the Acc es s Ba nk (‘a’ =

0), or in a GPR bank designated by the BSR (‘a’ = 1).

When the extended instruction set is enabled and ‘a’ =

0, however, a file register argument of 5Fh or less is

interpreted as an offset from the pointer value in FSR2

and not as a literal address. For practical purposes, this

means that all i nstructio ns that us e the Acc ess RAM b it

as an argument – that is, all byte-oriented and bit-

oriented instructions, or almost half of the core PIC18

instructions – may behave differently when the

extended instruction set is enabled.

When the content of FSR2 is 00h, the boundaries of the

Access RAM are essentially remapped to their original

values. This may be useful in creating backward

compatible code. If this technique is used, it may be

necessary to save the value of FSR2 and restore it

when moving back and forth between C and assembly

routines in order to preserve the Stack Pointer. Users

must also keep in mind the syntax requirements of the

extended instruction set (see Section 25.2.3.1

“Extended Instruction Syntax with Standard PIC18

Commands”).

Although the Indexed Literal Offset Addressing mode

can be very useful for dynamic stack and pointer

manipulation, it can also be very annoying if a simple

arithmetic operation is carried out on the wrong

programming must keep in mind that, when the

extende d inst ruction se t is ena bled, re giste r addres ses

of 5Fh or less are used for Indexed Literal Offset

Addressing.

Representative examples of typical byte-oriented and

bit-oriented instructions in the Indexed Literal Offset

Address ing mode are pro vided on the f ollowing p age to

show how execution is affected. The operand condi-

tions shown in the examples are applicable to all

instructions of these types.

25.2.3.1 Extended Instruction Syntax with

Standard PIC18 Commands

When the extended instruction set is enabled, the file

bit-or iented command s is replaced with the li teral offs et

value, ‘k ’. As al rea dy no ted, this occurs only when ‘f’ is

less t han or eq ual to 5Fh. When an of fset val ue is use d,

it must be indicated by square brackets (“[ ]”). As with

the exte nded ins tructions , the us e of brac kets indicate s

to the com pil er th at the val ue is to be in terp rete d as an

index or an offset. Omitting the brackets, or using a

value greater than 5Fh within brackets, will generate an

error in the MPASM assembler.

If the ind ex argume nt is p roperly brackete d for Indexe d

Literal O ffset Addre ssing, the Acc ess RAM argument i s

never specified; it will automatically be assumed to be

‘0’. This is in contrast to standard operation (extended

instruction set disabled) when ‘a’ is set on the basis of

the target address. Declaring the Access RAM bit in

this mode will also generate an error in the MPASM

assembler.

The destination argument, ‘d’, functions as before.

In the latest versions of the MPASM™ assembler,

languag e s upp ort for the extended i ns truc tio n s et m ust

be explicitly invoked. This is done with either the

command line option, /y, or the PE directive in the

source lis tin g.

25.2.4 CONSIDERATIONS WHEN

ENABLING THE EXTENDED

INSTRUCTION SET

It is i mport ant to note that the ex tensions to th e ins truc-

tion set may not be beneficial to all users. In particular,

users who are not writing code that uses a software

stack may not benefit from using the extens ions to the

instruction set.

Additionally, the Indexed Literal Offset Addressing

mode may create issues with legacy applications

written to the PIC18 assembler. This is because

instruc t ion s i n th e le gac y cod e m ay atte mp t to a ddress

registers in the Access Bank below 5Fh. Since these

addresses are interpreted as literal offsets to FSR2

when the instruction set extension is enabled, the

application may read or write to the wrong data

addresses.

When porting an application to the PIC18(L)F2X/

4XK22, i t is very im portant to co nsider the type of code.

A large, re-entrant application that is written in ‘C’ and

would benefit from efficient compilation will do well

when using the instruction set extensions. Legacy

applic ations tha t heavily use the Ac cess Ban k will mos t

likely not benefit from using the extended instruction

set.

Note: Enabling the PIC18 instruction set

extension may cause legacy applications

to behave erratically or fail entirely.

 2010-2012 Microchip Technology Inc. DS41412F- page 421

PIC18(L)F2X/4XK22

ADDWF ADD W to Indexed

(Indexed Literal Offset mode)

Syntax: ADDWF [k] {,d}

Operands: 0  k  95

d  [0,1]

Operation: (W) + ((FSR2) + k)  dest

Status Affected: N, OV, C, DC, Z

Encoding: 0010 01d0 kkkk kkkk

Description: The contents of W are added to the

contents of the register indicated by

FSR2, offset by the value ‘k’.

If ‘d’ is ‘0’, the result is stored in W. If ‘d’

is ‘1’, the result is stored back in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

Data Write to

destination

Example:ADDWF [OFST] , 0

Before Instruction

W = 17h

OFST = 2Ch

FSR2 = 0A00h

Contents

of 0A2Ch = 20h

After Instruction

W = 37h

Contents

of 0A2Ch = 20h

BSF Bit Set Indexed

(Indexed Literal Offset mode)

Syntax : BSF [k], b

Operands: 0  f  95

0  b  7

Operation: 1  ((FSR2) + k)

Status Affected: None

Encoding: 1000 bbb0 kkkk kkkk

Description: Bit ‘b’ of t he register indicated by FSR2,

offset by the value ‘k’, is set.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example:BSF [FLAG_OFST], 7

Before Instruction

FLAG_OFST = 0Ah

FSR2 = 0A00h

Contents

of 0A0Ah = 55h

After Instruction

Contents

of 0A0Ah = D5h

SETF Set Indexed

(Indexed Literal Offset mode)

Syntax : SETF [k]

Operands: 0  k  95

Operation: FFh  ((FSR 2) + k)

Status Affected: None

Encoding: 0110 1000 kkkk kkkk

Description: The contents of the register indicated

by FSR2, offset by ‘k’, are set to FFh.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

Data Write

Example:SETF [OFST]

Before Instruction

OFST = 2Ch

FSR2 = 0A00h

Contents

of 0A2Ch = 00h

After Instruction

Contents

of 0A2Ch = FFh

PIC18(L)F2X/4XK22

DS41412F-page 422  2010-2012 Microchip Technology Inc.

25.2.5 SPECIAL CONSIDERATIONS WITH

MICROCHIP MPL AB ® IDE TOOLS

The la test ver sions of Microc hip’s softwa re tools h ave

been de signe d t o full y sup port th e exte nded i nstruc tion

set of the PIC18(L)F2X/4XK22 family of devices. This

includes the MPLAB C18 C compiler, MPASM

assembly language and MPLAB Integrated

Development Environment (IDE).

When selecting a target device for software

development, MPLAB IDE will automatically set default

Configuration bits f or that device. The default setting for

the XINST Configuration bit is ‘0’, disabling the

extended instruction set and Indexed Literal Offset

Address ing mod e. For pr oper e xecution o f app licat ions

developed to take advantage of the extended

instruction set, XINST must be set during

programming.

To develop software for the extended instruction set,

the user must enable support for the instructions and

the Index ed Address ing mode i n their lang uage tool(s).

Depending on the environment being used, this may be

done in several ways:

• A menu option, or dialog box within the

environment, that allows the user to configure the

language tool and its settings for the project

• A command line option

• A directive in the source code

These options vary between different compilers,

assemblers and development environments. Users are

encouraged to re view the documentation acc ompanying

their development systems for the appropriate

information.

 2010-2012 Microchip Technology Inc. DS41412F- page 423

PIC18(L)F2X/4XK22

26.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers and dsPIC® digital signal

controllers are supported with a full range of software

and hardware development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Devi ce

Families

- HI-TECH C® for Various Device Families

- MPASMTM Assembler

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Progra mmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Dev elopment Boards,

Evaluation Kits, and Starter Kits

26.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Deb ugger (so ld separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Exten si ve on-l in e help

• Integration of select third party tools, such a s

IAR C Compilers

The MPLAB IDE allows you to:

• Edit your sou rce files ( either C or assembly)

• One-tou ch compile o r assemble , and download to

emulator and simulator tools (automatically

updates all project information)

• Debug us ing :

- Sour ce files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC18(L)F2X/4XK22

DS41412F-page 424  2010-2012 Microchip Technology Inc.

26.2 MPLAB C Compilers for Various

Device Families

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microc hip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

For easy source level debugging, the comp ilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

26.3 HI-TECH C for Various Device

Families

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontroll ers and the dsPIC family of digita l

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

For easy source level debugging, the comp ilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

process or , and one-s tep driver , and can run on multipl e

platforms.

26.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly co de

• Conditional assembly for multi-purpose

sour ce fil es

• Directives that allow complete control ov er the

assembly process

26.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLA B C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB O bject Li brarian manage s the cre ation an d

modification of library files of precompiled code. When

a rout in e from a l ibra ry is called fro m a so urc e f ile, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, re placement, delet ion and extraction

26.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the asse mbler to pro duce i ts o bje ct file . The ass embl er

generates relocatable object files that can then be

archived or lin ked with other relocatable ob ject files and

arch ives to c rea te an e xecu tabl e fil e. N otab le fe atu res

of the assembler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-po int data

• Command line interface

• Rich dire cti ve set

• Flexible macro language

• MPLAB IDE compatibility

 2010-2012 Microchip Technology Inc. DS41412F- page 425

PIC18(L)F2X/4XK22

26.7 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most periph erals and i nternal regi sters.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

developm ent tool .

26.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC® Flash MCUs and dsPIC® Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated D evelopment Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The emulator is field upgrad able through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers

significant advantages over competitive emulators

including low-cost, full-speed emulation, run-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

26.9 MPLAB ICD 3 In-Circuit Debugger

System

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

device s. It debugs and programs PIC® Flash microco n-

trollers and dsPIC® DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nect ed to t he des ign e nginee r's PC using a hig h-spee d

USB 2.0 i nte rfac e a nd is co nnected to the ta rget with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

26.10 PICkit 3 In-Circuit Debugger/

Programmer and

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC® and dsPIC® Flash microcontrollers at a

most af fordable price point using the powerful graphi cal

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller , hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

PIC18(L)F2X/4XK22

DS41412F-page 426  2010-2012 Microchip Technology Inc.

26.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

The P ICkit™ 2 Develo pment Program mer/Debu gger i s

a low-cost development tool with an easy to use inter-

face fo r programmin g and debu gging Micr ochip’s Flash

families of microcontrollers. The full featured

Windows® programming interface supports baseline

(PIC10F, PIC12F5xx, PIC16F5xx), midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families o f 8 -bi t, 1 6-b it, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

produ cts . With Mic rochip ’s power ful MPL AB Integrate d

Development Environment (IDE) the PICkit™ 2

enables in-circuit debugging on most PIC® microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file reg ist ers can be ex amin ed and m odifie d.

The PICkit 2 Debug Express inclu de the PICkit 2, demo

board and microcontroller , hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

26.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64 ) for me nus an d err or messag es an d a modu-

lar, detachable socket assembly to support various

package type s. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Devic e Programmer can rea d, verify an d program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPL AB PM3 has high-spe ed comm unications and

optimized algorithms for quick programming of large

memory devices and inc orporates an MMC card for file

storage and data applications.

26.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The board s suppo rt a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory .

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Also available are starter kits that contain everything

needed to experience t he specified d evice. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

 2010-2012 Microchip Technology Inc. DS41412F- page 427

PIC18(L)F2X/4XK22

27.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature.............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, and MCLR) ..................................................-0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS

PIC18LF2X/4XK22 ................................................................................................... -0.3V to +4.5V

PIC18F2X/4XK22 ..................................................................................................... -0.3V to +6.5V

Volta ge on MCLR with respect to VSS (Note 2)............................................................................................0 V to +11.0V

Total power dissipation (Note 1) ...............................................................................................................................1.0W

Maximum curr ent out of VSS pin (-40°C to +85°C) .............................................................................................. 300 mA

Maximum curr ent out of VSS pin (+85°C to +125°C)............................................................................................ 125 mA

Maximum curr ent into VDD pin (-40°C to +85°C) ................................................................................................ 200 mA

Maximum curr ent into VDD pin (+85°C to +125°C) ................................................................................................85 mA

Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin....................................................................................................25 mA

Maximum curr ent sunk byall ports (-40°C to +85°C)........................................................................................... 200 mA

Maximum curr ent sunk byall ports (+85°C to +125°C).........................................................................................110 mA

Maximum current sourced by all ports (-40°C to +85°C) ......................................................................................185 mA

Maximum current sourced by all ports (+85°C to +125°C) .....................................................................................70 mA

Note 1: Power diss ipation is calcula ted as follow s :

Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL)

2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause

latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP/

RE3 pin, rather than pulling this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This is a stre ss rating onl y and functi onal operati on of the devi ce at those or an y other condi tions abov e those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC18(L)F2X/4XK22

DS41412F-page 428  2010-2012 Microchip Technology Inc.

FIGURE 27-1: PIC18LF2X/4XK22 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL

TEMPERATURE)

FIGURE 27-2: PIC18LF2X /4X K22 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED

TEMPERATURE)

Frequency (MHz)

Voltage

3.6V

1.8V

3.0V

2.7V

2.3V

10 20 6030 40

Note 1: Maximum Frequency 20 MHz, 1.8V to 2.7V, -40°C to +85°C

2: Maximum Frequency 64 MHz, 2.7V to 3.6V, -40°C to +85°C

5.5V

5.0V

4.0V

4816

Frequency (MHz)

Voltage

3.6V

1.8V

3.0V

2.7V

2.3V

10 20 6030 40

Note 1: Maximum Frequency 16 MHz, 1.8V to 2.7V, +85°C to +125°C

2: Maximum Frequency 48 MHz, 2.7V to 3.6V, +85°C to +125°C

5.5V

5.0V

4.0V

4816

 2010-2012 Microchip Technology Inc. DS41412F- page 429

PIC18(L)F2X/4XK22

FIGURE 27-3: PIC18F2X/4XK22 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL

TEMPERATURE)

FIGURE 27-4: PIC18F2X /4X K22 FAMI LY VOLTAGE-FREQUENCY GRAPH (EXTENDED

TEMPERATURE)

Frequency (MHz)

Voltage

3.6V

1.8V

3.0V

2.7V

2.3V

10 20 6030 40

Note 1: Maximum Frequency 20 MHz, 2.3V to 2.7V, -40°C to +85°C

2: Maximum Frequency 64 MHz, 2.7V to 5.5V, -40°C to +85°C

5.5V

5.0V

4.0V

4816

Frequency (MHz)

Voltage

3.6V

1.8V

3.0V

2.7V

2.3V

10 20 6030 40

Note 1: Maximum Frequency 16 MHz, 2.3V to 2.7V, +85°C to +125°C

2: Maximum Frequency 48 MHz, 2.7V to 5.5V, +85°C to +125°C

5.5V

5.0V

4.0V

4816

PIC18(L)F2X/4XK22

DS41412F-page 430  2010-2012 Microchip Technology Inc.

27.1 DC Characteristics: Supply Voltage, PIC18(L)F2X/4XK22

PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise

stated)

Operating temperature -40°C  TA  +125°C

Param

No. Symbol Characteristic Min Typ Max Units Conditions

D001 VDD Supply V oltage PIC18LF2X/4XK22 1.8 — 3.6 V

PIC18F2X/4XK22 2.3 — 5.5 V

D002 VDR RAM Data Retention Voltage(1) 1.5 — — V

D003 VPOR VDD Start V oltage to ensure internal

Power-on Reset signal — — 0.7 V See sectio n on Power-on Reset

for details

D004 SVDD VDD Rise Rate to ensure internal

Power-on Reset signal 0.05 — — V/ms See section on Power-on Reset

for details

D005 VBOR Brown-out Reset Voltage

BORV<1:0> = 11(2) 1.75 1.9 2.05 V

BORV<1:0> = 10 2.05 2.2 2.35 V

BORV<1:0> = 01 2.35 2.5 2.65 V

BORV<1:0> = 00(3) 2.65 2.85 3.05 V

Note 1: This is the li mi t to whi ch V DD can be lowered in Sleep mode, or during a devic e Reset, w ithout los ing RAM

data.

2: On PIC 18LF2X/4 XK22 devices with BOR enabled, op erat ion is s upporte d until a BOR occ urs. This is valid

although VDD may be below the minimum rated supply voltage.

3: With BOR enable d, full-spee d operation (FOSC = 64 MHz or 48 MHz) is supported unt il a BOR occurs. This

is valid although VDD may be below the minimum voltage for this frequency.

 2010-2012 Microchip Technology Inc. DS41412F- page 431

PIC18(L)F2X/4XK22

27.2 DC Characteristi cs: Power-D own Current, PIC18(L) F2X/4XK22

PIC18LF2X/4XK22 Standard Operating Conditions (unles s otherwise stated)

Operati ng tem per ature -40°C  TA  +125°C

PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Operati ng tem per ature -40°C  TA  +125°C

Param

No. Device Characte ristics Typ

+25°C Typ

+60°C Max

+85°C Max

+125°C Units Conditions

VDD Notes

Power-down Base Current (IPD)(1)

D006 Sleep mode 0.01 0.04 2 10 A1.8V

WDT, BOR, FVR and

SOSC disabled, all

Peripherals i nactive

0.01 0.06 2 10 A3.0V

12 13 25 35 A2.3V

13 14 30 40 A3.0V

13 14 35 50 A5.0V

Powe r-down Mo dule Differential C urrent (delta IPD)

D007 Watchdog Timer 0.3 0.3 2.5 2.5 A1.8V

0.5 0.5 2.5 2.5 A3.0V

0.35 0.35 5.0 5.0 A2.3V

0.5 0.5 5.0 5.0 A3.0V

0.5 0.5 5.0 5.0 A5.0V

D008 Brown-out Reset(2) 88.51516 A2.0V

99.51516 A3.0V

3.4 3.4 15 16 A2.3V

3.8 3.8 15 16 A3.0V

5.2 5.2 15 16 A5.0V

D010 High/Low Voltage Detect(2) 6.5 6.7 15 15 A2.0V

77.51515 A3.0V

2.1 2.1 15 15 A2.3V

2.4 2.4 15 15 A3.0V

3.2 3.2 15 15 A5.0V

D011 Secondary Oscillato r 0.5 1 3 10 A1.8V

32 kHz on SO SC

0.6 1.1 4 10 A3.0V

0.5 1 3 10 A2.3V

0.6 1.1 410 A3.0V

0.6 1.1 510 A5.0V

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS

and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: On PIC18LF2 X/4XK22 the BOR, HLVD and FVR enable inte rnal band gap re ference . With more than one

of these modules enabled, the current consumption will be less than the sum of the specifications. On

PIC18F2X/4XK22, the internal band gap reference is always enabled and its current consumption is

included in the Power-down Base Current (IPD).

3: A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the

FRC turn off as soon as conversion (if any) is complete.

PIC18(L)F2X/4XK22

DS41412F-page 432  2010-2012 Microchip Technology Inc.

D015 Comparators 771818A1.8V

LP mode

771818A3.0V

7 7 18 18 A2.3V

7 7 18 18 A3.0V

8 8 20 20 A5.0V

D016 Comparators 38 38 95 95 A1.8V

HP mode

40 40 105 105 A3.0V

39 39 95 95 A2.3V

40 40 105 105 A3.0V

40 40 105 105 A5.0V

D017 DAC 14 14 25 25 A2.0V

20 20 35 35 A3.0V

15 15 30 30 A2.3V

20 20 35 35 A3.0V

32 32 60 60 A5.0V

D018 FVR(2) 15 16 25 25 A1.8V

15 16 25 25 A3.0V

28 28 45 45 A2.3V

31 31 55 55 A3.0V

66 66 100 100 A5.0V

D013 A/D Converter(3) 185 185 370 370 A1.8V

A/D on, not converting

210 210 400 400 A3.0V

200 200 380 380 A2.3V

210 210 400 400 A3.0V

250 250 450 450 A5.0V

27.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/4XK22 (Continued)

PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Operati ng tem pe rature -40°C  TA  +125°C

PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Operati ng tem pe rature -40°C  TA  +125°C

Param

No. Device Characte ristics Typ

+25°C Typ

+60°C Max

+85°C Max

+125°C Units Conditions

VDD Notes

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS

and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: On PIC18 LF2 X/4XK2 2 the BO R, HLVD and FVR enable internal b and g ap re feren ce . With m ore t han o ne

of these modules enabled, the current consumption will be less than the sum of the specifications. On

PIC18F2X/4XK22, the internal band gap reference is always enabled and its current consumption is

included in the Power-down Base Current (IPD).

3: A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the

FRC turn off as soon as conversion (if any) is complete.

 2010-2012 Microchip Technology Inc. DS41412F- page 433

PIC18(L)F2X/4XK22

27.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/4XK22

PIC18LF2X/4XK22 Standard Operating Condition s (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No. Devic e C ha r a c terist ic s Typ Max Units Conditions

D020 Supply Current (IDD)(1),(2) 3.6 23 A-40°C VDD = 1.8V FOSC = 31 kHz

(RC_RUN mode,

LFINTOSC

source)

3.9 25 A +25°C

3.9 — A +60°C

3.9 28 A +85°C

4.0 30 A 125°C

D021 8.1 26 A-40°C V

DD = 3.0V

8.4 30 A +25°C

8.6 — A +60°C

8.7 35 A +85°C

10.7 40 A +125°C

D022 16 35 A-40°C VDD = 2.3V FOSC = 31 kHz

(RC_RUN mode,

LFINTOSC

source)

17 35 A+25°C

18 35 A+85°C

19 50 A+125°C

D023 18 50 A-40°C VDD = 3.0V

20 50 A+25°C

21 50 A+85°C

22 60 A+125°C

D024 19 55 A-40°C VDD = 5.0V

21 55 A+25°C

22 55 A+85°C

23 70 A+125°C

D025 0.14 0.25 mA -40°C to +125°C VDD = 1.8V FOSC = 500 kHz

(RC_RUN mode,

MFINTOSC

source)

D026 0.17 0.30 mA -40°C to +125°C VDD = 3.0V

D027 0.18 0.25 mA -40°C to +125°C VDD = 2.3V FOSC = 500 kHz

(RC_RUN mode,

MFINTOSC

source)

D028 0.20 0.30 mA -40°C to +125°C VDD = 3.0V

D029 0.25 0.35 mA -40°C to +125°C VDD = 5.0V

Note 1: The supply current is mainly a function of operating volt age, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’.

2: The test conditions for all IDD measurements in active operation mode are:

All I/O pins set as outputs driven to Vss;

MCLR = VDD;

OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).

PIC18(L)F2X/4XK22

DS41412F-page 434  2010-2012 Microchip Technology Inc.

D030 0.35 0.50 mA -40°C to +125°C VDD = 1.8V FOSC = 1 MHz

(RC_RUN mode,

HFINTOSC

source)

D031 0.45 0.65 mA -40°C to +125°C VDD = 3.0V

D032 0.40 0.60 mA -40°C to +125°C VDD = 2 .3V FOSC = 1 MHz

(RC_RUN mode,

HFINTOSC

source)

D033 0.50 0.65 mA -40°C to +125°C VDD = 3 .0V

D034 0.55 0.75 mA -40°C to +125°C VDD = 5 .0V

D035 1.3 2.0 mA -40°C to +125°C VDD = 1.8V FOSC = 16 MHz

(RC_RUN mode,

HFINTOSC

source)

D036 2.2 3.0 mA -40°C to +125°C VDD = 3.0V

D037 1.7 2.0 mA -40°C to +125°C VDD = 2.3V FOSC = 16 MHz

(RC_RUN mode,

HFINTOSC

source)

D038 2.2 3.0 mA -40°C to +125°C VDD = 3.0V

D039 2.5 3.5 mA -40°C to +125°C VDD = 5.0V

D041 6.2 8.5 mA -40°C to +125°C VDD = 3.0V FOSC = 64 MHz

(RC_RUN mode,

HFINTOSC + PLL

source)

D043 6.2 8.5 mA -40°C to +125°C VDD = 3.0V FOSC = 64 MHz

(RC_RUN mode,

HFINTOSC + PLL

source)

D044 6.8 9.5 mA -40°C to +125°C VDD = 5.0V

27.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/4XK22 (Continued)

PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No. Devic e C ha r a c terist ic s Typ Max Units Conditions

Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

Test condition: All Peripheral Module Control bits in PM D0, PMD1 and PMD2 set to ‘1’.

2: The test conditions for all IDD measurements in active operation mode are:

All I/O pins set as outputs driven to Vss;

MCLR = VDD;

OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).

 2010-2012 Microchip Technology Inc. DS41412F- page 435

PIC18(L)F2X/4XK22

27.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/4XK22

PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C  TA  +125°C

PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C  TA  +125°C

Par a m

No. Device Characteristics Typ Max Units Condit ions

D045 Supply Current (IDD)(1),(2) 0.5 18 A -40°C VDD = 1.8V FOSC = 31 kHz

(RC_IDLE mode,

LFINTOSC source)

0.6 18 A+25°C

0.7 — A+60°C

0.75 20 A+85°C

2.3 22 A +125°C

D046 1.1 20 A -40°C VDD = 3.0V

1.2 20 A+25°C

1.3 — A+60°C

1.4 22 A+85°C

3.2 25 A +125°C

D047 17 30 A-40°C VDD = 2.3V FOSC = 31 kHz

(RC_IDLE mode,

LFINTOSC source)

13 30 A+25°C

14 30 A+85°C

15 45 A+125°C

D048 19 35 A-40°C VDD = 3.0V

15 35 A+25°C

16 35 A+85°C

17 50 A+125°C

D049 21 40 A-40°C VDD = 5.0V

15 40 A+25°C

16 40 A+85°C

18 60 A+125°C

D050 0.11 0.20 mA -40°C to +125°C VDD = 1.8V FOSC = 500 kHz

(RC_IDLE mode,

MFINTOSC source)

D051 0.12 0.25 mA -40°C to +125°C VDD = 3.0V

D052 0.14 0.21 mA -40°C to +125°C VDD = 2.3V FOSC = 500 kHz

(RC_IDLE mode,

MFINTOSC source)

D053 0.15 0.25 mA -40°C to +125°C VDD = 3.0V

D054 0.20 0.31 mA -40°C to +125°C VDD = 5.0V

Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’.

2: The test conditions for all IDD measurements in active operation mode are:

All I/O pins set as outputs driven to Vss;

MCLR = VDD;

OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).

PIC18(L)F2X/4XK22

DS41412F-page 436  2010-2012 Microchip Technology Inc.

D055 0.25 0.40 mA -40°C to +125°C VDD = 1.8V FOSC = 1 MHz

(RC_IDLE mode,

HFINTOSC source)

D056 0.35 0.50 mA -40°C to +125°C VDD = 3.0V

D057 0.30 0.45 mA -40°C to +125°C VDD = 2.3V FOSC = 1 MHz

(RC_IDLE mode,

HFINTOSC source)

D058 0.40 0.50 mA -40°C to +125°C VDD = 3.0V

D059 0.45 0.60 mA -40°C to +125°C VDD = 5.0V

D060 0.50 0.7 mA -40°C to +125°C VDD = 1.8V FOSC = 16 MHz

(RC_IDLE mode,

HFINTOSC source)

D061 0.80 1.1 mA -40°C to +125°C VDD = 3.0V

D062 0.65 1.0 mA -40°C to +125°C VDD = 2.3V FOSC = 16 MHz

(RC_IDLE mode,

HFINTOSC source)

D063 0.80 1.1 mA -40°C to +125°C VDD = 3.0V

D064 0.95 1.2 mA -40°C to +125°C VDD = 5.0V

D066 2.5 3 .5 mA -40°C to +125°C VDD = 3.0V FOSC = 64 MHz

(RC_IDLE mode,

HFINTOSC + PLL

source)

D068 2.5 3.5 mA -40° C to +125°C VDD = 3.0V FOSC = 64 MHz

(RC_IDLE mode,

HFINTOSC + PLL

source)

D069 3.0 4.5 mA -40° C to +125°C VDD = 5.0V

27.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/4XK22 (Continued)

PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C  TA  +125°C

PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C  TA  +125°C

Par a m

No. Device Characteristics Typ Max Units Condit ions

Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

Test condition: All Peripheral Module Control bits in PM D0, PMD1 and PMD2 set to ‘1’.

2: The test conditions for all IDD measurements in active operation mode are:

All I/O pins set as outputs driven to Vss;

MCLR = VDD;

OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).

 2010-2012 Microchip Technology Inc. DS41412F- page 437

PIC18(L)F2X/4XK22

27.5 DC Characteristics: Primary Run Supply Current, PIC18(L)F2X/4XK22

PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C  TA  +125°C

PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C  TA  +125°C

Par a m

No. Device Characteristics Typ Max Units Condit ions

D070 Supply Current (IDD)(1),(2) 0.11 0.20 mA -40°C to +125°C VDD = 1.8V FOSC = 1 MHz

(PRI_RUN mode,

ECM source)

D071 0.17 0.25 mA -40°C to +125°C VDD = 3.0V

D072 0.15 0.25 mA -40°C to +125°C VDD = 2.3V FOSC = 1 MHz

(PRI_RUN mode,

ECM source)

D073 0.20 0.30 mA -40°C to +125°C VDD = 3.0V

D074 0.25 0.35 mA -40°C to +125°C VDD = 5.0V

D075 1.45 2.0 mA -40°C to +125°C VDD = 1.8V FOSC = 20 MHz

(PRI_RUN mode,

ECH source)

D076 2.60 3.5 mA -40°C to +125°C VDD = 3.0V

D077 1.95 2.5 mA -40°C to +125°C VDD = 2.3V FOSC = 20 MHz

(PRI_RUN mode,

ECH source)

D078 2.65 3.5 mA -40°C to +125°C VDD = 3.0V

D079 2.95 4.5 mA -40°C to +125°C VDD = 5.0V

D080 7.5 10 m A -40°C to +125°C VDD = 3.0V FOSC = 64 MHz

(PRI_RUN,

ECH oscillator)

D081 7.5 10 mA -40°C to +125°C VDD = 3. 0V FOSC = 64 MHz

(PRI_RUN mode,

ECH source)

D082 8.5 11.5 mA -4 0°C to +125°C VDD = 5.0V

D083 1.0 1 .5 mA -40°C to +125°C VDD = 1.8V FOSC = 4 MHz

16 MHz Internal

(PRI_RUN mode,

ECM + PLL source)

D084 1.8 3 .0 mA -40°C to +125°C VDD = 3.0V

D085 1.4 2.0 mA -40° C to +125°C VDD = 2.3V FOSC = 4 MHz

16 MHz Internal

(PRI_RUN mode,

ECM + PLL source)

D086 1.85 2.5 mA -40°C to +125°C VDD = 3.0V

D087 2.1 3.0 mA -40° C to +125°C VDD = 5.0V

D088 6.35 9.0 mA -40°C to +125°C VDD = 3.0V FOSC = 16 MHz

64 MHz Internal

(PRI_RUN mode,

ECH + PLL sour ce )

D089 6.35 9.0 mA -40°C to +125°C VDD = 3.0V FOSC = 16 MHz

64 MHz Internal

(PRI_RUN mode,

ECH + PLL sour ce )

D090 7.0 10 mA -40°C to +125°C VDD = 5. 0V

Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’.

2: The test conditions for all IDD measurements in active operation mode are:

All I/O pins set as outputs driven to Vss;

MCLR = VDD;

OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).

PIC18(L)F2X/4XK22

DS41412F-page 438  2010-2012 Microchip Technology Inc.

27.6 DC Characteristics: Primary Idle S upply Current , PIC18(L)F2X/4XK22

PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C  TA  +125°C

PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C  TA  +125°C

Par a m

No. Device Characteristics Typ Max Units Condit ions

D100 Supply Current (IDD)(1),(2) 0.030 0.050 mA -40°C to +125°C VDD = 1.8V Fo sc = 1 M Hz

(PRI_IDLE mode,

ECM source)

D101 0.045 0.0 65 mA -40°C to +125°C VDD = 3.0V

D102 0.06 0.12 mA -40°C to +125°C VDD = 2.3V Fosc = 1 MH z

(PRI_IDLE mode,

ECM source)

D103 0.08 0.15 mA -40°C to +125°C VDD = 3.0V

D104 0.13 0.20 mA -40°C to +125°C VDD = 5.0V

D105 0.45 0.8 mA -40°C to +125°C VDD = 1.8V Fosc = 20 MHz

(PRI_IDLE mode,

ECH source)

D106 0.70 1.0 mA -40°C to +125°C VDD = 3.0V

D107 0.55 0.8 mA -40°C to +125°C VDD = 2.3V Fosc = 20 MHz

(PRI_IDLE mode,

ECH source)

D108 0.75 1.0 mA -40°C to +125°C VDD = 3.0V

D109 0.90 1.2 mA -40°C to +125°C VDD = 5.0V

D110 2.25 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 64 MHz

(PRI_IDLE mode,

ECH source)

D111 2.25 3.0 mA -40°C t o +125°C VDD = 3.0V Fosc = 64 MHz

(PRI_IDLE mode,

ECH source)

D112 2.60 3.5 mA -40° C to +125°C VDD = 5.0V

D113 0.35 0.6 mA -40°C to +125°C VDD = 1.8V Fosc = 4 MH z

16 MHz Internal

(PRI_IDLE mode,

ECM + PLL source)

D114 0.55 0.8 mA -40°C to +125°C VDD = 3.0V

D115 0.45 0.6 mA -40° C to +125°C VDD = 2.3V Fosc = 4 MHz

16 MHz Internal

(PRI_IDLE mode,

ECM + PLL source)

D116 0.60 0.9 mA -40° C to +125°C VDD = 3.0V

D117 0.70 1.0 mA -40° C to +125°C VDD = 5.0V

D118 2.2 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 16 MHz

64 MHz Internal

(PRI_IDLE mode,

ECH + PLL sour ce )

D119 2.2 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 16 MHz

64 MHz Internal

(PRI_IDLE mode,

ECH + PLL sour ce )

D120 2.5 3.5 mA -40° C to +125°C VDD = 5.0V

Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

Test condition: All Peripheral Module Control bits in PM D0, PMD1 and PMD2 set to ‘1’.

2: The test conditions for all IDD measurements in active operation mode are:

All I/O pins set as outputs driven to Vss;

MCLR = VDD;

OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).

 2010-2012 Microchip Technology Inc. DS41412F- page 439

PIC18(L)F2X/4XK22

27.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/4XK22

PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C  TA  +125°C

PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C  TA  +125°C

Par a m

No. Device Characteristics Typ Max Units Condit ions

D130 Supply Current (IDD)(1),(2) 3.5 23 A -40°C VDD = 1.8V Fosc = 32 kHz

(SEC_RUN mode,

SOSC source)

3.7 25 A+25°C

3.8 — A+60°C

4.0 28 A+85°C

5.1 30 A +125°C

D131 6.2 26 A -40°C VDD = 3.0V

6.4 30 A+25°C

6.5 — A+60°C

6.8 35 A+85°C

7.8 40 A +125°C

D132 15 35 A-40°C VDD = 2.3V Fosc = 32 kHz

(SEC_RUN mode,

SOSC source)

16 35 A+25°C

17 35 A+85°C

19 50 A+125°C

D133 18 50 A-40°C VDD = 3.0V

19 50 A+25°C

21 50 A+85°C

22 60 A+125°C

D134 19 55 A-40°C VDD = 5.0V

20 55 A+25°C

22 55 A+85°C

23 70 A+125°C

Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to ‘1’.

2: The test conditions for all IDD measurements in active operation mode are:

All I/O pins set as outputs driven to Vss;

MCLR = VDD;

SOSCI / SOSCO = complementary external square wave, from rail-to-rail.

PIC18(L)F2X/4XK22

DS41412F-page 440  2010-2012 Microchip Technology Inc.

D135 0.9 18 A -40°C VDD = 1.8V Fosc = 32 kHz

(SEC_IDLE mode,

SOSC source)

1.0 18 A+25°C

1.1 — A+60°C

1.3 20 A+85°C

2.3 22 A +125°C

D136 1.3 20 A -40°C VDD = 3.0V

1.4 20 A+25°C

1.5 — A+60°C

1.8 22 A+85°C

2.9 25 A +125°C

D137 12 30 A-40°C VDD = 2.3V Fosc = 32 kHz

(SEC_IDLE mode,

SOSC source)

13 30 A+25°C

14 30 A+85°C

16 45 A+125°C

D138 13 35 A-40°C VDD = 3.0V

14 35 A+25°C

16 35 A+85°C

18 50 A+125°C

D139 14 40 A-40°C VDD = 5.0V

15 40 A+25°C

16 40 A+85°C

18 60 A+125°C

27.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/4XK22

PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C  TA  +125°C

PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C  TA  +125°C

Par a m

No. Device Characteristics Typ Max Units Condit ions

Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

Test condition: All Peripheral Module Control bits in PM D0, PMD1 and PMD2 set to ‘1’.

2: The test conditions for all IDD measurements in active operation mode are:

All I/O pins set as outputs driven to Vss;

MCLR = VDD;

SOSCI / SOSCO = complementary external square wave, from rail-to-rail.

 2010-2012 Microchip Technology Inc. DS41412F- page 441

PIC18(L)F2X/4XK22

27.8 DC Characteristics:Input/Output Characteristics, PIC18(L)F2X/4XK22

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C TA  +125°C

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

VIL Input Low Voltage

I/O PORT:

D140 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V

D140A — — 0.15 VDD V1.8V  VDD  4.5V

D141 with Schmitt Trigger

buffer ——0.2V

DD V2.0V  VDD  5.5V

with I2C™ levels — — 0.3 VDD V

with SMBus levels — — 0.8 V 2.7V  VDD  5.5V

D142 MCLR, OSC1 (RC

mode)(1) ——0.2VDD V

D142A OSC1 (HS mode) — — 0.3 VDD V

VIH Input High Voltage

I/O ports: — —

D147 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V

D147A 0.25 VDD +

0.8 ——V1.8V  VDD  4.5V

D148 with Schmitt Trigger

buffer 0.8 VDD ——V2.0V  VDD  5.5V

with I2C™ levels 0.7 VDD ——V

with SMBus levels 2.1 — — V 2.7V  VDD  5.5V

D149 MCLR 0.8 VDD ——V

D150A OSC1 (HS mode) 0.7 VDD ——V

D150B OSC1 (RC mode)(1) 0.9 VDD ——V

IIL Input Leakage I/O and

MCLR(2),(3) VSS VPIN VDD,

Pin at hi gh-impedance

D155 I/O ports and MCLR —

—

0.1

0.7

100

200

1000

+25°C(4)

+60°C

+85°C

+125°C

IPU Weak Pull-up Current(4)

D158 IPURB PORTB weak pull-up

current 25

25 85

130 200

300 A

AVDD = 3.3V, VPIN = VSS

VDD = 5.0V, VPIN = VSS

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that

the PIC® device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Paramete r is chara cteriz ed but not tes ted .

PIC18(L)F2X/4XK22

DS41412F-page 442  2010-2012 Microchip Technology Inc.

VOL Output Low Voltage

D159 I/O ports ——0.6V

IOL = 8 mA, VDD = 5V

IOL = 6 mA, VDD = 3.3V

IOL = 1.8 mA, VDD = 1.8V

VOH Output High Voltage(3)

D161 I/O ports VDD - 0.7 — — V IOH = 3.5 mA, VDD = 5V

IOH = 3 mA, VDD = 3.3V

IOH = 1 mA, VDD = 1.8V

27.8 DC C ha rac teris tics :Input/Output Characteristics, P I C 1 8 (L)F 2X/ 4 X K22 (Continu e d)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C TA  +125°C

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that

the PIC® device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Paramete r is chara cteriz ed but not tes ted .

 2010-2012 Microchip Technology Inc. DS41412F- page 443

PIC18(L)F2X/4XK22

27.9 Memory Programming Requirements

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Internal Program Memory

Program m in g Speci fic at ion s(1)

D170 VPP Voltage on MCLR/VPPpin 8 — 9 V (Note 3), (Note 4)

D171 IDDP Supply Cu rre nt durin g

Programming ——10mA

Data EEPROM Memory

D172 EDByte En du ra nc e 100K — — E/ W - 40C to +85C

D173 VDRW VDD for Rea d/Write VDDMIN —VDDMAX V Using EECON to read/

write

D175 TDEW Erase/Write Cycle Time — 3 4 ms

D176 TRETD Characteristic Retention — 40 — Year Provided no other

specifications are violated

D177 TREF Number of Total Erase/Write

Cycles before Refresh(2) 1M 10M — E/W -40°C to +85°C

Program Flash Memory

D178 EPCell Endurance 10K — — E/W -40C to +85C (Note 5)

D179 VPR VDD for Read VDDMIN —VDDMAX V

D181 VIW VDD for Row Erase or Write 2.2 — VDDMAX V PIC18LF2X/4XK22

D182 VIW VDDMIN —VDDMAX V PIC18F2X/4XK22

D183 TIW Self-timed Write Cycle Time — 2 — ms

D184 TRETD Characteristic Retention — 40 — Year Provided no other

specifications are violated

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: These sp ec i fic at i on s a re f or pr og r amm in g t h e on - ch i p pr o gr am mem or y t h ro ug h t he us e o f table wri t e i n st r uc -

tions.

2: Refer to Section 7.8 “Using the Data EEPROM” for a mo re de tailed disc us sio n on data EEP RO M

endurance.

3: Require d on ly if sing le -su pp ly pro gr am m ing is disa ble d.

4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the MPLAB ICD 2 VPP voltage must

be placed between theMPLAB ICD 2 and target system when programming or debugging with the MPLAB

ICD 2.

5: Self-write and Block Erase.

PIC18(L)F2X/4XK22

DS41412F-page 444  2010-2012 Microchip Technology Inc.

27.10 Analog Characteristics

TABLE 27-1: COMPARATOR SPECIFICATIONS

Operating Condit ions : 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

CM01 VIOFF Input Offs et Voltage — 3 40 m V High-Power mode

VREF = VDD/2

— 4 60 mV Low-Powe r m ode

VREF = VDD/2

CM02 VICM Input Comm on-m ode Voltage VSS —VDD V

CM04* TRESP Response Time(1) — 200 400 ns High-Power mode

— 600 3500 ns Lo w -Power mode

CM05* TMC2OV Comparator Mo de Change t o

Output Valid ——10s

* These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at VDD/2, while th e other input tran sitions from VSS to VDD.

TABLE 27-2: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS

Operating Condit ions : 2.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

CV01* CLSB Step Size(2) —VDD/32 — V

CV02* CACC Absolute Accuracy — — 1/2 LSb VSRC 2.0V

CV03* CRUnit Resistor Value (R) — 5k — 

CV04* CST Settling Time(1) ——10s

CV05* VSRC+ DAC Positive Referenc e VSRC- +2 — VDD V

CV06* VSRC- DAC Negative Reference VSS —VSRC+ -2 V

CV07* VSRC DAC Refere nc e Range

(VSRC+ - VSRC-) 2—V

DD V

* These parameters are characterized but not tested.

Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.

2: See Section 22.0 “Digital-to-Analog Converter (DAC) Module” for more information.

 2010-2012 Microchip Technology Inc. DS41412F- page 445

PIC18(L)F2X/4XK22

TABLE 27-3: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS

Operating Condit ions : -40° C < TA < +125°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

VR01 VROUT VR voltage output to ADC 0.973 1.024 1.085 V 1x output, VDD 2.5V

1.946 2.048 2.171 V 2x output, VDD 2.5V

3.891 4.096 4.342 V 4x output, VDD 4.75V

(PIC18F2X/4XK22)

VR02 VROUT VR voltage output all other

modules 0.942 1.024 1.096 V 1x output, VDD 2.5V

1.884 2.048 2.191 V 2x output, VDD 2.5V

3.768 4.096 4.383 V 4x output, VDD 4.75V

(PIC18F2X/4XK22)

VR04* TSTABLE Settling Time — 25 100 s 0 to 125°C

* These parameters are characterized but not tested.

TABLE 27-4: CHARGE TIME MEASUREMENT UNIT (CTMU) SPECIFICATIONS

Operating Condit ions : 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ(1) Max Units Comments

CT01 IOUT1 CTMU Current Source,

Base Range —0.55— AIRNG<1:0>=01

CT02 IOUT2 CTMU Current Source,

10X Range —5.5— AIRNG<1:0>=10

CT03 IOUT3 CTMU Current Source,

100X Rang e —55— AIRNG<1:0>=11

VDD  3.0V

Note 1: Nominal value at center point of current trim range (CTMUICON<7:2>=000000).

PIC18(L)F2X/4XK22

DS41412F-page 446  2010-2012 Microchip Technology Inc.

FIGURE 27-5:

High/Low-Voltage Detect Characteristics

VHLVD

HLVDIF

VDD

(HLVDIF set by hardware)

(HLVDIF can be

cleared by sof tware)

TABLE 27-5: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

S tandard Operating Conditions (unless othe rwis e stated)

Operati ng tem pera ture -40°C  TA  +125°C

Param

No. Symbol Characteristic HLVDL<3:0> Min Typ† Max Units Conditions

HLVD V olt age on VDD

Transition High-to-

Low

0000 1.69 1.84 1.99 V

0001 1.92 2.07 2.22 V

0010 2.08 2.28 2.48 V

0011 2.24 2.44 2.64 V

0100 2.34 2.54 2.74 V

0101 2.54 2.74 2.94 V

0110 2.62 2.87 3.12 V

0111 2.76 3.01 3.26 V

1000 3.00 3.30 3.60 V

1001 3.18 3.48 3.78 V

1010 3.44 3.69 3.94 V

1011 3.66 3.91 4.16 V

1100 3.90 4.15 4.40 V

1101 4.11 4.41 4.71 V

1110 4.39 4.74 5.09 V

1111 V(HLVDIN pin) v

† Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.

 2010-2012 Microchip Technology Inc. DS41412F- page 447

PIC18(L)F2X/4XK22

27.11 AC (Timin g) Characteristics

27.11.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created

using one of the following formats:

1. TppS2ppS 3. TCC:ST (I2C™ specifications only)

2. TppS 4. Ts (I2C specifications only)

TF Frequency T Time

Lowercase letters (pp) and their meanings:

pp cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T13CKI

mc MCLR wr WR

Uppe rcase lett ers and their meanings:

SF Fall P Period

HHigh RRise

I Invalid (High-impedance) V Valid

L Low Z High-impedance

I2C only

AA outpu t access High High

BUF Bus free Low Low

TCC:ST (I2C specifications only)

CC HD Hold SU Setup

ST DAT DATA input hold STO Stop condition

STA Start condition

PIC18(L)F2X/4XK22

DS41412F-page 448  2010-2012 Microchip Technology Inc.

27.11.2 TIMING CONDITIONS

The temperature and voltages specified in Table 27-6

apply to all timing specifications unless otherwise

noted. Figure 27-6 specifies the load conditions for the

timing specification s.

TABLE 27-6: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

FIGURE 27-6: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

AC CHARACTERISTICS

S tandard Operating Conditions (unle ss otherwis e stated)

Operating temperature -40°C  TA +125°C

Operating voltage VDD range as described in Section 27.1 “DC Characteristics:

Supply Voltage , PIC18(L)F2X/4XK22” and Section 27.9 “M emory Programming

Requirements”.

VDD/2

VSS

RL=464

CL= 50 pF for all pi ns except OSC2/CLKOUT

and including D and E outputs as ports

Load Condition 1 Load Condition 2

Legend:

 2010-2012 Microchip Technology Inc. DS41412F- page 449

PIC18(L)F2X/4XK22

27.11.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 27-7: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

23344

TABLE 27-7: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.

No. Symbol Characteristic Min Max Units Conditions

1A FOSC Externa l CLKI N

Frequency(1) DC

0.5

MHz

EC, ECIO Oscillator mode (low power)

EC, ECIO Oscillator mode (me dium power)

EC, ECIO Oscillator mode (high power)

Oscillator Frequency(1) DC 4 MHz RC Oscillator mode

5 200 kHz LP Oscillator mode

0.1 4 MHz XT Oscillator mode

4 4 MHz HS Oscillator mode, VDD < 2.7V

4 16 MHz HS Oscillator mode, VDD 2.7V,

Medium-Power mode (HSMP)

4 20 MHz HS Oscillator mode, VDD 2.7V,

High-Power mo de (HSHP)

OSC External CLKIN Period(1) 2.0

62.5

15.6

—

s

EC, ECIO Oscillator mode (low power)

EC, ECIO Oscillator mode (me dium power)

EC, ECIO Oscillator mode (high power)

Oscillator Period(1) 250 — ns RC Oscillator mode

5 200 s LP Oscillator mode

0.25

250 10

250 s

ns XT Oscillator mode

HS Oscillator mode, VDD < 2.7V

62.5 250 ns HS Oscillator mode, VDD 2.7V,

Medium-Power mode (HSMP)

50 250 ns HS Oscillator mode, VDD 2.7V,

High-Power mo de (HSHP)

CY Instruction Cycle Time(1) 62.5 — ns TCY = 4/FOSC

OSL,

TOSHExternal Clock in (OSC1)

High or Low Time 2.5 — s LP Oscillator mode

30 — ns XT Oscillator mode

10 — ns HS Oscillator mode

OSR,

TOSFExternal Clock in (OSC1)

Rise or Fall Time — 50 ns LP Oscillator mode

— 20 ns XT Oscillator mode

— 7.5 ns HS Oscillator mode

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All

specified values are based on characterization data for that particular oscillator type under standard operating condi-

tions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation

and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external

clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no

clock) for all devices.

PIC18(L)F2X/4XK22

DS41412F-page 450  2010-2012 Microchip Technology Inc.

TABLE 27-8: PLL CLOCK TIMING SPECIFICATIONS

Param.

No. Sym Characteristic Min Max Units Conditions

F10 FOSC Oscillator Frequency Range 4 5 MHz VDD < 2.7V,

-40° C t o +85°C

44MHz

VDD < 2.7V,

+85°C to +125°C

416MHz

2.7V  VDD,

-40° C t o +85°C

412MHz

2.7V  VDD,

+85°C to +125°C

F11 FSYS On-Chip VCO System Frequency 16 20 MHz VDD < 2.7V,

-40° C t o +85°C

16 16 MHz VDD < 2.7V,

+85°C to +125°C

16 64 MHz 2.7V  VDD,

-40° C t o +85°C

16 48 MHz 2.7V  VDD,

+85°C to +125°C

F12 trc PLL Start-up Time (Lock Time) — 2 ms

TABLE 27-9: AC CHARACTERISTICS:INTERNAL OSCILLATORS ACCURACY PIC18(L)F46K22

S tandard Operating Conditions (unless othe rwis e stated)

Operati ng tem pera ture -40°C  TA  +125°C

Param.

No. Characteristics Freq.

Tolerance Min Typ† Max Units Conditions

OA1 Internal Calibrated

HFINTOSC Frequency(1)  2% — 16 .0 — MHz 0°C TA +60°C, VDD 2.5V

 3% — 16 . 0 — MHz +60°C TA +85°C, VDD 2.5V

 5% — 16 .0 — MHz -40°C TA +125°C

OA2 Internal Calibrated

MFINTOSC Frequency(1)  2% — 500 — kHz 0°C TA +60°C, VDD 2.5V

 3% — 5 00 — kHz +60°C TA +85°C, VDD 2.5V

 5% — 5 00 — kHz -40°C TA +125°C

OA3 Internal Calibrated

LFINTOSC Frequency(1)  20% — 31 — kHz -40°C TA +125°C

† Data in “Typ” column is at 3. 0V, 25°C unless oth erwis e s t ate d. Th ese parameters are for des ig n gu ida nc e

only and are not tested.

Note 1: To ensure these osc il lat or freq uen cy tol eran ce s, VDD and VSS must be capacitively decoupled as close to

the device as possible. 0.1 F and 0.01 F values in parallel are recommended.

 2010-2012 Microchip Technology Inc. DS41412F- page 451

PIC18(L)F2X/4XK22

FIGURE 27-8: CLKOUT AND I/O TIMING

Note: Refer to Figure 27-6 for load conditions.

OSC1

CLKOUT

I/O pin

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

13 14

20, 21

19 18

Old Value New Value

TABLE 27-10: CLKOUT AND I/O TIMING REQUIREMENTS

Param.

No. Symbol Characteristic Min Typ Max Units Conditions

10 TosH2ckL OSC1  to CLKOUT  — 75 200 ns (Note 1)

11 TosH2ckH OSC1  to CLKOUT  — 75 200 ns (Note 1)

12 TckR CLKOUT Rise Time — 35 100 ns (Note 1)

13 TckF CLKOUT Fall Time — 35 100 ns (Note 1)

14 TckL2ioV CLKOUT  to Port Out Valid — — 0.5 TCY + 20 n s (Note 1)

15 TioV2ckH Port In Valid before CLKOUT  0.25 TCY + 25 — — ns (Note 1)

16 TckH2ioI P ort In Hold after CLKOUT  0——ns(Note 1)

17 TosH2ioV OSC1  (Q1 cycle) to Port Out Valid — 50 150 ns

18 TosH2ioI OSC1  (Q2 cycle) to Port Input Invalid

(I/O in hold time) 100 — — ns

19 TioV2osH Port Input V alid to OSC1 (I/O in setup time) 0 — — ns

20 TioR Port Outpu t Rise Time —

—40

15 72

32 ns

ns VDD = 1.8V

VDD = 3.3V - 5.0V

21 TioF Por t Output Fall Time —

—28

15 55

30 ns

ns VDD = 1.8V

VDD = 3.3V - 5.0V

22† TINP INTx pin High or Low Time 20 — — ns

23† TRBP RB<7:4> Change KBIx High or Low Time TCY ——ns

† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC.

PIC18(L)F2X/4XK22

DS41412F-page 452  2010-2012 Microchip Technology Inc.

FIGURE 27-9: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

FIGURE 27-10: BROWN-OUT RESET TIMING

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

I/O pins

Note: Refer to Figure 27-6 for load conditions.

VDD BVDD

35 VBGAP = 1.2V

VIVRST

Enable Internal

Internal Reference 36

Reference V olt age

Voltage Stable

 2010-2012 Microchip Technology Inc. DS41412F- page 453

PIC18(L)F2X/4XK22

Note 1: Minimum pulse width that will consistently trigger a reset or interrupt. Shorter pulses may intermittently trigger a response.

FIGURE 27-11: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 27-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Param.

No. Symbol Characteristic Min Typ Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2 — — s

31 TWDT Watchdog Timer Time-out Period

(no postscaler) 3.5 4.1 4.7 ms 1:1 prescaler

32 TOST Oscillation Start-u p Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period

33 TPWRT Power-up Timer Period 54.8 64.4 74.1 ms

34 TIOZ I/O High-Impedance from MCLR

Low or Watchdog Timer Reset —2—s

35 TBOR Brown-out Reset Pulse Width 2001—— sVDD  BVDD (see

D005)

36 TIVRST Internal Reference Voltage Stable — 25 35 s

37 THLVD High/Low-V oltage Detect Pulse

Width 2001—— sVDD  VHLVD

38 TCSD CPU Start-up Time 5 — 10 s

39 TIOBST Time for HF-INTOSC to Stabilize — 0.25 1 ms

Note: Refer to Figure 27-6 for load conditions.

T0CKI

T1OSO/T13CKI

TMR0 or

TMR1

PIC18(L)F2X/4XK22

DS41412F-page 454  2010-2012 Microchip Technology Inc.

FIGURE 27-12: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)

TABLE 27-12: TIMER0 AND TIMER1/3/5 EXTERNAL CLOCK REQUIREMENTS

Param.

No. Symbol Characteristic Min Max Units Conditions

40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

41 Tt0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

42 Tt0P T0CKI Period No prescaler TCY + 10 — ns

With prescaler G reat er of:

20 ns or

(TCY + 40)/N

— ns N = prescale

value

(1, 2, 4,..., 256)

45 Tt1H TxCKI High

Time Synchronous, no prescaler 0.5 TCY + 20 — ns

Synchronous,

with prescaler 10 — ns

Asynchronous 30 — ns

46 Tt1L TxCKI Low

Time Synchronous, no prescaler 0.5 TCY + 5 — ns

Synchronous,

with prescaler 10 — ns

Asynchronous 30 — ns

47 Tt1P TxCKI Input

Period Synchronous Greater of:

20 ns or

(TCY + 40)/N

— ns N = prescale

value (1, 2, 4, 8)

Asynchronous 60 — ns

Ft1 TxCKI Clock Input Frequency Range DC 50 kHz

48 Tcke2tmrI Delay from External TxCKI Clock Edge to Timer

Increment 2 TOSC 7 TOSC —

Note: Refer to Figure 27-6 for load conditions.

CCPx

(Capture Mode)

50 51

CCPx

53 54

(Compare or PWM Mode)

 2010-2012 Microchip Technology Inc. DS41412F- page 455

PIC18(L)F2X/4XK22

FIGURE 27-13 : EX AMP L E SPI MA STER MODE TIMING (CKE = 0)

TABLE 27-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)

Param .

No. Symbol Characteristic Min Max Units Conditions

50 TccL CCPx Input Low

Time No prescaler 0.5 TCY + 20 — n s

With

prescaler 10 — ns

51 TccH CCPx Input

High Time No prescaler 0.5 TCY + 20 — ns

With

prescaler 10 — ns

52 TccP CCPx Input Period 3 TCY + 40

N—nsN = prescale

value (1, 4 or

16)

53 TccR CCPx Output Fall Time — 25 ns

54 TccF CCPx Output Fall Time — 25 ns

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76

MSb LSb

bit 6 - - - - - -1

MSb In LSb In

bit 6 - - - -1

Note: Refer to Figure 27-6 for load conditions.

PIC18(L)F2X/4XK22

DS41412F-page 456  2010-2012 Microchip Technology Inc.

FIGURE 27-14 : EXAMP L E SPI MA STER MODE TIMING (CKE = 1)

TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0 OR 1)

Param.

No. Symbol Characteristic Min Max Units Conditions

70 TssL2scH,

TssL2scL SS  to SCK  or SCK  Input TCY —ns

73 TdiV2scH,

TdiV2scL Setup Time of SDI Data Input to SCK Edge 25 — ns

74 TscH2diL,

TscL2diL Hold Time of SDI Data Input to SCK Edge 25 — ns

75 TdoR SDO Data Output Rise Time — 30 ns

76 TdoF SDO Data Output Fall Time — 20 ns

78 TscR SCK Output Rise Time

(Master mo de) —30ns

79 TscF SCK Output Fall Time (Master mode) — 20 ns

80 TscH2doV,

TscL2doV SDO Data Output Valid after SCK Edge — 20 ns

81 TdoV2scH,

TdoV2scL SDO Data Output Setup to SCK Edge TCY —ns

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76

MSb

MSb In

bit 6 - - - - - -1

LSb In

bit 6 - - - -1

LSb

Note: Refer to Figure 27-6 for load conditions.

 2010-2012 Microchip Technology Inc. DS41412F- page 457

PIC18(L)F2X/4XK22

FIGURE 27-15 : EXAMP L E SPI SLAVE MODE TIMING (CKE = 0)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76 77

SDI

MSb LSb

bit 6 - - - - - -1

MSb In bit 6 - - - -1 LSb In

Note: Refer to Figure 27-6 for load conditions.

TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0 OR 1)

Param.

No. Symbol Characteristic Min Max Units Conditions

70 TssL2scH,

TssL2scL SS  to SCK  or SCK  Input TCY —ns

71 TscH SCK Input High Ti m e Continuous 25 — ns

72 TscL SCK Input Low Time Continuous 30 — ns

73 TdiV2scH ,

TdiV2scL Setup Tim e of SDI Data Input to SCK Edge 25 — ns

74 TscH2diL,

TscL2diL Hold Time of SDI Data Input to SCK Edge 25 — ns

75 TdoR SDO Data Output Rise Time — 30 ns

76 TdoF SDO Data Output Fall Time — 20 ns

77 TssH2doZ SS to SDO Output High-Impedance 10 50 ns

80 TscH2doV,

TscL2doV SDO Data Output Valid after SCK Edge — 60 ns

82 TssL2doV SDO Data Output Valid after SS  Edge — 60 ns

83 TscH2ssH,

TscL2ssH SS  after SCK edge 1. 5 TCY + 40 — ns

PIC18(L)F2X/4XK22

DS41412F-page 458  2010-2012 Microchip Technology Inc.

FIGURE 27-16 : EXAMP L E SPI SLAVE MODE TIMING (CKE = 1)

FIGURE 27-17 : I2C™ BUS START/STOP BITS TIMING

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

SDI

75, 76

MSb bit 6 - - - - - -1 LS b

MSb In bit 6 - - - -1 LSb In

Note: Re fe r to Figure 27-6 for load conditions.

Note: Refer to Figure 27-6 for load conditions.

SCL

SDA

Start

Condition Stop

Condition

 2010-2012 Microchip Technology Inc. DS41412F- page 459

PIC18(L)F2X/4XK22

FIGURE 27-18 : I2C™ BUS DATA TIMING

TABLE 27-16: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

Param.

No. Symbol Characteristic Min Max Units Conditions

90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated

Start condition

Setup Time 400 kHz mode 600 —

91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first

clock pulse is generated

Hold Time 400 kHz mode 600 —

92 TSU:STO Stop Condition 100 kHz mode 4700 — ns

Setup Time 400 kHz mode 600 —

93 THD:STO Stop Conditio n 100 kHz mode 4000 — ns

Hold Time 400 kHz mode 600 —

Note: Refer to Figure 27-6 for load conditions.

91 92

100

101

103

106 107

109 109 110

102

SCL

SDA

Out

PIC18(L)F2X/4XK22

DS41412F-page 460  2010-2012 Microchip Technology Inc.

TABLE 27-17: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

No. Symbol Characteristic Min Max Units Conditions

100 THIGH Clock High Time 100 kHz mode 4.0 — s Must operate at a minimum

of 1.5 MHz

400 kHz mode 0. 6 — s Must operate at a minimum

of 10 MHz

SSP Module 1.5 TCY —

101 TLOW Clock Low Time 100 kHz mode 4.7 — s Must operate at a minimum

of 1.5 MHz

400 kHz mode 1. 3 — s Must operate at a minimum

of 10 MHz

SSP Module 1.5 TCY —

102 TRSDA and S CL Rise

Time 100 kHz mode — 1000 ns

400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from

10 to 400 pF

103 TFSDA and SCL Fall

Time 100 kHz mode — 300 ns

400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from

10 to 400 pF

90 TSU:STA Start Condition

Setup Time 100 kHz mode 4 .7 — s Only relevant for Repeated

Start condition

400 kHz mode 0. 6 — s

91 THD:STA Start Condition

Hold Time 100 kHz mode 4.0 — s After this period, the first

clock pulse is generated

400 kHz mode 0. 6 — s

106 THD:DA

TData Input Hold

Time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 s

107 TSU:DAT Data Input Setup

Time 100 kHz mode 250 — ns (Note 2)

400 kHz mode 100 — ns

92 TSU:STO Stop Condition

Setup Time 100 kHz mode 4 .7 — s

400 kHz mode 0. 6 — s

109 TAA Output Valid from

Clock 100 kHz mode — 3500 ns (Note 1)

400 kHz mode — — ns

110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free

before a new transmi s sion

can start

400 kHz mode 1. 3 — s

D102 CBBus Capacitive Loading — 400 pF

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A fast mode I2C bus device can be us ed in a standard mode I2C bus sy ste m but the requ ire me nt,

TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the

standard mode I2C bus specification), before the SCL line is released.

 2010-2012 Microchip Technology Inc. DS41412F- page 461

PIC18(L)F2X/4XK22

FIGURE 27-19: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS

FIGURE 27-20: MASTER SSP I2C™ BUS DATA TIMING

Note: Refer to Figure 27-6 for load conditions.

91 93

SCL

SDA

Start

Condition Stop

Condition

90 92

TABLE 27-18: MASTER SSP I2C™ BUS ST ART/STOP BITS REQUIREMENTS

Param.

No. Symbol Characteristic Min Max Units Conditions

90 TSU:STA Start Condition 100 k Hz mode 2(TOSC)(BRG + 1) — ns Only relevant for

Repeated Start

condition

Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

91 THD:STA Star t Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the

first clock puls e is

generated

Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns

Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — n s

Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

Note 1: Maximum pin capacitance = 10 pF for all I2C pins.

Note: Refer to Figure 27-6 for load conditions.

90 91 92

100 101

103

106 107

109 109 110

102

SCL

SDA

Out

PIC18(L)F2X/4XK22

DS41412F-page 462  2010-2012 Microchip Technology Inc.

TABLE 27-19: MASTER SSP I2C™ BUS DATA REQUIREMENTS

Param.

No. Symbol Characteristic Min Max Units Conditions

100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

102 TRSDA and SCL

Rise Time 100 kHz mode — 1000 ns CB is specified to be

from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) — 300 ns

103 TFSDA and SCL

Fall Time 100 kHz mode — 300 ns CB is specified to be

from

10 to 400 pF

400 kHz mode 20 + 0.1 CB 300 ns

1 MHz mode(1) — 100 ns

90 TSU:STA Start Condition

Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms Only releva nt for

Repeated Start

condition

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

91 THD:STA Start Conditi on

Hold Time 100 kHz mode 2(TOSC)(BRG + 1) — ms Af ter this period, the first

clock pulse is generated

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

106 THD:DAT Data Input

Hold Time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 ms

107 TSU:DAT Data Input

Setup Time 100 kHz mode 250 — ns (Note 2)

400 kHz mode 100 — ns

92 TSU:STO Stop Condition

Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

109 TAA Output Valid

from Clock 100 kHz mode — 3500 ns

400 kHz mode — 1000 ns

1 MHz mode(1) ——ns

110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be

free before a new trans-

mission can start

400 kHz mode 1.3 — ms

D102 CBBus Capacitive Loading — 400 pF

Note 1: Maximum pin capacitance = 10 pF for all I2C pins.

2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter 107 250 ns

must then be met. This will automatically be the case if the device does not stretch the Low period of the

SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit

to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (f or 10 0 kHz mo de), before the

SCL line is released.

 2010-2012 Microchip Technology Inc. DS41412F- page 463

PIC18(L)F2X/4XK22

FIGURE 27-21: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

FIGURE 27-22: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

121 121

120 122

TXx/CKx

RXx/DTxpin

Note: Refer to Figure 27-6 for load conditions.

TABLE 27-20: EUSART SYNCHRONOUS TRANSMISSION REQUIREM ENTS

Param.

No. Symbol Characteristic Min Max Units Conditions

120 Tc kH2dtV SYNC XMIT (MASTER & SLAVE)

Clock High to Data Out Valid —40ns

121 Tckrf Clock Out Rise Time and Fall Time

(Master mode) —20ns

122 Tdtrf Data Out Rise Time and Fall Time —20ns

125

126

TXx/CKx

RXx/DTx

Note: Refer to Figure 27-6 for load conditions.

TABLE 27-21: EUSART SYNCHRONOUS RECE IV E REQUIREME NTS

Param.

No. Symbol Characteristic Min Max Units Conditions

125 TdtV2ckl SYNC RCV (MASTER & SLAVE)

Data Setup before CK  (DT setup time) 10 — ns

126 TckL2dtl Data Hold after CK  (DT hold time) 15 — ns

PIC18(L)F2X/4XK22

DS41412F-page 464  2010-2012 Microchip Technology Inc.

FIGURE 27-23: A/D CONVERSION TIMING

TABLE 27-22: A/D CONVERTER CHARACTERISTICS:PIC18(L)F2X/4XK22

PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated)

Operating temperature Tested at +25°C

Param.

No. Symbol Characteristic Min Typ Max Units Conditions

A01 NRResolution — — 10 bits VREF  3.0V

A03 EIL Integral Linearity Error — ±0.5 ±1 LSb VREF = 3.0V

A04 EDL Differential Linearity Error — ±0.5 ±1 LSb VREF  3.0V

A06 EOFF Offs et Error — ±0.7 ±2 LSb VREF  3.0V

A07 EGN Gain Error — ±0.7 ±2 LSb VREF  3.0V

A08 ETOTL Tota l Error — ±0.8 ±3 LSb VREF  3.0V

A20 VREF Reference Voltage Range

(VREFH – VREFL)2—V

DD V

A21 VREFH Refe rence Voltage High VDD/2 — VDD + 0.3 V

A22 VREFL Refe rence Voltage Low VSS – 0.3V — VDD/2 V

A25 VAIN Analog Input Voltage VREFL —VREFH V

A30 ZAIN Recommended Impedance of

Analog Voltage Source —— 3k

Note: The A/D conversion res ult never decreas es with an increa se in the input v oltage and has no missing codes .

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

987 21 0

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEP instruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

.. . . . .

TCY

 2010-2012 Microchip Technology Inc. DS41412F- page 465

PIC18(L)F2X/4XK22

TABLE 27-23: A/D CONVERSION REQUIREMENTS PIC18(L)F2X/4XK22

S tandard Operating Conditions (unless othe rwis e stated)

Operating temperature Tested at +25°C

Param.

No. Symbol Characteristic Min Typ Max Units Conditions

130 TAD A/D Clock Period 1 — 25 s-40C to +85C

1— 4s+85C to +125C

131 TCNV Conversion Time

(not including acquisition time) (Note 1) 12 — 12 TAD

132 TACQ Acquisition Time (Note 2) 1.4 — — sVDD = 3V, Rs = 50

135 TSWC Switching Time from Convert  Sample — — (Note 3)

136 TDIS Discharge Time 2 — 2 TAD

Note 1: ADRES register may be read on the following TCY cycle.

2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the con-

versi o n (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50 .

3: On the following cycle of the device clock.

PIC18(L)F2X/4XK22

DS41412F-page 466  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 467

PIC18(L)F2X/4XK22

28.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS

Note: The grap hs and tables prov id ed following th is n ote are a statistic al s umm ary based on a l im ite d num be r of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g. outside specified power supply range) and therefore, outside the warranted range.

PIC18(L)F2X/4XK22

DS41412F-page 468  2010-2012 Microchip Technology Inc.

FIGURE 28-1: PIC18LF2X/4XK22 BASE IPD

FIGURE 28-2: PIC18F2X/4XK22 BASE IPD

Typ. 25°C

Typ. 60°C

Max. 85°C

Limited Accuracy

0.001

0.01

0.1

1.8 2.1 2.4 2.7 3 3.3

3.6

(µA)

(V)

Typ. 25°C

Typ. 60°C

Max. 85°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

ΔI

(µA)

VDD (V)

 2010-2012 Microchip Technology Inc. DS41412F- page 469

PIC18(L)F2X/4XK22

FIGURE 28-3: PIC18LF2X/4XK22 DELTA IPD WATCHDOG TIMER (WDT)

FIGURE 28-4: PIC18F2X/4XK22 DELTA IPD WATCHDOG TIMER (WDT)

Typ.

Max.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

1.8 2.1 2.4 2.7 3 3.3

3.6

ΔI

(µA)

(V)

Typical

Max.

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

ΔI

(µA)

VDD (V)

PIC18(L)F2X/4XK22

DS41412F-page 470  2010-2012 Microchip Technology Inc.

FIGURE 28-5: PIC18LF2X/4XK22 DELTA IPD BROWN-OUT RESET (BOR)

FIGURE 28-6: PIC18F2X/4XK22 DELTA IPD BROWN-OUT RESET (BOR)

Typical

Max. 85°C

1.8 2.1 2.4 2.7 3 3.3

3.6

ΔI

(µA)

VDD (V)

Typical

Max. 85°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

ΔI

(µA)

VDD (V)

 2010-2012 Microchip Technology Inc. DS41412F- page 471

PIC18(L)F2X/4XK22

FIGURE 28-7: PIC18LF2X/4XK22 DELTA IPD HIGH/LOW-VOLTAGE DETECT (HLVD)

FIGURE 28-8: PIC18F2X/4XK22 DELTA IPD HIGH/LOW-VOLTAGE DETECT (HLVD)

Typical

Max.

1.8 2.1 2.4 2.7 3 3.3 3.6

ΔI

(µA)

(V)

Typical

Max.

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

ΔI

(µA)

VDD (V)

PIC18(L)F2X/4XK22

DS41412F-page 472  2010-2012 Microchip Technology Inc.

FIGURE 28-9: PIC18LF2X/4XK22 DELTA IPD SECONDARY OSCILLATOR

FIGURE 28-10: PIC18F2X/4XK22 DELTA IPD SECONDARY OSCILLATOR

Typ. 25°C

Typ. 60°C

Max. 85°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

1.8 2.1 2.4 2.7 3 3.3

3.6

ΔI

(µA)

(V)

Typical

Max. 85°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

ΔI

(µA)

VDD (V)

 2010-2012 Microchip Technology Inc. DS41412F- page 473

PIC18(L)F2X/4XK22

FIGURE 28-11: PIC18LF2X/4XK22 DELTA IPD COMPARATOR LOW-POWER MODE

FIGURE 28-12: PIC18F2X/4XK22 DELTA IPD COMPARATOR LOW-POWER MODE

Typical

Max.

1.8 2.1 2.4 2.7 3 3.3

3.6

ΔI

(µA)

(V)

Typical

Max.

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

ΔI

(µA)

VDD (V)

PIC18(L)F2X/4XK22

DS41412F-page 474  2010-2012 Microchip Technology Inc.

FIGURE 28-13: PIC18LF2X/4XK22 DELTA IPD COMPARATOR HIGH-POWER MODE

FIGURE 28-14: PIC18F2X/4XK22 DELTA IPD COMPARATOR HIGH-POWER MODE

Typ.

Max.

100

120

1.8 2.1 2.4 2.7 3 3.3

3.6

ΔI

(µA)

(V)

Typical

Max.

100

120

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

ΔI

(µA)

VDD (V)

 2010-2012 Microchip Technology Inc. DS41412F- page 475

PIC18(L)F2X/4XK22

FIGURE 28-15: PIC18LF2X/4XK22 DELTA IPD DAC

FIGURE 28-16: PIC18F2X/4XK22 DELTA IPD DAC

Typical

Max.

1.8 2.1 2.4 2.7 3 3.3 3.6

ΔI

(µA)

(V)

Typical

Max.

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

ΔI

(µA)

VDD (V)

PIC18(L)F2X/4XK22

DS41412F-page 476  2010-2012 Microchip Technology Inc.

FIGURE 28-17: PIC18LF2X/4XK22 DELTA IPD FVR

FIGURE 28-18: PIC18F2X/4XK22 DELTA IPD FVR

Typ. 25°C

Typ. 60°C

Max.

1.8 2.1 2.4 2.7 3 3.3

3.6

ΔI

(µA)

(V)

Typical

Max.

100

120

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

ΔI

(µA)

VDD (V)

Note 1: On the PIC18F2X/4XK22, enabling the FVR results in significantly more

Sleep current when the part enters Voltage Regulation mode at VDD ~ 3.2V.

 2010-2012 Microchip Technology Inc. DS41412F- page 477

PIC18(L)F2X/4XK22

FIGURE 28-19: PIC18(L)F2X/4XK22 DELTA IDD A/D CONVERTOR1

Typical

Max.

100

150

200

250

300

350

400

450

500

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

ΔI

(µA)

VDD (V)

Note 1: A/D converter differential currents apply only in Run mode. In Sleep or Idle mode, both the

ADC and the FRC turn off as soon as conversion (if any) is complete.

PIC18(L)F2X/4XK22

DS41412F-page 478  2010-2012 Microchip Technology Inc.

FIGURE 28-20: PIC18LF2X/4XK22 TYPICAL IDD: RC_RUN LF-INTOSC 31 kHz

FIGURE 28-21: PIC18LF2X/4XK22 MAXIMUM IDD: RC_RUN LF-INTOSC 31 kHz

-40°C

25°C

85°C

125°C

1.8 2.1 2.4 2.7 3 3.3

3.6

(µA)

VDD (V)

-40°C

25°C

85°C

125°C

1.8 2.1 2.4 2.7 3 3.3

3.6

(µA)

VDD (V)

 2010-2012 Microchip Technology Inc. DS41412F- page 479

PIC18(L)F2X/4XK22

FIGURE 28-22: PIC18F2X/4XK22 TYPICAL IDD: RC_RUN LF-INTOSC 31 kHz

FIGURE 28-23: PIC18F2X/4XK22 MAXIMUM IDD: RC_RUN LF-INTOSC 31 kHz

-40°C

25°C

85°C

125°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(µA)

(V)

-40°C to +85°C

125°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(µA)

VDD (V)

PIC18(L)F2X/4XK22

DS41412F-page 480  2010-2012 Microchip Technology Inc.

FIGURE 28-24 : PIC 18LF2X /4X K22 IDD: RC_RUN MF-INTOSC 500 kHz

FIGURE 28-25 : PIC 18F2X /4X K22 IDD: RC_RUN MF-INTOSC 500 kHz

Typical

Max

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

Typical

Max.

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(mA)

VDD (V)

 2010-2012 Microchip Technology Inc. DS41412F- page 481

PIC18(L)F2X/4XK22

FIGURE 28-26: PIC18LF2X/4XK22 TYPICAL IDD: RC_RUN HF-INTOSC

FIGURE 28-27: PIC18LF2X/4XK22 MAXIMUM IDD: RC_RUN HF-INTOSC

1 MHz

2 MHz

4 MHz

8 MHz

16 MHz

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

1 MHz

2 MHz

4 MHz

8 MHz

16 MHz

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

VDD (V)

PIC18(L)F2X/4XK22

DS41412F-page 482  2010-2012 Microchip Technology Inc.

FIGURE 28-28: PIC18F2X/4XK22 TYPICAL IDD: RC_RUN HF-INTOSC

FIGURE 28-29: PIC18F2X/4XK22 MAXIMUM IDD: RC_RUN HF-INTOSC

1 MHz

2 MHz

4 MHz

8 MHz

16 MHz

0.5

1.5

2.5

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

VDD (V)

1 MHz

2 MHz

4 MHZ

8 MHz

16 MHz

0.5

1.5

2.5

3.5

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

 2010-2012 Microchip Technology Inc. DS41412F- page 483

PIC18(L)F2X/4XK22

FIGURE 28-30: PIC18LF2X/4XK22 TYPICAL IDD: RC_RUN HF-INTOSC with PLL

FIGURE 28-31: PIC18LF2X/4XK22 MAXIMUM IDD: RC_RUN HF-INTOSC with PLL

16 MHz

32 MHz

64 MHz

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

16 MHz

32 MHz

64 MHz

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

PIC18(L)F2X/4XK22

DS41412F-page 484  2010-2012 Microchip Technology Inc.

FIGURE 28-32: PIC18F2X/4XK22 TYPICAL IDD: RC_RUN HF-INTOSC with PLL

FIGURE 28-33: PIC18F2X/4XK22 MAXIMUM IDD: RC_RUN HF-INTOSC with PLL

16 MHz

32 MHz

64 MHz

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

16 MHz

32 MHz

64 MHz

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

 2010-2012 Microchip Technology Inc. DS41412F- page 485

PIC18(L)F2X/4XK22

FIGURE 28-34: PIC18LF2X/4XK22 TYPICAL IDD: RC_IDLE LF-INTOSC 31 kHz

FIGURE 28-35: PIC18LF2X/4XK22 MAXIMUM IDD: RC_IDLE LF-INTOSC 31 kHz

-40°C

25°C

85°C

125°C

0.5

1.5

2.5

3.5

1.8 2.1 2.4 2.7 3 3.3 3.6

(µA)

(V)

25°C

85°C

125°C

1.8 2.1 2.4 2.7 3 3.3 3.6

(µA)

(V)

PIC18(L)F2X/4XK22

DS41412F-page 486  2010-2012 Microchip Technology Inc.

FIGURE 28-36: PIC18F2X/4XK22 TYPICAL IDD: RC_IDLE LF-INTOSC 31 kHz

FIGURE 28-37: PIC18F2X/4XK22 MAXIMUM IDD: RC_IDLE LF-INTOSC 31 kHz

-40°C

25°C

85°C

125°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(µA)

(V)

-40C

-40°C to +85°C

125°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(µA)

(V)

 2010-2012 Microchip Technology Inc. DS41412F- page 487

PIC18(L)F2X/4XK22

FIGURE 28-38 : PIC 18LF2X /4X K22 IDD: RC_IDLE MF-INTOSC 500 kHz

FIGURE 28-39 : PIC 18F2X /4X K22 IDD: RC_IDLE MF-INTOSC 500 kHz

Typical

Max.

0.05

0.1

0.15

0.2

0.25

0.3

1.8 2.1 2.4 2.7 3 3.3 3.6

(mA)

(V)

Typical

Max.

0.05

0.1

0.15

0.2

0.25

0.3

0.35

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(mA)

(V)

PIC18(L)F2X/4XK22

DS41412F-page 488  2010-2012 Microchip Technology Inc.

FIGURE 28-40: PIC18LF2X/4XK22 TYPICAL IDD: RC_IDLE HF-INTOS C

FIGURE 28-41: PIC18LF2X/4XK22 MAXIMUM IDD: RC_IDLE HF-INTOSC

1 MHz

2 MHz

4 MHz

8 MHz

16 MHz

0.2

0.4

0.6

0.8

1.2

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4

3.6

(mA)

VDD (V)

1 MHz

4 MHz

8 MHz

16 MHz

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4

3.6

(mA)

VDD (V)

 2010-2012 Microchip Technology Inc. DS41412F- page 489

PIC18(L)F2X/4XK22

FIGURE 28-42: PIC18F2X/4XK22 TYPICAL IDD: RC_IDLE HF-INTOSC

FIGURE 28-43: PIC18F2X/4XK22 MAXIMUM IDD: RC_IDLE HF-INTOSC

1 MHz

2 MHz

4 MHz

8 MHz

16 MHz

0.3

0.4

0.5

0.6

0.7

0.8

0.9

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

1 MHz

4 MHz

8 MHz

16 MHz

0.2

0.4

0.6

0.8

1.2

1.4

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(mA)

(V)

PIC18(L)F2X/4XK22

DS41412F-page 490  2010-2012 Microchip Technology Inc.

FIGURE 28-44: PIC18LF2X/4XK22 TYPICAL IDD: RC_IDLE HF-INTOSC with PLL

FIGURE 28-45: PIC18LF2X/4XK22 MAXIMUM IDD: RC_IDLE HF-INTOSC with PLL

16 MHz

32 MHz

64 MHz

0.5

1.5

2.5

3.5

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

16 MHz

32 MHz

64 MHz

0.5

1.5

2.5

3.5

4.5

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

 2010-2012 Microchip Technology Inc. DS41412F- page 491

PIC18(L)F2X/4XK22

FIGURE 28-46: PIC18F2X/4XK22 TYPICAL IDD: RC_IDLE HF-INTOSC with PLL

FIGURE 28-47: PIC18F2X/4XK22 MAXIMUM IDD: RC_IDLE HF-INTOSC with PLL

16 MHz

32 MHz

64 MHz

0.5

1.5

2.5

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

16 MHz

32 MHz

64 MHz

0.5

1.5

2.5

3.5

4.5

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

PIC18(L)F2X/4XK22

DS41412F-page 492  2010-2012 Microchip Technology Inc.

FIGURE 28-48: PIC18LF2X/4XK22 TYPICAL IDD: PRI_RUN EC MEDIUM POWER

FIGURE 28-49: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_RUN EC MEDIUM POWER

1 MHz

4 MHz

10 MHz

16 MHz

0.0

0.5

1.0

1.5

2.0

2.5

3.0

1.8 2.1 2.4 2.7 3 3.3 3.6

(mA)

(V)

1 MHz

4 MHz

10 MHz

16 MHz

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1.8 2.1 2.4 2.7 3 3.3 3.6

(mA)

(V)

 2010-2012 Microchip Technology Inc. DS41412F- page 493

PIC18(L)F2X/4XK22

FIGURE 28-50: PIC18F2X/4XK22 TYPICAL IDD: PRI_RUN EC MEDIUM POWER

FIGURE 28-51: PIC18F2X/4XK22 MAXIMUM IDD: PRI_RUN EC MEDIUM POWER

1 MHz

4 MHz

10 MHz

16 MHz

0.5

1.5

2.5

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

1 MHz

4 MHz

10 MHz

16 MHz

0.5

1.5

2.5

3.5

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

PIC18(L)F2X/4XK22

DS41412F-page 494  2010-2012 Microchip Technology Inc.

FIGURE 28-52: PIC18LF2X/4XK22 TYPICAL IDD: PRI_RUN EC HIGH POWER

FIGURE 28-53: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_RUN EC HIGH POWER

4 MHz

10 MHz

16 MHz

20 MHz

40 MHz

64 MHz

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

4 MHz

10 MHz

16 MHz

20 MHz

40 MHz

64 MHz

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

 2010-2012 Microchip Technology Inc. DS41412F- page 495

PIC18(L)F2X/4XK22

FIGURE 28-54: PIC18F2X/4XK22 TYPICAL IDD: PRI_RUN EC HIGH POWER

FIGURE 28-55: PIC18F2X/4XK22 MAXIMUM IDD: PRI_RUN EC HIGH POWER

4 MHz

10 MHz

16 MHz

20 MHz

40 MHz

64 MHz

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

VDD (V)

4 MHz

10 MHz

16 MHz

20 MHz

40 MHz

64 MHz

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

VDD (V)

PIC18(L)F2X/4XK22

DS41412F-page 496  2010-2012 Microchip Technology Inc.

FIGURE 28-56: PIC18LF2X/4XK22 TYPICAL IDD: PRI_RUN EC with PLL

FIGURE 28-57: PIC18LF2X/4XK22 MAXIMIUM IDD: PRI_RUN EC with PLL

16 MHz

32 MHz

64 MHz

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

16 MHz

32 MHz

64 MHz

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

 2010-2012 Microchip Technology Inc. DS41412F- page 497

PIC18(L)F2X/4XK22

FIGURE 28-58: PIC18F2X/4XK22 TYPICAL IDD: PRI_RUN EC with PLL

FIGURE 28-59: PIC18F2X/4XK22 MAXIMUM IDD: PRI_RUN EC with PLL

16 MHz

32 MHz

64 MHz

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

16 MHz

32 MHz

64 MHz

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

PIC18(L)F2X/4XK22

DS41412F-page 498  2010-2012 Microchip Technology Inc.

FIGURE 28-60: PIC18LF2X/4XK22 TYPICAL IDD: PRI_IDLE EC MEDIUM POWE R

FIGURE 28-61: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_IDLE EC MEDIUM POWER

1 MHz

4 MHz

10 MHz

16 MHz

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.8 2.1 2.4 2.7 3 3.3 3.6

(mA)

(V)

1 MHz

4 MHz

10 MHz

16 MHz

0.2

0.4

0.6

0.8

1.2

1.8 2.1 2.4 2.7 3 3.3 3.6

(mA)

(V)

 2010-2012 Microchip Technology Inc. DS41412F- page 499

PIC18(L)F2X/4XK22

FIGURE 28-62: PIC18F2X/4XK22 TYPICAL IDD: PRI_IDLE EC MEDIUM POWER

FIGURE 28-63: PIC18F2X/4XK22 MAXIMUM IDD: PRI_IDLE EC MEDI UM POWE R

1 MHz

4 MHz

10 MHz

16 MHz

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(mA)

(V)

1 MHz

4 MHz

10 MHz

16 MHz

0.2

0.4

0.6

0.8

1.2

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(mA)

(V)

PIC18(L)F2X/4XK22

DS41412F-page 500  2010-2012 Microchip Technology Inc.

FIGURE 28-64: PIC18LF2X/4XK22 TYPICAL IDD: PRI_IDLE EC HIGH POWER

FIGURE 28-65: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_IDLE EC HIGH POWER

4 MHz

10 MHz

16 MHz

20 MHz

40 MHz

64 MHz

0.5

1.5

2.5

3.5

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

4 MHz

10 MHz

16 MHz

20 MHz

40 MHz

64 MHz

0.5

1.5

2.5

3.5

4.5

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

 2010-2012 Microchip Technology Inc. DS41412F- page 501

PIC18(L)F2X/4XK22

FIGURE 28-66: PIC18F2X/4XK22 TYPICAL IDD: PRI_IDLE EC HIGH POWER

FIGURE 28-67: PIC18F2X/4XK22 MAXIMUM IDD: PRI_IDLE EC HIGH POWER

4 MHz

10 MHz

16 MHz

20 MHz

40 MHz

64 MHz

0.5

1.5

2.5

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

4 MHz

10 MHz

16 MHz

20 MHz

40 MHz

64 MHz

0.5

1.5

2.5

3.5

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

PIC18(L)F2X/4XK22

DS41412F-page 502  2010-2012 Microchip Technology Inc.

FIGURE 28-68: PIC18LF2X/4XK22 TYPICAL IDD: PRI_IDLE EC with PLL

FIGURE 28-69: PIC18LF2X/4XK22 MAXIMUM IDD: PRI_IDLE EC with PLL

16 MHz

32 MHz

64 MHz

0.5

1.5

2.5

3.5

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

16 MHz

32 MHz

64 MHz

0.5

1.5

2.5

3.5

4.5

1.8 2.1 2.4 2.7 3 3.3

3.6

(mA)

(V)

 2010-2012 Microchip Technology Inc. DS41412F- page 503

PIC18(L)F2X/4XK22

FIGURE 28-70: PIC18F2X/4XK22 TYPICAL IDD: PRI_IDLE EC with PLL

FIGURE 28-71: PIC18F2X/4XK22 MAXIMUM IDD: PRI_IDLE EC with PLL

16 MHz

32 MHz

64 MHz

0.5

1.5

2.5

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

16 MHz

32 MHz

64 MHz

0.5

1.5

2.5

3.5

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(mA)

(V)

PIC18(L)F2X/4XK22

DS41412F-page 504  2010-2012 Microchip Technology Inc.

FIGURE 28-72: PIC18LF2X/4XK22 TYPICAL IDD: SEC_RUN 32.768 kHz

FIGURE 28-73: PIC18LF2X/4XK22 MAXIMUM IDD: SEC_RUN 32.768 kHz

-40°C

25°C

60°C

85°C

125°C

1.8 2.1 2.4 2.7 3 3.3

3.6

(µA)

(V)

-40°C

25°C

85°C

1.8 2.1 2.4 2.7 3 3.3

3.6

(µA)

(V)

 2010-2012 Microchip Technology Inc. DS41412F- page 505

PIC18(L)F2X/4XK22

FIGURE 28-74: PIC18F2X/4XK22 TYPICAL IDD: SEC_RUN 32.768 kHz

FIGURE 28-75: PIC18F2X/4XK22 MAXIMUM IDD: SEC_RUN 32.7 68 k Hz

-40°C

25°C

85°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(µA)

(V)

-40°C to +85°C

125°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(µA)

(V)

PIC18(L)F2X/4XK22

DS41412F-page 506  2010-2012 Microchip Technology Inc.

FIGURE 28-76: PIC18LF2X/4XK22 TYPICAL IDD: SEC_IDLE 32.768 kHz

FIGURE 28-77: PIC18LF2X/4XK22 MAXIMUM IDD: SEC_IDLE 32.768 kHz

-40°C

25°C

60°C

85°C

0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

2.1

2.3

1.8 2.1 2.4 2.7 3 3.3

3.6

(µA)

(V)

-40°C

25°C

85°C

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4

3.6

(µA)

VDD (V)

 2010-2012 Microchip Technology Inc. DS41412F- page 507

PIC18(L)F2X/4XK22

FIGURE 28-78: PIC18F2X/4XK22 TYPICAL IDD: SEC_IDLE 32.768 kHz

FIGURE 28-79: PIC18F2X/4XK22 MAXIMUM IDD: SEC_IDLE 32.768 kHz

-40°C

25°C

85°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(µA)

(V)

-40°C to +85°C

125°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

5.5

(µA)

VDD (V)

PIC18(L)F2X/4XK22

DS41412F-page 508  2010-2012 Microchip Technology Inc.

FIGURE 28-80: PIC18(L)F2X/4XK22 TTL BUFFER INPUT LOW VOLTAGE

FIGURE 28-81: PIC18(L)F2X/4XK22 SCHMITT TRIGGER BUFFER INPUT LOW VOLTAGE

-40°C

25°C

85°C

125°C

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5

5.4

(V)

Max.

-40°C

25°C

85°C

125°C

Max.

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

(V)

VDD (V)

 2010-2012 Microchip Technology Inc. DS41412F- page 509

PIC18(L)F2X/4XK22

FIGURE 28-82: PIC18(L)F2X/4XK22 TTL BUFFER INPUT HIGH VOLTAGE

FIGURE 28-83: PIC18(L)F2X/4XK22 SCHMITT TRIGGER BUFFER INPUT HIGH VOLTAGE

-40°C

25°C

85°C

125°C

0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

2.1

1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5

5.4

(V)

VDD (V)

Min.

-40°C

25°C

85°C

125°C

Min.

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 5.4

(V)

VDD (V)

PIC18(L)F2X/4XK22

DS41412F-page 510  2010-2012 Microchip Technology Inc.

FIGURE 28-84: PIC18(L)F2X/ 4XK22 PIN INPUT LEAKAGE

Typical

Max.

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120

125

Input Leakage (A)

Temperature (°C)

 2010-2012 Microchip Technology Inc. DS41412F- page 511

PIC18(L)F2X/4XK22

FIGURE 28-85: PIC18(L)F2X/4XK22 OUTPUT LOW VOLTAGE

FIGURE 28-86: PIC18(L)F2X/4XK22 OUTPUT HIGH VOLTAGE

0.2

0.4

0.6

0.8

1.2

1.4

1.6

0 5 10 15 20 25

(V)

(mA)

Typ. 5V

Typ. 3V

Typ. 2V

Max. 2V

Max. 3V

Max. 5V

0 5 10 15 20

(V)

(mA)

Typ. 5V

Min. 5V

Typ. 3V

Min. 3V

Min. 2V Typ. 2V

PIC18(L)F2X/4XK22

DS41412F-page 512  2010-2012 Microchip Technology Inc.

FIGURE 28-87: PIC18(L)F2X/4XK22 COMPARATOR OFFSET VOLTAGE,

NORMAL-POWER MODE; VDD=5.5V

FIGURE 28-88: PIC18(L)F2X/4XK22 COMPARATOR OFFSET VOLTAGE,

NORMAL-POWER MODE; VDD=3.0V

6 sigma

Typical

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

5.5

Abs. Offset (mV)

REF

(V)

6 sigma

Typical

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8

3.0

Abs. Offset (mV)

REF

(V)

 2010-2012 Microchip Technology Inc. DS41412F- page 513

PIC18(L)F2X/4XK22

FIGURE 28-89 : PIC 18LF2X /4X K22 COMPARATOR OFFSET VOLTAGE,

NORMAL-POWER MODE; VDD=1.8V

6 sigma

Typical

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

1.8

Abs. Offset (mV)

VREF (V)

PIC18(L)F2X/4XK22

DS41412F-page 514  2010-2012 Microchip Technology Inc.

FIGURE 28-90: PIC18(L)F2X/4XK22 COMPARATOR OFFSET VOLTAGE,

LOW-POWER MODE; VDD=5.5V

FIGURE 28-91: PIC18(L)F2X/4XK22 COMPARATOR OFFSET VOLTAGE,

LOW-POWER MODE; VDD=3.0V

6 sigma

Typical

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

5.5

Abs. Offset (mV)

VREF (V)

6 sigma

Typical

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8

3.0

Abs. Offset (mV)

VREF (V)

 2010-2012 Microchip Technology Inc. DS41412F- page 515

PIC18(L)F2X/4XK22

FIGURE 28-92 : PIC 18LF2X /4X K22 COMPARATOR OFFSET VOLTAGE,

LOW-POWER MODE; VDD=1.8V

6 sigma

Typical

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

1.8

Abs. Offset (mV)

VREF (V)

PIC18(L)F2X/4XK22

DS41412F-page 516  2010-2012 Microchip Technology Inc.

FIGURE 28-93: PIC18(L)F2X/4XK22 TYPICAL DAC ABS. ERROR VDD = 2.5V, 3.0V, & 5.5V

Max LSb Limit

5.5V

3.0V

2.5V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

Absolute Error (LSb)

REF

(V)

Minimum VREF

Limit

 2010-2012 Microchip Technology Inc. DS41412F- page 517

PIC18(L)F2X/4XK22

FIGURE 28-94 : PI C18( L) F2X/ 4XK22 TYPICAL FIXED VOLTAGE REFERENCE 1X OUTPUT

FIGURE 28-95 : PI C18( L) F2X/ 4XK22 TYPICAL FIXED VOLTAGE REFERENCE 1X OUTPUT

2.5V

5.5V

1.005

1.010

1.015

1.020

1.025

1.030

1.035

-40 -20 0 20 40 60 80 100 120

FVR x1 (V)

Temperature (°C)

Max.

Min.

0.96

0.98

1.00

1.02

1.04

1.06

1.08

1.10

2.5 3 3.5 4 4.5 5

5.5

FVR x1 (V)

(V)

40°C

25°C

85°C

125°C

PIC18(L)F2X/4XK22

DS41412F-page 518  2010-2012 Microchip Technology Inc.

FIGURE 28-96 : PI C18( L) F2X/ 4XK22 TYPICAL FIXED VOLTAGE REFERENCE 2X OUTPUT

FIGURE 28-97 : PI C18( L) F2X/ 4XK22 TYPICAL FIXED VOLTAGE REFERENCE 2X OUTPUT

2.5V

5.5V

2.015

2.025

2.035

2.045

2.055

2.065

-40 -20 0 20 40 60 80 100 120

FVR x2 (V)

Temperature (°C)

Min.

Max.

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.5 3 3.5 4 4.5 5

5.5

FVR x2 (V)

(V)

-40°C

25°C

85°C

125°C

 2010-2012 Microchip Technology Inc. DS41412F- page 519

PIC18(L)F2X/4XK22

FIGURE 28-98: PIC18F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 4X OUTPUT

FIGURE 28-99: PIC18F2X/4XK22 TYPICAL FIXED VOLTAGE REFERENCE 4X OUTPUT

4.5V

5.5V

4.03

4.05

4.07

4.09

4.11

4.13

-40 -20 0 20 40 60 80 100 120

FVR x4 (V)

Temperature (°C)

Min.

Max.

3.85

3.90

3.95

4.00

4.05

4.10

4.15

4.20

4.25

4.30

4.35

4.40

4.5 4.7 4.9 5.1 5.3

5.5

FVR x4 (V)

(V)

25°C

40°C

85°C

125°C

PIC18(L)F2X/4XK22

DS41412F-page 520  2010-2012 Microchip Technology Inc.

FIGURE 28-100: PIC18(L)F2X/4XK22 HF-INTOSC FREQUENCY vs. TEMPERATURE at 16 MHZ

MIN / MAX: ± 2%, T = 0°C to +70°C

+2% / -3%, T = +70°C to +85°C

± 5%, T = -40°C to 0°C and +85°C to +125°C

15.20

15.36

15.52

15.68

15.84

16.00

16.16

16.32

16.48

16.64

16.80

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120

Freq (MHz)

Temp (°C)

Max.

Min.

Typical

 2010-2012 Microchip Technology Inc. DS41412F- page 521

PIC18(L)F2X/4XK22

FIGURE 28-10 1: PIC18LF 2X /4X K22 TYPICAL LF-INTOSC FREQUENCY vs. VDD

Min/Max = 31.25 kHz ± 15%, T = -40°C to +85°C

FIGURE 28-102: PIC18F2X/4XK22 TYPICAL LF-INTOSC FREQUENCY vs. VDD

Min/Max = 31.25 kHz ± 15%, T = -40°C to +85°C

-40°C

25°C

85°C

125°C

29.0

29.5

30.0

30.5

31.0

31.5

32.0

32.5

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4

3.6

Frequency (kHz)

VDD (V)

-40°C

25°C

85°C

125°C

29.0

29.5

30.0

30.5

31.0

31.5

32.0

32.5

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

Frequency (kHz)

VDD (V)

PIC18(L)F2X/4XK22

DS41412F-page 522  2010-2012 Microchip Technology Inc.

FIGURE 28-10 3: PIC18LF 2X/4X K22 TYPICAL LF-INTOSC FREQUENCY vs. TEMPERATURE

Min/Max = 31.25 kHz ± 15%, T = -40°C to +85°C

FIGURE 28-104: PIC18F2X/4XK22 TYPICAL LF-INTOSC FREQUENCY vs. TEMPERATURE

Min/Max = 31.25 kHz ± 15%, T = -40°C to +85°C

1.8V

3.6V

29.0

29.5

30.0

30.5

31.0

31.5

32.0

32.5

-40 -20 0 20 40 60 80 100 120

Frequency (kHz)

Temperature (°C)

2.5V

3.0V

5.5V

29.0

29.5

30.0

30.5

31.0

31.5

32.0

32.5

-40 -20 0 20 40 60 80 100 120

Frequency (kHz)

Temperature (°C)

 2010-2012 Microchip Technology Inc. DS41412F- page 523

PIC18(L)F2X/4XK22

29.0 PACKAGING INFORMATION

29.1 Package Marking Information

Legend: XX...X Customer-specific information or Microc hip part number

Y Year code (last digit of calendar year)

YY Year code (last 2 digi ts of calendar year)

WW Week code (w eek of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC design ator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microc hip p art num ber cannot be marked on one lin e, it wi ll

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

28-Lead SPDIP (.300”) Example

PIC18F25K22

0810017

28-Lead SOIC (7.50 mm) Example

YYWWNNN

XXXXXXXXXXXXXXXXXXXX

PIC18F25K22

28-Lead SSOP (5.30 mm) Example

PIC18F25K22

0810017

-E/SS

-E/SP

-E/SO 0810017

PIC18(L)F2X/4XK22

DS41412F-page 524  2010-2012 Microchip Technology Inc.

Package Marking Information (Continue d)

Legend: XX...X Customer-specific information or Microchip part number

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the eve nt the full Microc hip p ar t numbe r cannot b e marke d on one li ne, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

28-Lead QFN (6x6 mm) Example

XXXXXXXX

YYWWNNN

PIN 1 PIN 1

18F25K22

-E/ML

0610017

28-Lead UQFN (4x4x0.5 mm) Example

PIN 1 PIN 1

E/MV

810017

PIC18

F23K22

40-Lead PDIP (600 mil) Example

XXXXXXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXXXXXXXXX

PIC18F45K22

-E/P

0810017

 2010-2012 Microchip Technology Inc. DS41412F- page 525

PIC18(L)F2X/4XK22

Package Marking Information (Continue d)

Legend: XX...X Customer-specific information or Microchip part number

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the eve nt the full Microc hip p ar t numbe r cannot b e marke d on one li ne, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

40-Lead UQFN (5x5x0.5 mm) Example

PIN 1 PIN 1

PIC18F

-I/MV

0810017

45K22

44-Lead QF N (8x8x0.9 mm ) Exampl e

XXXXXXXXXXX

YYWWNNN

XXXXXXXXXXX

PIN 1 PIN 1

1845K22

-E/ML

0810017

44-Lead TQFP (10x10x1 mm) Example

XXXXXXXXXX

YYWWNNN

XXXXXXXXXX

18F45K22

-E/PT

0810017

PIC18(L)F2X/4XK22

DS41412F-page 526  2010-2012 Microchip Technology Inc.

29.2 Package Details

The following sections give the technical details of the packages.

 !

"#

 

 

 

 

 

"# 



 

   

  

  

    

    

    

    

    

    

    

    

    

    

    

NOTE 1

   

 2010-2012 Microchip Technology Inc. DS41412F- page 527

PIC18(L)F2X/4XK22

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC18(L)F2X/4XK22

DS41412F-page 528  2010-2012 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2010-2012 Microchip Technology Inc. DS41412F- page 529

PIC18(L)F2X/4XK22

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC18(L)F2X/4XK22

DS41412F-page 530  2010-2012 Microchip Technology Inc.

$%&'( &!

"#

 

 

 



 

   

  

  

    

    

    

    

    

    

    

  

    

   

    

NOTE 1 b

   

 2010-2012 Microchip Technology Inc. DS41412F- page 531

PIC18(L)F2X/4XK22

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC18(L)F2X/4XK22

DS41412F-page 532  2010-2012 Microchip Technology Inc.

)*+",-./. )*"!

0$(''1,$

"#

 

 



 

   

  

  

    

    

  

  

    

  

    

    

    

    

DEXPOSED D2

NOTE 1

TOP VIEW BOTTOM VIEW

PAD

   

 2010-2012 Microchip Technology Inc. DS41412F- page 533

PIC18(L)F2X/4XK22

)*+",-./. )*"!

0$(''1,$



PIC18(L)F2X/4XK22

DS41412F-page 534  2010-2012 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2010-2012 Microchip Technology Inc. DS41412F- page 535

PIC18(L)F2X/4XK22

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC18(L)F2X/4XK22

DS41412F-page 536  2010-2012 Microchip Technology Inc.

2. !

"#

 

 



 

   

  

  

    

    

    

    

    

    

    

    

    

    

    

NOTE 1

123

A1 b1

   

 2010-2012 Microchip Technology Inc. DS41412F- page 537

PIC18(L)F2X/4XK22

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC18(L)F2X/4XK22

DS41412F-page 538  2010-2012 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2010-2012 Microchip Technology Inc. DS41412F- page 539

PIC18(L)F2X/4XK22

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC18(L)F2X/4XK22

DS41412F-page 540  2010-2012 Microchip Technology Inc.

22)*+",-/ )*"!

"#

 

 



 

   

  

  

    

    

  

  

    

  

    

    

    

    

DEXPOSED

PAD

NOTE 1

BOTTOM VIEW

TOP VIEW

A3 A1

   

 2010-2012 Microchip Technology Inc. DS41412F- page 541

PIC18(L)F2X/4XK22

22)*+",-/ )*"!



PIC18(L)F2X/4XK22

DS41412F-page 542  2010-2012 Microchip Technology Inc.

223$)*435/5/5+( 3)*!

"#

 

 

 



 

   

  

  

    

    

    

    

  

   

  

  

  

  

    

    

   

   

NOTE 1 NOTE 2

123

   

 2010-2012 Microchip Technology Inc. DS41412F- page 543

PIC18(L)F2X/4XK22

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC18(L)F2X/4XK22

DS41412F-page 544  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 545

PIC18(L)F2X/4XK22

APPENDIX A: REVISION HISTORY

Revision A (February 2010)

Initial release of this document.

Revision B (April 2010)

Updated Figures 2-4, 12-1 and 18-2; Updated

Registers 2-2, 10-4, 10-5, 10-7, 17-2, 24-1 and 24-5;

Updated Sections 10.3.2, 18.8.4, Synchronizing

Comparator Output to Timer1; Updated Sections 27.2,

27-3, 27-4, 27-5, 27-6, 27-7 and 27-9; Updated Tables

27-2, 27-3, 27-4 and 27-7; Other minor corrections.

Revision C (July 2010)

Added 40-pin UQFN diagram; Updated Table 2 and

Table 1-3 to add 40-UQFN column; Updated Table 1-1

to add “40-pin UQFN”; Updated Figure 27-1; Added

Figure 27-2; Updated Table 27-6; Added 40-Lead

UQFN Package Marking Information and Details;

Updated Packaging Information section; Updated

Table B-1 to add “40-pin UQFN”; Updated Product

Identification System section; Other minor corrections.

Revision D (November 2010)

Updated the data sheet to new format; Revised Tables

1-2, 1-3, 5-2, 10-1, 10-5, 10-6, 10-8, 10-9, 10-11, 10-

14, 14-13 and Register 14-5; Updated the Electrical

Characteristics section .

Revision E (January 2012)

Updated Section 2.5.2, EC Mode; Updated Table 3-2;

Removed Table 3-3; Updated Section 14.4.8;

Removed CM2CON Register; Updated the Electrical

Characteristics section; Updated the Packaging

Information section; Updated the Char. Data section;

Other minor corrections.

Revision F (May 2012)

Minor corrections ; rel ease of Fi nal data sheet.

PIC18(L)F2X/4XK22

DS41412F-page 546  2010-2012 Microchip Technology Inc.

APPENDIX B: DEVICE

DIFFERENCES

The differences between the devices listed in this data

sheet are shown in Table B-1.

TABLE B-1: DEVICE DIFFERENCES

Features(1) PIC18F23K22

PIC18LF23K22 PIC18F24K22

PIC18LF24K22 PIC18F25K22

PIC18LF25K22 PIC18F26K22

PIC18LF26K22 PIC18F43K22

PIC18LF43K22 PIC18F44K22

PIC18LF44K22 PIC18F45K22

PIC18LF45K22 PIC18F46K22

PIC18LF46K22

Program Memory

(Bytes) 8192 16384 32768 65536 8192 16384 32768 65536

SRAM (Bytes) 512 768 1536 3896 512 768 1536 3896

EEPROM (Bytes) 256 256 256 1024 256 256 256 1024

Interru pt So ur ces 26 26 3 3 33 26 26 3 3 33

I/O Ports Ports A, B, C,

(E) Ports A, B, C,

D, E Port s A, B, C,

D, E Ports A, B, C,

D, E

Capture/Compare/PWM

Modules (CCP) 22 2 2 2 2 2 2

Enhanced CCP Modules

(ECCP) Full Bridge 11 1 1 2 2 2 2

ECCP Module

Half Bridge 22 2 2 1 1 1 1

10-bit Analog-to-Digital

Module 17 input

channels 17 input

channels 28 input

channels

Packag es 28-pin PDIP

28-pin SOIC

28-pin SSO P

28-pin QFN

28-pin UQFN

28-pin PDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

28-pin UQFN

28-pin PD IP

28-pin SOIC

28-pin SSO P

28-pin QFN

28-pin PDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

40-pin PDIP

40-pin UQFN

44-pin TQFP

44-pin QFN

40-pin PDIP

40-pin UQFN

44-pin TQFP

44-pin QFN

40-pin PD IP

40-pin UQFN

44-pin TQFP

44-pin QFN

40-pin PDI P

40-pin UQFN

44-pin TQFP

44-pin QFN

Note 1: PIC18FXXK22: operating voltage, 2.3V-5.5V.

PIC18LFXXK22: operati ng voltage, 1.8V-3.6V.

 2010-2012 Microchip Technology Inc. DS41412F- page 547

PIC18(L)F2X/4XK22

INDEX

A/D Analog Por t Pin s, Configur in g ......... .......... ...............310

Associ a te d Re g i sters ..... ..........................................310

Conversions ............................................................. 301

Converter Characteristics ........................................464

Discharge .................................................................302

Selecting and Configuring Acquisition Time ............298

Absolute Maximum Ratings .............................................427

AC (Timing) Characteristics .............................................447

Load Conditions for Device Timing Specifications ...448

Parame te r Symbolo g y ..... ........... ..................... ........447

Temperature and Voltage Specifications ................. 448

Timing Conditions .................. ....... .... .. .. .... .. ....... .. ....448

AC Characteristics

Internal RC Accuracy ...............................................450

Access Bank

Mapping with Indexed Literal Offset Mode .................94

ACKSTAT ........................................................................246

ACKSTAT Status Flag .....................................................246

ADC .................................................................................297

Acquisition Requirements ........................................308

Block Diag ram ........ ..................................................297

Calculating Acquisition Time ....................................308

Channel Selection ................ ......... .. .... .... .. ......... .. ....298

Configuration ............................................................298

Conversi o n Clo ck ....... ...... ..................... ...................299

Conversion Procedure ........................................... ..303

Internal Sampling Switch (RSS) IMPEDANCE .............308

Interrupts ..................................................................299

Operation ................................................................. 301

Operation During Sleep ...........................................302

Port Configuration ....................................................298

Power Management ................................ .. ......... .. ....302

Reference Voltage (VREF) ........................................298

Result For matting ..... .......... ................................ ......300

Source Impedance ............................................. .... ..308

Special Event Trigger ...............................................302

Starting an A/D Conversion .....................................300

ADCON0 Register ............................................................304

ADCON1 Register ............................................................305

ADCON2 Register ............................................................306

ADDFSR ..........................................................................416

ADDLW ............................................................................ 379

ADDULNK ........................................................................416

ADDWF ............................................................................379

ADDWFC ......................................................................... 380

ADRESH Register (ADFM = 0) ........................................307

ADRESH Register (ADFM = 1) ........................................307

ADRESL Register ( ADFM = 0) .........................................307

ADRESL Register ( ADFM = 1) .........................................307

Analog Input Connection Considerations . ........................315

Analog-to-Digital Converter. See AD C

ANDLW ............................................................................ 380

ANDWF ............................................................................381

Assembler

MPASM Assembler ..................................................424

Bank Select Regis ter (BSR) ... ..................... ............... ........76

BAUDCON Register ....................... ................. .................279

BC .................................................................................... 381

BCF ..................................................................................382

BF ............................................................................ 246, 248

BF Status Fla g ......................................................... 246, 248

Block Diagrams

(CCP) Capture Mode Operation .............................. 180

ADC ......................................................................... 297

ADC Transfer Function ............................................ 309

Analog Input Model .......................................... 309, 315

CCP PWM ................... ............................................ 186

Comparator 1 ........................................................... 312

Compare .................................................................. 183

Crys ta l Oper a ti o n .. .. ...... ..... ...... ...... ......... ...... ...... ...... . 35

CTMU ...................................................................... 321

CTM U C u rr e n t So u r ce Cal i b r a t ion Cir cuit .... .. ...... ... 32 4

CTMU Typical Connections and Internal

Configuration for Pulse Delay Generation ....... 332

CTMU Typical Connections and Internal

Configuration for Time Measurement .............. 331

Digital-to-Analog Converter (DAC) .......................... 346

EUSART Receive .................................................... 268

EUSA R T Tran sm i t ...... ..... .. ...... ...... ...... . ...... ...... ...... . 267

External POR Circuit (Slow VDD Power- u p ) ............ .. 61

External RC Mode ..................................................... 36

Fail-Safe Clock Monitor (FSCM) ................................ 44

Gen e ri c I/ O Port .. ...... ...... ..... ...... ...... ......... ...... ...... ... 13 5

High/Low-Voltage Detect with External Input .......... 350

Interrupt Logic .......................................................... 114

On-Chip Res et Circuit ......... ................ ....................... 59

PIC18F46K22 ............................................................ 16

PWM (Enhanced) .................................................... 190

Reads from Flash Program Memory ......................... 99

Resonator Operation ................................................. 35

Table Read Operation ......................................... .. .... 95

Table Write Operation ............................................... 96

Table Writes to Flash Program Memory .............. .... 101

Timer0 in 16-Bit Mode ............................................. 161

Timer0 in 8-Bit Mode ............................................... 160

Timer1/3/5 ............................................................... 163

Timer1/3/5 Gate ....................................... 169, 170, 171

Timer2/4/6 ............................................................... 175

Voltage Reference .......................... .... ....... .... .. .... .. .. 343

Voltage Reference Output Buffer Example ............. 346

Watchdog Timer ............................................ .. .... .... 366

BN .................................................................................... 382

BNC ................................................................................. 383

BNN ................................................................................. 383

BNOV .............................................................................. 384

BNZ ................................................................................. 384

BOR. See Brown-out Reset.

BOV ................................................................................. 387

BRA ................................................................................. 385

Break Character (12-bit) Transmit and Receive .............. 287

Brown-out Reset (BOR) ..................................................... 62

Detecting ................................................................... 62

Disabling in Sleep Mode ............................................ 62

Minimum Enable Time ............................................... 62

Software Enabled ................................................ .... .. 62

BSF ........ ........ ..... ........ ........ ....... ...... ........ ....... ........ ...... ... 385

BTFSC ............................................................................. 386

BTFSS ............................................................................. 386

BTG ................................................................................. 387

BZ .................................................................................... 388

C Compilers

PIC18(L)F2X/4XK22

DS41412F-page 548  2010-2012 Microchip Technology Inc.

MPLAB C18 ........ ............... ..................... ............... ..424

CALL ................................................................................388

CALLW .............................................................................417

Capture Module. See Enhanced Capture/Compare/

PWM(ECCP)

Capture/Compare/PWM ...................................................179

Capture/Compare/PWM (CCP)

Associated Registers w/ Capture .....................181, 182

Associated Registers w/ Compare ...................184, 185

Associated Registers w/ Enhanced PWM ................204

Associated Registers w/ PWM .........................189, 203

Associated Registers w/ Standard PWM .................189

Capture Mode .................... .... .. .. .... ....... .. .. .... .. .... .....180

CCPx Pin Configur a tion ............. ............................ ..180

Compare Mode .......................... .. .. ......... .. .. .... .. .......183

CCPx Pin Configur a tion .............. .......... ...........183

Software Interrupt Mode . .........................180, 183

Special Event Trigger .......................................184

Timer1 Mode Resource ...........................180, 183

Prescaler .................................................................. 181

PWM Mo de

Duty Cycle .............. ..................... .....................187

Effects of Reset ................................................188

Example PWM Frequencies and

Resolutio ns, 20 MHZ ...............................188

Example PWM Frequencies and

Resolutio ns, 32 MHZ ...............................188

Example PWM Frequencies and

Resolutio ns, 8 MHz ..................................188

Operation in Sleep Mode .................................188

Resolution ........................................................ 188

System Clock Frequency Changes ..................188

PWM Operatio n ............... .......... ........... .......... .........186

PWM Overvie w ............................ ............... .............186

PWM Period .... ..................... ............... .......... ...........187

PWM Setup ..... .......... ............... ........... .............. .......186

CCPTMRS0 Register .......................................................208

CCPTMRS1 Register .......................................................208

CCPxCON (ECCPx) Register ...... ..................... ...............205

Clock Accuracy with Asynchronous Operation ................276

Clock Sources

External Modes ..........................................................34

EC ...................................................................... 34

HS ...................................................................... 35

LP .......................................................................35

OST ....................................................................34

RC ...................................................................... 36

XT ......................................................................35

Internal Modes ...........................................................36

Frequency Selection ......................... .. .... .. ....... ..38

INTOSC .............................................................36

INTOSCIO ..........................................................36

LFINTOSC ......................................................... 38

Selectin g th e 31 k Hz So u rce ............... .......................29

Selection Using OSCCON Register ........ ................. ..29

Clock Switching ..................................................................41

CLRF ................................................................................389

CLRWDT ..........................................................................389

CM1CON0 Register .......... ...............................................317

CM2CON1 Register .......... ...............................................318

Code Examples

16 x 16 Signed Multiply Routine ..............................112

16 x 16 Unsigned Multiply Routine ............... .... .. .....112

8 x 8 Signed Multiply Routine ........................... .. .....111

8 x 8 Unsigned Multiply Routine ..............................111

A/D Conver sion ......................... ............................... 303

Capacitance Calibration Routine ............................. 328

Capacitive Touch Switch Routine ............................ 330

Changing Between Capture Prescalers ................... 181

Clearing RAM Using Indirect Addressing .................. 90

Computed GOTO Using an Offset Value ................... 73

Current Calibration Routine ..................................... 326

Data EEPROM Read ............................................... 107

Data EEPROM Refresh Routine .............................. 108

Data EEPROM Write ............................................... 107

Erasing a Flash Program Memory Row ................... 100

Fast R e g i s t e r Stack .. .. ...... ...... . ...... ...... ...... .. ..... ...... ... 7 3

Initializing PORTA .................................................... 135

Initializing PORTB .................................................... 140

Init i a li zi n g PORT C ........ ...... ..... ...... ...... ...... ..... ...... ... 1 4 4

Init i a li zi n g PORT D ........ ...... ..... ...... ...... ...... ..... ...... ... 1 4 8

Initializing PORTE .................................................... 151

Reading a Flash Program Memory Word ..... ............. 99

Saving Status, WREG and BSR Registers in RAM . 132

Setup for CTMU Calibration Routines ..................... 325

Writing to Flash Program Memory ................... 102–103

Code Protection . .............................................................. 355

COMF .............................................................................. 390

Comparator

Associated Registers ............................................... 319

Operation ................................................................. 311

Operation During Sleep ........................................... 315

Response Time ....................................... ............. .... 313

Comparator Module

C1 Output State Versus Input Conditions ................ 313

Comparator Specifications ............................................... 444

Comparator Voltage Reference (CVREF)

Effects of a Reset .......... ........................... ........... .... 315

Comparator Voltage Reference (CVREF)

Response Time ....................................... ............. .... 313

Comparators

C2OUT as T1/3/5 Ga te ............................. ............... 166

Effects of a Reset .......... ........................... ........... .... 315

Compare Module. See Enhanced Capture/Compare/

PWM (ECCP)

Computed GOTO ........................................... .................... 73

CONFIG1H Register ........................................................ 357

CONFIG2H Register ........................................................ 359

CONFIG2L Register ........................................................ 358

CONFIG3H Register ........................................................ 360

CONFIG4L Register ........................................................ 361

CONFIG5H Register ........................................................ 362

CONFIG5L Register ........................................................ 361

CONFIG6H Register ........................................................ 363

CONFIG6L Register ........................................................ 362

CONFIG7H Register ........................................................ 364

CONFIG7L Register ........................................................ 363

Configuration Bits ............................................................ 355

Configuration Register Protection .................................... 371

Context Saving Dur ing Interrupts ..................................... 132

CPFSEQ .......................................................................... 390

CPFSGT .......................................................................... 391

CPFSLT ........................................................................... 391

CTMU

Associated Registers ............................................... 335

Calibrating ............................................................... 324

Crea t i n g a D e l a y w i th ...... ...... ..... ...... ...... ...... ..... ...... . 332

Effects of a Reset .......... ........................... ........... .... 333

Initialization .............................................................. 323

Measuring Capacitance with ....................................329

 2010-2012 Microchip Technology Inc. DS41412F- page 549

PIC18(L)F2X/4XK22

Measurin g Time with ...... ..........................................331

Operation ................................................................. 322

Operation During Idle Mode .....................................332

Operation During Sleep Mode .................................332

Customer Change Notification Service ............................557

Custome r Notificatio n Se rvice .... ........... ..................... ......557

Customer Support ......................................... .... ............. ..557

CVREF Voltage Reference Specifications ........................444

Data Addressing Modes .....................................................90

Comparing Addressing Modes with the Extended

Instruction Set Enabled .....................................93

Direct ..........................................................................90

Indexed Literal Offset ............. ....... .. .. .... .. .... ....... .. .. ....92

Instructions Affected ..........................................92

Indirect ....................................................................... 90

Inherent and Literal ....................................................90

Data EEPROM

Code Protection . ......................................................371

Data EEPROM Memory

Associ a te d Re g i sters ..... ..........................................109

EEADR and EEADRH Registers .............................105

EECON1 and EECON2 Registers ...........................105

Operation During Code-Protect ...............................108

Protection Agai n st Spuriou s Write .............. .............108

Reading ....................................................................107

Using ........................................................................108

Write Verify ..............................................................107

Writing ......................................................................107

Data Memor y ...... ........... .......... ........... .......... .....................76

Access Ba n k ........ .......... ............... .......... ............... ....82

and the Extended Instruction Set . ..............................92

Bank Select Regis ter (BSR) ........................ ...............76

General Purpose Registers ........................................82

Map for PIC18F/LF23K22 and PIC18F/LF43K22

Devices .............................................................. 77

Map for PIC18F/LF24K22 and PIC18F/LF44K22

Devices .............................................................. 78

Special Function Registers ........................................82

DAW .................................................................................392

DC and AC Characteristics ..............................................467

DC Characteristics

Input/Output ............................................................. 441

Power-Down Current ...............................................431

Primary Idle Supply Current .....................................438

Primary Run Supply Current .... ................................437

RC Idle Supply Current ............................................435

RC Run Supply Current ............................ ......... .... ..433

Secondary Oscillator Supply Current .......................439

Supply Voltage .........................................................430

DCFSNZ ..........................................................................393

DECF ...............................................................................392

DECFSZ ...........................................................................393

Development Support ......................................................423

Device Differences ...........................................................546

Device Overview

Details on Individual Family Members .......................14

Features (tabl e ) ........ .......... ............... ..................... ....15

New Core Features ....................................................13

Other Special Features ..............................................14

Device Reset Timers ..........................................................63

PLL Lock Time-out .....................................................63

Power-up Timer (PWRT) .......... .......... .......................63

Time-out Sequence ............................................ .... ....63

DEVID1 Register ..............................................................364

DEVID2 Register ............................................................. 364

Digital-to-Analog Converter (DAC) .................................. 345

Associated Registers ............................................... 348

Effects of a Reset ...................................... .............. 346

Direct Add ressing .... .......................................................... 91

ECCP/CCP. See Enhanced Capture/Compare/PWM

ECCPxAS Register .......................................................... 209

EECON1 Regist e r .. ..................... ...... ...... ................... 97, 106

Effect on Standard PIC Instructions ................................. 420

Effects of Power Managed Modes on Various

Cloc k So urce s ........ ...... ..... ...... .. ...... ..... ...... ...... ...... .. . 40

Effects of R eset

PWM mode .............................................................. 188

Elect r i ca l C h a ra c t e r i stics ........ ..... ...... ...... .. ..... ...... ...... ..... 427

Enhanced Capture/Compare/PWM (ECCP) .................... 179

Enhanced PWM Mode ............................................. 190

Auto-Restart .................................................... 198

Auto-shutdown ................................................ 197

Direction Change in Full-Bridge Output Mode . 196

Full-Bridge Application ..................................... 194

Full-Bridge Mode ............................................. 194

Half-Bridge Application .................................... 193

Half-Bridge Application Examples ................... 199

Half-Bridge Mode ............................................. 193

Output Relationships (Active-High and

Activ e-L ow) ... ... ...... ...... ...... ... ...... ...... ...... . 191

Output R elationships Diagram ......................... 192

Programmable Dead Band Delay .................... 199

Shoot-through Current . .................................... 199

Start- u p Considerations ...... ........... ................ .. 201

Enhanced Universal Synchronous As ynchr onous

Receiver Transmitter (EUSART) ............................. 267

Errata ................................................................................. 12

EUSART .......................................................................... 267

Asynchronous Mode ................................................ 269

12-bit Break Transmit and Receive ................. 287

Associa te d Re gisters, Rece iv e ...... .......... ........ 275

Associ a te d Re gisters, Transmi t ....... .......... ...... 271

Auto-Wa ke-up on Break ............. ..................... 285

Baud Rate Generator (BRG) ........................... 280

Clock Accuracy ................................................ 276

Receiver .......................................................... 272

Setting up 9-bit Mode with Address Detect ..... 274

Transmitter ...................................................... 269

Baud Rate Generator (BRG)

Associ a te d Re gisters .............. ..................... .... 281

Auto Baud Rate Detect .................................... 284

Baud Rate Error, Calculating ........................... 280

Baud Rates, Asynchronous Modes ................. 281

Formula s ...... .................................................... 280

High Baud Rate Select (BRGH Bit) ................. 280

Clock polarity

Synchronous Mode .......................................... 288

Data polarity

Asynchronous Receive .................................... 272

Asynchronous Tra nsmit ................................... 269

Synchronous Mode .......................................... 288

Interrupts

Asychronous Receive ...................................... 273

Asynchronous Receive .................................... 273

Asynchronous Tra nsmit ................................... 269

Synchronous Master Mode .............................. 288, 293

Associa te d Re gisters, Rece iv e ...... .......... ........ 292

Associated Registers, Transmit ............... 289, 294

PIC18(L)F2X/4XK22

DS41412F-page 550  2010-2012 Microchip Technology Inc.

Reception .........................................................291

Transmis sion ....................................................288

Synchronous Slave Mode

Associated Registers, Receive ........................295

Reception .........................................................295

Transmis sion ....................................................293

Extended Instruction Set

ADDFSR ..................................................................416

ADDULNK ................................................................ 416

and Using MPLAB Tools ................................... .......422

CALLW .....................................................................417

Considerations for Use ............................................420

MOVSF ....................................................................417

MOVSS .................................................................... 418

PUSHL ..................................................................... 418

SUBFSR ..................................................................419

SUBULNK ................................................................ 419

Syntax ......................................................................415

Fail-Safe Clock Monitor ..............................................44, 355

Fail-Safe Condition Clearing ......................................44

Fail-Safe Detection ....................................................44

Fail-Safe Operation ....................................................44

Reset or Wak e -up from Slee p ....................................44

Fast Register Stack ............................................................72

Fixed Voltage Reference (FVR)

Associ a te d Re g i sters ............... ..................... ...........344

Flash Pr ogram Memo ry .... .............. ........... .............. ...........95

Associ a te d Re g i sters ............... ..................... ...........103

Control Reg i sters .......................................................96

EECON1 and EECON2 ...................... ...... .........96

TABLAT ( Ta b l e Latch) Regi ster .........................98

TBLP TR (T a b l e P o in t er) Re g i s t e r ...... ...... ......... .98

Erase Sequence .......................... ........... .... .... .........100

Erasing ..................................................................... 100

Operation During Code-Protect ...............................103

Reading ......................................................................99

Table Pointer

Boundaries Based on Operation ........................98

Table Pointer Boundaries ..........................................98

Table Reads and Table Writes . .................................95

Write Sequence .......................................................101

Writing To .................................................................101

Protection Against Spurious Writes .................103

Unexpected Termination ..................................103

Write Verify ......................................................103

GOTO ...............................................................................394

Hardware Multiplie r .............................. ..................... .......111

Introduction ..............................................................111

Operation .................................................................111

Performance Comparison ........................................111

High/Lo w -V o l tage Detect ............. ..................... ...............349

Applications ..............................................................352

Associ a te d Re g i sters ............... ..................... ...........353

Characteristics .........................................................446

Curren t Consumption ............. ..................... .............351

Effects of a Reset .....................................................353

Operation .................................................................350

During Sleep ....................................................353

Setup ........................................................................351

Start- u p Time .......... .................................................351

Typical Low-Voltage Detect Application .................. 352

HLVD. See High/Low-Voltage Detect. ............................. 349

I2C Mode (MSSPx)

Acknowledge Sequence Timing .............................. 250

Bus Collision

During a Repeated Start Condition .................. 255

During a Stop Condition . .................................256

Effects of a Reset .......... ........................... ........... .... 251

I2C Cloc k R a te w /BRG .. ...... ..... .. ...... ...... .. ..... ...... ..... 258

Master Mode

Operation .........................................................242

Reception ........................................................ 248

Start Condition Timing ............................. 244, 245

Transmission ................................................... 246

Multi-Master Communication, Bus Collision and

Arbitration ........................................................ 252

Mult i - Ma ster M o d e .. .. ...... ...... ..... ...... ...... ...... ..... ...... . 251

Read/Write Bit Information (R/W Bit) ....................... 227

Slave Mode

Transmission ................................................... 232

Sleep Operation .. ..................................................... 251

Stop Condition Timing ............................................. 250

ID Locations ............................................................. 355, 371

INCF ................................................................................ 394

INCFSZ ............................................................................395

In-Circuit Debugger .......................................................... 371

In-C i r cu i t Se rial Pro g ramming (IC S P ) .... ...... ...... ..... . 355, 3 7 1

Indexed Literal Offset Addressing

and Standard PIC18 Instructions ............................. 420

Indexed Literal Offset Mode ..... ........... ............................. 420

Indirect Addressing ............................................................ 91

INFSNZ ............................................................................ 395

Instruction Cycle ...................................... .......................... 74

Cloc ki n g Schem e .. .. ...... .. ...... ..... ...... ...... ...... . ...... ...... . 74

Instr uctio n Fl o w /Pip e l i n i n g .. ...... ...... ..... ...... ...... ..... ...... ...... . 74

Instr uctio n Se t .......... ..... ...... ...... .. ..... ...... ...... ...... ..... ...... .. . 373

ADD LW .... ........ ....... ........ ........ ..... ........ ........ ....... ..... 379

ADD WF ...... ...... ..... ...... .. ...... ..... ...... ...... ...... ..... .. ...... . 379

ADDWF (Indexed Literal Offset Mode) .................... 421

ADDWFC ................................................................. 380

AND LW .... ........ ....... ........ ........ ..... ........ ........ ....... ..... 380

AND WF ...... ...... ..... ...... .. ...... ..... ...... ...... ...... ..... .. ...... . 381

BC ............................................................................381

BCF ......................................................................... 382

BN ............................................................................382

BNC ......................................................................... 383

BNN ......................................................................... 383

BNOV ...................................................................... 384

BNZ ......................................................................... 384

BOV ......................................................................... 387

BRA ......................................................................... 385

BSF ........ ........ ..... ........ ........ ....... ...... ........ ....... ........ . 385

BSF (I n d e xe d L i te r al Offse t Mode ) .. ...... .. ..... ...... ..... 421

BTFSC ..................................................................... 386

BTFSS ..................................................................... 386

BTG ......................................................................... 387

BZ ............................................................................ 388

CALL ...... ........ ..... ........ ........ ..... ........ ........ ..... ........ ... 38 8

CLRF ....................................................................... 389

CLRWDT ................................................................. 389

COMF ...................................................................... 390

CPFSEQ .................................................................. 390

CPFSGT .................................................................. 391

CPFSLT ................................................................... 391

 2010-2012 Microchip Technology Inc. DS41412F- page 551

PIC18(L)F2X/4XK22

DAW .........................................................................392

DCFSNZ ..................................................................393

DECF .......................................................................392

DECFSZ ...................................................................393

Extended Instruction Set ..........................................415

General Format ....................................... .... ........... ..375

GOTO ......................................................................394

INCF .........................................................................394

INCFSZ .................................................................... 395

INFSNZ ....................................................................395

IORLW .....................................................................396

IORWF .....................................................................396

LFSR ........................................................................397

MOVF .......................................................................397

MOVFF ....................................................................398

MOVLB ....................................................................398

MOVLW ...................................................................399

MOVWF ................................................................... 399

MULLW .................................................................... 400

MULWF ....................................................................400

NEGF .......................................................................401

NOP .........................................................................401

Opcode Field Descriptions .......................................374

POP .........................................................................402

PUSH .......................................................................402

RCALL .....................................................................403

RESET .....................................................................403

RETFIE ....................................................................404

RETLW ....................................................................404

RETURN ..................................................................405

RLCF .............. ..........................................................405

RLNCF .....................................................................406

RRCF ....................................................................... 406

RRNCF ....................................................................407

SETF ........................................................................407

SETF (Indexed Literal Offset Mode) ........................421

SLEEP .....................................................................408

SUBFWB ..................................................................408

SUBLW ....................................................................409

SUBWF .................................................................... 409

SUBWFB ..................................................................410

SWAPF ....................................................................410

TBLRD ..................................................................... 411

TBLWT .....................................................................412

TSTFSZ ...................................................................413

XORLW ....................................................................413

XORWF ....................................................................414

INTCON Register .............................................................116

INTCON Registers ...........................................................115

INTCON2 Register ...........................................................117

INTCON3 Register ...........................................................118

Internal Oscillator Block

HFINTOSC Frequency Drift .......................................38

PLL in HFINTOSC Modes ...................................... .. ..39

Internal RC Oscillator

Use with WDT ..........................................................366

Internal Sampling Switch (RSS) IMPEDANCE .....................308

Inter n et Address ........... .......... ............... .......... ............... ..557

Inter rupt Sources ................. ............... ..................... ........355

ADC .........................................................................299

Interrupt-on-Change (RB7:RB4) ..............................140

INTn Pin ...................................................................132

PORTB, Interrupt-on-Change ..................................132

TMR0 .......................................................................132

TMR0 Overflow ........................................................161

Interrupts

TMR1/3/5 ................................................................. 168

IORLW ............................................................................. 396

IORWF ............................................................................. 396

IPR Registers ................................................................... 115

IPR1 Register .................................................................. 128

IPR2 Register .................................................................. 129

IPR3 Register .................................................................. 130

IPR4 Register .................................................................. 131

IPR5 Register .................................................................. 131

LFSR ............................................................................... 397

Low-Voltage ICSP Programm ing. See Single-Su pply

ICSP Programm i ng

Map ........ ...... ....... ........ ...... ....... ........ ...... ....... ........ ...... . 7 9, 80

Master Clear (MCLR) ...... ......... ...... ...... ...... ..... ...... ...... ...... . 61

Master Synchronous Serial Port. See MSSPx

Memory Organization

Data Memory ............................................................. 76

Prog r a m M e mory ........ ..... ...... ...... .. ...... ..... ...... ...... ..... 6 9

Microc h i p In te rnet Web Site .................. ..................... ...... 557

MOVF .............................................................................. 397

MOVFF ............................................................................ 398

MOVLB ............................................................................ 398

MOVLW ........................................................................... 399

MOVSF ............................................................................ 417

MOVSS ............................................................................ 418

MOVWF ........................................................................... 399

MPLAB ASM30 Assembler, Linker, Librarian .................. 424

MPLAB Integrated Development Environment Software . 423

MPL AB PM3 D e v i ce Progr a mmer ..... .. ...... .. ..... ...... ...... ... 42 6

MPLAB REAL ICE In-Circuit Emulator System ............... 425

MPL IN K Ob j e ct Linker/ MPLIB O b j ec t Li b ra ri a n ........ .. ..... 424

MSSPx ............................................................................. 211

SPI Mode ................................................................. 214

SSPxBUF Register ...................................... ............ 217

SSPxSR Register .................................................... 217

MULLW ............................................................................ 400

MULWF ............................................................................ 400

NEGF ............................................................................... 401

NOP ................................................................................. 401

OSCC ON Re g i s t e r .. ...... ...... ..... .......... ...... ..... ...... ...... ... 32 , 3 3

Oscillator Configuration

EC .............................................................................. 27

ECIO .......................................................................... 27

HS .............................................................................. 27

HSPLL ....................................................................... 27

LP .............................................................................. 27

RC ............................................................................. 27

XT .............................................................................. 27

Oscillat or S election .............. ....... ............ ....................... .. 355

Oscillator Start-up Timer (OST) ............ ....................... 40, 63

Oscillator Switching

Fail - Safe C l o c k Mon it o r ........... ...... . . ..... ...... .......... ..... 44

Two-Speed Clock Start-up ........................................ 42

OSCTUNE Register ........................................................... 37

P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/

PWM (ECCP) .......................................................... 190

PIC18(L)F2X/4XK22

DS41412F-page 552  2010-2012 Microchip Technology Inc.

Packagi n g Informa tio n ........... ............................... ...........523

Marking ....................................................................523

PIE Registers ...................................................................115

PIE1 Register ...................................................................124

PIE2 Register ...................................................................125

PIE3 Register3 .................................................................126

PIE4 Register ...................................................................127

PIE5 Register ...................................................................127

PIR1 Regi ster .............................................. .......... ...........119

PIR2 Regi ster .............................................. .......... ...........120

PLL Frequency Multiplier ...................................................39

POP ..................................................................................402

POR. See Power-on Reset.

PORTA

Associ a te d Re g i sters ............... ..................... ...........137

PORTA Register ......................................................135

TRISA Register ........................................................135

PORTB

Associ a te d Re g i sters ............... ..................... ...........143

PORTB Register ......................................................140

PORTC

Associ a te d Re g i sters ............... ..................... ...........147

PORTC Register ......................................................144

PORTD

Associ a te d Re g i sters ............... ..................... ...........151

PORTD Register ......................................................148

TRISD Register ... ........... ..........................................148

PORTE

Associ a te d Re g i sters ............... ..................... ...........152

PORTE Register ......................................................151

Power Managed Modes ....................... .. ....... .. .... .. .. .... .......47

and A/D Operation .................................... .. .. .... .. .....302

Effects on Clock Sources ...........................................40

Entering ......................................................................47

Exiting Idle and Sleep Modes ....................................54

by Interrupt .........................................................54

by Reset .............................................................54

by WDT Time-out ...............................................54

Without a Start-up Delay ....................................54

Idle Modes .................................................................51

PRI_IDLE ........................................................... 52

RC_IDLE ............................................................53

SEC_IDLE ..........................................................52

Multiple Sleep Functions . ...........................................48

Run Modes . ................................................................48

PRI_RUN ...........................................................48

SEC_RUN ..........................................................48

Selecting ....................................................................47

Sleep Mode ................................................................51

Summary (table) .................. ............................... .......47

Power-on Res e t (POR) ............ ..........................................61

Power-up Timer (PWRT) ....... ........... .......... ...............63

Time-out Sequence ..................................... .... .... .......63

Power-up Delays ......... .......................................................40

Power-up Timer (PWRT) ...... .......... ....................................40

Presca le r, Timer0 ................. ............................................161

PRI_IDLE Mode . ................................................................52

PRI_RUN Mode .................................................................48

Program Counter ................................................................70

PCL, PCH and PCU Registers ................................. ..70

PCLATH and PCLATU Registers ..............................70

Program Memory

and Extended Instruction Set .....................................94

Code Protection .......................................................369

Instructions .................................................................75

Two-Word .......................................................... 75

Interrupt Vector .......................................................... 69

Look-up Tables ............................... .. .... .... ......... .... .. .. 73

Map and Stack (diagram) . ......................................... 70

Reset Vec tor .................. ..................... ............... ........ 69

Program Verificat ion and Code Protection ...................... 368

Associated Registers ............................................... 368

PSTRxCON Register ....................................................... 210

PUSH ............................................................................... 402

PUSH and PO P In struc tio n s ...... ............ ...................... ...... 72

PUSHL ............................................................................. 418

PWM (ECCP Module)

PWM Steering ... .......................................... ............. 200

Steering Synchronization ......................................... 200

PWM Mode. See Enh anced Captur e/Compare/ PWM ..... 190

PWM Steering .................................................................. 200

PWMxCON Register ........................................................ 210

RAM. See Data Me mory .

RC_IDLE Mode .................................................................. 53

RC_RUN ............................................................................ 48

RCALL ............................................................................. 403

RCON Register .................................................................. 60

Bit Status During Initialization .................................... 67

RCREG ............................................................................ 274

RCSTA Regist e r ........................................................ ...... 278

Reader Response ............................................................ 558

RCREG Register ..................................................... 284

Registers

ADCON0 (ADC Control 0) ........ ................ ....... ........ 304

ADCON1 (ADC Control 1) ........ ................ ....... ........ 305

ADCON2 (ADC Control 2) ........ ................ ....... ........ 306

ADRESH (ADC Result High) with ADFM = 0) ......... 307

ADRESH (ADC Result High) with ADFM = 1) ......... 307

ADRESL (ADC Result Low) with ADFM = 0) ........... 307

ADRESL (ADC Result Low) with ADFM = 1) ........... 307

BAUDCON (Baud Rate Control) .............................. 279

BAUDCON (EUSART Baud Rate Control) .............. 279

CCPTMRS0 (PWM Timer Selection Control 0) ....... 208

CCPTMRS1 (PWM Timer Selection Control 1) ....... 208

CCPxCON (ECCPx Control) .................................... 205

CM1CON0 (C1 Control) ........................................... 317

CM2CON1 (C2 Control) ........................................... 318

CONFIG1H (Configuration 1 High) .......................... 357

CONFIG2H (Configuration 2 High) .......................... 359

CONFIG2L (Configuration 2 Low) ........................... 358

CONFIG3H (Configuration 3 High) .......................... 360

CONFIG4L (Configuration 4 Low) ........................... 361

CONFIG5H (Configuration 5 High) .......................... 362

CONFIG5L (Configuration 5 Low) ........................... 361

CONFIG6H (Configuration 6 High) .......................... 363

CONFIG6L (Configuration 6 Low) ........................... 362

CONFIG7H (Configuration 7 High) .......................... 364

CONFIG7L (Configuration 7 Low) ........................... 363

CTMUCONH (CTMU Control High) ................. ........ 333

CTMUCONL (CTMU Control Low) .......................... 334

CTMUICON (CTMU Current Control) ...................... 335

DEVID1 (De vice ID 1) .... ........... ...... ................. ........ 364

DEVID2 (De vice ID 2) .... ........... ...... ................. ........ 364

ECCPxAS (CCPx Auto-Shutdown Control) ............. 209

EECON1 (Data EEPROM Control 1) ................. 97, 106

HLVDCON (High/Low-Voltage Detect Control) ....... 349

INTC ON (I n te r r upt C o n trol) ........ ...... .......... ..... ......... 1 1 6

 2010-2012 Microchip Technology Inc. DS41412F- page 553

PIC18(L)F2X/4XK22

INTCON2 (Interrupt Contr ol 2) .................................117

INTCON3 (Interrupt Contr ol 3) .................................118

IPR1 (Peripheral Interrupt Priority 1) ........................128

IPR2 (Peripheral Interrupt Priority 2) ........................129

IPR3 (Peripheral Interrupt Priority) ...........................130

IPR4 (Peripheral Interrupt Priority) ...........................131

IPR5 (Peripheral Interrupt Priority) ...........................131

OSCCON (Oscillator Control) ..............................32, 33

OSCTUNE (Oscillator Tu n in g ) ...... ..................... ........37

PIE1 (Peripheral Interrupt Enable 1) ........................124

PIE2 (Peripheral Interrupt Enable 2) ........................125

PIE3 (Peripheral Interrupt Enable] ...........................126

PIE4 (Peripheral Interrupt Enable) ...........................127

PIE5 (Peripheral Interrupt Enable) ...........................127

PIR1 (Peripheral Interrupt Request 1) .....................119

PIR2 (Peripheral Interrupt Request 2) .....................120

PSTRxCON (PWM Steering Contr ol) ........ ..............210

PWMxCON (Enhanc ed PWM Contro l) ....................210

RCON (Reset Contr o l) ................................ .......60, 131

RCSTA (Receive Status and Control) ......................278

SLRCON (PORT Slew Rate Control) .......................158

SRCO N 0 ( SR Lat c h C o n trol 0) ........ ...... ......... ...... ...3 4 0

SRCO N 1 ( SR Lat c h C o n trol 1) ........ ...... ......... ...... ...3 4 1

SSPxADD (MSSPx Address and Baud Rate,

I2C Mode) ........................................................265

SSPxCON1 (MSSP x Control 1) ........ ..................... ..260

SSPxCON2 (SSPx Control 2) .......................... ........262

SSPxMS K (S SPx Mask) ................... .......... .............264

SSPxSTA T (SSPx Stat u s) .................. ............... ......259

STATUS .....................................................................89

STKPTR (St a ck Poin ter) ............................................72

T0CON (Timer0 Co n tr o l) ........ ........... ..................... ..159

TxCON ..................................................................... 177

TxCON (Timer1/3/5 Control) ................. ...................172

TxGCON (Timer1/ 3 /5 Gate Cont rol) ........................173

TXSTA (Transmit Status and Control) .....................277

VREFCON0 .............................................................344

VREFCON1 .............................................................347

VREFCON2 .............................................................348

WDTCON (Watchdog Tim er Contro l) ......................367

RESET ............................................................................. 403

Reset St a te of Registe rs ....................................................67

Resets .............................................................................. 355

Brown-out Reset (BOR) ...........................................355

Oscillator Start-up Timer (OST) ...............................355

Power-on Res e t (POR) ........ ....................................355

Power-up Timer (PWRT) .......... .......... .....................355

RETFIE ............................................................................404

RETLW ............................................................................404

RETURN .......................................................................... 405

Return Ad d ress Sta ck ............................. ............... .......... ..70

Return Stack Pointer (STKP TR) ........................................71

Revision History ...............................................................545

RLCF ................................................................................405

RLNCF ............................................................................. 406

RRCF ............................................................................... 406

RRNCF ............................................................................407

SEC_IDLE Mod e ................................................................52

SEC_RUN Mode ................................................................48

SETF ................................................................................407

Shoot-through Current .....................................................199

Single-Supply ICSP Programming.

SLEEP .............................................................................408

Sleep

OSC1 and OSC2 Pin States ...................................... 41

Sleep Mode ....................................................................... 51

Slew Rate ........................................................................ 153

SLRCON Register ........................................................... 158

Software Simulator (MPLAB SIM) ................................... 425

SPBRG ............................................................................ 280

SPBRGH ......................................................................... 280

Special Event Trigger ...................................................... 302

Special Function Registers ................................................ 82

Map ............................................................................ 83

SPI Mode (MSS Px)

Associated Registers ............................................... 221

SPI Clock ................................................................. 217

SR Latch

Associated Registers ............................................... 341

Effects of a Reset ...................................... .............. 337

SRCON0 Register ........................................................... 340

SRCON1 Register ........................................................... 341

SSPxADD Register .......................................................... 265

SSPxCON1 Register ....................................................... 260

SSPxCON2 Register ....................................................... 262

SSPxMS K Register ...... ................... .......... ........... ............ 264

SSPxOV .......................................................................... 248

SSPxOV Status Flag ....................................................... 248

SSPxSTAT Register ..................... ..................... .............. 259

R/W Bit .................................................................... 227

Stack Full/Underflow Resets .................................... .... ...... 72

Standard Instructions ....................................................... 373

STATUS Regi ster ........ .......... ........... ................................. 89

STKPTR Register ........ ...................................................... 72

SUBFSR .......................................................................... 419

SUBFWB ......................................................................... 408

SUBLW ............................................................................ 409

SUBULNK ........................................................................ 419

SUBWF ............................................................................ 409

SUBWFB ......................................................................... 410

SWAPF ............................................................................ 410

T0CON Registe r ...... ............................... ....... .......... ........ 159

Table Pointer Operations (table) ........................................ 98

Table Reads/Table Writes ................ .. .... .. .. ....... .. .... .. .. .... .. 73

TBLRD ............................................................................. 411

TBLWT ............................................................................ 412

Time-o u t in Various Situ a tions (tab l e ) ..... ........... ................ 64

Timer0 ............................................................................. 159

Associated Registers ............................................... 161

Operation ................................................................. 160

Overflow In terrupt ...... .......................................... .... 161

Prescaler ................................................................. 161

Prescaler Assignment (PSA Bit) .............................. 161

Presca le r Select (T 0 PS 2 :T0 PS0 Bi ts) ..................... 161

Prescaler. See Prescaler, Timer0.

Reads and Writes in 16-Bit Mode ............................ 160

Source Edge Select (T0SE Bit) ............................... 160

Source Select (T0CS Bit) ........................................ 160

Swit ch i n g Pre scal e r A ssignment ... .. ..... .. ...... ...... .. ... 16 1

Timer1/3/5 ....................................................................... 163

Associ a te d registers ...... .......................................... 174

Asynchronous Counter Mode .................................. 165

Reading and Writing ........................................ 165

Clock Source Selection ........................................... 164

Interrupt ................................................................... 168

Operation ................................................................. 164

Operation During Sleep ... ........................................ 168

Oscillator .................................................................. 165

PIC18(L)F2X/4XK22

DS41412F-page 554  2010-2012 Microchip Technology Inc.

Prescaler .................................................................. 165

Timer1/3/5 Gate

Selectin g So u rce ..............................................166

TMRxH Regis te r ................ ......................................163

TMRxL Register .......................................................163

Timer2/4/6 ........................................................................ 175

Associ a te d registers ....... .......... ............... .................178

Timers

Timer1/3/5

TxCON ............................................................. 172

TxGCON ..........................................................173

Timer2/4/6

TxCON ............................................................. 177

Timing Diagrams

A/D Conversion ... ........... ............................... ...........464

Acknowledge Sequence ..........................................250

Asynchronous Reception .........................................275

Asynchronous Transmission ....................................270

Asynchronous Transmission (Back to Back) ...........271

Auto Wake-up Bit (WUE) During Normal Operation 286

Auto Wake- u p Bit (WUE) During Sle e p ........ ...........286

Automatic Baud Rate Calculator ..............................285

Baud Rate Generator with Clock Arbitration ............243

BRG Reset Due to SDA Arbitration During Start

Condition ..........................................................254

Brown-out Reset (BOR) ...........................................452

Bus Collision During a Repeated Start Condition

(Case 1) ...........................................................255

Bus Collision During a Repeated Start Condition

(Case 2) ...........................................................255

Bus Collision During a Start Condition (SCL = 0) ....254

Bus Collision During a Stop Condition (Case 1) ......256

Bus Collision During a Stop Condition (Case 2) ......256

Bus Collision During Start Condition (SDA only) .....253

Bus Collision for Transmit and Acknowledge ...........252

Capture/Compare/PWM (CCP) ...... ..................... .....454

CLKO and I/O ..........................................................451

Clock Synchronization .............................................240

Clock/Instruction Cycle ..............................................74

Comparator Output ..................................................311

EUSART Synchronous Receiv e (Mast er/ Slave) ......463

EUSART Synchronous T ransm ission

(Master/Slave) ..................................................463

Example SPI Master Mode (CK E = 0) .....................455

Example SPI Master Mode (CK E = 1) .....................456

Example SPI Master Mode Tim ing .. ........................455

Example SPI Slave Mode (CKE = 0) .......................457

Example SPI Slave Mode (CKE = 1) .......................458

External Clock (All Modes except PLL) ....................449

Fail-Safe Clock Monitor (FSCM) ................................45

First Start Bit Timing ..................................... ...........244

Full-Bridge PWM Output ..........................................195

Half-Bridge PWM Output .................................193, 199

High/Low-Voltage Detect Characteristics ................446

High-Voltage Detect Operation (VDIRMAG = 1) ......352

I2C Bus Data ............................................................459

I2C Bus Start/Stop Bits .............................................458

I2C Master Mode (7 or 10-Bit Transmission) ...........247

I2C Master Mode (7-Bit Reception) ..........................249

I2C Stop Condition Receive or Transmit Mode ........251

Internal Oscillator Switch Timing ................................43

Low-Voltage Detect Operation (VDIRMAG = 0) .......351

Master SSP I2C Bus Data ........................................461

Master SSP I2C Bu s Start /S to p Bi t s ........ ...... .. ..... .. .461

PWM Auto-shutd o wn ..... .......... ..................... ...........198

Firmware Restart ............................................. 198

PWM Direction Change ....................................... .... 196

PWM Direction Change at Near 100% Duty Cycle .. 197

PWM Output (Active-High) ...................................... 191

PWM Output (A ctive-Low) ..... .................................. 192

Repeat Start Condition ........................... .. .. ....... .... .. 245

Reset, Watchdog Timer (WDT), Oscillator Start-up

Time r (OST), P o w e r-u p Ti mer ( PW R T) ...... ..... 452

Send Break Character Sequenc e ............................ 287

Slow Rise Time (MCLR Tied to VDD, VDD Rise >

TPWRT) ............................................................... 65

SPI Mode (Master Mode) ......... ..................... ........... 217

Synchronous Reception (Master Mode, SREN) ...... 292

Synchronous Transmission ..................................... 289

Synchronous Transmission (T hrough TXEN) . ......... 289

Time-out Sequence on POR w/PLL Enabled

(MCLR Tied to VDD) .......................................... 66

Time-out Sequence on Power-up (MCLR

Not Tied to VDD, Case 1) ................................... 64

Time-out Sequence on Power-up (MCLR

Not Tied to VDD, Case 2) ................................... 65

Time-out Sequence on Power-up (MCLR

Tied to VDD, VDD Ri s e < TPWRT) ....................... 64

Timer0 and Timer1 External Clock .......................... 453

Timer1/3/5 Incrementing Edge ................................ 169

Transition for Entry to SEC_RUN Mode .............. .. .. .. 49

Transition for Entry to Sleep Mode ............................ 51

Transition for Wake from Sleep (HSPLL) .................. 52

Transition from RC_RUN Mode to PRI_RUN Mode .. 50

Transition from SEC_RUN Mode to PRI_RUN

Mode (HSPLL) ................................................... 49

Transition Timing for Entry to Idle Mode .................... 52

Transition Timing for Wake from Idle to Run Mode ... 53

Timing Diagrams and Specifications ............................... 449

A/D Conversion Requirements ................................ 464

Capture/Compare/PWM Requirements ................... 455

CLKO and I/O Requirements ................................... 451

EUSART Synchronous Receive Requirements ....... 463

EUSART Synchronous Transmi ssion

Requirements .................................................. 463

Example SPI Mode Requireme nts

(Master Mode, CKE = 0) .................................. 456

(Slave Mode, CKE = 0) ....................................457

External Clock Requirements .. ................................ 449

I2C Bus Data Requirements (Slave Mode) .............. 460

I2C Bus Start/Stop Bits Requirements

(Slave Mode) ................................................... 459

Master SSP I 2C Bus Data Requirement s ................ 462

Master SSP I 2C Bus Start/S top Bits Requirements . 461

PLL Clock ................................................................ 450

Reset, Watchdog Timer, Oscillator Start -up Time r,

Power-up Timer and Brown-out Reset

Requirements .................................................. 453

Timer0 and Timer1 External Clock Requirements ... 454

Top-of-Stack Access .......................................................... 71

TSTFSZ ........................................................................... 413

Two-Spe ed Clock Start-up Mode ................ ....................... 42

Two-Speed Start-up ......... ..................... .............. ........... ..355

Two-Word Instructions

Example Cases .......................................................... 75

TxCON (Timer2/4/6) Register .......................................... 177

TxCON Register ............................................... ............... 172

TxGCON Regist e r ..... ................................ ..................... .. 173

TXREG ............................................................................ 269

TXSTA Reg ister ............................. ............... ........... ........ 277

 2010-2012 Microchip Technology Inc. DS41412F- page 555

PIC18(L)F2X/4XK22

BRGH Bit .................................................................280

Voltage Reference (VR)

Specifications ...........................................................445

VREF. SEE ADC Reference Voltage

VREFCO N0 Register ............................ .............. ........... ..344

VREFCON1 (Digital-to-Analog Converter Control 0)

VREFCON2 (Digital-to-Analog Converter Control 1)

Wake-up on Break ...........................................................285

Watchdog Timer (WDT) ...........................................355, 366

Associ a te d Re g i sters ..... ..........................................367

Control Reg i ster ......... .......... ....................................367

Programming Consi der a tions ............... ...................366

WCOL ..................... .. ..... .... .. .. .. .... .. ..... .... .243, 246, 248, 250

WCOL Status Flag ......................... ....... .. .243, 246, 248, 250

WDTCON Registe r .............. ............................................367

WWW Address .................................................................557

WWW, On-Line Support ....................................................12

XORLW ............................................................................413

XORWF ............................................................................414

PIC18(L)F2X/4XK22

DS41412F-page 556  2010-2012 Microchip Technology Inc.

NOTES:

 2010-2012 Microchip Technology Inc. DS41412F- page 557

PIC18(L)F2X/4XK22

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Microc hip pro vides onl ine s upport v ia our W WW site at

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Customers should contact their distributor,

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support. Local sales offices are also available to help

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Technical support is avail able throug h the web si te

at: http://microchip.com/support

PIC18(L)F2X/4XK22

DS41412F-page 558  2010-2012 Microchip Technology Inc.

READER RESP ONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our

documentation can better serve you, please FAX your comments to the Technical Publications Manager at

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DS41412FPIC18(L)F2X/4XK22

1. What are the best feat ures of this docume nt?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

 2010-2012 Microchip Technology Inc. DS41412F- page 559

PIC18(L)F2X/4XK22

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: PIC18F46K22, PIC18LF46K22

PIC18F45K22, PIC18LF45K22

PIC18F44K22, PIC18LF44K22

PIC18F43K22, PIC18LF43K22

PIC18F26K22, PIC18LF26K22

PIC18F25K22, PIC18LF25K22

PIC18F24K22, PIC18LF24K22

PIC18F23K22, PIC18LF23K22

Tape and Reel

Option: Blank = standard packagi ng (tu be or tra y)

T = Tape and Reel(1), (2)

Temperature

Range: E= -40C to +125C (Extended)

I= -40C to +85C (Industrial)

Package: ML = QFN

MV = UQFN

P=PDIP

PT = TQFP (Thin Quad Flatpack)

SO = SOIC

SP = Skinny Plastic DIP

SS = SSOP

Pattern: QTP, SQTP, Code or Special Requirements

(blank oth erwis e )

Examples:

a) PIC18(L)F45K22-E/P 301 = Extended temp.,

PDIP package, QTP pattern #301 .

b) PIC18F46K22-I/SO = Industrial temp., SOIC

package.

c) PIC18F46K22-E/P = Extended temp., PDIP

package.

d) PIC18F46K22T-I/ML = Tape and reel, Industrial

temp., QFN package.

Note 1: Tape and Reel opt ion is ava ila ble for ML,

MV, PT, SO and SS packages with industrial

Temperature Range only.

2: Tape and Reel identifier only appears in

catalog part number description. This

identifier is used for ordering purposes and

is not printed on the device package.

[X](2)

Tape and Reel

Option

DS41412F-page 560  2010-2012 Microchip Technology Inc.

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Worldwide Sales and Service

11/29/11