DATA SHEET PFE3000-12-069RA FEATURES Best-in-class, Platinum efficiency Wide input voltage range: 90-300 VAC AC input with power factor correction DC input voltage range: 192-400 VDC Hot-plug capable Parallel operation with active analog current sharing Full digital controls for improved performance High density design: 30.5 W/in3 Small form factor: 69 x 42 x 555 mm I2C communication interface for control, programming and monitoring with PMBusTM protocol Overtemperature, output overvoltage and overcurrent protection RoHS Compliant 2 Status LEDs: AC OK and DC OK with fault signalling Safety-approved to IEC/EN 60950-1 and UL/CSA 60950-1 2nd Ed. DESCRIPTION The PFE3000-12-069RA is a 3000 Watt AC/DC power-factor-corrected (PFC) and DC/DC power supply that converts standard AC mains power or high voltage DC bus voltages into a main output of 12 VDC for powering intermediate bus architectures (IBA) in high performance and reliability servers, routers, and network switches. The PFE3000-12-069RA meets international safety standards and displays the CE-Mark for the European Low Voltage Directive (LVD). BCD.00297_AA Nov-25-2013 1 APPLICATIONS o HIGH PERFORMANCE SERVERS o ROUTERS o SWITCHES www.power-one.com DATA SHEET 1 1) 2 ORDERING INFORMATION PFE 3000 - 12 - 069 R A Product Family PFE Front-Ends Power Level 3000 W Dash V1 Output 12 V Dash Width 69 mm Airflow Input A: AC R: Reversed1) Front to rear OVERVIEW The PFE3000-12-069RA AC/DC-DC power supply is a fully DSP controlled, highly efficient front-end. It incorporates resonance-soft-switching technology and interleaved power trains to reduce component stresses, providing increased system reliability and very high efficiency. With a wide input operating voltage range and minimal linear derating of output power with respect to ambient temperature, the PFE3000-12-069RA maximizes power availability in demanding server, switch, and router applications. The front-end is fan cooled and ideally suited for server integration with a matching airflow path. The PFC stage is digitally controlled using a state-of-the-art digital signal processing algorithm to guarantee best efficiency and unity power factor over a wide operating range. The DC-DC stage uses soft switching resonant techniques in conjunction with synchronous rectification. An active OR-ing device on the output ensures no reverse load current and renders the supply ideally suited for operation in redundant power systems. The always-on +12V standby output provides power to external power distribution and management controllers. Its protection with an active OR-ing device provides for maximum reliability. Status information is provided with front-panel LEDs. In addition, the power supply can be controlled and the fan speed set via the I2C bus. It allows full monitoring of the supply, including input and output voltage, current, power, and inside temperatures. Cooling is managed by a fan, controlled by the DSP controller. The fan speed is adjusted automatically depending on the actual power demand and supply temperature and can be overridden through the I2C bus. Figure 1 - PFE3000-12-0069RA Block Diagram L V1 DC Vsb Filter +12V SB PFC DC PE GND PWM N Aux Converter EEPROM PWM FAN Digital Prim Controls Communication Bus V1Sense+ Digital Sec Controls V1SenseI2C Logic Signals 3 ABSOLUTE MAXIMUM RATINGS Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long-term reliability, and cause permanent damage to the supply. PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT Vi maxc Maximum Input BCD.00297_AA Nov-25-2013 Continuous 300 2 VAC www.power-one.com DATA SHEET 4 INPUT General Condition: TA = 0... 45 C unless otherwise noted. PARAMETER DESCRIPTION / CONDITION Vi nom AC Nominal Input Voltage Vi AC Input Voltage Ranges Vinom DC DC Nominal input voltage Vi DC DC Input voltage ranges Normal operating (Vi min to Vi max) Vi red Derated Input Voltage Range See Figure 20 and Figure 33 Ii max Max Input Current Vi > 200 VAC, >100VAC Ii p Inrush Current Limitation Vi min to Vi max, 0 TNTC = 25C (Figure 5) Fi Input Frequency PF Power Factor Turn-on Input Vi off Turn-off Input Voltage2) Thold 2) The 4.1 Voltage2) Efficiency without Fan Hold-up Time NOM MAX UNIT 100 230 277 VAC 90 300 VAC 240 380 VDC 192 400 VDC 90 180 VAC 17 Arms 47 Vi nom, 50Hz, > 0.3 I1 nom Vi on Normal operating (Vi min to Vi max) MIN 50/60 50 Ap 63 Hz 0.96 W/VA Ramping up 80 87 VAC Ramping down 75 85 VAC Vi nom, 0.1Ix nom, Vx nom, TA = 25C 90.0 91.85 Vi nom, 0.2Ix nom, Vx nom, TA = 25C 93.0 94.40 Vi nom, 0.5Ix nom, Vx nom, TA = 25C 94.5 94.95 Vi nom, Ix nom, Vx nom, TA = 25C 93.0 93.75 After last AC zero point, V1 > 10.8V, VSB within regulation, Vi = 230VAC, Px nom 12 % ms Front-End is provided with a minimum hysteresis of 3V during turn-on and turn-off within the ranges. INPUT FUSE Quick-acting 25 A input fuses (6.3 x 32 mm) in series with both the L- and N-line inside the power supply protect against severe defects. The fuses are not accessible from the outside and are therefore not serviceable parts. 4.2 INRUSH CURRENT The AC-DC power supply exhibits an X-capacitance of only 4.3F, resulting in a low and short peak current, when the supply is connected to the mains. The internal bulk capacitor will be charged through an NTC which will limit the inrush current. NOTE: Do not repeat plug-in / out operations within a short time, or else the internal in-rush current limiting device (NTC) may not sufficiently cool down and excessive inrush current or component failure(s) may result. 4.3 INPUT UNDER-VOLTAGE If the RMS value of input voltage (either AC or DC) stays below the input undervoltage lockout threshold Vi on, the supply will be inhibited. Once the input voltage returns within the normal operating range, the supply will return to normal operation again. 4.4 POWER FACTOR CORRECTION Power factor correction (PFC) (see Figure 4) is achieved by controlling the input current waveform synchronously with the input voltage. A fully digital controller is implemented giving outstanding PFC results over a wide input voltage and load ranges. The input current will follow the shape of the input voltage. If for instance the input voltage has a trapezoidal waveform, then the current will also show a trapezoidal waveform. At DC input voltage the PFC is still in operation, but the input current will be DC in this case. 4.5 EFFICIENCY The high efficiency (see Figure 2) is achieved by using state-of-the-art silicon power devices in conjunction with soft-transition topologies minimizing switching losses and a full digital control scheme. Synchronous rectifiers on the output reduce the losses in the high current output path. The rpm of the fan is digitally controlled to keep all components at an optimal operating temperature regardless of the ambient temperature and load conditions. Figure 3 shows efficiency when input voltage is supplied from a high voltage DC source. BCD.00297_AA Nov-25-2013 3 www.power-one.com DATA SHEET Figure 3 - DC Input Efficiency vs. load current (ratio metric loading) 96 96 95 95 94 94 93 93 Efficiency [%] Efficiency [%] Figure 2 - AC Input Efficiency vs. Load current (ratio metric loading) 92 91 Vi = 230Vac, fan internal Vi = 230Vac, fan external Platinum 90 89 500 1000 1500 2000 91 Vi = 380Vdc, fan internal Vi = 380Vdc, fan external Platinum 90 89 88 0 92 2500 88 3000 0 Po [W] Figure 4 - Power factor vs. Load current 500 1000 1500 Po [W] 2000 2500 3000 Figure 5 - Inrush current, Vin = 230Vac, 0phase angle CH4: Vin (200V/div), CH3: Iin (10A/div) 1 0,96 Power factor 0,92 0,88 Vi = 230Vac Vi = 277Vac Vi = 300Vac 0,84 0,8 0 500 1000 1500 2000 2500 3000 Po [W] 5 OUTPUT General Condition: Ta = 0 ... +45 C unless otherwise noted. PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT +0.5 % V1 nom +1 % V1 nom Main Output V1 V1 nom Nominal Output Voltage V1 set Output Setpoint Accuracy dV1 tot Total Regulation Vi min to Vi max, 0 to 100% I1 nom, Ta min to Ta max P1 nom Nominal Output Power V1 = 12.3 VDC, Vin < 180Vac I1 nom Nominal Output Current P1 nom Nominal Output Power I1 nom 0.5 I1 nom, Tamb = 25 C 12.3 -0.5 -1 VDC 1400 W V1 = 12.3 VDC, Vin < 180Vac 114 ADC V1 = 12.3 VDC, Vin > 180Vac 3000 W Nominal Output Current V1 = 12.3 VDC, Vin > 180Vac 244 ADC IV1 ol Short time over load current V1 = 12.3 VDC, Vin > 180Vac Ta min to Ta max, maximum duration 20ms (See Section 5.2) 292 A v1 pp Output Ripple Voltage V1 nom, I1 nom, 20MHz BW (See Section 5.1) 160 mVpp dV1 Load Regulation Load dV1 Line Vi = Vi nom, 0 - 100 % I1 nom Line Regulation Vi =Vi min...Vi max I1 max Current limitation Vi < 180 VAC, Vi < 180 VAC, Vi > 180 VAC, Vi > 180 VAC, dIshare Current Sharing dVdyn Dynamic Load Regulation BCD.00297_AA Nov-25-2013 mV 170 0 mV 120 92 127 99 248 186 274 212 Deviation from I1 tot / N, I1 > 25% I1 nom -5% +5% A I1 = 50% I1 nom, I1 = 5 ... 100% I1 nom, -0.6 0.6 V Ta < 45C Ta = 55 C 3) Ta < 45C Ta = 55 C 3) 4 ADC www.power-one.com DATA SHEET 3) Trec Recovery Time dI1/dt = 1A/s, recovery within 1% of V1 nom tAC V1 Start-up Time from AC V1 = 10.8 VDC (see Figure 7) tV1 rise Rise Time V1 = 10...90% V1 nom (see Figure 8) CLoad Capacitive Loading Ta = 25C 0.5 ms 3 sec 2.5 ms 30000 F see Figure 20 for linear derating > 45C PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT +0.5 %VSBnom +1 %VSBnom Standby Output VSB VSB nom Nominal Output Voltage VSB set Output Setpoint Accuracy 12 dVSB tot Total Regulation Vi min to Vi max, 0 to 100% ISB nom, Ta min to Ta max PSB nom Nominal Output Power VSB = 12 VDC 60 ISB nom Nominal Output Current VSB = 12 VDC 5 VSB pp Output Ripple Voltage VSB nom, ISB nom, 20 MHz BW (See Section 5.1) dVSB Droop 0 - 100 % ISB nom ISB max Current Limitation dVSBdyn Dynamic Load Regulation 0.5 ISB nom, Tamb = 25C -0.5 -1 W ADC 120 200 Recovery Time ISB = 50% ISB nom, ISB = 5 ... 100% ISB nom, dIo/dt = 1 A/s, recovery within 1% of V1 nom tAC VSB Start-up Time from AC VSB = 90% VSB nom (see Figure 7) tVSB rise Rise Time Trec VDC mVpp mV 6 9 ADC -0.6 0.6 VSBnom 0.5 ms 2 sec VSB = 10...90% VSB nom (see 10 ms Figure 9) CLoad 5.1 Capacitive Loading Tamb = 25C 3000 F OUTPUT VOLTAGE RIPPLE The internal output capacitance at the power supply output (behind OR-ing element) is minimized to prevent disturbances during hot plug. In order to provide low output ripple voltage in the application, external capacitors should be added close to the power supply output. The setup of Figure has been used to evaluate suitable capacitor types. The capacitor combinations of Table 1 and Table 2 should be used to reduce the output ripple voltage. The ripple voltage is measured with 20 MHz BWL, close to the external capacitors. Figure 6 - Output ripple test setup L Vout N C PSU Probe Load Gnd Scope 20MHz BW Note: Care must be taken when using ceramic capacitors with a total capacitance of 1 F to 50 F on output V1, due to their high quality factor the output ripple voltage may be increased in certain frequency ranges due to resonance effects. Table 1 - Suitable capacitors for V1 External capacitor V1 2Pcs 47F/16V/X5R/1210 1Pcs 1000F/16V/Low ESR Aluminum/o10x20 1Pcs 270F/16V/Conductive Polymer/o8x12 2Pcs 47F/16V/X5R/1210 plus 1Pcs 270F Conductive Polymer OR 1Pcs 1000F Low ESR AlCap BCD.00297_AA Nov-25-2013 dV1max 160 160 160 90 Table 2 - Suitable capacitors for VSB Unit mVpp mVpp mVpp mVpp External capacitor VSB 1Pcs 10F/16 V/X7R/1206 5 dV1max 80 Unit mVpp www.power-one.com DATA SHEET The output ripple voltage on VSB is influenced by the main output V1. Evaluating VSB output ripple must be done when maximum load is applied to V1. 5.2 SHORT TIME OVERLOAD The main output has a capability to allow load current to reach 120% of the nominal output current rating for a maximum duration of 20ms. This allows the system to consume extended power for short time dynamic processes. 5.3 OUTPUT ISOLATION Main and standby output and all signals are isolated from the chassis and protective earth connection, although the applied voltage must not exceed 100Vpeak to prevent any damage of the supply. Internal to the supply the main output ground, standby output ground and signal ground are interconnected through 10ohm resistors to prevent any circulating current within the supply. In order to prevent any potential difference in outputs or signals within the application these 3 grounds must be directly interconnected at system level. See also section 14 for pins to be interconnected. Figure 7: Turn-On AC Line 230 VAC, full load (500 ms/div) Figure 8: Turn-On AC Line 230 VAC, full load (1 ms/div) CH1: V1 (2 V/div); CH2: VSB (2 V/div); CH3: Vin (200 V/div) CH1: V1 (2 V/div) Figure 9: Turn-On AC Line 230 VAC, full load (5 ms/div) Figure 10: CH2: VSB (2 V/div) BCD.00297_AA Nov-25-2013 Turn-Off AC Line 230 VAC, full load (20 ms/div) CH1: V1 (2 V/div); CH2: VSB (2 V/div); CH3: Vin (200 V/div) 6 www.power-one.com DATA SHEET Figure 11: Short circuit on V1 (50ms/div) CH1: V1 (2V/div) CH2: VSB (2V/div) CH4: I1 (200A/div) Figure 12: AC drop out 12ms (10ms/div) CH1: V1 (2V/div) CH2: VSB (2V/div) CH3: Vin (200V/div) Figure 13: AC drop out 40 ms, full load (20 ms/div) CH1: V1 (2 V/div); CH2: VSB (2 V/div); CH3: Vin (200 V/div) AC drop out 40 ms, full load (200 ms/div), V1 restart after 1 sec CH1: V1 (5 V/div); CH2: VSB (2 V/div); CH3: I1 (200 V/div) Figure 15: Load transient V1, 3 to 125 A (500 s/div) CH1: V1 (200 mV/div); CH4: I1 (100 A/div) Figure 16: Load transient V1, 125 to 3 A (500 s/div) CH1: V1 (200 mV/div); CH4: I1 (100 A/div) BCD.00297_AA Nov-25-2013 Figure 14: 7 www.power-one.com DATA SHEET Figure 17: Load transient V1, 122 to 244 A (500 s/div) CH1: V1 (200 mV/div); CH4: I1 (100 A/div) 6 PROTECTION PARAMETER F Input Fuses (L+N) V1 OV OV Threshold V1 tOV V1 OV Latch Off Time V1 VSB OV OV Threshold VSB tOV VSB OV Latch Off Time VSB 4) DESCRIPTION / CONDITION MIN Not user accessible, quick-acting (F) MAX 25 13.6 13.3 Ta < 45C Ta = 55 C 3) Ta < 45C Ta = 55 C 3) NOM 14.2 13.9 UNIT A 14.8 VDC 1 ms 14.5 VDC 1 ms 120 92 127 99 248 186 274 212 IV1 lim Current limitation Vi < 180 VAC, Vi < 180 VAC, Vi > 180 VAC, Vi > 180 VAC, tV1 lim Current limit blanking time Time to latch off when in over current 20 22 24 ms IV1 ol lim Current limit during short time overload V1 Maximum duration 20ms 292 300 308 A IV1 SC Max Short Circuit Current V1 V1 < 3V tV1 SC off Short circuit latch off time Time to latch off when in short circuit IVSB lim Current limitation VSB 9 A tVSB lim Current limit blanking time Time to hit hiccup when in over current 1 ms Over temperature on critical points Inlet Ambient Temperature PFC Primary Heatsink Temperature Secondary Sync Mosfet Temperature Secondary OR-ing Mosfet Temperature 60 80 115 125 C TSD 3) Figure 18: Load transient V1, 244 to 122 A (500 s/div) CH1: V1 (200 mV/div); CH4: I1 (100 A/div) 350 4) 10 6 A A ms See Figure 20 for linear derating > 45C Limit set don't include effects of main output capacitive discharge. 6.1 AUTOMATIC RETRY For all fault conditions except current limitation on Standby output, the supply will shut down for 10sec and restart automatically. The supply will restart from a fault up to 5 times, after that it will latch off. The latch and restart counter can be cleared by disconnecting the input voltage or by toggling the PSON_L input. A failure on one output will only shut down this output, while the other one will continue to operate 6.2 OVERVOLTAGE PROTECTION The PFE front-ends provide a fixed threshold overvoltage (OV) protection implemented with a HW comparator. Once an OV condition has been triggered, the supply will shut down and latch the fault condition. BCD.00297_AA Nov-25-2013 8 www.power-one.com DATA SHEET 6.3 UNDERVOLTAGE DETECTION Both main and standby outputs are monitored. LED and PWOK_L pin signal if the output voltage exceeds 7% of its nominal voltage. Output undervoltage protection is provided on both outputs. When either V1 or VSB falls below 93% of its nominal voltage, the output is inhibited. 6.4 CURRENT LIMITATION MAIN OUTPUT: Two different over current protection features are implemented on the main output. A static over current protection will shut down the output, if the output current does exceed IV1 lim for more than 20ms. If the output current is increased slowly this protection will shut down the supply. The main output current limitation level IV1lim will decrease if the ambient (inlet) temperature increases beyond 45 C (see Figure 20). Note that the actual current limitation on V1 will kick in at a current level approximately 20A higher than what is shown in Figure 20 (see also section 9 for additional information). The 2nd protection is a substantially rectangular output characteristic controlled by a software feedback loop. This protects the power supply and system during the 20ms blanking time of the static over current protection. If the output current is rising fast and reaches IV1 ol lim, the supply will immediately reduce its output voltage to prevent the output current from exceeding IV1 ol lim. When the output current is reduced below IV1 ol lim, the output voltage will return to its nominal value. Figure 19 - Current Limitation on V1 (Vi = 230VAC) Figure 20: Derating on V1 vs. Ta 250 10 Main Output Nominal Current [A] Main Output Voltage [V] 12 8 6 4 Force Current Limitation Static Over Current Protection 2 0 0 100 200 300 200 150 100 Nominal Current > 180Vac Current Limitation > 180Vac Nominal Current < 180Vac Current Limitation < 180Vac 50 0 0 11 Main Output Current [A] 22 33 44 55 Ambient Temperature [C] STANDBY OUTPUT On the standby output a hiccup type over current protection is implemented. This protection will shut down the standby output immediately when standby current reaches or exceeds IVSB lim. After an off-time of 1s the output automatically tries to restart. If the overload condition is removed the output voltage will reach again its nominal value. At continuous overload condition the output will repeatedly trying to restart with 1s intervals. Figure 21: Current limitation on VSB Standby Output Voltage [V] 12 10 8 6 4 2 0 0 2 4 6 8 Standby Output Current [A] BCD.00297_AA Nov-25-2013 9 www.power-one.com DATA SHEET 7 MONITORING PARAMETER Vi mon Input RMS Voltage Ii mon Input RMS Current Pi mon True Input Power V1 mon V1 Voltage I1 mon V1 Current Po nom Total Output Power VSB mon Standby Voltage ISB mon Standby Current 8 DESCRIPTION / CONDITION MIN Vi min Vi Vi max -2.5 NOM MAX UNIT +2.5 % Ii > 4 Arms -5 +5 % Ii 4 Arms -0.2 +0.2 Arms Pi > 700 W -5 +5 % Pi 700 W -35 +35 W -2 +2 % I1 > 30 A -2 +2 % I1 30 A -0.6 +0.6 A Po > 200 W -5 +5 % Po 200 W -10 +10 W -2 +2 % ISB ISB nom -0.2 +0.2 A SIGNALING AND CONTROL 8.1 ELECTRICAL CHARACTERISTICS PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT PSKILL / PSON_L inputs VIL Input low level voltage -0.2 0.8 V VIH Input high level voltage 2.0 3.6 V IIL, H Maximum input sink or source current 1 mA 0 RpuPSKILL Internal pull up resistor on PSKILL 10 k RpuPSON_L Internal pull up resistor on PSON_L 10 k PWOK_L output VOL Output low level voltage VpuPWOK_L External pull up voltage RpuPWOK_L Recommended external pull up resistor on PWOK_L at VpuPWOK_L = 3.3V Low level output All outputs are turned on and within regulation High level output In standby mode or V1/VSB have triggered a fault condition Isink < 4 mA -0.2 0.4 V 12 V 10 k INOK_L output VOL Output low level voltage VpuINOK_L External pull up voltage RpuINOK_L Recommended external pull up resistor on INOK_L at VpuINOK_L= 3.3V Low level output Input voltage is within range for PSU to operate High level output Input voltage is not within range for PSU to operate Isink < 4 mA -0.2 0.4 V 12 V 10 k SMB_ALERT_L output VOL Output low level voltage VpuSMB_ALERT_L External pull up voltage RpuSMB_ALERT_L Recommended external pull up resistor on SMB_ALERT_L at VpuSMB_ALERT_L= 3.3V Low level output PSU in warning or failure condition High level output PSU is ok BCD.00297_AA Nov-25-2013 Isink < 4 mA -0.2 10 10 0.4 V 12 V k www.power-one.com DATA SHEET 8.2 INTERFACING WITH SIGNALS A 15V zener diode is added on all signal pins versus signal ground SGND to protect internal circuits from negative and high positive voltage. Signal pins of several supplies running in parallel can be interconnected directly. A supply having no input power will not affect the signals of the paralleled supplies. ISHARE pins must be interconnected without any additional components. This in-/output also has a 15 V zener diode as a protection device and is disconnected from internal circuits when the power supply is switched off. 8.3 FRONT LEDS The front-end has 2 front LEDs showing the status of the supply. LED number one is green and indicates AC power is on or off, while LED number two is bi-colored: green and yellow, and indicates DC power presence or fault situations. For the position of the LEDs see Table 3 lists the different LED status. Table 3 - LED Status OPERATING CONDITION AC LED AC Line within range AC Line UV condition DC LED 5) Normal Operation PSON_L High V1 or VSB out of regulation Over temperature shutdown Output over voltage shutdown (V1 or VSB) Output under voltage shutdown (V1 or VSB) Output over current shutdown (V1 or VSB) Over temperature warning Minor fan regulation error (>5%, <15%) 5) 8.4 LED SIGNALING Solid Green Off Solid Green Blinking Yellow (1:1) Solid Yellow Blinking Yellow/Green (2:1) Blinking Yellow/Green (1:1) The order of the criteria in the table corresponds to the testing precedence in the controller. PRESENT_L The PRESENT_L is normally a trailing pin within the connector and will contact only once all other connector contacts are closed. This active-low pin is used to indicate to a power distribution unit controller that a supply is plugged in. The maximum sink current on PRESENT_L pin should not exceed 10 mA. Figure 22 - PRESENT_L signal pin PFE PDU V1 VSB PRESENT_L 8.5 PSKILL INPUT The PSKILL input is an active-low and normally a trailing pin in the connector and is used to disconnect the main output as soon as the power supply is being plugged out. This pin should be connected to SGND in the power distribution unit. The standby output will remain on regardless of the PSKILL input state. 8.6 AC TURN-ON / DROP-OUTS / INOK_L The power supply will automatically turn-on when connected to the AC line under the condition that the PSON_L signal is pulled low and the AC line is within range. The INOK_L is an open collector output that requires an external pull-up to a maximum of 12V indicating whether the input is within the range the power supply can use and turn on. The INOK_L signal is active-low. The timing diagram is shown in Figure 23 and referenced in Table 4. BCD.00297_AA Nov-25-2013 11 www.power-one.com DATA SHEET Table 4 - AC Turn-on / Dip Timing OPERATING CONDITION tAC VSB AC Line to 90% VVSB tAC V1 AC Line to 90% V1 tINOK_L on1 INOK_L signal on delay (start-up) tINOK_L on2 INOK_L signal on delay (dips) tV1 holdup Effective V1 holdup time tVSB holdup Effective VSB holdup time tINOK_L V1 INOK_L to V1 holdup tINOK_L VSB INOK_L to VSB holdup tV1 off Minimum V1 off time tVSB off Minimum VSB off time tV1dropout Minimum V1 dropout time tVSBdropout Minimum VSB dropout time Figure 23 - AC turn-on timing MIN MAX UNIT 2 sec 3 sec 1800 ms 0 100 ms 12 300 ms 40 300 ms 7 ms 27 ms 1000 1200 ms 1000 1200 ms 12 ms 40 ms AC Input VSB tV1 rise tVSB rise V1 tAC VSB tAC V1 PSON_L tINOK_L on1 INOK_L PWOK_L Figure 24 - AC short dips Figure 25 - AC long dips AC Input VSB tPWOK_L del AC Input TV1dropout TVSBdropout tVSB holdup VSB tVSB off tV1 holdup tV1 off V1 PSON_L INOK_L PWOK_L 8.7 tINOK_L on2 tV1 holdup V1 tINOK_L on2 PSON_L tINOK_L V1 INOK_L tPWOK_L warn PWOK_L tV1 off tINOK_L V1 tINOK_L VSB tPWOK_L warn PSON_L INPUT The PSON_L is an internally pulled-up (3.3 V) input signal to enable / disable the main output V1 of the front-end. This activelow pin is also used to clear any latched fault condition. The timing diagram is given in Figure 26 and the parameters in Table 5. Table 5 - PSON_L timing OPERATING CONDITION tPSON_L V1on PSON_L to V1 delay (on) tPSON_L V1off PSON_L to V1 delay (off) 8.8 MIN 150 0 MAX 250 100 UNIT ms ms PWOK_L SIGNAL The PWOK_L is an open collector output that requires an external pull-up to a maximum of 12 V indicating whether both VSB and V1 outputs are within regulation. This pin is active-low. The timing diagram is shown in Figure 26 and referenced in Table 6. BCD.00297_AA Nov-25-2013 12 www.power-one.com DATA SHEET Table 6 - PWOK_H timing Figure 26 - PSON_L turn-on/off timing OPERATING CONDITION tPWOK_L del V1 to PWOK_L delay (on) tPWOK_L V1 to PWOK_L delay (off) AC Input warn MIN 250 MAX 350 UNIT ms 0 5 ms VSB V1 tPSON_L V1on tV1 rise tPSON_L V1off PSON_L INOK_L PWOK_L 8.9 tPWOK_L del tPWOK_L warn CURRENT SHARE The PFE front-ends have an active current share scheme implemented for V1. All the ISHARE current share pins need to be interconnected in order to activate the sharing function. If a supply has an internal fault or is not turned on, it will disconnect its ISHARE pin from the share bus. This will prevent dragging the output down (or up) in such cases. The current share function uses an analog bus. The controller implements a Master/Slave current share function. The power supply providing the largest current among the group is automatically the Master. The other supplies will operate as Slaves and increase their output current to a value close to the Master by slightly increasing their output voltage. The voltage increase is limited to +250 mV. The standby output uses a passive current share method (droop output voltage characteristic). Table 7 - Power available when PSU in redundant operation No of paralleled PSUs Maximum available power on main 12V without redundancy Maximum available power on main 12V with n+1 redundancy Maximum available power on standby output 1 3000W - 60W 2 5850W 3000W 60W 3 8700W 5850W 60W 4 11550W 8700W 60W 5 14400W 11550W 60W 6 17250W 14400W 60W 8.10 SENSE INPUTS Main output has sense lines implemented to compensate for voltage drop on load wires. The maximum allowed voltage drop is 200 mV on the positive rail and 100 mV on the PGND rail. With open sense inputs the main output voltage will rise by 250 mV. Therefore if not used, these inputs should be connected to the power output and PGND close to the power supply connector. The sense inputs are protected against short circuit. In this case the power supply will shut down. 8.11 I2C / SMBUS COMMUNICATION The interface driver in the PFE supply is referenced to the SGND. The PFE supply is a communication slave device only; it never initiates messages on the I2C/SMBus by itself. The communication bus voltage and timing is defined in Table 8 and further characterized through: BCD.00297_AA Nov-25-2013 13 www.power-one.com DATA SHEET Figure 27 - Physical layer of communication interface There are 100k internal pull-up resistors The SDA/SCL IOs must be pull-up externally to 3.30.3V Pull-up resistor should be 2 - 5k to ensure SMBUS compliant signal rise times Full SMBus clock speed of 100 kbps Clock stretching limited to 1 ms SCL low time-out of >25 ms with recovery within 10 ms Recognizes any time Start/Stop bus conditions 3.3V RX 3.3V 100k TX Rpull-up SDA/SCL PFE The SMB_ALERT_L signal indicates that the power supply is experiencing a problem that the system agent should investigate. This is a logical OR of the Shutdown and Warning events. Communication to the DSP or the EEPROM will be possible as long as the input AC (DC) voltage is provided. If no AC (DC) is present, communication to the unit is possible as long as it is connected to a live VSB output (provided e.g. by the redundant unit). If only V1 is provided, communication is not possible. Table 8 - I2C / SMBus Specification PARAMETER DESCRIPTION CONDITION ViL ViH Vhys VoL tr tof Ii Ci fSCL Rpu tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO Input low voltage Input high voltage Input hysteresis Output low voltage Rise time for SDA and SCL Output fall time ViHmin ViLmax Input current SCL/SDA Capacitance for each SCL/SDA SCL clock frequency External pull-up resistor Hold time (repeated) START Low period of the SCL clock High period of the SCL clock Setup time for a repeated START tBUF Data hold time Data setup time Setup time for STOP condition Bus free time between STOP and START EEPROM_WP ViL ViH Ii Rpu Input low voltage Input high voltage Input sink or source current Internal pull-up resistor to 3.3V 5) 4 mA sink current 10 pF < Cb1 < 400 pF 0.1 VDD < Vi < 0.9 VDD MIN MAX UNIT -0.2 2.1 0.15 0 20+0.1Cb1 20+0.1Cb1 -10 0.4 3.6 V V V V ns ns A pF kHz s s s s s ns s 0 fSCL 100 kHz fSCL 100 kHz fSCL 100 kHz fSCL 100 kHz fSCL 100 kHz 4.0 4.7 4.0 4.7 fSCL 100 kHz fSCL 100 kHz fSCL 100 kHz 0 250 4.0 fSCL 100 kHz 4.7 0.4 300 250 10 10 100 1000 ns / Cb5) 3.45 s -0.2 2.1 -1 0.4 3.6 1 V V mA 10k Cb = Capacitance of bus line in pF, typically in the range of 10...400 pF Figure 28 - I2C / SMBus Timing tof tLOW tHIGH tLOW tr SDA tSUSTA tHDSTA tHDDAT tSUDAT tSUSTO tBUF SCL BCD.00297_AA Nov-25-2013 14 www.power-one.com DATA SHEET 8.12 ADDRESS The supply supports PMBus communication protocol, address for PMBus communication is at fixed to 0x20. The EEPROM is at fixed address = 0xA0. 8.13 CONTROLLER AND EEPROM ACCESS The controller and the EEPROM in the power supply share the same I2C bus physical layer (see Figure 29). In order to write to the EEPROM, the write protection needs to be disabled by setting EEPROM_WP input correctly The EEPROM provides 2k bytes of user memory. None of the bytes are used for the operation of the power supply. Figure 29 - I2C Bus to DSP and EEPROM Address 3.3V SDAi SDA DSP SCLi SCL EEPROM_WP WP EEPROM Addr Protection PFE 8.14 EEPROM PROTOCOL The EEPROM follows the industry communication protocols used for this type of device. Even though page write / read commands are defined, it is recommended to use the single byte write / read commands. WRITE The write command follows the SMBus 1.1 Write Byte protocol. After the device address with the write bit cleared a first byte with the data address to write to is sent followed by the data byte and the STOP condition. A new START condition on the bus should only occur after 5ms of the last STOP condition to allow the EEPROM to write the data into its memory. S Address W A Data Address A Data A P READ The read command follows the SMBus 1.1 Read Byte protocol. After the device address with the write bit cleared the data address byte is sent followed by a repeated start, the device address and the read bit set. The EEPROM will respond with the data byte at the specified location. S Address W A S Address R Data Address A Data A nA P 8.15 PMBusTM PROTOCOL The Power Management Bus (PMBusTM) is an open standard protocol that defines means of communicating with power conversion and other devices. For more information, please see the System Management Interface Forum web site at : www.powerSIG.org. PMBusTM command codes are not register addresses. They describe a specific command to be executed. The PFE1100-12-054xA supply supports the following basic command structures: Clock stretching limited to 1 ms SCL low time-out of >25 ms with recovery within 10 ms Recognized any time Start/Stop bus conditions WRITE The write protocol is the SMBus 1.1 Write Byte/Word protocol. Note that the write protocol may end after the command byte or after the first data byte (Byte command) or then after sending 2 data bytes (Word command). BCD.00297_AA Nov-25-2013 15 www.power-one.com DATA SHEET S Address W A Data Low Byte1) A 1) Command A Data High Byte1) A P Optional In addition, Block write commands are supported with a total maximum length of 255 bytes. See PFE Programming Manual for further information. S Address W A Byte 1 Command A A Byte Count A Byte N A P READ The read protocol is the SMBus 1.1 Read Byte/Word protocol. Note that the read protocol may request a single byte or word. S Address W A S Address R 1) A Command A Data (Low) Byte A Data High Byte1) nA P Optional In addition, Block read commands are supported with a total maximum length of 255 bytes. See PFE3000-12-069RA PMBus Communication Manual BCA.00070 for further information. S Address W A Byte Count A Command Byte 1 A A S Address R Byte N A nA P 8.16 GRAPHICAL USER INTERFACE Power-One provides with its "Power-One I2C Utility" a Windows(R) XP/Vista/Win7 compatible graphical user interface allowing the programming and monitoring of the PFE3000-12-069A Front-End. The utility can be downloaded on www.power-one.com and supports both the PSMI and PMBusTM protocols. The GUI allows automatic discovery of the units connected to the communication bus and will show them in the navigation tree. In the monitoring view the power supply can be controlled and monitored. If the GUI is used in conjunction with the PFE3000-12-069RA Evaluation Kit it is also possible to control the PSON_L pin(s) of the power supply. Figure 30 - Monitoring dialog of the I2C Utility BCD.00297_AA Nov-25-2013 16 www.power-one.com DATA SHEET 9 TEMPERATURE AND FAN CONTROL To achieve best cooling results sufficient airflow through the supply must be ensured. Do not block or obstruct the airflow at the rear of the supply by placing large objects directly at the output connector. The PFE3000-12-069RA is provided with a reverse airflow, which means the air enters through the front of the supply and leaves at the rear. PFE supplies have been designed for horizontal operation. The fan inside of the supply is controlled by a microprocessor. The rpm of the fan is adjusted to ensure optimal supply cooling and is a function of output power and the inlet temperature. Figure 31 - Airflow direction Airflow Direction Figure 32 - Fan speed vs. main output load for PFE3000-12-069RA Figure 33 - Thermal derating for PFE3000-12-069RA 3000 20 Main Output Power [W] Fan Speed [1000xRPM] 25 15 10 25C 45C 55C 5 0 0% 20% 40% 60% 80% 2250 1500 750 Vi > 180VAC Vi < 180VAC 0 100% 0 Main Output Current [%] 11 22 33 Ambient Temperature [C] 44 55 10 ELECTROMAGNETIC COMPATIBILITY 10.1 IMMUNITY NOTE: Most of the immunity requirements are derived from EN 55024:1998/A2:2003. PARAMETER DESCRIPTION / CONDITION ESD Contact Discharge ESD Air Discharge Radiated Electromagnetic Field Burst Surge RF Conducted Immunity Voltage Dips and Interruptions BCD.00297_AA Nov-25-2013 IEC / EN 61000-4-2, 8 kV, 25+25 discharges per test point (metallic case, LEDs, connector body) IEC / EN 61000-4-2, 15 kV, 25+25 discharges per test point (non-metallic user accessible surfaces) IEC / EN 61000-4-3, 10 V/m, 1 kHz/80% Amplitude Modulation, 1 s Pulse Modulation, 10 kHz...2 GHz IEC / EN 61000-4-4, level 3 AC port 2 kV, 1 minute DC port 1 kV, 1 minute IEC / EN 61000-4-5 Line to earth: level 3, 2 kV Line to line: level 2, 1 kV IEC/EN 61000-4-6, Level 3, 10 Vrms, CW, 0.1 ... 80 MHz IEC/EN 61000-4-11 1: Vi 230Volts, 100% Load, Dip 100%, Duration 12ms 2: Vi 230Volts, 100% Load, Dip 100%, Duration < 150 ms 3. Vi 230Volts, 100% Load, Dip 100%, Duration > 150 ms 17 CRITERION A A A A A A A V1: B, VSB: A B www.power-one.com DATA SHEET 10.2 EMISSION PARAMETER DESCRIPTION / CONDITION Conducted Emission Radiated Emission Harmonic Emissions EN55022 / CISPR 22: 0.15 ... 30 MHz, QP and AVG, EN55022 / CISPR 22: 30 MHz ... 1 GHz, QP, IEC61000-3-2, Vin = 115/230 VAC, 50 Hz, 100% Load Sound power statistical declaration (ISO 9296, ISO 7779, IS9295) @ 50% load IEC / EN 61000-3-3, dmax < 3.3% Acoustical Noise AC Flicker CRITERION Class A Class A Class A 60 dBA PASS 11 SAFETY / APPROVALS Maximum electric strength testing is performed in the factory according to IEC/EN 60950, and UL 60950. Input-to-output electric strength tests should not be repeated in the field. Power-One will not honor any warranty claims resulting from electric strength field tests. PARAMETER Agency Approvals DESCRIPTION / CONDITION MIN UL 60950-1 Second Edition CAN/CSA-C22.2 No. 60950-1-07 Second Edition IEC 60950-1:2005 EN 60950-1:2006 NOM dC Creepage / Clearance Basic Input (L/N) to output Reinforced Output to case (PE) Functional Primary (L/N) to protective earth (PE) mm Primary to secondary According to safety standard Input to case Electrical Strength Test UNIT Approved by independent body (see CE Declaration) Input (L/N) to case (PE) Isolation Strength MAX Input to output kVAC Output and Signals to case 12 ENVIRONMENTAL PARAMETER TA TAext TS Na DESCRIPTION / CONDITION MAX UNIT 0 +45 C Derated output (see Figure 20 and Figure 33) +45 +55 C Non-operational -20 +70 C 10,000 Feet Ambient Temperature Vi min to Vi max, I1 nom, ISB nom Extended Temp. Range Storage Temperature Altitude Operational, above Sea Level Audible Noise Vi nom, 50% Io nom, TA = 25C Cooling System Back Pressure MIN NOM 60 dBA 0.5 in-H20 13 MECHANICAL PARAMETER DESCRIPTION / CONDITION Width Dimensions M NOM MAX UNIT 69 Height 42 Depth 555 Weight BCD.00297_AA Nov-25-2013 MIN 2.60 18 mm kg www.power-one.com DATA SHEET Figure 34: Bottom view NOTE: A 3D step file of the power supply casing is available on request. Figure 35: Side view Reverse Air Flow Direction Figure 36: Top view Figure 37: Front and rear view DC LED AC LED BCD.00297_AA Nov-25-2013 19 www.power-one.com DATA SHEET 14 CONNECTIONS 1 2 P1 Unit: Counterpart: P2 3 P3 P4 D C B P5 A 4 1 2 3 4 5 FCI Connectors P/N 51939-768LF FCI Connectors P/N 51915-401LF For Main Output Pins, see section 15 Note: A1 and A2 are Trailing Pin (short pins) Pin Output Name Description 3,4 1,2 V1 PGND +12 VDC main output +12 VDC main output ground Input Pins P1 P2 P3 P4 P5 LIVE N.C NEUTRAL N.C. P.E. AC Live Pin No metal pin connection AC Neutral Pin No metal pin connection Protective Earth Pin Control Pins A1 PSKILL Power supply kill (trailing pin): active-low B1 PWOK_L Power OK signal output: active-low C1 INOK_L Input OK signal: active-low D1 PSON_L Power supply on input: active-low A2 PRESENT_L Power supply present (trailing pin): active-low B2 SGND Signal ground6) (return) C2 SGND Signal ground6) (return) D2 SGND Signal ground6) (return) A3 SCL I2C clock signal line B3 SDA I2C data signal line C3 SMB_ALERT_L SMB Alert signal output: active-high D3 ISHARE V1 Current share bus A4 EEPROM_WP EEPROM write protect B4 RESERVED Reserved C4 V1_SENSE_R Main output negative sense D4 V1_SENSE Main output positive sense A5 VSB Standby positive output B5 VSB Standby positive output C5 VSB_GND Standby Ground6) D5 VSB_GND Standby Ground6) 6) These pins should be connected to PGND on the system. See section 8 for pull up resistor settings of signal pins All signal pins are referred to SGND BCD.00297_AA Nov-25-2013 20 www.power-one.com DATA SHEET 15 SHELF LEVEL CONFIGURATION BCD.00297_AA Nov-25-2013 21 www.power-one.com DATA SHEET 16 ACCESSORIES ITEM DESCRIPTION ORDERING PART NUMBER SOURCE Power-One I2C Utility Windows XP/Vista/7 compatible GUI to program, control and monitor PFE Front-Ends (and other I2C units) N/A Single Connector Board Connector board to operate PFE3000-12-069RA unit. Includes an on-board USB to I2C converter (use Power-One I2C Utility as desktop software). YTM.U0M00.0 Power-One C20F.0011 Schurter Inc. 20GENG3E-R Delta Electronics AC Can Filter Recommended AC can filter used on system side. www.power-one.com NUCLEAR AND MEDICAL APPLICATIONS - Power-One products are not designed, intended for use in, or authorized for use as critical components in life support systems, equipment used in hazardous environments, or nuclear control systems without the express written consent of the respective divisional president of Power-One, Inc. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on the date manufactured. Specifications are subject to change without notice. BCD.00297_AA Nov-25-2013 22 www.power-one.com