PCA9518PW-T - NXP Semiconductors / Philips Semiconductors

1. General description

The PCA9518 is a BiCMOS integrated circuit intended for application in I2C-bus and

SMBus systems.

While retaining all the operating modes and features of the I2C-bus system, it permits

extension of the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus

enabling virtually an unlimited number of buses of 400 pF.

The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length.

Using the PCA9518 enables the system designer to divide the bus into an unlimited

number of segments off of a hub where any segment to segment transition sees only one

repeater delay and is multiple master capable on each segment.

Using multiple PCA9518 parts, any width hub (in multiples of ﬁve)1 can be implemented

using the expansion pins.

The PCA9518 is a wider voltage range (2.3 V to 3.6 V) version of the PCA9518 and also

improves partial power-down performance, keeping I2C-bus I/O pins in high-impedance

state when VDD is below 2.0 V.

A PCA9518 cluster cannot be put in series with a PCA9515/16 or with another

PCA9518 cluster. Multiple PCA9518 devices can be grouped with other PCA9518

devices into any size cluster thanks to the EXPxxxn pins that allow the I2C-bus signals to

be sent/received from/to one PCA9518 to/from another PCA9518 within the cluster. Since

there is no direction pin, slightly different ‘legal’ low voltage levels are used to avoid

lock-up conditions between the input and the output of individual repeaters in the cluster.

A ‘regular LOW’ applied at the input of any of the PCA9518 devices will then be

propagated as a ‘buffered LOW’ with a slightly higher value to all enabled outputs in the

PCA9518 cluster. When this ‘buffered LOW’ is applied to a PCA9515 and PCA9516 or

separate PCA9518 cluster (not connected via the EXPxxxn pins) in series, the second

PCA9515 and PCA9516 or PCA9518 cluster will not recognize it as a ‘regular LOW’ and

will not propagate it as a ‘buffered LOW’ again. The PCA9510/9511/9513/9514 and

PCA9512 cannot be used in series with the PCA9515 and PCA9516 or PCA9518, but can

be used in series with themselves since they use shifting instead of static offsets to avoid

lock-up conditions.

PCA9518

Expandable 5-channel I2C-bus hub

Rev. 05 — 2 December 2008 Product data sheet

1. Only four ports per device are available if individual Enable is required.

Product data sheet Rev. 05 — 2 December 2008 2 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

2. Features

nExpandable 5 channel, bidirectional buffer

nI2C-bus and SMBus compatible

nActive HIGH individual repeater enable inputs

nOpen-drain input/outputs

nLock-up free operation

nSupports arbitration and clock stretching across the repeater

nAccommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters

nPowered-off high-impedance I2C-bus pins

nOperating supply voltage range of 3.0 V to 3.6 V

n5 V tolerant I2C-bus and enable pins

n0 Hz to 400 kHz clock frequency2

nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

nPackage offerings: SO20 and TSSOP20

3. Ordering information

2. The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.

Table 1. Ordering information

amb

−

C to +85

Type number Topside mark Package

Name Description Version

PCA9518D PCA9518D SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

PCA9518PW PCA9518 TSSOP20 plastic thin shrink small outline package; 20 leads;

body width 4.4 mm SOT360-1

Product data sheet Rev. 05 — 2 December 2008 3 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

4. Block diagram

A more detailed view of Figure 1 buffer is shown in Figure 2.

The output pull-down voltage of each internal buffer is set for approximately 0.5 V, while

the input threshold of each internal buffer is set about 0.07 V lower, when the output is

internally driven LOW. This prevents a lock-up condition from occurring.

Fig 1. Block diagram of PCA9518

PCA9518

002aae325

EXPSCL1

VCC

EXPSCL2

EXPSDA2

SCL0

EXPSDA1

SDA0

EN4

SCL1

SDA4

SDA1

SCL4

EN1

EN3

SCL2

SDA3

SDA2

SCL3

GND

BUFFER

HUB

LOGIC

BUFFER

HUB

LOGIC

BUFFER

EN2

Fig 2. Buffer detail

002aac531

to output

inc

data

enable

Product data sheet Rev. 05 — 2 December 2008 4 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 3. Pin conﬁguration for SO20 Fig 4. Pin conﬁguration for TSSOP20

PCA9518D

EXPSCL1 VCC

EXPSCL2 EXPSDA2

SCL0 EXPSDA1

SDA0 EN4

SCL1 SDA4

SDA1 SCL4

EN1 EN3

SCL2 SDA3

SDA2 SCL3

GND EN2

002aac739

PCA9518PW

002aac740

EXPSCL1 VCC

EXPSCL2 EXPSDA2

SCL0 EXPSDA1

SDA0 EN4

SCL1 SDA4

SDA1 SCL4

EN1 EN3

SCL2 SDA3

SDA2 SCL3

GND EN2

Table 2. Pin description

Symbol Pin Description

EXPSCL1 1 expandable serial clock pin 1

EXPSCL2 2 expandable serial clock pin 2

SCL0 3 serial clock bus 0

SDA0 4 serial data bus 0

SCL1 5 serial clock bus 1

SDA1 6 serial data bus 1

EN1 7 active HIGH bus 1 enable input

SCL2 8 serial clock bus 2

SDA2 9 serial data bus 2

GND 10 supply ground

EN2 11 active HIGH bus 2 enable input

SCL3 12 serial clock bus 3

SDA3 13 serial data bus 3

EN3 14 active HIGH bus 3 enable input

SCL4 15 serial clock bus 4

SDA4 16 serial data bus 4

EN4 17 active HIGH bus 4 enable input

EXPSDA1 18 expandable serial data pin 1

EXPSDA2 19 expandable serial data pin 2

VCC 20 supply voltage

Product data sheet Rev. 05 — 2 December 2008 5 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

6. Functional description

The PCA9518 BiCMOS integrated circuit is a ﬁve-way hub repeater, which enables

I2C-bus and similar bus systems to be expanded in increments of ﬁve with only one

repeater delay and no functional degradation of system performance.

The PCA9518 BiCMOS integrated circuit contains ﬁve multi-directional, open-drain buffers

speciﬁcally designed to support the standard low-level contention arbitration of the

I2C-bus. Except during arbitration or clock stretching, the PCA9518 acts like a pair of

non-inverting, open-drain buffers, one for SDA and one for SCL.

Refer to Figure 1 “Block diagram of PCA9518”.

6.1 Enable

The enable pins EN1 through EN4 are active HIGH and have internal pull-up resistors.

Each enable pin ENn controls its associated SDAn and SCLn ports. When LOW, the ENn

pin blocks the inputs from SDAn and SCLn, as well as disabling the output drivers on the

SDAn and SCLn pins. The enable pins should only change state when both the global bus

and the local port are in an idle state to prevent system failures.

The active HIGH enable pins allow the use of open-drain drivers which can be wire-ORed

to create a distributed enable where either centralized control signal (master) or spoke

signal (sub-master) can enable the channel when it is idle.

Unused channels must have pull-up resistors unless their enable pin (ENn) is always

LOW. Port 0 must always have pull-up resistors since it is always present in the bus and

cannot be disabled.

6.2 Expansion

The PCA9518 includes 4 open-drain I/O pins used for expansion. Two expansion pins,

EXPSDA1 and EXPSDA2 are used to communicate the internal state of the serial data

within each hub to the other hubs. The EXPSDA1 pins of all hubs are connected together

to form an open-drain bus. Similarly, all EXPSDA2 pins, EXPSCL1 pins, and all EXPSCL2

pins are connected together forming a 4-wire bus between hubs.

When it is necessary to be able to deselect every port, each expansion device only

contributes 4 ports which can be enabled or disables because the ﬁfth does not have an

enable pin.

Pull-up resistors are required on the EXPxxxn3 pins even if only one PCA9518 is used.

6.3 I2C-bus systems

As with the standard I2C-bus system, pull-up resistors are required to provide the logic

HIGH levels on the buffered bus. (Standard open-collector or open-drain conﬁguration of

the I2C-bus). The size of these pull-up resistors depends on the system, but each side of

the repeater must have a pull-up resistor. This part is designed to work with

Standard-mode (0 Hz to 100 kHz) and Fast-mode (0 Hz to 400 kHz) I2C-bus devices in

addition to SMBus devices. Standard-mode I2C-bus devices only specify 3 mA output

drive; this limits the termination current to 3 mA in a generic I2C-bus system where

3. ‘xxxn’ is SDA1, SDA2, SCL1 or SCL2. ‘xxx’ is SDA or SCL.

Product data sheet Rev. 05 — 2 December 2008 6 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

Standard-mode devices and multiple masters are possible. Please see application note

AN255, I

C/SMBus Repeaters, Hubs and Expanders

for additional information on sizing

resistors.

7. Application design-in information

A typical application is shown in Figure 5. In this example, the system master is running

on a 3.3 V I2C-bus while the slaves are connected to a 3.3 V or 5 V bus. All buses run at

100 kHz unless slave 3, slave 4 and slave 5 are isolated from the bus. Then the master

bus and slave 1, slave 2 and slave 6 can run at 400 kHz.

Any segment of the hub can talk to any other segment of the hub. Bus masters and slaves

can be located on any segment with 400 pF load allowed on each segment.

The PCA9518 is 5 V tolerant, so it does not require any additional circuitry to translate

between the different bus voltages.

When one port of the PCA9518 is pulled LOW by a device on the I2C-bus, a CMOS

hysteresis type input detects the falling edge and drives the EXPxxx1 line LOW, when the

EXPxxx1 voltage is less than 0.5VCC, the other ports are pulled down to the VOL of the

PCA9518 which is typically 0.5 V.

In order to illustrate what would be seen in a typical application, refer to Figure 6. If the

bus master in Figure 5 were to write to the slave through the PCA9518, we would see the

waveform shown in Figure 6. This looks like a normal I2C-bus transmission except for the

small foot preceding each clock LOW-to-HIGH transition and proceeding each data

LOW-to-HIGH transition for the master. The foot height is the difference between the LOW

level driven by the master and the higher voltage LOW level driven by the PCA9518

repeater. Its width corresponds to an effective clock stretching coming from the PCA9518

that delays the rising edge of the clock. That same magnitude of delay is seen on the

rising edge of the data. The foot on the rising edge of the data is extended through the 9th

clock pulse as the PCA9518 repeats the acknowledge from the slave to the master. The

clock of the slave looks normal except the VOL is the ~0.5 V level generated by the

PCA9518. The SDA at the slave has a particularly interesting shape during the 9th clock

cycle where the slave pulls the line below the value driven by the PCA9518 during the

acknowledge and then returns to the PCA9518 level creating a foot before it completes

the LOW-to-HIGH transition. SDA lines other than the one with the master and the one

with the slave have a uniform LOW level driven by the PCA9518 repeater.

The other four waveforms are the expansion bus signals and are included primarily for

timing reference points. All timing on the expansion bus is with respect to 0.5VCC.

EXPSDA1 is the expansion bus that is driven LOW whenever any SDA pin falls below

0.3VCC. EXPSDA2 is the expansion bus that is driven LOW whenever any pin is ≤0.4 V.

EXPSCL1 is the expansion bus that is driven LOW whenever any SCL pin falls below

0.3VCC. EXPSCL2 is the expansion bus that is driven LOW whenever any SCL pin is

≤0.4 V. The EXPSDA2 returns HIGH after the SDA pin that was the last one being held

below 0.4 V by an external driver starts to rise. The last SDA to rise above 0.4 V is held

down by the PCA9518 to ~0.5 V until after the delay of the circuit which determines that it

was the last to rise, then it is allowed to rise above the ~0.5 V level driven by the

PCA9518. Considering the bus 0 SDA to be the last one to go above 0.4 V, then the

EXPSDA1 returns to HIGH after the EXPSDA2 is HIGH and either the bus 0 SDA rise time

Product data sheet Rev. 05 — 2 December 2008 7 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

is 1 µs or, when the bus 0 SDA reaches 0.7VCC, whichever occurs ﬁrst. After both

EXPSDA2 and EXPSDA1 are HIGH the rest of the SDA lines are allowed to rise. The

same description applies for the EXPSCL1, EXPSCL2, and SCL pins.

Only two of the ﬁve channels on the PCA9518 Device 2 are being used. EN3 and EN4 are connected to GND to disable

channels 3 and 4 and/or SDA3/SCL3 and SDA4/SCL4 are pulled up to VCC. SDA0 and SCL0 can be used as a normal I2C-bus

port, but if unused then it must be pulled up to VCC since there is no enable pin.

The pull-ups shown on Device 2 channels 3 and 4 are not required if their enable pins (ENn) are permanently held LOW.

Fig 5. Typical application: multiple expandable 5-channel I2C-bus hubs

002aae326

VCC

EXPSDA2

EXPSDA1

SCL1

SDA1

GND

EXPSCL1

EXPSCL2

SUBSYSTEM 1

SDA

SCL

400 kHz

5 V

SCL2

SDA2

SUBSYSTEM 2

SDA

SCL

400 kHz

3.3 V

SCL3

SDA3

SUBSYSTEM 3

SDA

SCL

100 kHz

5 V

SCL4

SDA4

SUBSYSTEM 4

SDA

SCL

100 kHz

3.3 V

PCA9518

SCL

SDA

EN2

EN1

EN3

EN4

SCL0

SDA0

DEVICE 1

BUS

MASTER

400 kHz

3.3 V

GND

EN2

EN1

EN3

EN4

SCL4

SDA4

VCC

EXPSDA2

EXPSDA1

EXPSCL1

EXPSCL2

PCA9518

SCL0

SDA0

DEVICE 2

SCL1

SDA1

SUBSYSTEM 5

SDA

SCL

100 kHz

5 V

SCL2

SDA2

SUBSYSTEM 6

SDA

SCL

400 kHz

3.3 V

SCL3

SDA3

3.3 V

or 5 V

3.3 V

or 5 V

disabled;

not connected

Product data sheet Rev. 05 — 2 December 2008 8 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

It is important to note that any arbitration or clock stretching events on Bus 1 require that

the VOL of the devices on Bus 1 be 70 mV below the VOL of the PCA9518 (see VOL−VILc in

Section 9 “Static characteristics”) to be recognized by the PCA9518 and then transmitted

to Bus 0.

Fig 6. Bus waveforms

Bus 0

VOL of master

SCL of

master

SDA of

master

9th clock cycle

tstretch

VOL of PCA9518 9th clock cycle

EXPSDA1

tPHL1

EXPSDA2

tPHL2 tPLH2

tPLH2, tPLH1

expansion

bus

EXPSCL1

EXPSCL2

SCL of

slave

SDA of

slave

Bus 1

tPHL tPLH

Bus n

with n > 1

VOL of slave VOL of PCA9518

002aae327

tPLH1

Product data sheet Rev. 05 — 2 December 2008 9 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

8. Limiting values

[1] Voltages with respect to pin GND.

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage VCC to GND [1] −0.5 +7 V

VI2C-bus I2C-bus voltage SCL or SDA [1] −0.5 +7 V

IIinput current any pin - 50 mA

Ptot total power dissipation - 300 mW

Tstg storage temperature −55 +125 °C

Tamb ambient temperature operating −40 +85 °C

Product data sheet Rev. 05 — 2 December 2008 10 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

9. Static characteristics

[1] VIL speciﬁcation is for the ﬁrst LOW level seen by the SDAn/SCLn lines.

[2] VILc is for the second and subsequent LOW levels seen by the SDAn/SCLn lines.

[3] Test performed with IOL =10µA.

Table 4. Static characteristics

=3.0V to 3.6V; GND=0V; T

amb

−

Cto+85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VCC supply voltage 3.0 3.3 3.6 V

ICCH HIGH-level supply current both channels HIGH

VCC = 3.6 V;

SDAn = SCLn = VCC

- 7.5 10 mA

ICCL LOW-level supply current both channels LOW

VCC = 3.6 V;

one SDA and one SCL = GND;

other SDA and SCL open

- 9 11 mA

ICCLc contention LOW-level supply

current VDD = 3.6 V; SDAn = SCLn = VSS - 9 11 mA

Input SCL; input/output SDA

VIH HIGH-level input voltage SCL, SDA 0.7VCC - 5.5 V

VIL LOW-level input voltage SCL, SDA [1] −0.5 - +0.3VCC V

VILc contention LOW-level input voltage SCL, SDA [2] −0.5 - +0.4 V

VIK input clamping voltage II=−18 mA - - −1.2 V

ILI input leakage current VI= 3.6 V - - ±1µA

IIL LOW-level input current SCL, SDA; VI= 0.2 V - - 20 µA

VOL LOW-level output voltage SCL, SDA; IOL =0mA

[3] or 6 mA 0.47 0.52 0.6 V

VOL−VILc difference between LOW-level

outputandLOW-levelinputvoltage

contention

guaranteed by design - - 70 mV

Ciinput capacitance VI=3V or 0V - 6 8 pF

Enable 1 to Enable 4 (EN1 to EN4)

VIL LOW-level input voltage −0.5 - +0.8 V

VIH HIGH-level input voltage 2.0 - 5.5 V

IIL LOW-level input current VI= 0.2 V; EN1 to EN4 - 10 30 µA

ILI input leakage current −1-+1 µA

Ciinput capacitance VI= 3.0 V or 0 V - 3 7 pF

Expansion pins (EXPSCL1, EXPSCL2, EXPSDA1, EXPSDA2)

VIH HIGH-level input voltage EXPxxxn 0.55VCC - 5.5 V

VIL LOW-level input voltage EXPxxxn −0.5 - +0.45VCC V

IIL LOW-level input current EXPxxxn; VI= 0.2 V - - 5 µA

VOL LOW-level output voltage EXPxxxn; IOL =12mA - - 0.5 V

Ciinput capacitance VI= 3.0 V or 0 V - 6 8 pF

Product data sheet Rev. 05 — 2 December 2008 11 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

10. Dynamic characteristics

[1] The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times are mostly internally controlled and are

only sensitive to load capacitance. The rise times are RC time constant controlled and therefore a speciﬁc numerical value can only be

given for ﬁxed RC time constants.

[2] The SDA HIGH to LOW propagation delay includes the fall time from VCC to 0.5VCC of the EXPSDA1 or EXPSCL1 pins and the SDA or

SCL fall time from the quiescent HIGH (usually VCC) to below 0.3VCC. The SDA and SCL outputs have edge rate control circuits

included which make the fall time almost independent of load capacitance.

[3] The SDA or SCL LOW to HIGH propagation delay includes the rise time constant from the quiescent LOW to 0.5VCC for the EXPSDA1

or EXPSCL2, the rise time constant for the quiescent LOW to 0.5VCC for the EXPSDA1 or EXPSCL1, and the rise time constant from

the quiescent external driven LOW to 0.7VCC for the SDA or SCL output. All of these rise times are RC time constants determined by the

external resistance and total capacitance for the various nodes.

Table 5. Dynamic characteristics

Symbol Parameter Conditions Min Typ Max Unit

tPHL HIGH to LOW propagation delay SDA to SDAn, or

SCL to SCLn; Figure 7 [1][2] 105 202 389 ns

tPLH LOW to HIGH propagation delay SDA to SDAn, or

SCL to SCLn; Figure 7 [1][3] 110 259 265 ns

tPHL1 HIGH to LOW propagation delay 1 EXPSDA1 to SDA, or

EXPSCL1 to SCL; Figure 7 109 193 327 ns

tPLH1 LOW to HIGH propagation delay 1 EXPSDA1 to SDA, or

EXPSCL1 to SCL; Figure 7 130 153 179 ns

tPLH2 LOW to HIGH propagation delay 2 EXPSDA2 to SDA, or

EXPSCL2 to SCL; Figure 7 160 234 279 ns

tTHL HIGH to LOW output transition time SDA, SCL; Figure 7 58 110 187 ns

tTLH LOW to HIGH output transition time SDA, SCL; Figure 7 - 0.85 RC - ns

tsu set-up time enable to START condition 300 - - ns

thhold time enable after STOP condition 300 - - ns

Fig 7. AC waveforms

input SDA or SCL

tTHL

0.7VCC

002aae328

EXPSDA1 or EXPSCL1

effective

stretch

0.3VCC

0.4 V 0.3VCC

0.4 V

tTLH 0.7VCC

0.5VCC

tPHL

tPHL1

0.5VCC

EXPSDA2 or EXPSCL2

output SDA or SCL

tPHL2

tPHL1

tTHL

0.7VCC

0.3VCC

0.52 V

tPLH2

0.3VCC

tPLH

tPLH1

tPLH2

tTLH

0.7VCC

Product data sheet Rev. 05 — 2 December 2008 12 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

11. Test information

RL= load resistor; 1.1 kΩ for I2C-bus, and 500 Ω for EXPxxxn.

CL= load capacitance includes jig and probe capacitance; 100 pF for I2C-bus, and 100 pF for

EXPxxxn.

RT= termination resistance should be equal to Zo of the pulse generators.

Fig 8. Test circuit for open-drain outputs

PULSE

GENERATOR

002aad479

VCC

DUT

Product data sheet Rev. 05 — 2 December 2008 13 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

12. Package outline

Fig 9. Package outline SOT163-1 (SO20)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 13.0

12.6 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT163-1

detail X

0.25

075E04 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.51

0.49 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

vMA

(A )

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

99-12-27

03-02-19

Product data sheet Rev. 05 — 2 December 2008 14 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

Fig 10. Package outline SOT360-1 (TSSOP20)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 6.6

6.4 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.5

0.2 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT360-1 MO-153 99-12-27

03-02-19

0.25

110

20 11

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

max.

1.1

Product data sheet Rev. 05 — 2 December 2008 15 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

Product data sheet Rev. 05 — 2 December 2008 16 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

13.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 11) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 6 and 7

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 11.

Table 6. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 7. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 05 — 2 December 2008 17 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

14. Abbreviations

MSL: Moisture Sensitivity Level

Fig 11. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 8. Abbreviations

Acronym Description

CDM Charged-Device Model

BiCMOS Bipolar Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

I/O Input/Output

I2C-bus Inter-Integrated Circuit bus

MM Machine Model

RC Resistor Capacitor network

SMBus System Management Bus

Product data sheet Rev. 05 — 2 December 2008 18 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

15. Revision history

Table 9. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9518_5 20081202 Product data sheet - PCA9518_4

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Section 6.1 “Enable”: added new 3rd paragraph

•Figure 5 “Typical application: multiple expandable 5-channel I2C-bus hubs”: added 2nd paragraph

below drawing.

•Figure 6 “Bus waveforms”:

–changed symbol from “tst” to “tstretch”

–changed symbol from “tr1” to “tPHL1”

–changed symbol from “tr2” to “tPHL2”

–changed symbol from “tEr1” to “tPLH2, tPLH1”

•Table 3 “Limiting values”:

–changed symbol/parameter from “VCC to GND, supply voltage range VCC” to

“VCC, supply voltage” (and placed “VCC to GND” in Conditions column)

–changed symbol/parameter from “Vbus, voltage range I2C-bus, SCL or SDA” to

“VI2C-bus,I

2C-bus voltage” (and placed “SCL or SDA” in Conditions column)

–changed symbol/parameter from “I, DC current (any pin)” to “II, input current” (and placed

“any pin” in Conditions column)

–changed parameter for Ptot from “power dissipation” to “total power dissipation”

•Table 4 “Static characteristics”:

–sub-section “Supplies”; symbol ICCH: changed parameter from “quiescent supply current, both

channels HIGH” to “HIGH-level supply current”; moved “both channels HIGH” to Conditions

column

–sub-section “Supplies”; symbol ICCL: changed parameter from “quiescent supply current, both

channels LOW” to “LOW-level supply current”; moved “both channels LOW” to Conditions

column

–sub-section “Supplies”; symbol ICCLc: changed parameter from “quiescent supply current in

contention” to “contention LOW-level supply current”

–sub-section “Input SCL; input/output SDA”, symbol used for parameter “input leakage current”

changed from “II” to “ILI”

–sub-section “Input SCL; input/output SDA”, symbol VOL−VILc: parameter changed from “LOW

level input voltage below output LOW level voltage” to “difference between LOW-level output

and LOW-level input voltage contention”

–(old) table note 1 is split into (new) Table note [1] and Table note [2]

Product data sheet Rev. 05 — 2 December 2008 19 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

Modiﬁcations:

(continued) •Table 5 “Dynamic characteristics”:

–symbol/parameter “tPHLs, Propagation delay SDA to SDAn or SCL to SCLn” changed to

“tPHL, HIGH to LOW propagation delay” (moved “SDA to SDAn or SCL to SCLn” to Conditions

column)

–symbol/parameter “tPLHs, Propagation delay SDA to SDAn or SCL to SCLn” changed to

“tPLH, HIGH to LOW propagation delay” (moved “SDA to SDAn or SCL to SCLn” to Conditions

column)

–symbol/parameter “tPHLE1s, Propagation delay EXPSDA1 to SDA or EXPSCL1 to SCL” changed

to “tPHL1, HIGH to LOW propagation delay 1” (moved “EXPSDA1 to SDA or EXPSCL1 to SCL” to

Conditions column)

–symbol/parameter “tPLHE1s, Propagation delay EXPSDA1 to SDA or EXPSCL1 to SCL” changed

to “tPLH1, LOW to HIGH propagation delay 1” (moved “EXPSDA1 to SDA or EXPSCL1 to SCL” to

Conditions column)

–symbol/parameter “tPLHE2s, Propagation delay EXPSDA2 to SDA or EXPSCL2 to SCL” changed

to “tPLH2, LOW to HIGH propagation delay 2” (moved “EXPSDA2 to SDA or EXPSCL2 to SCL” to

Conditions column)

–symbol/parameter “tTHLs, Transition time, SDA/SCL” changed to “tTHL, HIGH to LOW transition

time” (moved “SDA, SCL” to Conditions column)

–symbol/parameter “tTLHs, Transition time, SDA/SCL” changed to “tTLH, LOW to HIGH transition

time” (moved “SDA, SCL” to Conditions column)

–symbol/parameter “tSET, Enable to Start condition” changed to “tsu, set-up time” (moved “enable

to START condition” to Conditions column)

–symbol/parameter “tHOLD, Enable after Stop condition” changed to “th, hold time” (moved

“enable to START condition” to Conditions column)

•Figure 7 “AC waveforms”: timing symbols updated as per symbol/parameter changes detailed

above for Table 5 “Dynamic characteristics”

PCA9518_4

(9397 750 14109) 20040929 Product data sheet - PCA9518_3

PCA9518_3

(9397 750 13253) 20040624 Product data sheet - PCA9518_2

PCA9518_2

(9397 750 12295) 20031110 Product data ECN 853-2364 30410

dated 2003 Oct 03 PCA9518_1

PCA9518_1

(9397 750 10258) 20020820 Product data ECN 853-2364 28791

dated 2002 Aug 20 -

Table 9. Revision history

…continued

Document ID Release date Data sheet status Change notice Supersedes

Product data sheet Rev. 05 — 2 December 2008 20 of 21

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PCA9518

Expandable 5-channel I2C-bus hub

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 December 2008

Document identifier: PCA9518_5

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 5

6.1 Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.3 I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Application design-in information . . . . . . . . . . 6

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9

9 Static characteristics. . . . . . . . . . . . . . . . . . . . 10

10 Dynamic characteristics . . . . . . . . . . . . . . . . . 11

11 Test information. . . . . . . . . . . . . . . . . . . . . . . . 12

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

13 Soldering of SMD packages . . . . . . . . . . . . . . 15

13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 15

13.2 Wave and reﬂow soldering . . . . . . . . . . . . . . . 15

13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 15

13.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 16

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20

16.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

17 Contact information. . . . . . . . . . . . . . . . . . . . . 20

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21