A
Microchip Technology Company
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
Data Sheet
www.microchip.com
Features:
Organized as 128K x16 / 256K x16 / 512K x16
Single Voltage Read and Write Operations
3.0-3.6V for SST39LF200A/400A/800A
2.7-3.6V for SST39VF200A/400A/800A
Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
Low Power Consumption
(typical values at 14 MHz)
Active Current: 9 mA (typical)
Standby Current: 3 µA (typical)
Sector-Erase Capability
Uniform 2 KWord sectors
Block-Erase Capability
Uniform 32 KWord blocks
Fast Read Access Time
55 ns for SST39LF200A/400A/800A
70 ns for SST39VF200A/400A/800A
Latched Address and Data
Fast Erase and Word-Program
Sector-Erase Time: 18 ms (typical)
Block-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Word-Program Time: 14 µs (typical)
Chip Rewrite Time:
2 seconds (typical) for SST39LF/VF200A
4 seconds (typical) for SST39LF/VF400A
8 seconds (typical) for SST39LF/VF800A
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bit
Data# Polling
CMOS I/O Compatibility
JEDEC Standard
Flash EEPROM Pinouts and command sets
Packages Available
48-lead TSOP (12mm x 20mm)
48-ball TFBGA (6mm x 8mm)
48-ball WFBGA (4mm x 6mm)
48-bump XFLGA (4mm x 6mm) 4 and 8Mbit
All non-Pb (lead-free) devices are RoHS compliant
2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
The SST39LF200A/400A/800A and SST39VF200A/400A/800A devices are 128K
x16 / 256K x16 / 512K x16 CMOS Multi-Purpose Flash (MPF) manufactured with
SST proprietary, high-performance CMOS SuperFlash technology. The split-gate
cell design and thick oxide tunneling injector attain better reliability and manufac-
turability compared with alternate approaches. The SST39LF200A/400A/800A
write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF200A/400A/
800A write (Program or Erase) with a 2.7-3.6V power supply. These devices con-
form to JEDEC standard pinouts for x16 memories.
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
2
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Product Description
The SST39LF200A/400A/800A and SST39VF200A/400A/800A devices are 128K x16 / 256K x16 /
512K x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST proprietary, high-performance
CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate approaches. The SST39LF200A/400A/800A
write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF200A/400A/800A write (Program
or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16
memories.
Featuring high-performance Word-Program, the SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices provide a typical Word-Program time of 14 µsec. The devices use Toggle Bit or Data#
Polling to detect the completion of the Program or Erase operation. To protect against inadvertent
write, they have on-chip hardware and software data protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at greater than 100 years.
The SST39LF200A/400A/800A and SST39VF200A/400A/800A devices are suited for applications that
require convenient and economical updating of program, configuration, or data memory. For all system
applications, they significantly improve performance and reliability, while lowering power consumption.
They inherently use less energy during Erase and Program than alternative flash technologies. When
programming a flash device, the total energy consumed is a function of the applied voltage, current,
and time of application. Since for any given voltage range, the SuperFlash technology uses less cur-
rent to program and has a shorter erase time, the total energy consumed during any Erase or Program
operation is less than alternative flash technologies. These devices also improve flexibility while lower-
ing the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-
gram times increase with accumulated Erase/Program cycles.
To meet surface mount requirements, the SST39LF200A/400A/800A and SST39VF200A/400A/800A
are offered in 48-lead TSOP packages and 48-ball TFBGA packages as well as Micro-Packages. See
Figures 2, 3, and 4 for pin assignments.
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
3
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Block Diagram
Figure 1: Functional Block Diagram
Pin Assignments
Figure 2: Pin Assignments for 48-Lead TSOP
Y-Decoder
I/O Buffers and Data Latches
1117 B1.2
Address Buffer Latches
X-Decoder
DQ15 -DQ
0
Memory Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1117 48-tsop P01.3
Standard Pinout
Top View
Die Up
SST39LF/VF200A
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
400A
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
800A SST39LF/VF200A
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
400A
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
800A
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
4
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Figure 3: Pin Assignments for 48-Ball TFBGA
A13
A9
WE#
NC
A7
A3
A12
A8
NC
NC
NC
A4
A14
A10
NC
NC
A6
A2
A15
A11
NC
NC
A5
A1
A16
DQ7
DQ5
DQ2
DQ0
A0
NC
DQ14
DQ12
DQ10
DQ8
CE#
DQ15
DQ13
VDD
DQ11
DQ9
OE#
VSS
DQ6
DQ4
DQ3
DQ1
VSS
1117 48-tfbga P02 2.0
SST39LF/VF200A
TOP VIEW (balls facing down)
6
5
4
3
2
1
ABCDEFGH
A13
A9
WE#
NC
A7
A3
A12
A8
NC
NC
A17
A4
A14
A10
NC
NC
A6
A2
A15
A11
NC
NC
A5
A1
A16
DQ7
DQ5
DQ2
DQ0
A0
NC
DQ14
DQ12
DQ10
DQ8
CE#
DQ15
DQ13
VDD
DQ11
DQ9
OE#
VSS
DQ6
DQ4
DQ3
DQ1
VSS
1117 48-tfbga P02 4.0
SST39LF/VF400A
TOP VIEW (balls facing down)
6
5
4
3
2
1
ABCDEFGH
A13
A9
WE#
NC
A7
A3
A12
A8
NC
NC
A17
A4
A14
A10
NC
A18
A6
A2
A15
A11
NC
NC
A5
A1
A16
DQ7
DQ5
DQ2
DQ0
A0
NC
DQ14
DQ12
DQ10
DQ8
CE#
DQ15
DQ13
VDD
DQ11
DQ9
OE#
VSS
DQ6
DQ4
DQ3
DQ1
VSS
1117 48-tfbga P02 8.0
SST39LF/VF800A
TOP VIEW (balls facing down)
6
5
4
3
2
1
ABCDEFGH
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
5
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Figure 4: Pin Assignments for 48-Ball WFBGA and 48-Bump XFLGA
A2
A1
A0
CE#
VSS
A4
A3
A5
DQ8
OE#
DQ0
A6
A7
NC
DQ10
DQ9
DQ1
A17
NC
NC
DQ2
NC
DQ3
NC
VDD
WE#
DQ12
NC
NC
NC
DQ13
A9
A10
A8
DQ4
DQ5
DQ14
A11
A13
A12
DQ11
DQ6
DQ15
A14
A15
A16
DQ7
VSS
TOP VIEW (balls facing down)
AB C D E F G H J K L
6
5
4
3
2
1
1117 48-xflga P03 4.0
SST39LF/VF400A
A2
A1
A0
CE#
VSS
A4
A3
A5
DQ8
OE#
DQ0
A6
A7
A18
DQ10
DQ9
DQ1
A17
NC
NC
DQ2
NC
DQ3
NC
VDD
WE#
DQ12
NC
NC
NC
DQ13
A9
A10
A8
DQ4
DQ5
DQ14
A11
A13
A12
DQ11
DQ6
DQ15
A14
A15
A16
DQ7
VSS
TOP VIEW (balls facing down)
AB C D E F G H J K L
6
5
4
3
2
1
1117 48-xflga P03 8.0
SST39LF/VF800A
A2
A1
A0
CE#
V
SS
A4
A3
A5
DQ8
OE#
DQ0
A6
A7
NC
DQ10
DQ9
DQ1
NC
NC
NC
DQ2
NC
DQ3
NC
V
DD
WE#
DQ12
NC
NC
NC
DQ13
A9
A10
A8
DQ4
DQ5
DQ14
A11
A13
A12
DQ11
DQ6
DQ15
A14
A15
A16
DQ7
V
SS
TOP VIEW (balls facing down)
AB C D E F G H J K L
6
5
4
3
2
1
1117 48-xflga P03 2.0
SST39VF200A
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
6
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Table 1: Pin Description
Symbol Pin Name Functions
AMS1-A0
1. AMS = Most significant address
AMS =A
16 for SST39LF/VF200A, A17 for SST39LF/VF400A, and A18 for SST39LF/VF800A
Address Inputs To provide memory addresses. During Sector-Erase AMS-A11 address lines will
select the sector. During Block-Erase AMS-A15 address lines will select the
block.
DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
VDD Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF200A/400A/800A
2.7-3.6V for SST39VF200A/400A/800A
VSS Ground
NC No Connection Unconnected pins.
T1.2 25001
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
7
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39LF200A/400A/800A and SST39VF200A/400A/800A is controlled by
CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE#
is the output control and is used to gate data from the output pins. The data bus is in high impedance
state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure
5).
Word-Program Operation
The SST39LF200A/400A/800A and SST39VF200A/400A/800A are programmed on a word-by-word
basis. Before programming, the sector where the word exists must be fully erased. The Program oper-
ation is accomplished in three steps. The first step is the three-byte load sequence for Software Data
Protection. The second step is to load word address and word data. During the Word-Program opera-
tion, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The
data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the
internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever
occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 6 and 7
for WE# and CE# controlled Program operation timing diagrams and Figure 18 for flowcharts. During
the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks. Any commands issued during the internal
Program operation are ignored.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39LF200A/400A/800A and SST39VF200A/400A/800A offers both Sec-
tor-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord.
The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is ini-
tiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector
address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte com-
mand sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The
sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H
or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after
the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Tog-
gle Bit methods. See Figures 11 and 12 for timing waveforms. Any commands issued during the Sec-
tor- or Block-Erase operation are ignored.
Chip-Erase Operation
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the “1” state. This is useful when the entire device
must be quickly erased.
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
8
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the ris-
ing edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid
read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing dia-
gram, and Figure 21 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored.
Write Operation Status Detection
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide two software means to detect
the completion of a write (Program or Erase) cycle, in order to optimize the system write cycle time.
The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-
Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or
Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ7or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the write cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the SST39LF200A/400A/800A and SST39VF200A/400A/800A are in the internal Program oper-
ation, any attempt to read DQ7will produce the complement of the true data. Once the Program oper-
ation is completed, DQ7will produce true data. Note that even though DQ7may have valid data
immediately following the completion of an internal Write operation, the remaining data outputs may
still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after
an interval of 1 µs.During internal Erase operation, any attempt to read DQ7will produce a ‘0’. Once
the internal Erase operation is completed, DQ7will produce a ‘1’. The Data# Polling is valid after the
rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling
timing diagram and Figure 19 for a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6will produce
alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is
completed, the DQ6bit will stop toggling. The device is then ready for the next operation. The Toggle
Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-
or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for
Toggle Bit timing diagram and Figure 19 for a flowchart.
Data Protection
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
9
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide the JEDEC approved Soft-
ware Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program
operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to
initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g.,
during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte
sequence. This group of devices are shipped with the Software Data Protection permanently enabled.
See Table 4 for the specific software command codes. During SDP command sequence, invalid com-
mands will abort the device to Read mode within TRC. The contents of DQ15-DQ8can be VIL or VIH,
but no other value, during any SDP command sequence.
Common Flash Memory Interface (CFI)
The SST39LF200A/400A/800A and SST39VF200A/400A/800A also contain the CFI information to
describe the characteristics of the device. In order to enter the CFI Query mode, the system must write
three-byte sequence, same as Software ID Entry command with 98H (CFI Query command) to
address 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system
can read CFI data at the addresses given in Tables 5 through 9. The system must write the CFI Exit
command to return to Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices as the SST39LF/VF200A, SST39LF/VF400A
and SST39LF/VF800A and manufacturer as SST. This mode may be accessed by software operations.
Users may use the Software Product Identification operation to identify the part (i.e., using the device
ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software opera-
tion, Figure 13 for the Software ID Entry and Read timing diagram, and Figure 20 for the Software ID
Entry command sequence flowchart.
Table 2: Product Identification
Address Data
Manufacturer’s ID 0000H 00BFH
Device ID
SST39LF/VF200A 0001H 2789H
SST39LF/VF400A 0001H 2780H
SST39LF/VF800A 0001H 2781H
T2.3 25001
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
10
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to
the Read mode. This command may also be used to reset the device to the Read mode after any inad-
vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor-
rectly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program
or Erase operation. See Table 4 for software command codes, Figure 15 for timing waveform, and Fig-
ure 20 for a flowchart.
Operations
Table 3: Operation Modes Selection
Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Program VIL VIH VIL DIN AIN
Erase VIL VIH VIL X1
1. X can be VIL or VIH, but no other value.
Sector or Block address,
XXH for Chip-Erase
Standby VIH X X High Z X
Write Inhibit X VIL X High Z/ DOUT X
XXV
IH High Z/ DOUT X
Product Identification
Software Mode VIL VIL VIH See Table 4
T3.4 25001
Table 4: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr
1
1. Address format A14-A0(Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.
AMS = Most significant address
AMS =A
16 for SST39LF/VF200A, A17 for SST39LF/VF400A, and A18 for SST39LF/VF800A
Data
2
2. DQ15-DQ8can be VIL or VIH, but no other value, for the Command sequence
Addr1
Data
2
Addr
1
Data
2
Addr
1
Data
2Addr1
Data
2
Addr
1
Data
2
Word-Program
5555H
AAH
2AAAH
55H
5555H
A0H WA3
3. WA = Program word address
Data
Sector-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H AAH
2AAAH
55H SA
X4
30H
Block-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H AAH
2AAAH
55H BA
X4
50H
Chip-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H AAH
2AAAH
55H 5555H
10H
Software ID
Entry5,6
5555H
AAH
2AAAH
55H
5555H
90H
CFI Query Entry5
5555H
AAH
2AAAH
55H
5555H
98H
Software ID Exit7/
CFI Exit
XXH
F0H
Software ID Exit7/
CFI Exit
5555H
AAH
2AAAH
55H
5555H
F0H
T4.3 25001
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
4. SAXfor Sector-Erase; uses AMS-A11 address lines
BAXfor Block-Erase; uses AMS-A15 address lines
5. The device does not remain in Software Product ID mode if powered down.
6. With AMS-A1= 0; SST Manufacturer’s ID = 00BFH, is read with A0=0,
SST39LF/VF200A Device ID = 2789H, is read with A0=1.
SST39LF/VF400A Device ID = 2780H, is read with A0=1.
SST39LF/VF800A Device ID = 2781H, is read with A0=1.
7. Both Software ID Exit operations are equivalent
Table 5: CFI Query Identification String1for SST39LF200A/400A/800A and
SST39VF200A/400A/800A
1. Refer to CFI publication 100 for more details.
Address Data Data
10H 0051H Query Unique ASCII string “QRY”
11H 0052H
12H 0059H
13H 0001H Primary OEM command set
14H 0007H
15H 0000H Address for Primary Extended Table
16H 0000H
17H 0000H Alternate OEM command set (00H = none exists)
18H 0000H
19H 0000H Address for Alternate OEM extended Table (00H = none exits)
1AH 0000H
T5.0 25001
Table 6: System Interface Information for SST39LF200A/400A/800A and SST39VF200A/
400A/800A
Address Data Data
1BH 0027H1
1. 0030H for SST39LF200A/400A/800A and 0027H for SST39VF200A/400A/800A
VDD Min (Program/Erase)
0030H1DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH 0036H VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH 0000H VPP min (00H = no VPP pin)
1EH 0000H VPP max (00H = no VPP pin)
1FH 0004H Typical time out for Word-Program 2Nµs (24=1s)
20H 0000H Typical time out for min size buffer program 2Nµs (00H = not supported)
21H 0004H Typical time out for individual Sector/Block-Erase 2Nms (24=16ms)
22H 0006H Typical time out for Chip-Erase 2Nms (26=64ms)
23H 0001H Maximum time out for Word-Program 2Ntimes typical (21x2
4=3s)
24H 0000H Maximum time out for buffer program 2Ntimes typical
25H 0001H Maximum time out for individual Sector/Block-Erase 2Ntimes typical (21x2
4=32ms)
26H 0001H Maximum time out for Chip-Erase 2Ntimes typical (21x2
6= 128 ms)
T6.2 25001
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
12
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Table 7: Device Geometry Information for SST39LF/VF200A
Address Data Data
27H 0012H Device size = 2NByte (12H = 18; 218 = 256 KByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of bytes in multi-byte write = 2N(00H = not supported)
2BH
2CH 0002H Number of Erase Sector/Block sizes supported by device
2DH 003FH Sector Information (y+1=Number of sectors; z x 256B = sector size)
2EH 0000H y = 63+1=64sectors (003FH = 63)
2FH 0010H
30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
31H 0003H Block Information (y+1=Number of blocks; z x 256B = block size)
32H 0000H y=3+1=4blocks(0003H = 3)
33H 0000H
34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T7.2 25001
Table 8: Device Geometry Information for SST39LF/VF400A
Address Data Data
27H 0013H Device size = 2NByte (13H = 19; 219 = 512 KByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of bytes in multi-byte write = 2N(00H = not supported)
2BH 0000H
2CH 0002H Number of Erase Sector/Block sizes supported by device
2DH 007FH Sector Information (y+1=Number of sectors; z x 256B = sector size)
2EH 0000H y = 127+1=128sectors (007FH = 127)
2FH 0010H
30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
31H 0007H Block Information (y+1=Number of blocks; z x 256B = block size)
32H 0000H y=7+1=8blocks(0007H = 7)
33H 0000H
34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T8.1 25001
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
13
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Table 9: Device Geometry Information for SST39LF/VF800A
Address Data Data
27H 0014H Device size = 2NBytes (14H = 20; 220 = 1 MByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of bytes in multi-byte write = 2N(00H = not supported)
2BH 0000H
2CH 0002H Number of Erase Sector/Block sizes supported by device
2DH 00FFH Sector Information (y+1=Number of sectors; z x 256B = sector size)
2EH 0000H y = 255+1=256sectors (00FFH = 255)
2FH 0010H
30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
31H 000FH Block Information (y+1=Number of blocks; z x 256B = block size)
32H 0000H y = 15+1=16blocks(000FH = 15)
33H 0000H
34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T9.0 25001
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
14
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-
ditions may affect device reliability.)
Temperature Under Bias ............................................. -55°C to +125°C
Storage Temperature ................................................ -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential ............................-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential ..................-2.0V to VDD+2.0V
Voltage on A9Pin to Ground Potential .....................................-0.5V to 13.2V
Package Power Dissipation Capability (TA= 25°C) .................................. 1.0W
Surface Mount Solder Reflow Temperature1...........................260°C for 10 seconds
Output Short Circuit Current2.................................................. 50mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest
information.
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range: SST39LF200A/400A/800A
Range Ambient Temp VDD
Commercial 0°C to +70°C 3.0-3.6V
T9.1 25001
Operating Range: SST39VF200A/400A/800A
Range Ambient Temp VDD
Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V
T9.1 25001
Table 10:AC Conditions of Test1
1. See Figures 16 and 17
Input Rise/Fall Time
Output Load
SST39LF200A/400A/800A
Output Load
SST39VF200A/400A/800A
5ns CL=30pF C
L= 100 pF
T10.1 25001
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
15
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Table 11:DC Operating Characteristics –VDD = 3.0-3.6V for SST39LF200A/400A/800A and
2.7-3.6V for SST39VF200A/400A/800A1
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD Power Supply Current Address input=VILT/VIHT, at f=1/TRC
Min, VDD=VDD Max
Read230 mA CE#=VIL, OE#=WE#=VIH, all I/Os
open
Program and Erase 30 mA CE#=WE#=VIL, OE#=VIH
ISB Standby VDD Current 20 µA CE#=VIHC,V
DD=VDD Max
ILI Input Leakage Current 1 µA VIN=GND to VDD,V
DD=VDD Max
ILO Output Leakage Current 10 µA VOUT=GND to VDD,V
DD=VDD Max
VIL Input Low Voltage 0.8 VDD=VDD Min
VIH Input High Voltage 0.7VDD VV
DD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
T11.7 25001
1. Typical conditions for the Active Current shown on page 1 are average values at 25°C (room temperature),
and VDD = 3V for VF devices. Not 100% tested.
2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.
Table 12:Recommended System Power-up Timings
Symbol Parameter Minimum Units
TPU-READ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Power-up to Read Operation 100 µs
TPU-WRITE1Power-up to Program/Erase Operation 100 µs
T12.0 25001
Table 13:Capacitance (TA= 25°C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum
CI/O1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
I/O Pin Capacitance VI/O =0V 12pF
CIN1Input Capacitance VIN =0V 6pF
T13.0 25001
Table 14:Reliability Characteristics
Symbol Parameter Minimum Specification Units Test Method
NEND1,2
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would
result in a higher minimum specification.
Endurance 10,000 Cycles JEDEC Standard A117
TDR1Data Retention 100 Years JEDEC Standard A103
ILTH1Latch Up 100 + IDD mA JEDEC Standard 78
T14.2 25001
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
16
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
AC Characteristics
Table 15:Read Cycle Timing Parameters VDD = 3.0-3.6V
Symbol Parameter
SST39LF200A/400A/800A-
55
UnitsMin Max
TRC Read Cycle Time 55 ns
TCE Chip Enable Access Time 55 ns
TAA Address Access Time 55 ns
TOE Output Enable Access Time 30 ns
TCLZ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
CE# Low to Active Output 0 ns
TOLZ1OE# Low to Active Output 0 ns
TCHZ1CE# High to High-Z Output 15 ns
TOHZ1OE# High to High-Z Output 15 ns
TOH1Output Hold from Address Change 0 ns
T15.7 25001
Table 16:Read Cycle Timing Parameters VDD = 2.7-3.6V
Symbol Parameter
SST39VF200A/400A/800A-
70 Unit
sMin Max
TRC Read Cycle Time 70 ns
TCE Chip Enable Access Time 70 ns
TAA Address Access Time 70 ns
TOE Output Enable Access Time 35 ns
TCLZ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
CE# Low to Active Output 0 ns
TOLZ1OE# Low to Active Output 0 ns
TCHZ1CE# High to High-Z Output 20 ns
TOHZ1OE# High to High-Z Output 20 ns
TOH1Output Hold from Address Change 0 ns
T16.7 25001
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
17
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Table 17:Program/Erase Cycle Timing Parameters
Symbol Parameter Min Max Units
TBP Word-Program Time 20 µs
TAS Address Setup Time 0 ns
TAH Address Hold Time 30 ns
TCS WE# and CE# Setup Time 0 ns
TCH WE# and CE# Hold Time 0 ns
TOES OE# High Setup Time 0 ns
TOEH OE# High Hold Time 10 ns
TCP CE# Pulse Width 40 ns
TWP WE# Pulse Width 40 ns
TWPH1WE# Pulse Width High 30 ns
TCPH1CE# Pulse Width High 30 ns
TDS Data Setup Time 30 ns
TDH1Data Hold Time 0 ns
TIDA1Software ID Access and Exit Time 150 ns
TSE Sector-Erase 25 ms
TBE Block-Erase 25 ms
TSCE Chip-Erase 100 ms
T17.0 25001
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
18
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Figure 5: Read Cycle Timing Diagram
Figure 6: WE# Controlled Program Cycle Timing Diagram
1117 F03.2
ADDRESS A
MS-0
DQ
15-0
WE#
OE#
CE#
T
CE
T
RC
T
AA
T
OE
T
OLZ
V
IH
HIGH-Z
T
CLZ
T
OH
T
CHZ
HIGH-Z
DATA VALIDDATA VALID
T
OHZ
Note: AMS = Most significant address
AMS =A
16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
1117 F04.4
ADDRESS AMS-0
DQ15-0
TDH
TWPH TDS
TWP
TAH
TAS
TCH
TCS
CE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
XXAA XX55 XXA0 DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
OE#
WE#
TBP
Note: AMS = Most significant address
AMS =A
16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
X can be VIL or VIH, but no other value.
©2011 Silicon Storage Technology, Inc. DS25001A 03/11
19
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Figure 7: CE# Controlled Program Cycle Timing Diagram
Figure 8: Data# Polling Timing Diagram
1117 F05.4
ADDRESS AMS-0
DQ15-0
TDH
TCPH TDS
TCP
TAH
TAS
TCH
TCS
WE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
XXAA XX55 XXA0 DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
OE#
CE#
TBP
Note: AMS = Most significant address
AMS =A
16
for SST39LF/VF200A, A
17
for SST39LF/VF400A and A
18
for SST39LF/VF800A
X can be V
IL
or V
IH,
but no other value.
1117 F06.3
ADDRESS AMS-0
DQ7DATA DATA # DATA # DATA
WE#
OE#
CE#
TOEH
TOE
TCE
TOES
Note: AMS = Most significant address
AMS =A
16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A