IRFR5410PbF
IRFU5410PbF
HEXFET® Power MOSFET
VDSS = -100V
RDS(on) = 0.205Ω
ID = -13A
12/13/04
Parameter Typ. Max. Units
RθJC Junction-to-Case 1.9
RθJA Junction-to-Ambient (PCB mount)** 50 °C/W
RθJA Junction-to-Ambient 110
Thermal Resistance
D-Pak
T
O-252AA I-Pak
TO-251AA
lUltra Low On-Resistance
lP-Channel
lSurface Mount (IRFR5410)
lStraight Lead (IRFU5410)
lAdvanced Process Technology
lFast Switching
lFully Avalanche Rated
Description
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ -10V -13
ID @ TC = 100°C Continuous Drain Current, VGS @ -10V -8.2 A
IDM Pulsed Drain Current -52
PD @TC = 25°C Power Dissipation 66 W
Linear Derating Factor 0.53 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy194 mJ
IAR Avalanche Current-8.4 A
EAR Repetitive Avalanche Energy6.3 mJ
dv/dt Peak Diode Recovery dv/dt -5.0 V/ns
TJOperating Junction and -55 to + 150
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
Absolute Maximum Ratings
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
The D-Pak is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU series) is for through-hole mounting
applications. Power dissipation levels up to 1.5 watts are
possible in typical surface mount applications.
S
D
G
PD -95314A
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lLead-Free
IRFR/U5410PbF
2www.irf.com
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage -1.6 V TJ = 25°C, IS = -7.8A, VGS = 0V
trr Reverse Recovery Time 130 190 ns TJ = 25°C, IF = -8.4A
Qrr Reverse Recovery Charge 650 970 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
-13
-52
A
Notes:
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact
Starting TJ = 25°C, L = 6.4mH
RG = 25Ω, IAS = -7.8A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
ISD ≤ -7.8A, di/dt ≤ 200A/µs, VDD ≤ V
(BR)DSS,
TJ ≤ 150°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
S
D
G
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage -100 V VGS = 0V, ID = -250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient -0.12 V/°C Reference to 25°C, ID = -1.0mA
RDS(on) Static Drain-to-Source On-Resistance 0.205 ΩVGS = -10V, ID = -7.8A
VGS(th) Gate Threshold Voltage -2.0 -4.0 V VDS = VGS, ID = -250µA
gfs Forward Transconductance 3.2 S VDS = -50V, ID = -7.8A
-25 µA VDS = -100V, VGS = 0V
-250 VDS = -80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage 100 VGS = 20V
Gate-to-Source Reverse Leakage -100 nA VGS = -20V
QgTotal Gate Charge 58 ID = -8.4A
Qgs Gate-to-Source Charge 8.3 nC VDS = -80V
Qgd Gate-to-Drain ("Miller") Charge 32 VGS = -10V, See Fig. 6 and 13
td(on) Turn-On Delay Time 15 VDD = 50V
trRise Time 58 ID = -8.4A
td(off) Turn-Off Delay Time 45 RG = 9.1Ω
tfFall Time 46 RD =6.2Ω, See Fig. 10
Between lead,
6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance 760 VGS = 0V
Coss Output Capacitance 260 pF VDS = -25V
Crss Reverse Transfer Capacitance 170 = 1.0MHz, See Fig. 5
nH
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
LDInternal Drain Inductance
LSInternal Source Inductance
IGSS
ns
4.5
7.5
IDSS Drain-to-Source Leakage Current
S
D
G
Uses IRF9530N data and test conditions.
IRFR/U5410PbF
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.01
0.1
1
10
100
0.1 1 10 100
20µs PULS E WID TH
T = 25 C
J°
TOP
BOTTOM
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
-V , Drain-to-So urce Vo ltage (V)
-I , Drai n-to-Source Current (A)
DS
D
-4.5V
0.1
1
10
100
0.1 1 10 100
20µs PULS E WI DTH
T = 150 C
J°
TOP
BOTTOM
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
-V , Drain-to-Source Voltage (V)
-I , Drain-t o-Source Current (A)
DS
D
-4.5V
0.1
1
10
100
45678910
V = 10V
20µs PULSE WIDTH
DS
-V , Gate-to-Source Voltage (V)
-I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 150 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160
0.0
0.5
1.0
1.5
2.0
2.5
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
-10V
-14A
IRFR/U5410PbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0.1
1
10
100
0.2 0.8 1.4 2.0 2.6
-V ,Source -to-Dra in V olta g e (V)
-I , Revers e Drain Current ( A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 150 C
J°
0
400
800
1200
1600
2000
1 10 100
C , Capa ci tanc e (pF)
A
DS
-V , Drain-to-Source Voltage (V)
V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
GS
iss gs gd ds
rss gd
os s d s gd
C
iss
C
oss
C
rss
010 20 30 40 50 60
0
5
10
15
20
Q , To ta l Ga te Cha rge (nC)
-V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
-8.4A
V =-20V
DS
V =-50V
DS
V =-80V
DS
1
10
100
1000
1 10 100 100
0
OPERATION IN TH IS AREA LIMI TED
BY RDS(on)
Single Pulse
T
T = 150 C
= 25 C
°°
J
C
-V , Drain-to-Source Voltage (V)
-I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
IRFR/U5410PbF
www.irf.com 5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
VDS
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
VDD
RG
D.U.T.
+
-
V
DS
9
0%
1
0%
V
GS
t
d(on)
t
r
t
d(off)
t
f
25 50 75 100 125 150
0
3
6
9
12
15
T , C ase Temperature ( C)
-I , Drain Current (A)
°
C
D
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. D u ty factor D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SIN GLE PULSE
(THERMAL RESPONSE)
IRFR/U5410PbF
6www.irf.com
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Q
G
Q
GS
Q
GD
V
G
Charge
-10V
D.U.T. VD
S
ID
IG
-3mA
VGS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tpV
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
V
DS
V
DD
DRIVER
A
15V
-20V
-
+VDD
25 50 75 100 125 150
0
100
200
300
400
500
Starting T , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
-3.5A
-4.9A
-7.8A
IRFR/U5410PbF
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Peak Diode Recovery dv/dt Test Circuit
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
RG
VDD
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T*Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
* Reverse Polarity of D.U.T for P-Channel
VGS
[ ]
[ ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
[ ] ***
Fig 14. For P-Channel HEXFETS
IRFR/U5410PbF
8www.irf.com
D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
12
IN THE ASSEMBLY LIN E " A"
ASSEMBLED ON WW 16, 1999
EXAMPLE: WIT H AS S EMBL Y
THIS IS AN IRFR120
LOT CODE 1234 YEAR 9 = 199
9
DATE CODE
WE EK 16
PART NUMBER
LOGO
INTERNATIONAL
RECTIFIER
AS S EMBL Y
LOT CODE
916A
IRFU120
34
YEAR 9 = 1999
DATE CODE
OR
P = DES IGNAT E S LEAD-FREE
PROD UCT (OPTION AL)
Note: "P" in assembly line po sition
indicates "Lead-F ree"
12 34
WE EK 16
A = AS S E MBL Y S IT E CODE
PART N UMBER
IRFU120
LINE A
LOGO
LOT CODE
AS S EMBL Y
INTERNATIONAL
RECTIFIER
IRFR/U5410PbF
www.irf.com 9
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
ASS EMBLY
EXAMPLE: WITH ASSEMBLY
THIS IS AN IRFU120
YEAR 9 = 199
9
DATE C ODE
LINE A
WEEK 1 9
IN THE ASSEMBLY LINE "A"
ASSEMBLED ON WW 19, 1999
LOT CODE 56 78
PART NUMBER
56
IRFU120
INTERNATIONAL
LOGO
RECTIFIER
LOT COD E
919A
78
Note: "P" in asse mb ly line
po s ition indicates "L ead-Free"
OR
56 78
ASSEMBLY
LOT CODE
RECTIFIER
LOGO
INTERNATIONAL
IRFU120
PART NUMBER
WEEK 19
DATE CODE
YEAR 9 = 1999
A = ASSEMBLY SITE CODE
P = DESIGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
IRFR/U5410PbF
10 www.irf.com
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) F E E D DI R E CTIO N F E E D DI R E CTIO N
16.3 ( .641
)
15.7 ( .619
)
TRR TRL
N
OTE S :
1
. CONTR OLLING DIM E NS ION : MIL LIMETER.
2
. ALL DIMENSIO NS ARE SHOWN IN MILLIMETERS ( INCHES ).
3
. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLIN E CONFORMS TO EI A-481.
16 mm
13 INCH
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
