CY7C027
CY7C028
32K/64K × 16 Dual-Port Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-06042 Rev. *M Revised August 1, 2017
32K/64K × 16 Dual-Port Static RAM
Features
■True dual-ported memory cells which allow simultaneous
access of the same memory location
■32K × 16 organization (CY7C027)
■64K × 16 organization (CY7C028)
■0.35 micron CMOS for optimum speed and power
■High speed access: 15 and 20 ns
■Low operating power
■Active: ICC = 180 mA (typical)
■Standby: ISB3 = 0.05 mA (typical)
■Fully asynchronous operation
■Automatic power down
■Expandable data bus to 32 bits or more using Master/Slave
chip select when using more than one device
■On-chip arbitration logic
■Semaphores included to permit software handshaking
between ports
■INT flags for port-to-port communication
■Separate upper-byte and lower-byte control
■Dual chip enables
■Pin select for Master or Slave
■Commercial and industrial temperature ranges
■Available in 100-pin TQFP
■Pb-free packages available
Functional Description
The CY7C027 and CY7C028 are low power CMOS 32K,
64K × 16 dual-port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can be
used as standalone 16-bit dual-port static RAMs or multiple
devices can be combined to function as a 32-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 32-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor and
multiprocessor designs, communications status buffering, and
dual-port video/graphics memory.
Each port has independent control pins: dual chip enables (CE0
and CE1), read or write enable (R/W), and output enable (OE).
Two flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore)
at any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power down feature is controlled
independently on each port by the chip enable pins.
The CY7C027 and CY7C028 are available in 100-pin Thin Quad
Flat pack (TQFP) packages.
For a complete list of related documentation, click here.
Selection Guide
Parameter CY7C027/CY7C028
-15
CY7C027/CY7C028
-20 Unit
Maximum Access Time 15 20 ns
Typical Operating Current 190 180 mA
Typical Standby Current for ISB1 (Both ports TTL level) 50 45 mA
Typical Standby Current for ISB3 (Both ports CMOS level) 0.05 0.05 mA
CY7C02732K/64K × 16 Dual-Port Static RAM
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 2 of 24
R/WL
CE0L
CE1L
OEL
I/O8L–I/O15L
I/O
Control
Address
Decode
A0L–A14/15L
CEL
OEL
R/WL
BUSYL
I/O
Control
CEL
Interrupt
Semaphore
Arbitration
SEML
INTL
M/S
UBL
LBL
I/O0L–I/O7L
R/WR
CE0R
CE1R
OER
I/O8L–I/O15R
CER
UBR
LBR
I/O0L–I/O7R
UBL
LBL
Logic Block Diagram
A0L–A14/15L
True Dual-Ported
RAM Array
A0R–A14/15R
CER
OER
R/WR
BUSYR
SEMR
INTR
UBR
LBR
Address
Decode A0R–A14/15R
[1] [1]
[2] [2]
[3] [3]
[4] [4]
[3] [3]
15/16
8
8
15/16
8
8
15/16 15/16
Notes
1. I/O8–I/O15 for × 16 devices
2. I/O0–I/O7 for × 16 devices
3. A0–A14 for 32K; A0–A15 for 64K devices.
4. BUSY is an output in master mode and an input in slave mode.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 3 of 24
Contents
Pin Configurations ........................................................... 4
Pin Definitions ..................................................................5
Maximum Ratings .............................................................6
Operating Range ............................................................... 6
Electrical Characteristics .................................................6
Capacitance ...................................................................... 7
AC Test Loads and Waveforms .......................................7
Data Retention Mode ........................................................ 7
Timing ................................................................................ 7
Switching Characteristics ................................................8
Switching Waveforms .................................................... 10
Architecture ....................................................................16
Functional Overview ...................................................... 16
Write Operation ......................................................... 16
Read Operation .........................................................16
Interrupts ................................................................... 17
Busy .......................................................................... 17
Master/Slave .............................................................17
Semaphore Operation ............................................... 17
Ordering Information ...................................................... 19
32K × 16 Asynchronous Dual-Port SRAM ................ 19
64K × 16 Asynchronous Dual-Port SRAM ................ 19
Ordering Code Definitions ......................................... 19
Package Diagram ............................................................ 20
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 4 of 24
Pin Configurations
Figure 1. 100-pin TQFP pinout (Top View)
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A9R
A10R
A11R
A12R
A13R
A14R
UBR
NC
LBR
CE1R
SEMR
OER
GND
NC
A15R
GND
R/WR
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
CE0R
58
57
56
55
54
53
52
51
CY7C027 (32K × 16)
A9L
A10L
A11L
A12L
A13L
A14L
UBL
NC
LBL
CE1L
SEML
OEL
GND
NC
A15L
VCC
R/WL
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
CE0L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8L
A7L
A6L
A5L
A4L
A3L
INTL
A1L
NC
GND
M/S
A0R
A1R
A0L
A2L
BUSYR
INTR
A2R
A3R
A4R
A5R
A6R
A7R
A8R
BUSYL
34 35 36 424139 403837 43 44 45 5048 494746
NC
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/01R
I/O4R
I/O2R
GND
I/O0L
I/O2L
I/O3L
I/O3R
I/O5R
I/O1L
GND
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
I/O0R
3332313029282726
CY7C028 (64K × 16)
[5] [5]
Note
5. This pin is NC for CY7C027.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 5 of 24
Pin Definitions
Left Port Right Port Description
CE0L, CE1L CE0R, CE1R Chip Enable (CE is LOW when CE0 VIL and CE1 VIH)
R/WLR/WRRead/Write Enable
OELOEROutput Enable
A0L–A15L A0R–A15R Address (A0–A14 for 32K; A0–A15 for 64K devices)
I/O0L–I/O15L I/O0R–I/O15R Data Bus Input/Output (I/O0–I/O15 for × 16 devices)
SEML SEMRSemaphore Enable
UBLUBRUpper Byte Select (I/O8–I/O15 for × 16 devices)
LBLLBRLower Byte Select (I/O0–I/O7 for × 16 devices)
INTLINTRInterrupt Flag
BUSYLBUSYRBusy Flag
M/S Master or Slave Select
VCC Power
GND Ground
NC No Connect
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 6 of 24
Maximum Ratings
Exceeding maximum ratings [6] may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Supply Voltage to Ground Potential .............–0.3 V to +7.0 V
DC Voltage Applied to Outputs
in High Z State ...................................... –0.5 V to +7.0 V DC
Input Voltage [7] ...........................................–0.5 V to +7.0 V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage .......................................... > 1100V
Latch-Up Current ................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0 °C to +70 °C 5 V 10%
Industrial –40 °C to +85 °C 5 V 10%
Electrical Characteristics
Over the Operating Range
Symbol Parameter
CY7C027/CY7C028
Unit-15 -20
Min Typ Max Min Typ Max
VOH Output HIGH Voltage (VCC = Min, IOH = –4.0 mA) 2.4 – – 2.4 – – V
VOL Output LOW Voltage (VCC = Min, IOH = +4.0 mA) – 0.4 – 0.4 V
VIH Input HIGH Voltage 2.2 – 2.2 – V
VIL Input LOW Voltage – 0.8 – 0.8 V
IOZ Output Leakage Current –10 10 –10 10 A
ICC Operating Current
(VCC = Max, IOUT= 0 mA)
Outputs Disabled
Commercial – 190 280 – 180 265 mA
Industrial – 305 290 mA
ISB1 Standby Current
(Both Ports TTL Level)
CEL & CER VIH, f = fMAX
Commercial 50 70 45 65 mA
Industrial – 60 80 mA
ISB2 Standby Current
(One Port TTL Level)
CEL | CER VIH, f = fMAX
Commercial 120 180 110 160 mA
Industrial – 125 175 mA
ISB3 Standby Current
(Both Ports CMOS Level)
CEL & CER VCC – 0.2 V, f = 0
Commercial 0.05 0.5 0.05 0.5 mA
Industrial – 0.05 0.5 mA
ISB4 Standby Current
(One Port CMOS Level)
CEL | CER VIH, f = fMAX[8]
Commercial 110 160 100 140 mA
Industrial – 115 155 mA
Notes
6. The voltage on any input or I/O pin cannot exceed the power pin during power up.
7. Pulse width < 20 ns.
8. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
ISB3.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 7 of 24
Data Retention Mode
The CY7C027 and CY7C028 are designed with battery backup
in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
1. Chip enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2 V.
2. CE must be kept between VCC – 0.2 V and 70% of VCC during
the power up and power down transitions.
3. The RAM can begin operation > tRC after VCC reaches the
minimum operating voltage (4.5 V).
Capacitance
Parameter [9] Description Test Conditions Max Unit
CIN Input Capacitance TA = 25 °C, f = 1 MHz, VCC = 5.0 V 10 pF
COUT Output Capacitance 10 pF
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.0 V
GND 90% 90%
10%
3ns 3ns
10%
ALL INPUT PULSES
(a) Normal Load (Load 1)
R1 = 893
5 V
OUTPUT
R2 = 347
C =30pF
VTH = 1.4 V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay(Load 2)
R1 = 893
R2 = 347
5 V
OUTPUT
C= 5pF
RTH = 250
(Used for tCKLZ, tOLZ, & tOHZ
including scope and jig)
Timing
Figure 3. Timing
Parameter Test Conditions [10] Max Unit
ICCDR1 At VCCDR = 2 V 1.5 mA
Notes
9. Tested initially and after any design or process changes that may affect these parameters.
10. CE = VCC, VIN = GND to VCC, TA = 25 °C. This parameter is guaranteed but not tested.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 8 of 24
Switching Characteristics
Over the Operating Range
Parameter [11] Description
CY7C027/CY7C028
Unit-15 -20
Min Max Min Max
Read Cycle
tRC Read Cycle Time 15 –20 –ns
tAA Address to Data Valid –15 –20 ns
tOHA Output Hold From Address Change 3 – 3 – ns
tACE[12] CE LOW to Data Valid –15 –20 ns
tDOE OE LOW to Data Valid –10 –12 ns
tLZOE[13, 14, 15] OE LOW to Low Z 3 – 3 – ns
tHZOE[13, 14, 15] OE HIGH to High Z –10 –12 ns
tLZCE[13, 14, 15] CE LOW to Low Z 3 – 3 – ns
tHZCE[13, 14, 15] CE HIGH to High Z –10 –12 ns
tPU[15] CE LOW to Power Up 0 – 0 – ns
tPD[15] CE HIGH to Power Down –15 –20 ns
tABE[12] Byte Enable Access Time –15 –20 ns
Write Cycle
tWC Write Cycle Time 15 –20 –ns
tSCE[12] CE LOW to Write End 12 –15 –ns
tAW Address Valid to Write End 12 –15 –ns
tHA Address Hold From Write End 0 – 0 – ns
tSA[12] Address Setup to Write Start 0 – 0 – ns
tPWE Write Pulse Width 12 –15 –ns
tSD Data Setup to Write End 10 –15 –ns
tHD Data Hold From Write End 0 – 0 – ns
tHZWE[14, 15] R/W LOW to High Z –10 –12 ns
tLZWE[14, 15] R/W HIGH to Low Z 3 – 3 – ns
tWDD[16] Write Pulse to Data Delay –30 –45 ns
tDDD[16] Write Data Valid to Read Data Valid –25 –30 ns
Notes
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH
and 30 pF load capacitance.
12. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
14. Test conditions used are Load 2.
15. This parameter is guaranteed by design, but it is not production tested.
16. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 on page 13.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 9 of 24
Busy Timing[17]
tBLA BUSY LOW from Address Match –15 –20 ns
tBHA BUSY HIGH from Address Mismatch –15 –20 ns
tBLC BUSY LOW from CE LOW –15 –20 ns
tBHC BUSY HIGH from CE HIGH –15 –17 ns
tPS Port Setup for Priority 5 – 5 – ns
tWB R/W HIGH after BUSY (Slave) 0 – 0 – ns
tWH R/W HIGH after BUSY HIGH (Slave) 13 –15 –ns
tBDD[18] BUSY HIGH to Data Valid –15 –20 ns
Interrupt Timing[17]
tINS INT Set Time –15 –20 ns
tINR INT Reset Time –15 –20 ns
Semaphore Timing
tSOP SEM Flag Update Pulse (OE or SEM)10 –10 –ns
tSWRD SEM Flag Write to Read Time 5 – 5 – ns
tSPS SEM Flag Contention Window 5 – 5 – ns
tSAA SEM Address Access Time –15 –20 ns
Switching Characteristics (continued)
Over the Operating Range
Parameter [11] Description
CY7C027/CY7C028
Unit-15 -20
Min Max Min Max
Notes
17. Test conditions used are Load 1.
18. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 10 of 24
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access) [19, 20, 21]
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) [19, 22, 23]
Figure 6. Read Cycle No. 3 (Either Port) [19, 21, 22, 23]
tRC
tAA
tOHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
tOHA
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
tLZCE
tPU tPD
ISB
ICC
DATA OUT
OE
CE and
LB or UB
CURRENT
UB or LB
DATA OUT
tRC
ADDRESS
tAA tOHA
CE
tLZCE
tABE
tHZCE
tHZCE
tACE
tLZCE
Notes
19. R/W is HIGH for read cycles.
20. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.
21. OE = VIL.
22. Address valid prior to or coincident with CE transition LOW.
23. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 11 of 24
Figure 7. Write Cycle No. 1 (R/W Controlled Timing) [24, 25, 26, 27]
Figure 8. Write Cycle No. 2 (CE Controlled Timing) [24, 25, 26, 31, 32]
Switching Waveforms (continued)
tAW
tWC
tPWE
tHD
tSD
tHA
CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
tHZOE
tSA
tHZWE tLZWE
[30]
[30]
[27]
[28, 29]
NOTE 31 NOTE 31
tAW
tWC
tSCE
tHD
tSD
tHA
CE
R/W
DATA IN
ADDRESS
tSA
[28, 29]
Notes
24. R/W must be HIGH during all address transitions.
25. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
26. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
27. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as
short as the specified tPWE.
28. To access RAM, CE = VIL, SEM = VIH.
29. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
30. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
31. During this period, the I/O pins are in the output state, and input signals must not be applied.
32. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 12 of 24
Figure 9. Semaphore Read After Write Timing, Either Side [33]
Figure 10. Timing Diagram of Semaphore Contention [34, 35, 36]
Switching Waveforms (continued)
tSOP
tSAA
VALID ADRESS VALID ADRESS
tHD
DATAIN VALID DATAOUT VALID
tOHA
tAW
tHA
tACE
tSOP
tSCE
tSD
tSA tPWE
tSWRD tDOE
WRITE CYCLE READ CYCLE
OE
R/W
I/O0
SEM
A0–A 2
MATCH
tSPS
A0L–A2L
MATCH
R/WL
SEML
A0R–A2R
R/WR
SEM R
Notes
33. CE = HIGH for the duration of the above timing (both write and read cycle).
34. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
35. Semaphores are reset (available to both ports) at cycle start.
36. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 13 of 24
Figure 11. Timing Diagram of Read with BUSY (M/S = HIGH) [37]
Figure 12. Write Timing with Busy Input (M/S = LOW)
Switching Waveforms (continued)
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATA INR
DATAOUTL
tWC
ADDRESSR
tPWE
VALID
tSD tHD
ADDRESSL
tPS
tBLA tBHA
tBDD
BUSYL
tPWE
R/W
BUSY
tWB tWH
Note
37. CEL = CER = LOW.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 14 of 24
Figure 13. Busy Timing Diagram No.1 (CE Arbitration) [38]
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration) [38]
Switching Waveforms (continued)
ADDRESS MATCH
tPS
tBLC tBHC
ADDRESS MATCH
tPS
tBLC tBHC
CERValid First:
ADDRESS L,R
BUSY
R
CEL
CER
BUSYL
CER
CE L
ADDRESSL,R
CELValid First:
ADDRESS MATCH
tPS
ADDRESSL
BUSYR
ADDRESS MISMATCH
tRC or tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDRESS MISMATCH
tPS
ADDRESSL
BUSY L
tRC or tWC
tBLA tBHA
ADDRESSR
Right Address Valid First:
Left Address Valid First:
Note
38. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 15 of 24
Figure 15. Interrupt Timing Diagrams
Switching Waveforms (continued)
WRITE 7FFF (FFFF for CY7C028)
tWC
Right Side Clears INTR:
tHA
READ 7FFF
tRC
tINR
WRITE 7FFE (FFFE for CY7C028)
tWC
Right Side Sets INTL:
Left Side Sets INTR:
Left Side Clears INTL:
READ 7FFE
tINR
tRC
ADDRESSR
CE L
R/W L
INT L
OE L
ADDRESSR
R/WR
CE R
INTL
ADDRESSR
CER
R/WR
INTR
OE R
ADDRESSL
R/WL
CE L
INTR
tINS
tHA
tINS
(FFFF for CY7C028)
(FFFE for CY7C028)
[39]
[40]
[40]
[40]
[39]
[40]
Notes
39. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
40. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 16 of 24
Architecture
The CY7C027 and CY7C028 consist of an array of 32K and 64K
words of 16 bits each of dual-port RAM cells, I/O and address
lines, and control signals (CE, OE, R/W). These control pins
permit independent access for reads or writes to any location in
memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. Two interrupt
(INT) pins can be used for port-to-port communication. Two
semaphore (SEM) control pins are used for allocating shared
resources. With the M/S pin, the devices can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The devices also have an automatic power down feature
controlled by CE. Each port is provided with its own output
enable control (OE), which allows data to be read from the
device.
Functional Overview
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W to guarantee a valid write. A write operation is controlled
by either the R/W pin (see Figure 7 on page 11) or the CE pin
(see Figure 8 on page 11). Required inputs for non-contention
operations are summarized in Ta b l e 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port tDDD after
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Table 1. Non-Contending Read/Write
Inputs Outputs
CE R/W OE UB LB SEM I/O8–I/O15 I/O0–I/O7Operation
H X X X X H High Z High Z Deselected: Power Down
X X X H H H High Z High Z Deselected: Power Down
L L X L H H Data In High Z Write to Upper Byte Only
L L X H L H High Z Data In Write to Lower Byte Only
L L X L L H Data In Data In Write to Both Bytes
L H L L H H Data Out High Z Read Upper Byte Only
L H L H L H High Z Data Out Read Lower Byte Only
L H L L L H Data Out Data Out Read Both Bytes
X X H X X X High Z High Z Outputs Disabled
H H L X X L Data Out Data Out Read Data in Semaphore Flag
X H L H H L Data Out Data Out Read Data in Semaphore Flag
H X X X L Data In Data In Write DIN0 into Semaphore Flag
X X H H L Data In Data In Write DIN0 into Semaphore Flag
L X X L X L Not Allowed
L X X X L L Not Allowed
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 17 of 24
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF for the CY7C027,
FFFF for the CY7C028) is the mailbox for the right port and the
second-highest memory location (7FFE for the CY7C027, FFFE
for the CY7C028) is the mailbox for the left port. When one port
writes to the other port’s mailbox, an interrupt is generated to the
owner. The interrupt is reset when the owner reads the contents
of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy is
summarized in Table 2.
Busy
The CY7C027 and CY7C028 provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
both ports’ CEs are asserted and an address match occurs within
tPS of each other, the busy logic determines which port has
access. If tPS is violated, one port definitely gains permission to
the location, but it is not predictable which port gets that
permission. BUSY is asserted tBLA after an address match or
tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This allows
the device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY input has settled (tBLC or tBLA), otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S pin allows the device to be used as a master
and, therefore, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C027 and CY7C028 provide eight semaphore latches,
which are separate from the dual-port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports.The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for tSOP before attempting to read the semaphore.
The semaphore value is available tSWRD + tDOE after the rising
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource,
otherwise (reads a one) it assumes the right port has control and
continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the left
side succeeds in gaining control of the semaphore. If the left side
no longer requires the semaphore, a one is written to cancel its
request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. Table 3 shows sample semaphore
operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to access
the semaphore within tSPS of each other, the semaphore is
definitely obtained by one side or the other, but there is no
guarantee which side controls the semaphore.
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH) [41]
Left Port Right Port
Function R/WLCELOELA0L–14LINTLR/WRCEROERA0R–14R INTR
Set Right INTR FlagL LX 7FFF XXXX X L
[42]
Reset Right INTR Flag X X X X X X L L 7FFF H [43]
Set Left INTL Flag X X X X L [43] LLX7FFEX
Reset Left INTL Flag X L L 7FFE H [42] XXXXX
Notes
41. A0L–15L and A0R–15R, FFFF/FFFE for the CY7C028.
42. If BUSYL = L, then no change.
43. If BUSYR = L, then no change.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 18 of 24
Table 3. Semaphore Operation Example
Function I/O0–I/O15 Left I/O0–I/O15 Right Status
No action 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore
Left port writes 1 to semaphore 1 0 Right port obtains semaphore token
Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to semaphore 0 1 Left port obtains semaphore token
Left port writes 1 to semaphore 1 1 Semaphore free
Right port writes 0 to semaphore 1 0 Right port has semaphore token
Right port writes 1 to semaphore 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Left port writes 1 to semaphore 1 1 Semaphore free
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 19 of 24
Ordering Information
Ordering Code Definitions
32K × 16 Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
20 CY7C027-20AXC A100 100-pin TQFP (Pb-free) Commercial
CY7C027-20AXI A100 100-pin TQFP (Pb-free) Industrial
CY7C027-20AXIT A100 100-pin TQFP (Pb-free) Industrial
64K × 16 Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
15 CY7C028-15AXC A100 100-pin TQFP (Pb-free) Commercial
CY7C028-15AI A100 100-pin TQFP Industrial
CY7C028-15AXI A100 100-pin TQFP (Pb-free) Industrial
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free (RoHS Compliant)
Package Type:
A = 100-pin TQFP
Speed Grade: XX = 20 or 15
20 = 20 ns; 15 = 15 ns
Depth: X = 7 or 8
7 = 32K; 8 = 64K
Width: 02 = × 16
Technology Code: C = CMOS
Marketing Code: 7 = Dual Port SRAM
Company ID: CY = Cypress
CCY 02 - XX XX XX
7X
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 20 of 24
Package Diagram
Figure 16. 100-pin TQFP (14 × 14 × 1.4 mm) A100SA Package Outline, 51-85048
51-85048 *J
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 21 of 24
Acronyms Document Conventions
Units of Measure
Acronym Description
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
TQFP Thin Quad Flat Pack
TTL Transistor-Transistor Logic
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
mA milliampere
mm millimeter
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 22 of 24
Document History Page
Document Title: CY7C027/CY7C028, 32K/64K × 16 Dual-Port Static RAM
Document Number: 38-06042
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 110190 SZV 09/29/2001 Change from Spec number: 38-00666 to 38-06042
*A 122292 RBI 12/27/2002 Updated Maximum Ratings:
Added Note 6 and referred the same note in “maximum ratings”.
*B 236765 YDT 6/23/2004 Updated Features (Removed cross information from this section).
*C 377454 PCX 06/13/2005 Updated Ordering Information (Added Pb-free Logo, added Pb-free parts to
ordering information namely CY7C027-20AXC, CY7C028-12AXC,
CY7C028-15AXC, CY7C028-15AI, CY7C028-15AXI).
*D 2623540 VKN /
PYRS
12/17/2008 Updated Ordering Information (Added CY7C027-15AXI in the Ordering
information table).
*E 2897217 RAME 03/22/2010 Updated Ordering Information (Updated part numbers).
Updated Package Diagram.
*F 3111417 ADMU 12/15/2010 Added Ordering Code Definitions under Ordering Information.
*G 3352028 ADMU 08/23/2011 Updated Features (Removed CY7C037/CY7C038 related information and also
removed -12 speed bin related information).
Updated Functional Description (Removed CY7C037/CY7C038 related
information).
Updated Pin Configurations (Removed CY7C037/CY7C038 related
information).
Updated Selection Guide (Removed CY7C037/CY7C038 related information
and also removed -12 speed bin related information).
Updated Electrical Characteristics (Removed CY7C037/CY7C038 related
information and also removed -12 speed bin related information).
Updated AC Test Loads and Waveforms (Removed -12 speed bin related
information).
Updated Switching Characteristics (Removed CY7C037/CY7C038 related
information and also removed -12 speed bin related information).
Updated Package Diagram.
Added Acronyms and Units of Measure.
Updated to new template.
*H 3721632 ADMU 08/23/2012 Updated Operating Range (Removed the Note “Industrial parts are available
in CY7C028 only.” and its reference).
Updated Electrical Characteristics (Removed the Note “Industrial parts are
available in CY7C028 only.” and its reference).
Updated Ordering Information (Updated part numbers).
Updated Package Diagram (spec 51-85048 (Changed revision from *E to *G)).
*I 3846315 SMCH 12/19/2012 Updated Ordering Information (Updated part numbers).
*J 4106180 SMCH 08/28/2013 Updated Pin Configurations:
Updated Figure 1 (Removed overline on “R” in “CE1R” in pin 63).
Updated Package Diagram:
spec 51-85048 – Changed revision from *G to *H.
Updated to new template.
Completing Sunset Review.
*K 4580622 SMCH 11/26/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagram:
spec 51-85048 – Changed revision from *H to *I.
*L 5436673 NILE 09/14/2016 Updated Package Diagram:
spec 51-85048 – Changed revision from *I to *J.
Updated to new template.
Completing Sunset Review.
CY7C027
CY7C028
Document Number: 38-06042 Rev. *M Page 23 of 24
*M 5840744 NILE 08/01/2017 Updated to new template.
Completing Sunset Review.
Document History Page (continued)
Document Title: CY7C027/CY7C028, 32K/64K × 16 Dual-Port Static RAM
Document Number: 38-06042
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 38-06042 Rev. *M Revised August 1, 2017 Page 24 of 24
CY7C027
CY7C028
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