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FEATURES
APPLICATIONS
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Low-Power, Highly-Integrated, Programmable16-Bit, 26-KSPS, Dual-Channel CODEC
•Differential and Single-Ended AnalogInput/Output•Stereo 16-Bit Oversampling Sigma-Delta A/DConverter •Built-In Analog Functions:•Stereo 16-Bit Oversampling Sigma-Delta D/A – Analog and Digital SidetoneConverter
– Antialiasing Filter (AAF)•Support Maximum Master Clock of 100 MHz to
– Programmable Input and Output GainAllow DSPs Output Clock to be Used as a
Control (PGA)Master Clock
– Microphone/Handset/Headset Amplifiers•Selectable FIR/IIR Filter With Bypassing
– AIC20/21/20K Have a Built-In 8- ΩSpeakerOption
Driver•Programmable Sampling Rate up to:
– Power Management With Hardware/Software– Max 26 Ksps With On-Chip IIR/FIR Filter
Power-Down Modes 30 µW– Max 104 Ksps With IIR/FIR Bypassed
•Separate Software Control for ADC and DAC•On-Chip FIR Produced 84-dB SNR for ADC Power Downand 92-dB SNR for DAC over 13-Khz BW
•Fully Compatible With Common TMS320
®
DSP•Smart Time Division Multiplexed ( SMARTDM
®
) Family and Microcontroller Power SuppliesSerial Port
– 1.65-V - 1.95-V Digital Core Power– Glueless 4-Wire Interface to DSP
– 1.1-V - 3.6-V Digital I/O– Automatic Cascade Detection (ACD)
– 2.7-V - 3.6-V AnalogSelf-Generates Master/Slave Device
•Internal Reference Voltage (V
ref
)Addresses
•2s Complement Data Format– Programming Mode to Allow On-The-Fly
•Test Mode Which Includes Digital LoopbackReconfiguration
and Analog Loopback– Continuous Data Transfer Mode to MinimizeBit Clock Speed– Support Different Sampling Rate for Each
•Wireless AccessoriesDevice
•Hands-Free Car Kits– Turbo Mode to Maximize Bit Clock For
•VOIPFaster Data Transfer and Allow Multiple
•Cable ModemSerial Devices to Share the Same Bus
•Speech Processing– Allows up to Eight Devices to be Connectedto a Single Serial Port•Host port– 2-Wire Interface– Selectable I
2
C or S
2
C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SMARTDM, TMS320, TMS320C5000, TMS320C6000 are registered trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
The TLV320AIC2x is a low-cost, low-power, highly-integrated, high-performance, dual-voice codec. It featurestwo 16-bit analog-to-digital (A/D) channels and two 16-bit digital-to-analog (D/A) channels, which can beconnected to a handset, headset, speaker, microphone, or a subscriber line via a programmable analogcrosspoint.
The TLV320AIC2x provides high resolution signal conversion from digital-to-analog (D/A) and fromanalog-to-digital (A/D) using oversampling sigma-delta technology with programmable sampling rate.
The TLV320AIC2x implements the smart time division multiplexed serial port (SMARTDM™) . The SMARTDMport is a synchronous 4-wire serial port in TDM format for glue-free interface to TI DSPs (i.e., TMS320C5000
®
,TMS320C6000
®
DSP platforms) and microcontrollers. The SMARTDM™ supports both continuous data transfermode and on-the-fly reconfiguration programming mode. The TLV320AIC2x can be gluelessly cascaded to anySMARTDM-based device to form a multichannel codec, and up to eight TLV320AIC2x codecs can be cascadedto a single serial port.
The TLV320AIC2x provides a flexible host port. The host port interface is a two-wire serial interface that can beprogrammed to be either an industrial standard I
2
C or a simple S
2
C (start-stop communication protocol).
The TLV320AIC2x integrates all of the critical functions needed for most voice-band applications including MICpreamplifier, handset amplifier headset amplifier, 8- Ωspeaker driver, sidetone control, antialiasing filter (AAF),input/output programmable gain amplifier (PGA), and selectable low-pass IIR/FIR filters.
The TLV320AIC2x implements an extensive power management; including device power-down, independentsoftware control for turning off ADC, DAC, operational-amplifiers, and IIR/FIR filter (bypassable) to maximizesystem power conservation. The TLV320AIC2x consumes only 14.9 mW per channel at 3 V.
The TLV320AIC2x low power operation from 2.7-V to 3.6-V power supplies along with extensive powermanagement make it ideal for portable applications including wireless accessories, hands-free car kits, VOIP,cable modem, and speech processing. Its low group delay characteristic makes it suitable for single ormultichannel active control applications.
The TLV320AIC2x is characterized for commercial operation from 0°C to 70°C, and industrial operation from-40°C to 85°C. The TLV320AIC2xk is characterized for industrial operation from -40°C to 85°C.
ORDERING INFORMATION
T
A
48-TQFP PFB PACKAGE
(1)
0°C to 70°C TLV320AIC2xC-40°C to 85°C TLV320AIC2xI
(1) For the most current package and ordering information, see the Package Option Addendum at theend of this document, or see the TI website at www.ti.com .
2
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PFB
TOP VIEW
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19
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21
22
23
24
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
MICBIAS
MICI+
MICI-
AVDD1
AVSS1
CIDI+
CIDI-
DRVSS2
SPKO-
DRVDD
SPKO+
DRVSS1
VSS
RESET
MCLK
M/S
SCLK
FS
DIN
DOUT
DVSS
DVDD
FSD
IOVSS
LCDAC
HNSO-
HNSO+
HNSI-
HNSI+
AVDD
AVSS
LINEI+
LINEI-
LINEO-
LINEO+
NC
HDSI-
HDSI+
HDSO-
HDSO+
AVDD2
AVSS2
TESTP
NC
PWRDN
SDA
SCL
IOVDD
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Terminal Functions
TERMINAL
NAME NO. I/O DESCRIPTION
HDSI- 1
I Head-set input. The Head-set input can be treated similar to the Line-input pinsHDSI+ 2HDSO- 3
O 150- ΩoutputHDSO+ 4AVDD2 5 I Analog power supplyAVSS2 6 I Analog groundTESTP 7 I Test pin. Should be connected to digital ground.NC 8, 48 Not connectedPWRDN 9 I Power downSDA 10 I/O I
2
C/S
2
C dataSCL 11 I I
2
C/S
2
C clockIOVDD 12 I I/O power supplyIOVSS 13 I I/O groundFSD 14 O Frame sync delayedDVDD 15 I Digital supply (1.8 V)DVSS 16 I Digital groundDOUT 17 O Data OUTDIN 18 I Data INFS 19 I/O Frame syncSCLK 20 I/O Serial clock
3
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TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Terminal Functions (continued)
TERMINAL
NAME NO. I/O DESCRIPTION
M/S 21 I Master slave select applied to CODEC1 only. CODEC2 is always a slave.MCLK 22 I Master clockRESET 23 I ResetVSS 24 I Device ground. Typically this should be connected to the Analog Ground.DRVSS1 25 I Driver groundSPKO+ 26
O 8- ΩoutputSPKO- 28DRVDD 27 I Driver supplyDRVSS2 29 I Driver groundCIDI- 30
I Caller-ID input. The Caller-ID input can be treated similar to the Line-input pinsCIDI+ 31AVDD1 33 I Analog supplyAVSS1 32 I Analog groundMICI- 34 I Microphone inputMICI+ 35 I Microphone inputMICBIAS 36 I Microphone biasLCDAC 37 O 6-Bit DAC output may be used to drive LCDACHNSO- 38
O 150- ΩoutputHNSO+ 39HNSI- 40
I Hand-set input. The Hand-set input can be treated similar to the Line-input pinsHNSI+ 41AVDD 42 I Analog supplyAVSS 43 I Analog groundLINEI+ 44
I Line inputLINEI- 45LINEO- 46
O 600- ΩoutputLINEO+ 47
4
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Electrical Characteristics
Absolute Maximum Ratings
(1)
Recommended Operating Conditions
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
All specifications are common across the AIC20, AIC21, AIC24, AIC25, AIC20K, and AIC24K except whereexplicitly stated.
AIC20/21/24/25: Over Recommended Operating Free-Air Temperature Range, AVDD = 3.3 V, DVDD = 1.8 V,IOVDD = 3.3 V (Unless Otherwise Noted)
AIC20K/24K: Over Recommended Operating Free-Air Temperature Range, AVDD = 3.3 V, DVDD = 1.8 V,IOVDD = 3.3 V (Unless Otherwise Noted)
over Operating Free-Air Temperature Range (Unless Otherwise Noted)
TLV320AIC2x
V
CC
Supply voltage range: DVDD
(2)
-0.3 V to 2.25 VAVDD, IOVDD, DRVDD
(2)
-0.3 V to 4 VV
O
Output voltage range, all digital output signals -0.3 V to IOVDD + 0.3 VV
I
Input voltage range, all digital input signals -0.3 V to IOVDD + 0.3 VT
A
Operating free-air temperature range -40°C to 85°CT
stg
Storage temperature range -65°C to 150°CCase temperature for 10 seconds: package 260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to V
SS
.
MIN NOM MAX UNIT
Analog, AVDD 2.7 3.3 3.6 VAnalog output driver, DRVDD
(1)
2.7 3.3 3.6 VV
CC
Supply voltage
Digital core, DVDD 1.65 1.8 1.95 VDigital I/O, IOVDD 1.1 3.3 3.6 VAnalog single-ended peak-to-peak input voltage, V
I(analog)
2 VBetween LINEO+ and LINEO- (differential) 600Between HDSO+ and HDSO- (differential) 150R
L
Output load resistance, ΩBetween HNSO+ and HDSO- (differential) 150Between SPKO+ and SPKO- (differential) 8C
L
Analog output load capacitance 20 pFDigital output capacitance 20 pFMaster clock 100 MHzADC or DAC conversion rate 26 kHzT
A
Operating free-air temperature, -40 85 °C
(1) DRVDD should be kept at the same voltage as AVDD.
5
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Digital Inputs and Outputs
ADC PATH FILTER
ADC DYNAMIC PERFORMANCE
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
FS = 8 KHz, outputs not loaded
PARAMETER MIN TYP MAX UNIT
V
OH
High-level output voltage, DOUT 0.8 IOVDD VV
OL
Low-level output voltage, DOUT 0.1 IOVDD VI
IH
High-level input current, any digital input 5 µAI
IL
Low-level input current, any digital input 5 µAC
i
Input capacitance 3 pFC
o
Output capacitance 5 pF
FS = 8 KHz
(1) (2)
TESTPARAMETER MIN TYP MAX MIN TYP MAX UNITCONDITIONS
PATH FILTER FIR FILTER IIR FILTER
0 Hz to 60 Hz -27 / 0.07 -27 / 0.1560 Hz to 200 Hz -1 / 0.07 -0.75 / 0.15200 Hz to 300 Hz -0.03 / 0.05 0. 11 / 0.15300 Hz to 2.4 KHz -0.1 0.15 -0.1 0.25Filter gain relative to gain
2.4 kHz to 3 kHz -0.05 0.15 -0.5 0.2 dBat 1020 Hz
3 kHz to 3.4 KHz -0.5 0.1 -0.5 0.23.4 kHz to 3.6 KHz -0.4 0.154 KHz -26 -424.5 KHz to 72 kHz -52 -52
(1) The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The analog input test signal is a sine wave with0 dB = 4 V
I(PP)
as the reference level for the analog input signal. The pass band is 0 to 3600 Hz for an 8-KHz sample rate. This passband scales linearly with the sample rate.(2) The filter characteristics are specified by design and are not tested in production. In places where more than one value is specified, thefirst value is with the High Pass Filter on and the second value is with the HPF off
With FIR Filter, FS = 8 KHz
(1)
TESTPARAMETER MIN TYP MAX MIN TYP MAX UNITCONDITIONS
Line In Driver AIC20/21/24/25 AIC20k/24k
V
I
= -3 dB 81 84 70 84SNR Signal-to-noise ratio
V
I
= -9 dB 73 76 76V
I
= -3 dB 83 90 70 90THD Total harmonic distortion dBV
I
= -9 dB 81 88 88V
I
= -3 dB 80 83 83Signal-to-harmonic
THD+N
distortion + noise
V
I
= -9 dB 73 76 76
(1) The test condition is a differential 1020-Hz input signal with an 8-KHz conversion rate. Input and output common mode is 1.35 V.
6
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ADC DYNAMIC PERFORMANCE
ADC CHANNEL CHARACTERISTICS
DAC PATH FILTER
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
With IIR Filter, FS = 8 KHz
TESTPARAMETER MIN TYP MAX MIN TYP MAX UNITCONDITIONS
AIC20/21/24/25 AIC20k/24k
V
I
= -3 dB 82 82SNR Signal-to-noise ratio
V
I
= -9 dB 76 76V
I
= -3 dB 83 83THD Total harmonic distortion dBV
I
= -9 dB 77 77V
I
= -3 dB 78 78Signal-to-harmonic
THD+N
distortion + noise
V
I
= -9 dB 70 70
AIC20/21/24/25/20k/24kPARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
V
I(pp)
Differential-ended input level PGA gain = 0 dB 4 VV
IO
Input offset voltage ±5 mVI
B
Input bias current 125 µACommon mode voltage 1.35 VDynamic range V
I
= -3 dB 87 dBZero DigitalMute attenuation PGA = MUTE dBCodeIntrachannel isolation 87 dBE
G
Gain error V
I
= -3 dB at 1020 Hz -0.45 dBE
O(ADC)
ADC converter offset error ±15 mVCommon-mode rejection ratio at INMx andCMRR V
I
= -100 mV at 1020 Hz 50 dBINPx
Idle channel noise V
(INP,INM,MICIN)
= 0 V 70 µVrmsR
i
Input resistance T
A
= 25°C 10 k ΩC
i
Input capacitance T
A
= 25°C 2 pFIIR 5/f
s
SChannel delay
FIR 17/f
s
S
FS = 8 KHz
(1) (2)
FIR FILTER IIR FILTERPARAMETER TEST CONDITIONS
MIN TYP MAX MIN TYP MAX UNIT
PATH FILTER, FS = 8 KHz
0 Hz to 200 Hz 0.1 0.05200 Hz to 300 Hz -0.05 0.05300 Hz to 2.4 KHz -0.25 0.15 -0.1 0.12.4 kHz to 3 kHz -0.3 0.1 -0.2 0.1Filter gain relative to gain
dBat 1020 Hz
3 kHz to 3.4 KHz -0.55 0.05 -0.25 0.053.4 kHz to 3.6 KHz -30 04 KHz -28 -344.5 KHz to 72 KHZ -70 -70
(1) The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The input signal is the digital equivalent of asine wave (digital full scale = 0 dB). The nominal differential DAC channel output with this input condition is 4 V
I(PP)
. The pass band is0 to 3600 Hz for an 8-kHz sample rate. This pass band scales linearly with the conversion rate.(2) The filter characteristics are specified by design and are not tested in production.
7
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DAC DYNAMIC PERFORMANCE
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
AIC20/21/24/25 AIC20k/24kPARAMETER TEST CONDITIONS
MIN TYP MAX MIN TYP MAX UNIT
The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate.DAC Line Output (LINEO-, LINEO+)
The test is measured at output of the application schematic low-pass filter. The test is conducted inUsing FIR Filter
16-bit mode.
V
I
= 0 dB 88 92 80 92SNR Signal-to-noise ratio
V
I
= -9 dB 81 83 83V
I
= 0 dB 84 90 70 90THD Total Harmonic Distortion dBV
I
= -9 dB 77 84 84V
I
= 0 dB 82 88 88Signal-to-total HarmonicTHD+N
Distortion + noise
V
I
= -9 dB 76 80 80The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate.DAC Line Output (LINEO-, LINEO+)
The test is measured at output of the application schematic low-pass filter. The test is conducted inUsing IIR Filter
16-bit mode.
V
I
= 0 dB 83 83SNR Signal-to-noise ratio
V
I
= -9 dB 74 74V
I
= 0 dB 85 85THD Total Harmonic Distortion dBV
I
= -9 dB 80 80V
I
= 0 dB 80 80Signal-to-total HarmonicTHD+N
Distortion + noise
V
I
= -9 dB 73 73The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate.DAC Headphone Output (HDSO-,
The test is measured at output of the application schematic low-pass filter. The test is conducted inHDSO+), (HNSO-, HNSO+)
(1)
16-bit mode.
V
I
= 0 dB 92 92SNR Signal-to-noise ratio
V
I
= -9 dB 83 83V
I
= 0 dB 90 90THD Total Harmonic Distortion dBV
I
= -9 dB 89 89V
I
= 0 dB 88 88Signal-to-total HarmonicTHD+N
Distortion + noise
V
I
= -9 dB 82 82The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate.DAC Speaker Output (SPKO-,
The test is measured at output of the application schematic low-pass filter. The test is conducted inSPKO+)
(1) (2)
16-bit mode.
V
I
= 0 dB 91 91SNR Signal-to-noise ratio
V
I
= -9 dB 83 83V
I
= 0 dB 91 91THD Total Harmonic Distortion dBV
I
= -9 dB 91 91V
I
= 0 dB 88 88Signal-to-total HarmonicTHD+N
Distortion + noise
V
I
= -9 dB 82 82
(1) The conversion rate is 8 kHz.(2) The speaker driver is valid only for the AIC20/21/20K.
8
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DAC CHANNEL CHARACTERISTICS
OUTPUT AMPLIFIER CHARACTERISTICS
BIAS AMPLIFIER CHARACTERISTICS
POWER-SUPPLY REJECTION
(1)
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dynamic range V
I
= 0 dB at 1020 Hz 92 dBInterchannel isolation 90 dBE
G
Gain error, 0 dB V
O
= 0 dB at 1020 Hz -0.7 dBMute attenuation PGA = Mute 90 dBCommon-mode voltage 1.35 VIdle channel narrow band noise 0 - 4 kHz
(1)
40 V rmsOutput offset voltage at OUTP1_150V
OO
DIN = All zeros ±8 V(differential)V
O
Analog output voltage, (3.3 V) HDSO+ 0.35 2.35 VIIR 5/f
s
sChannel delay
FIR 18/f
s
s
(1) The conversion rate is 8 kHz.
AIC20/21/24/25/20k/24kPARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
SPEAKER INTERFACE
(1)
Speaker output power 250 mWV
CC
= 3.3 V, fullydifferential, 8- ΩloadMaximum output current 250 mA
HANDSET AND HEADSET INTERFACE
Speaker output power 13 mWV
CC
= 3.3 V, fullydifferential, 150- ΩloadMaximum output current 13 mA
LINE INTERFACE
Speaker output power 3.5 mWV
CC
= 3.3 V, fullydifferential, 600- ΩloadMaximum output current 3.5 mA
(1) The speaker driver is valid only for the AIC20/21/20k.
AIC20/21/24/25/20k/24kPARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
V
O
Output voltage 1.35/2.35 VIntegrated noise 300 Hz – 13 KHz 20 µVV
S
Offset voltage 10 mVCurrent drive 5 mAUnity gain bandwith 1 MHzDC gain 90 dBPSRR 70 dB
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply-voltage rejection ratio, analog supplyAV
DD
Differential 75(fj = 0 to f
s
/2 )
(1) Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200 mV peak-to-peak signalapplied to the appropriate supply.
9
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POWER-CONSUMPTION
LCD DAC
Typical ADC performance With PGA Gain Setting Using FIR
(1)
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
AIC20/21/24/25/20k/24kPARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
ADC (single channel) 5.7DAC (single channel) Without drivers 3.5Speaker driver
(1)
No signal 9.3Handset driver No signal 2Headset driver No signal 2Lineout driver No signal 2 mWReference 2.3Digital PLL off 3.4Analog 4.6PLL
Digital 1.8Total Analog with all sections on No signal, PLL off 35.8
POWER DOWN CURRENT
Hardware power-down (no clock) 1Analog, PLL off 2 µASoftware power-down
Digital 650
(1) The speaker driver is valid only for the AIC20/21/20k.
AIC20/21/20kPARAMETER
MIN TYP MAX UNIT
V
O
Output range 0.35 2.35 VSampling rate 104 kHzINL ±0.5 LSBDNL ±0.25 LSBV
S
Offset voltage ±25 mVE
G
Gain error ±0.02 dB
PGA GAIN SETTING SNR THD SINAD UNIT
9 dB 83 90 8118 dB 83 97 83 dB24 dB 78 95 7736 dB 72 95 72
(1) Test condition is a 1020-Hz input differential signal with an 8-kHz conversion rate. Input amplitude is given such that output of PGA is at-3 dB level.
10
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DAC
+
+
Σ-∆
DAC
0dB to -42 dB
(1.5 dB Steps).
-48 dB, -54 dB
Analog Sidetone
-9 dB to -27 dB
Σ-∆
ADC
0dB to 42dB
(1.5 dB Steps).
48 dB, 54 dB
CODEC 1 (Channel 1)
Σ-∆
DAC
0dB to -42 dB
(1.5 dB Steps).
-48 dB, -54 dB
Σ-∆
ADC
0dB to 42dB
(1.5 dB Steps).
48 dB, 54 dB
CODEC 2 (Channel 2)
Analog Sidetone
-9 dB to -27 dB
1.35 V / 2.35
2 mA
SMARTDM
Serial Port
Internal Clock
Generator
Host Port
SPKO+
SPKO-
Speaker
8 Ω Output
LINE0+
LINEO-
Line Output
600 Ω
HNSO+
HNSO-
Handset
150 Ω Output
HNSI+
HNSI-
Handset
Input
HDSO+
HDSO-
Headset
150 Ω Output
HDSI+
HDSI-
Headset
Input
MICI+
MICI-
Microphone
Input
LINEI+
LINEI-
Line
Input
CIDI+
CIDI-
MICBIAS
LCDAC
MCLK FSD DOUT DIN SCLK FS M/S SDA SCL
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Functional Block Diagram - AIC20/21/20K
11
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DAC
+
+
Σ−∆
DAC
0 dB to −42 dB
(1.5 dB Steps).
−48 dB, −54 dB
Analog Sidetone
−9 dB to −27 dB
Σ−∆
ADC
0 dB to 42 dB
(1.5 dB Steps).
48 dB, 54 dB
Σ−∆
DAC
0 dB to −42 dB
(1.5 dB Steps).
−48 dB, −54 dB
Σ−∆
ADC
0 dB to 42 dB
(1.5 dB Steps).
48 dB, 54 dB
Analog Sidetone
−9 dB to −27 dB
1.35 V / 2.35
2 mA
SMARTDM
Serial Port
Internal Clock
Generator
Host Port
OUTP1
OUTM1
Line Output
600 Ω
OUTP2
OUTM2
150 Ω Output
INP2
INM2
Input
OUTP3
OUTM3
150 Ω Output
INP3
INM3
Input
MICI+
MICI−
Microphone
Input
INP1
INM1
Input
INP4
INM4
MICBIAS
LCDAC
MCLK FSD DOUT DIN SCLK FS M/S SDA SCL
CODEC 1 (Channel 1)
CODEC 2 (Channel 2)
Input
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Functional Block Diagram - AIC24/25/24K
12
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Analog
Loopback
PGA Low Pass
Filter Sigma-
Delta
DAC
Anti-
Aliasing
Filter
Sigma-
Delta
ADC Sinc
Filter
FIR Filter
IIR Filter
Decimation Filter
Sinc
Filter
FIR Filter
IIR Filter
Interpolation Filter
Digital Loopback
w/ Sidetone Control
and Mute
M/S
DOUT
DIN
FS
SCLK
FSD
PGA
SMARTDM
-9 dB to -27 dB
Serial
Port
0 dB to 42 dB (1.5 dB Steps)
48 dB, 54 dB
Vref
CODEC
0 dB to -42 dB (1.5 dB Steps)
-48 dB, -54 dB
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Functional Block Diagram (One of Two Channels Shown)
Definitions and Terminology
Data Transfer The time during which data is transferred from DOUT and to DIN.Interval The interval is 16 shift clocks, and the data transfer is initiated bythe falling edge of the FS signal.Signal Data This refers to the input signal and all of the converted representationsthrough the ADC channel and the signal through the DAC channel to theanalog output. This is contrasted with the purely digital software controldata.Frame Sync Frame sync refers only to the falling edge of the signal FS that initiatesthe data transfer intervalFrame Sync and Sampling Period Frame sync and sampling period is the time between falling edges ofsuccessive FS signals.f
s
The sampling frequencyADC Channel ADC channel refers to all signal processing circuits between the analoginput and the digital conversion result at DOUT.DAC channel DAC channel refers to all signal processing circuits between the digitaldata word applied to DIN and the differential output analog signalavailable at OUTP and OUTM.Dxx Bit position in the primary data word (xx is the bit number)DSxx Bit position in the secondary data word (xx is the bit number)d The alpha character d represents valid programmed or default data in thecontrol register format (see Section 3.2, Secondary Serial Communi-cation) when discussing other data bit portions of the register.PGA Programmable gain amplifierIIR Infinite impulse responseFIR Finite impulse response
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TIMING REQUIREMENTS
th1
2.4 V
MCLK
RESET
2.4 V
tsu1
2.4 V
twL
twH
td1 td2 td1 td2
ten td3 tdis
tsu2
th2
D15
D15
SCLK
FS
FSD
DOUT
DIN
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Figure 1. Hardware Reset Timing
Figure 2. Serial Communication Timing
TEST CONDITIONS MIN TYP MAX UNIT
t
wH
Pulse duration, MCLK high 5t
wL
Pulse duration, MCLK low 5t
su1
Setup time, RESET, before MCLK high (see Figure 1 ) 3t
h1
Hold time, RESET, after MCLK high (see Figure 1 ) 2t
d1
Delay time, SCLK ↑to FS/FSD ↓C
L
= 20 pF 5 nst
d2
Delay time, SCLK ↑to FS/FSD ↑5t
d3
Delay time, SCLK ↑to DOUT 15t
en
Enable time, SCLK ↑to DOUT 15t
dis
Disable time, SCLK ↑to DOUT 15t
su2
Setup time, DIN, before SCLK ↓10t
h2
Hold time, DIN, after SCLK ↓10
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SDA
SCL
tftLOW
tHD;STA tHD;DAT tHIGH
tSU;STA tSU;STO
tBUF
tr
tHD;STA
tf
tSU;DAT
tr
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Figure 3. I
2
C / S
2
C Timing Diagram
PARAMETER SYMBOL MIN MAX UNIT
SCL clock frequency t
SCL
0 900 kHzHold time (repeated START condition. After this period, the first clock pulse is t
HD;STA
100generated.
Low period of the SCL clock t
LOW
560High period of the SCL clock t
HIGH
560Set-up time for a repeated START condition t
SU;STA
100Data hold time t
HD;DAT
50
nsData set-up time t
SU;DAT
50Rise time of both SDA and SCL signals t
r
300Fall time of both SDA and SCL signals t
f
100Set-up time for STOP condition t
SU;STO
100Bus free time between a STOP and START condition t
BUF
500
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PARAMETER MEASUREMENT INFORMATION
−140
−120
−100
−80
−60
−40
−20
0
0 500 1000 1500 2000 2500 3000 3500 4000
Amplitude − dB
f − Frequency − Hz
−140
−120
−100
−80
−60
−40
−20
0
0 500 1000 1500 2000 2500 3000 3500 4000
Amplitude − dB
f − Frequency − Hz
0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
−140
−120
−100
−80
−60
−40
−20
0
Amplitude − dB
f − Frequency − Hz
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Figure 4. FFT—ADC Channel (-3 dB input)
Figure 5. FFT—ADC Channel (-9 dB input)
Figure 6. FFT—DAC Channel (0 dB input)
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0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
−140
−120
−100
−80
−60
−40
−20
0
Amplitude − dB
f − Frequency − Hz
0 2000 4000 6000 8000 10000 12000 14000 16000
−140
−120
−100
−80
−60
−40
−20
0
Amplitude − dB
f − Frequency − Hz
0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
−140
−120
−100
−80
−60
−40
−20
0
Amplitude − dB
f − Frequency − Hz
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 7. FFT—DAC Channel (-9 dB input)
Figure 8. FFT—ADC Channel in FIR/IIR Bypass Mode (-3 dB input)
Figure 9. FFT—DAC Channel in FIR/IIR Bypass Mode (0 dB input)
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−30
−25
−20
−10
−5
0
5
0 500 1000 1500 2000 2500 3000 3500 4000
−15
Filter Gain − dB
f − Frequency − Hz
0 500 1000 1500 2000 2500 3000 3500 4000
−80
−70
−50
−20
−10
0
10
−40
Filter Gain − dB
f − Frequency − Hz
−30
−60
−45
−40
−30
−10
−5
0
−25
Filter Gain − dB
f − Frequency − Hz
−20
−35
−15
5
0 500 1000 1500 2000 2500 3000 3500 4000
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 10. ADC FIR Frequency Response - HPF Off
Figure 11. ADC FIR Frequency Response - HPF On
Figure 12. ADC IIR Frequency Response - HPF Off
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0 500 1000 1500 2000 2500 3000 3500 4000
−80
−70
−50
−20
−10
0
−40
Filter Gain − dB
f − Frequency − Hz
−60
−30
10
−14
−12
−10
−8
−6
−4
−2
0
2
0 2000 4000 6000 8000 10000 12000 14000 16000
Filter Gain − dB
f − Frequency − Hz
20
0 1000 2000 3000 4000 5000 6000 7000 8000
0
−20
−40
−60
−80
−100
−120
−140
−160
Filter Gain − dB
f − Frequency − Hz
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 13. ADC IIR Frequency Response - HPF On
Figure 14. ADC Frequency Response - FIR/IIR Bypass Mode
Figure 15. DAC FIR Frequency Response
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0 1000 2000 3000 4000 5000 6000 7000 8000
20
0
−20
−40
−60
−80
−100
−120
−140
−160
Filter Gain − dB
f − Frequency − Hz
−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
0 4000 8000 12000 16000 20000 24000 28000 32000
Filter Gain − dB
f − Frequency − Hz
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 16. DAC IIR Frequency Response
Figure 17. DAC Channel Frequency Response - FIR/IIR Bypass Mode
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Functional Description
Operating Frequencies
MCLK 1/P
1/(MN) 128FS
(devnum x mode)/(MNP)
SCLK
1/(16 x mode x devnum) FS
en_dll
Digital
X 8
(DLL)
SCLK may not be a uniform clock depending upon value of devnum, mode, and MNP..
M = 1 - 128
N = 1 - 16
P = 1 - 8
When:
P1 = 8, DLL(PLL) is Enabled
devnum = Number of Channels in Cascade.
Note That for a Standalone Device, devnum = 2.
Mode = 1 (For Continious Data Transfer Mode)
Mode = 2 (For Programming Mode)
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
The sampling frequency is the frequency of the frame sync (FS) signal where falling edge starts digital-datatransfer for both ADC and DAC. The sampling frequency is derived from the master clock (MCLK) input by thefollowing equations:
•Coarse sampling frequency (default):– The coarse sampling is selected by programming P = 8 in the control register 4, which is the defaultconfiguration of AIC2x on power-up or reset.– FS = Sampling (conversion) frequency = MCLK / (16 x M x N x 8)•Fine sampling frequency (see Note 5):– FS = Sampling (conversion) frequency = MCLK/ (16 x M x N x P)
NOTE:
1. Use control register 4 to set the following values of M, N, and P2. M = 1, 2, . . . , 1283. N = 1, 2, . . . , 164. P = 1, 2, . . . , 85. The fine sampling rate needs an on-chip phase lock loop (frequency multiplier) togenerate internal clocks. The output of the PLL is only used to generate internalclocks that are needed by the data converters. Other clocks such as the serialinterface clocks in master mode are not generated from the PLL output. The clockgeneration scheme is as shown in Figure 18 . The PLL requires the relationshipbetween MCLK and P to meet the following condition: 10 MHz ≤(MCLK/P) ≤25MHz.
Figure 18. Clock Timing
6. Selecting the Fine sampling mode turns on the analog PLL, which startsgenerating after a finite time delay. The internal clocks are required to be presentin order to enable the DAC output drivers. Therefore, turning on any output driversimmediately after turning on the PLL causes the output of the DAC to go to thecommon-mode voltage. While using the PLL, the output drivers must first beenabled before the PLL is enabled in order to ensure correct operation of the part.This implies that register 6B for channel 1 and channel 2 in the codec must beprogrammed before register 4.
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Internal Architecture
Analog Low Pass Filter
Sigma-Delta ADC
Decimation Filter
Sigma-Delta DAC
Interpolation Filter
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Functional Description (continued)
7. Both equations of FS require that the following conditions should be met– (M x N x P) ≤(devnum mode) if the FIR/IIR filter is not bypassed.– [Integer(M/4) x N x P] ≥(devnum mode) if the FIR/IIR filter is bypassed.
Where:
devnum is the number of codec channels connecting in cascade (devnum = 2 forstandalone AIC20) mode is equal to 1 for continuous data transfer mode and 2 forprogramming mode.8. If the DAC OSR is set to 512, then M needs to be a multiple of 4. If the DAC OSRis set to 256, then M needs to be a multiple of 2. M can take any value between 1and 128 if the OSR is set to 128.
Example:
The MCLK comes from the DSP C5402 CLKOUT and equals to 20.48 MHz and theconversion rate of 8 kHz is desired. First, set P = 1 to satisfy condition 5 so that(MCLK/P) = 20.48 MHz/1 = 20.48 MHz. Next, pick M = 10 and N = 16 to satisfycondition 65 and derive 8 kHz for FS. That is, FS = 20.48 MHz/ (16 x 10 x 16 x 1) = 8kHz.
The built-in analog low pass antialiasing filter is a two-pole filter that has a 20-dB attenuation at 1 MHz.
The sigma-delta analog-to-digital converter is a sigma-delta modulator with 128x oversampling. The ADCprovides high-resolution, low-noise performance using oversampling techniques.
The decimation filters consist of a sinc filter stage followed by either FIR filters or IIR filters selected by bit D5 ofthe control register 1. The FIR filter provides linear-phase output with 17/f
s
group delay, whereas the IIR filtergenerates nonlinear phase output with negligible group delay. The decimation filters reduce the digital data rateto the sampling rate. This is accomplished by decimating with a ratio of 1:128. The output of the decimation filteris a 16-bit 2s-complement data word clocking at the sample rate selected for that particular data channel. TheBW of the filter is (0.45 × FS) and scales linearly with the sample rate.
The sigma-delta digital-to-analog converter is a sigma-delta modulator with 128x oversampling. The DACprovides high-resolution, low-noise performance using oversampling techniques. The oversampling ratio (OSR)in DAC is programmable to 256/512 using bits D0-D1 of register 3C, the default being 128. The OSR of 512 isrecommended when the FS is a maximum of 8 Ksps, and an OSR of 256 is recommended when the FS is amaximum of 16 Ksps. It is also required that the value of M used in programming the PLL be a multiple of 4 if theOSR is set to 512 and 2 if the OSR is set to 256
The interpolation filters consist of either FIR or IIR filters selected by bit D5 of control register 1 followed by a sincfilter stage. The FIR filter provides linear-phase output with 18/f
s
group delay, whereas the IIR filter generatesnonlinear phase output with negligible group delay. The interpolation filter resamples the digital data at a rate of128 times the incoming sample rate. The high-speed data output from the interpolation filter is then used in thesigma-delta DAC. The BW of the filter is (0.45 × FS) and scales linearly with the sample rate.
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Analog/Digital Loopback
Analog Sidetone
Digital Sidetone
Analog Input/Output
Analog Crosspoint
Analog Input Amplifier
Microphone Bias
Output Drivers
Speaker Driver
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Functional Description (continued)
The analog and digital loopbacks provide a means of testing the data ADC/DAC channels and can be used forin-circuit system level tests. The analog loopback always has the priority to route the DAC low pass filter outputinto the analog input where it is then converted by the ADC to a digital word. The digital loopback routes the ADCoutput to the DAC input on the device. Analog loopback is enabled by writing a 1 to bit D2 in the control register1. Digital loopback is enabled by writing a 1 to bit D1 in control register 1.
The analog sidetone attenuates the analog input and mixes it with the output of the DAC. The control register 5Cselects the attenuation level of the analog sidetone.
The digital sidetone attenuates the ADC output and mixes it with the input of the DAC. The control register 5Cselects the attenuation level of the digital sidetone.
To produce excellent common-mode rejection of unwanted signal performance, the analog signal is processeddifferentially until it is converted to digital data. The signal source driving the analog inputs should have lowsource impedance for lowest noise performance and accuracy. To obtain maximum dynamic range, the signalmust be ac coupled to the input terminal. The analog output is differential from the digital-to-analog converter.
The analog crosspoint is a lossless analog switch matrix controlled via the serial control port. It allows any sourcedevice to be connected to any sink device. Additionally, special summing connections with adjustable loss (7 × 3dB steps) are included to implement sidetone for the headset and handset ports. (Also included is mutingfunction on any of the sink devices). The control of the analog crosspoint, defined in the control register 6, is toallow any analog input or output to connect to a codec at one time. If more than one input is selected, theseinputs are mixed together before the conversion. Caution needs to be taken to make sure that both DACchannels are not connected to the same output.
The integrated programmable gain amplifier (PGA) controls the amplification of any analog input before theanalog-to-digital converter converts the signal. The PGA's gain from 0 dB to 42 dB in 1.5-dB steps and 48 dBand 54 dB are selected using the control register 5A.
To operate electret microphones properly, a bias voltage and current are provided. Typically, the current drawnby the microphone is in the order of 100 µA to 800 µA and the bias voltage is specified across the microphone at1.35 V or 2.35 V. The MICBIAS has good power supply noise rejection in the audio band and the bias voltage isselectable, via bit D3 of control register 1, for each interface.
The HSNO and HDSO are output from two audio amplifiers to drive low-voltage speakers like those in thehandset and headset. They can drive a load of 150 Ω. The drive amplifier is differential to minimize noise andEMC immunity problems. The frequency response is flat up to 26 kHz.
The SPKO is output from the audio amplifier that can drive an 8- Ωspeaker load. The drive amplifier is differentialto minimize noise and EMC immunity problems. The frequency response is flat up to 26 kHz.
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IIR/FIR Control
Overflow Flags
IIR/FIR Bypass Mode
System Reset and Power Management
Software and Hardware Reset
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Functional Description (continued)
The decimation IIR/FIR filter sets an overflow flag (bit D7) of control register 1 indicating that the input analogsignal has exceeded the range of internal decimation filter calculations. The interpolation IIR/FIR filter sets anoverflow flag (bit D4) of control register 1 indicating that the digital input has exceeded the range of internalinterpolation filter calculations. When the IIR/FIR overflow flag is set in the register, it remains set until the userreads the register. Reading this value resets the overflow flag. These flags need to be reset after power up byreading the register. If FIR/IIR overflow occurs, the input signal should be attenuated by either the PGA or someother method.
An option is provided to bypass IIR/FIR filter sections of the decimation filter and the interpolation filter. Thismode is selected through bit D6 of control register 2 and effectively increases the frequency of the FS signal tofour times normal output rate of the IIR/FIR-filter. For example, for a normal sampling rate of 8 Ksps (i.e., FS = 8kHz) with IIR/FIR, if the IIR/FIR is bypassed, the frequency of FS is readjusted to 4×8 kHz = 32 kHz. The syncfilters of the two paths can not be bypassed. A maximum of four devices in cascade can be supported in theIIR/FIR bypass mode.
In this mode , the ADC channel outputs data which has been decimated only till 4 FS. Similarly DAC channelinput needs to be preinterpolated to 4 FS before being given to the device. This mode allows users the flexibilityto implement their own filter in DSP for decimation and interpolation. M should be a multiple of 4 during IIR/FIRbypass mode.
The TLV320AIC2x resets internal counters and registers in response to either of two events:•A low-going reset pulse is applied to terminal RESET•A 1 is written to the programmable software reset bits (D3 of control register 3A)
NOTE: The TLV320AIC2x requires a power-up reset applied to the RESET pin.
Either event resets the control registers and clears all sequential circuits in the device. The H/W RESET (activelow) signal is at least 6 master clock periods long. As soon as the RESET input is applied, the TLV320AIC2xenters the initialization cycle that lasts for 132 MCLKs, during which the serial port of the DSP must be 3-stated.The initialization sequence performed by the AIC2x is known as Auto Cascade Detection (ACD). ACD is amechanism that allows a device to know its address in a cascade chain. Up to 8 AIC2x devices can be cascadedtogether.
The Master device is the first device on the chain i.e. the FS of the Master is connected to the FS of the DSP.
During ACD, each device gets to know the number of devices in the chain as well as its relative position in thechain. This is done upon hardware reset. Therefore. after power up, a hardware reset must be completed. ACDrequires 132 MCLKs after reset to complete operation. The number of MCLKs is independent of the number ofdevices in the chain.
Adjacent devices in the chain have their FS and FSD pins connected to each other. The master device’s FS isconnected to the FS pin of the DSP. The FSD pin on the last device in the chain is pulled high for master-slaveconfiguration, and it is pulled low for stand-alone slave configuration.
The master device has the highest address i.e., the master device has address equal to total no of channels incascade minus 1. For example, if 8 devices are cascaded, then the master device has address 15 and 14followed by the next device which has 13 and 12 etc.
During the first 64 MCLKs, FS is configured as an output and FSD as an input.
During the next 64 MCLKs, FS is configured as an input and FSD as an output.
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Power Management
Smart Time Division Multiplexed Serial Port (SMARTDM)
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Functional Description (continued)The Master device always has its FS configured as an output and the last slave in the cascade (i.e. channel withaddress 0) always has its FSD configured as an input.
To calculate the channel address, during the first 64 MCLKs, the device counts the number of clocks betweenACD starting (reset) and the FSD going high.
During the next 64 MCLKs, the device counts the number of clocks till FS is pulled low.
The sum total of the counts in the first phase and the second phase is the number of devices in the channel.
For a cascaded system the rise time of H/W RESET must be less than the MCLK period and should satisfy setuptime requirement of 2 ns with respect to MCLK rise-edge. If more than one codec is cascaded together, RESETmust be synchronized to MCLK. Additionally all devices must see the same edge of MCLK within a window of 0.5ns. This requirement does not exist for a single master or slave. MCLK and RESET can be asynchronousevents.
Most of the device (all except the digital interface) enters the power-down mode when D5 and D4, in controlregister 3A, are set to 1. When the PWRDN pin is low, the entire device is powered down. In either case, registercontents are preserved and the output of the amplifier is held at midpoint voltage to minimize pops and clicks.
The amount of power drawn during software power down is higher than during a hardware power down becauseof the current required to keep the digital interface active. Additional differences between software and hardwarepower-down modes are detailed in the following paragraphs.
Software Power-Down
Data bits D5 and D4 of control register 3A are used by TLV320AIC2x to turn on or off the software power-downmode, which takes effect in the next frame FS. The ADC and DAC can be powered down individually. In thesoftware power-down, the digital interface circuit is still active while the internal ADC and DAC channel and alldifferential analog outputs are disabled, and DOUT is put in 3-state in the data frame only. Register data in thecontrol frame is still accepted via DIN, but data in the data frame is ignored. The device returns to normaloperation when D7 and D6 of control register 3A are reset.
If the PLL is enabled (i.e., P is not set to 8), then executing a software power down and power up of the devicecauses the output drivers to go to the common-mode voltage. Therefore, before executing a software powerdown, the PLL must first be disabled (i.e., P should first be set to 8) before control register 3A is programmed.While bringing the codec out of software power down, the PLL should be re-enabled only after the codec isbrought out of power down (i.e., register 3A must be programmed first followed by register 4).
Hardware Power-Down
The TLV320AIC2x requires the PWRDN signal to be synchronized with MCLK. When PWRDN is held low, thedevice enters hardware power-down mode. In this state, the internal clock control circuit and the differentialoutputs are disabled. All other digital I/Os are disabled and DIN can not accept any data input. The device canonly be returned to normal operation by holding PWRDN high. When not holding the device in the hardwarepower-down mode, PWRDN must be tied high.
The SMART time division multiplexed serial port (SMARTDM) uses the four wires of DOUT, DIN, SCLK, and FSto transfer data into and out of the AIC2x. The TLV320AIC2xs SMARTDM supports three serial interfaceconfigurations (see Table 1 ): stand-alone master, stand-alone slave, and master-slave cascade, employing atime division multiplexed (TDM) scheme (a cascade of only-slaves is not supported). The SMARTDM allows for aserial connection of up to 8 stereo codecs to a single serial port. Data communication in the three serial interfaceconfigurations can be carried out in either standard operation (Default) or turbo operation. Each operation hastwo modes: programming mode (default mode) and continuous data transfer mode. To switch from theprogramming mode to the continuous data transfer mode, set bit D6 of control register 1 to 1, which is resetautomatically after switching back to programming mode. The TLV320AIC2x can be switched back from thecontinuous data transfer mode to the programming mode by setting the LSB of the data on DIN to 1, only if thedata format is (15+1), as selected by bit 0 of control register 1. The SMARTDM automatically adjusts the number
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Clock Source (MCLK, SCLK)
Serial Data Out (DOUT)
Serial Data In (DIN)
Frame-Sync FS
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Functional Description (continued)of time slots per frame sync (FS) to match the number of codecs in the serial interface so that no time slot iswasted. Both the programming mode and the continuous data transfer mode of the TLV320AIC2x are compatiblewith the TLV320AIC12. The TLV320AIC2x provides primary/secondary communication and continuous datatransfer with improvements and eliminates the requirements for hardware and software requests for secondarycommunication as seen in the TLV320AIC10. The TLV320AIC2x continuous data transfer mode now supportsboth master/slave stand-alone and cascade.
Table 1. Serial Interface Configurations
M/S PIN FSD PINTLV320AIC2x CONNECTIONS COMMENTSMASTER SLAVE MASTER SLAVE
Stand-alone High Low Pull high LowConnect to the next slave's FSMaster-slave cascade High Low Last slave's FSD pin is pulled high(see Figure 23 )Slave-slave cascade NA NA NA NA Not supported
MCLK is the external master clock input. The clock circuit generates and distributes necessary clocks throughoutthe device. SCLK is the bit clock used to receive and transmit data synchronously. When the device is in themaster mode, SCLK and FS are output and derived from MCLK in order to provide clocking the serialcommunications between the device and a digital signal processor (DSP). When in the slave mode, SCLK andFS are inputs. SCLK is controlled by TURBO bit (D7) in control register 2. In the standard operation (non-turbo,TURBO = 0), SCLK frequency is defined by:•SCLK = (16 × FS × #Devices × mode)
Where:
•FS is the frame-sync frequency. #Device is the number of the codec channels in cascade. (#Device = 2 forstand-alone AIC2x) Mode is equal to 1 for continuous data transfer mode and 2 for programming mode.
DOUT is placed in the high-impedance state after transmission of the LSB is completed. In data frame, the dataword is the ADC conversion result. In the control frame, the data is the register read results when requested bythe read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are allzeroes. Valid data on DOUT is taken from the high-impedance state by the falling edge of frame-sync (FS). Thefirst bit transmitted on the falling edge of FS is the MSB of valid data.
The data format of DIN is the same as that of DOUT, in which MSB is received first on the falling edge of firstSCLK after FS. In a data frame, the data word is the input digital signal to the DAC channel. If (15+1)-bit dataformat is used, the LSB (D0) of every DAC channel is set to 1 to switch from the continuous data transfer modeto the programming mode. In a control frame, the data is the control and configuration data that sets the devicefor a particular function as described in Section 3.9, Control Register Programming.
The frame-sync signal (FS) indicates the device is ready to send and receive data. FS is an output if the M/S pinis connected to HI (master mode) and an input if the M/S pin is connected to LO (slave mode).
Data is valid on the falling edge of the FS signal.
The frequency of FS is defined as the sampling rate of the TLV320AIC2x and derived from the master clockMCLK as followed (see Section 3.1 Operating Frequencies for details):•FS = MCLK / (16 × P × N × M)
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DIN/DOUT
(16 Bit)
MSB LSB
D15 D14 D15 D14
0 1 30 3129
D1
FS
32 SCLKs
D1 D0
MSB LSB
D0
Master (CH 1) Slave (CH 2)
SCLK
(Output)
Cascade Mode and Frame-Sync Delayed (FSD)
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Figure 19. Timing Diagram for FS in the Continuous Transfer Mode
In cascade mode, the DSP should be in slave mode, i.e., it receives all frame-sync pulses from the masterthough the master's FS. The master's FSD is output to the first slave and the first slave's FSD is output to thesecond slave device and so on. Figure 20 shows the cascade of four TLV320AIC2xs in which the closest one toDSP is the master and the rest are slaves. The FSD output of each device is input to the FS terminal of thesucceeding device. Figure 21 shows the FSD timing sequence in the cascade.
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MCLK
DIN
DOUT
M/SFSD
TLV320AIC20
1
FS
SCLK
3.3 V
MCLK
DIN
DOUT
M/SFSD
TLV320AIC20
2
FS
SCLK
MCLK
DIN
DOUT
M/SFSD
TLV320AIC20
3
FS
SCLK
MCLK
DIN
DOUT
M/SFSD
TLV320AIC20
4
FS
SCLK
IOVDD
CLKOUT
DR
DX
FSX
FSR
CLKX
CLKR
TMS320C5X
TMS320C6X
To CLKOUT
or External Oscillator
Stand-Alone Slave
Asynchronous Sampling (Codecs in cascade are sampled at different sampling frequency)
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Figure 20. Cascade Connection (to DSP Interface)
In the stand-alone slave connection, the FS and SCLK inputs must be synchronized to each other andprogrammed according to Section 3.1 (Operating Frequencies). The FS and SCLK input are not required tosynchronize to the MCLK input but must remain active at all times to assure continuous sampling in the dataconverter. FSD must be connected to LOW for stand-alone-slave. FS is output for initial 132 MCLK and it is keptlow. The host processor needs to keep the FS pin in high impedence state during this period to avoid contention.
The AIC2x SMARTDM supports different sampling frequencies between the different channels in cascade,connecting to a single serial port in which all codecs are sampled at the same frequency of FS.For example: FS1 and FS2 are the desired sampling rates for CH1 and CH2 respectively:1. FS = MCLK / (16 x M x N x P)2. FS = n1 x FS1 (n1 = 1, 2, . . ., 8 defined in the control register 3A of CH1)3. FS = n2 x FS2 (n2 = 1, 2, . . ., 8 defined in the control register 3A of CH2)
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DIN/DOUT
(16 Bit)
MSB LSB
D15 D14 D15 D14
0 1 30 3129
D1
FS
32 SCLKs
D1 D0
MSB LSB
D0
Master (CH 1) Slave (CH 2)
SCLK
(Output)
FSD
Master
Master FS
DIN/DOUT
AIC20-1 FSD,
AIC20-2 FS
Slave0 Slave6 Slave4 Slave2 Slave0Slave5 Slave3 Slave1 Slave6 Slave4Slave5Master
AIC20-1 AIC20-2 AIC20-3 AIC20-4
16 Bits
AIC20-2 FSD,
AIC20-3 FS
AIC20-3 FSD,
AIC20-4 FS
Programming Mode
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
For validating the conversion data from this operation:•For DAC: The DSP needs to give the same data for n1 samples. CH1 picks one of the n1 samples.•For ADC: CH1 gives the same data for the n1 samples. DSP should pick one of the n1 samples.
Figure 21. Timing Diagram for FSD Output
Figure 22. NOTE: AIC2x #4 FSD should be pulled high.
In the programming mode, the FS signal starts the input/output data stream. Each period of FS contains twoframes as shown in Figures 3-10 and 3-11: data frame and control frame. The data frame contains datatransmitted from the ADC or to the DAC. The control frame contains data to program each codec control register.The SMARTDM automatically sets the number of time slots per frame equal to the number of codec channels inthe interface. Each time slot contains 16-bit data. The SCLK is used to perform data transfer for the serialinterface between the AIC2x codecs and the DSP. The frequency of SCLK varies, depending on the selectedmode of serial interface. In the stand alone-mode, there are 64 SCLKs (or four time slots) per sampling period. Inthe master-slave cascade mode, the number of SLCKs equals 32x(number of codec channels in the cascade).The digital output data from the ADC is taken from DOUT. The digital input data for the DAC is applied to DIN.The synchronization clock for the serial communication data and the frame-sync is taken from SCLK. Theframe-sync signal that starts the ADC and DAC data transfer interval is taken from FS. The SMARTDM alsoprovides a turbo operation, in which the FS's frequency is always the device's sampling frequency, but SCLK isrunning at a much higher speed. Thus, there are more than 64 SCLKs for each AIC2x per sampling period, inwhich the data frame and control frame occupy only the first 64 SCLKs from the falling edge of the frame-syncFS.
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SCLK
FS
DIN
DOUT
64 SCLKS
Data Frame Control Frame
Slot 0
CH1 16-Bit DAC
Slot 2
CH1 Register Data
CH1 Register Data CH2 Register Data
Slot 3
CH2 Register Data
Slot 1
CH2 16-Bit DAC
CH1 16-Bit ADC CH2 16-Bit ADC
SCLK
FS
DIN/
DOUT
0 1 2 2n-12n-22n-3
Master Slave
n-1 Slave
n-2 Slave
3Slave
2Slave
1Master Slave
n-1 Slave
n-2 Slave
3Slave
2Slave
1
Data Frame Control Frame
(Register R/W)
16 SCLKs Per Slot
Slot
Number
NOTE: n/2 is the total number of AIC20s in the cascade
Continuous Data Transfer Mode
SCLK
32 SCLKS
Data Frame
Slot 0
CH1 16-Bit DAC
CH1 16-Bit ADC CH1 16-Bit ADCCH2 16-Bit ADC CH2 16-Bit ADC
Slot 0
CH1 16-Bit DAC
Slot 1
CH2 16-Bit DAC
Slot 1
CH2 16-Bit DAC
Data Frame
FS
DIN
DOUT
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Figure 23. Programming Mode: Stand-Alone Timing
Figure 24. Standard Operation/Programming Mode: Master-Slave Cascade Timing
The continuous data transfer mode, selected by setting bit D6 of each codec's control register 1 to 1, containsconversion data only. In continuous data transfer mode, the control frame is eliminated, and the period of FSsignal contains only the data frame in which the 16-bit data is transferred contiguously, with no inactivity betweenbits. The control frame can be reactivated by setting the LSB of DIN data to 1 if the data is in the 15+1 format. Toreturn the programming mode in the 16-bit DAC data format mode, write 0 in bit D6 of each codec's controlregister 1 using I
2
C or S
2
C, or do a hardware reset to come out of continuous data transfer mode. If continuousdata transfer mode needs to be used with turbo mode, then the codec should first be set in turbo mode before itis switched from the default programming mode to the continuous data transfer mode.
Figure 25. Standard Operation/Continuous Data Transfer Mode: Stand-Alone Timing
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SCLK
FS
DIN/
DOUT
0 1 2 n-1n-2n-3 0 1 2 n-1n-2n-3
Master Slave
n-1 Slave
n-2 Slave
3Slave
2Slave
1Master Slave
n-1 Slave
n-2 Slave
3Slave
2Slave
1
Data Frame / Sample 1
NOTE: n/2 is the total number of AIC20s in the cascade
16 SCLKs Per Time Slot
Data Frame / Sample 2
Slot
Number
Turbo Operation (SCLK)
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Figure 26. Standard Operation/Continuous Data Transfer Mode: Master-Slave Cascade Timing
Setting TURBO = 1 (bit D7) in each codec's control register 2 enables the AIC2x's turbo mode that requires thefollowing condition to be met:•M × N > #Devices × mode
Where:
•M, N, and P are clock divider values defined in the control register 4. #Device is the number of codecchannels in cascade. ( Number of Device = 2 for stand-alone AIC2x) Mode is equal to 1 for continuous datatransfer mode and 2 for programming mode.
The turbo operation is useful for applications that require more bandwidth for multitasking processing persampling period. In the turbo mode (see Figure 27 ), the FS frequency is always the device's sampling frequency,but the SCLK is running at much higher speed. The output SCLK frequency is equal to (MCLK/P) and up to amaximum speed of 25 MHz. The data/control frame is still 32-SCLK long and the FS is one-SCLK pulse. If theAIC2x is in slave mode and the device is not set to turbo mode, only the first FS is used to synchronize the datatransfer. The AIC2x ignores all subsequent FS signals and utilizes an internally generated FS. However, if theAIC2x is set to turbo mode while in slave mode, then the data transfer synchronizes on every FS signal.Therefore, it is recommended that if the AIC2x is set to slave mode, then the turbo mode is used. Also note thatin turbo mode, it is recommended that SCLK should be a multiple of 32 x FS.
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Stand-Alone Case:
... ...
15 14 1 0 1415 1 0
One SCLK
Data Frame
Hi-Z
FS
DIN / DOUT
Data Frame
Stand-Alone Case:
Cascade Case (Master + 4 Slaves):
Turbo SCLK
FS
DIN / DOUT
Sampling Period
Data Frame
Hi-Z
Data Frame
TURBO PROGRAMMING MODE
TURBO CONTINUOUS DATA TRANSFER MODE
Sampling Period
Hi-Z
Hi-Z
Data Frame
ADC/DAC Data Control Frame
Register Data
Hi-Z
Turbo SCLK
FS
DIN / DOUT Master
(CH 1) Master
Slave
(CH 2) Master
(CH 1) Slave
(CH 2)
Sampling Period
Cascade Case (Master + 4 Slaves):
Turbo SCLK
FS
DIN / DOUT
Sampling Period
Data Frame Hi-Z Data Frame
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
NOTE: SCLK is not drawn to scale.
Turbo SCLK
Control Frame Control Frame
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Figure 27. Timing Diagram for Turbo Operation
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Control Register Programming
Data Frame Format
D0
D15 - D1
A/D and D/A Data
D15 - D0
D15 - D0
A/D and D/A Data
D15 - D0
DIN
(15+1) Bit Mode
(Continuous Data Transfer Mode Only)
DOUT
(16 Bit A/D Data)
DIN
16 Bit Mode
DOUT
16 Bit Mode
Control Frame
Request
Control Frame Format (Programming Mode)
Broadcast Register Write
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Each channel in the TLV320AIC2x contains six control registers that are used to program available modes ofoperation. All register programming occurs during the control frame through DIN. New configuration takes effectafter a delay of one frame sync. The TLV320AIC2x is defaulted to the programming mode upon power up. Set bit6 in control register 1 to switch to continuous data transfer mode. If the 15+1 data format of DIN has beenselected, the LSB of the DIN to 1 to switch from continuous data transfer mode to programming set mode.Otherwise, either the device needs to be reset or the host port writes 0 to bit D6 of each codec's control register1 during the continuous data transfer mode to switch back to the programming mode. The control registers arereplicated for each channel in the AIC2x, and these need to be programmed separately for the individualchannels. Register bits that control resources that are common to both channels are shadowed (i.e., writing tothe appropriate register bit of one channel is automatically reflected in the register bits for the other channel).See the control register tables for a more detailed description of the exact register bits that are shadowed.
Figure 28. Data Frame Format
During the control frame, the DSP sends 16-bit words to each codec's time slot SMARTDM(TM) through DIN toread or write control registers in each codec shown in Table 4 . The upper byte (Bits D15-D8) of the 16-bitcontrol-frame word defines the read/write command. Bits D15-D13 define the control register address withregister content occupied the lower byte D7-D0. Bit D12 is set to 0 for a write or to 1 for a read. Bit D11 in thewrite command is used to perform the broadcast mode. During a register write, the register content is located inthe lower byte of DIN. During a register read, the register content is output in the lower byte of DOUT in thesame control frame, whereas the lower byte of DIN is ignored.
Broadcast operation is very useful for a cascading system of SMARTDM codecs in which all registerprogramming can be completed in one control frame. During the control frame and in any register-write time slot,if the broadcast bit (D11) is set to 1, the register content of that time slot is written into the specified register of alldevices in cascade (see Figure 29 ). This reduces the DSP's overhead of doing multiple writes to program thesame data into cascaded devices.
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111D110
111
X
1DIN (Read)
DIN (Write)
Don’t care
D15
D15 D13D14
D13D14
0D9D10D11DOUT (Read) D15 D13D14 D12
Data to be Written Into Register
D7 - D0
D7 - D0
D7 - D0
R/W Broadcast
Register
Address
Register
Address
SMARTDM Device
Address Register Content
Master FS
DIN Master Slave2 Slave1 Slave0 Master Slave2 Slave1 Slave0 Master Slave2 Slave1 Slave0Slave0
Write
Command
Reg Addr (D15-D13)
R/W (D12)
Broadcast (D11)
D10-D8
001
0
1
111
010
0
1
111
100
0
1
111
110
0
1
111
Data Frame Control Frame
Time Slot
AIC20 #1 AIC20 #2 AIC20 #1 AIC20 #2
Data Frame
Host Port Interface
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Figure 29. Control Frame Data Format
A. NOTE: In this example, the broadcast operation (D11 = 1) is used to program the four control registers of Reg.1,Reg.2, Reg.4, and Reg.6 in all four DSP codecs of two TLV320AIC2xs in cascade (Master, Slave2, Slave1, andSlave0) during the same frame (i.e., register 1 of the four codecs contains the same data).
The host port uses a 2-wire serial interface (SCL, SDA) to program channel six of each of the codec controlregisters, and selectable protocol between S
2
C mode and I
2
C mode. The S
2
C is a write-only mode, and the I
2
Cis a read-write mode selected by bits D1-D0 (HPC bits) of control register 2. If the host interface is not needed,the two pins of SCL and SDA can be programmed to become general-purpose I/Os. If selected to be used as I/Opins, the SDA and SCL pins become output and input pins respectively, determined by D1 and D0.
Both S
2
C and I
2
C require a SMARTDM device address to communicate with the AIC2x. One of SMARTDM'sadvanced features is the automatic cascade detection (ACD) that enables SMARTDM to automatically detect thetotal number of codecs in the serial connection and use this information to assign each codec a distinctSMARTDM device address. Table 2 lists device addresses assigned to each codec in the cascade by theSMARTDM. The master always has the highest position in the cascade. For example in Figure 20 , there is atotal of 4 codecs in the cascade (i.e., one master and 3 slaves), then the device addresses in row 4 are used inwhich the master is codec 1 with a device address of 0000.
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D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SCL
SDA
Start Bit = 0 Stop Bit = 1
SMARTDM Device
Address
(see Table 3-1)
Register
Address Register Content
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Table 2. SMARTDM Device Addresses
TOTAL CHANNELS POSITION IN CASCADE (1 CODEC HAS 2 CHANNELS)CHAN-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0NELS
1 00002 0001 00003 0010 0001 00004 0011 0010 0001 00005 0100 0011 0010 0001 00006 0101 0100 0011 0010 0001 00007 0110 0101 0100 0011 0010 0001 00008 0111 0110 0101 0100 0011 0010 0001 00009 1000 0111 0110 0101 0100 0011 0010 0001 000010 1001 1000 0111 0110 0101 0100 0011 0010 0001 000011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 000012 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 000013 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 000014 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 000015 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 000016 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
S
2
C (Start-Stop Communication)
The S
2
C is a write-only interface selected by programming bits D1-D0 of control register 2 to 01. The SDA inputis normally in a high state, pulled low (START bit) to start the communication, and pulled high (STOP bit) afterthe transmission of the LSB. Figure 30 shows the timing diagram of S
2
C. The S
2
C also supports a broadcastmode in which the same register of all devices in cascade is programmed in a single write. To use S
2
C'sbroadcast mode, execute the following steps:1. Write 111 1000 1111 1111 after the start bit to enable the broadcast mode.2. Write data to program control register as specified in Figure 30 with bits D14-D11 = XXXX (don't care).3. Write 111 1000 0000 0000 after the start bit to disable the broadcast mode.
Figure 30. S
2
C Programming
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I2C Write Sequence
SCL
SDA A5 A4 A3 A2 A1 A0 0 ACK B7 B6 B5 B4 B3 R2 R1 R0
I2C
6
A6
I2C
5I2C
4
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
ACK ACK ACK
Programmable 12C Device Address
Set by Control Register 2
Start Bit = 0 SMARTDM Device
Address
(see Table 3-1) 00000 = Default
11111 = Broadcast Mode
Index Register Address
(Index) Control Register Data for Write
(Index)
Control Register Data for Write
(Index+1)
SCL
SDA A5 A4 A3 A2 A1 A0 0ACK B7 B6 B5 B4 B3 R2 R1 R0
I2C
6
A6 ACK
I2C
5
I2C
4
SCL
SDA A5 A4 A3 A2 A1 A0 1ACK D7 D6 D5 D4 D3 D2 D1 D0
I2C
6
A6
I2C
5
I2C
4
D7 D6 D5 D4 D3 D2 D1 D0
ACK ACK
Start Bit = 0
Programmable 1 C Device Address
2
Set by Control Register 2
SMARTDM Device Address
(see Table 1)
Index Register Address
(Index)
Stop Bit = 1
xxxxx = Don't Care
Start Bit = 0
Programmable 1 C Device Address
2
Set by Control Register 2
SMARTDM Device Address
(see Table 1)
Control Register Data
(Index)
Control Register Data
(Index+1)
I C Read Sequence
2
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
I
2
C•Each I
2
C read-from or write-to each codec control register is given by an index register address.•Read/write sequence always starts with the first byte as I
2
C address followed by 0. During the second byte,default/broadcast mode is set and the index register address is initialized. For write operation control register,data to be written is given from the third byte onwards. For read operation, stop-start is performed after thesecond byte. Now the first byte is I
2
C address followed by 1. From the second byte onwards, control registerdata appears.•Each time read/write is performed, the index register address is incrimented so that the next read/write isperformed on the next control register.•During the first write cycle and all write cycles in the broadcast, only the device with address 0000 issuesACK to the I
2
C.•Similarly, for a register with multiple sub-registers the sub-register index automatically increments with eachread/write. For example, the first read/write to register 3 read/writes to register 3A, the next to register 3Band so forth until the last sub-register is reached. At this time the sub-register index wraps back around tothe first sub-register
Figure 31. I
2
C Write Sequence
Figure 32. I
2
C Read Sequence
Each codec has an index register address. To perform a write operation, make the LSB of the first byte as 0(write) (see Figure 33 ). During the second byte, the index register address is initialized and mode(broadcast/default) is set. From the third byte onwards, write data to the control register (given by index register)and increment the index register until stop or repeated start occurs. For operation, make the LSB of the first byteas 1 (read). From the second byte onwards, AIC starts transmitting data from the control register (given by theindex register) and increments the index register. For setting the index register perform operation the same aswrite case for 2 bytes, and then give a stop or repeated start.
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S/Sr I2C Device Address (3 Bit)+
SMARTDM Device Address +
R/W
= 0
Mode (5 Bit) + Index
Register Address
(3 Bit)
Ack Ack Control Register
Data (Write) Ack Control Register
Data (Write)
7 Bit 1 Bit 8 Bit 8 Bit 8 Bit
Increment Index Register Address
Default/Broadcast
(00000/11111)
Write Mode
To the Address Given
by Index Register
Address
To the Address Given
by Index Register
Address
S/Sr I2C Device Address (3 Bit)+
SMARTDM Device Address +
R/W
= 1
Control Register Data
(Read)
Ack Ack Control Register
Data (Read) Ack
7 Bit 1 Bit 8 Bit 8 Bit
Read Mode
From the Address Given
by Index Register Address
From the Address Given
by Index Register Address
Increment Index
Register Address
Increment Index
Register Address
S/Sr I2C Device Address (3 Bit)+
SMARTDM Device Address +
R/W
= 0
Mode (5 Bit) + Index
Register Address
(3 Bit)
Ack Ack
7 Bit 1 Bit 8 Bit
For Initializing Index Register Address Stop
Register Map
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
•S/Sr -> Start/Repeated Start.
Figure 33. Index Register Addresses
Each AIC2x codec consists of 2 channels. Each channel has 6 registers to enable the user to control variouscomponents. Registers that control resources that are common across the two channels are shadowed. Thismeans that writing to the appropriate register in one channel automatically updates the contents of the sameregister in the other channel to reflect the change. For example, writing to register 4 in channel 1 automaticallyupdates the contents of register 4 for channel 2 and vice versa. Refer to the individual register description for amore detailed description of the exact register bits that are shadowed. Bits D15 through D13 represent thecontrol register address that is written with data carried in D7 through D0. Bit D12 determines a read or a writecycle to the addressed register. When D12 = 0, a write cycle is selected. When D12 = 1, a read cycle is selected.Bit D11 controls the broadcast mode as described above, in which the broadcast mode is enabled if D11 is set to1. Always write 1s to the bits D10 through D8.
Table 3 shows the register map.
Table 3. Register Map
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register Address RW BC 1 1 1 Control Register Content
Table 4. Register Addressing
REGISTER NO. D15 D14 D13 REGISTER NAME
0 0 0 0 No operation1 0 0 1 Control 12 0 1 0 Control 23 0 1 1 Control 34 1 0 0 Control 45 1 0 1 Control 56 1 1 0 Control 6
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Control Register Content Description
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Control Register 1
(1)
D7 D6 D5 D4 D3 D2 D1 D0ADOVF CX IIR DAOVF BIASV ALB DLB DAC16R R/W/S R/W R R/W/S R/W R/W R/W/S
(1) NOTE: R = Read, W = Write, S = Shadowed
Control Register 1 Bit Summary
RESETBIT NAME FUNCTIONVALUE
ADC over flow. This bit indicates whether the ADC is overflow.D7 ADOVF 0 ADOVF = 0 No overflowADOVF = 1 A/D is overflow.Continuous data transfer mode. This bit selects between programming mode and continuous data transfermode.D6 CX 0
CX = 0 Programming modeCX = 1 Continuous data transfer modeIIR Filter. This bit selects between FIR and IIR for decimation/interpolation low-pass filter.D5 IIR 0 IIR = 0 FIR filter is selectedIIR = 1 IIR filter is selected.DAC over flow. This bit indicates whether the DAC is overflowD4 DAOVF 0 DAOVF = 0 No overflowDAOVF = 1 DAC is overflowBias voltage. This bit selects the output voltage for BIAS pinBIASV = 0D3 BIASV 0 BIAS pin = 1.35 VBIASV = 1BIAS pin = 2.35 VAnalog loop backD2 ALB 0 ALB = 0 Analog loopback disabledALB = 1 Analog loopback enabledDigital loop backD1 DLB 0 DLB = 0 Digital loopback disabledDLB = 1 Digital loopback enabledDAC 16-bit data format. This bit applies to the continuous data transfer mode only to enable the 16-bit dataformat for DAC input.DAC16 = 0 DAC input data length is 15 bits. Writing a 1 to the LSB of the DAC input toD0 DAC16 0
switch from continuous data transfer mode to programming mode.DAC16 = 1 DAC input data length is 16 bit.
Control Register 2
(1)
D7 D6 D5 D4 D3 D2 D1 D0TURBO DIFBP I
2
C6 I
2
C5 I
2
C4 GPO HPCR/W/S R/W/S R/W/S R/W/S R/W/S R/W/S R/W/S R/W/S
(1) NOTE: R = Read, W = Write, S = Shadowed
Control Register 2 Bit Summary
RESETBIT NAME FUNCTIONVALUE
Turbo mode. This bit is used to set the SCLK rate.D7 TURBO 0 TURBO = 0 SCLK = (16 × FS × number of device × mode)TURBO = 1 SCLK = MCLK/P (P is determined in register 4)Decimation/interpolation filter bypass. This bit is used to bypass both decimation and interpolation filters.D6 DIFBP 0 DIFBP = 0 Decimation/interpolation filters are operated.DIFBP = 1 Decimation/interpolation filters are bypassed.I
2
C device address. These three bits are programmable to define three MSBs of the I
2
C device addressD5-D3 I
2
Cx 100 (reset value is 100). These three bits are combined with the 4-bit SMARTDM device address to form 7-bitI
2
C device address.
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TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Control Register 2 Bit Summary (continued)
RESETBIT NAME FUNCTIONVALUE
D2 GPO 0 General-purpose outputHost port control bits. Write the following values into D1-D0 to select the appropriate configuration for twopins SDA and SCL. The SDA and SCL pins are used for I
2
C interface if D1-D0 = 00. The SDA and SCL pinsD1-D0 HPC 00
are used for S
2
C interface if D1-D0 = 01. If D1-D0 = 10, the SDA pin = D2, input going into the SCL pin isoutput to DOUT (11), the SDA pin = control frame flag.
Control Register 3A
(1)
D7 D6 D5 D4 D3 D2 D1 D000 PWDN SWRS ASRFR/W R/W R/W/S R/W
(1) NOTE: R = Read, W = Write
Control Register 3A Bit Summary
RESETBIT NAME FUNCTIONVALUE
Power down PWDN = 00No power down PWDN = 01D5-D4 PWDN 00 Power-down A/DPWDN = 10Power-down D/APWDN = 11Software power down the entire deviceD3 SWRS 0 Software reset. Set this bit to 1 to reset the device.Asynchronous sampling rate factor. These three bits define the ratio n between FS frequency and thedesired sampling frequency fs (Applied only if different sampling rate between CODEC1 and CODEC2 isdesired)
ASRF = 001, n = FS/fs = 1ASRF = 010, n = FS/fs = 2D2-D0 ASRF 001 ASRF = 011, n = FS/fs = 3ASRF = 100, n = FS/fs = 4ASRF = 101, n = FS/fs = 5ASRF = 110, n = FS/fs = 6ASRF = 111, n = FS/fs = 7ASRF = 000, n = FS/fs = 8
Control Register 3B
(1)
D7 D6 D5 D4 D3 D2 D1 D001 8KBF Reserved MHNS MHDS MLDO MSPKR/W R/W R/W/S
(1) NOTE: R = Read, W = Write
Control Register 3B Bit Summary
RESETBIT NAME FUNCTIONVALUE
8 kHz band pass filter. Set this bit to 1 to enable the band-bass filter [300 Hz -3.3 kHz] with the samplingD5 8KBF 0
rate at 8 kHz.D4 Reserved 0
Mute handset. This bit controls the MUTE function of handset output driver.D3 MHNS 0 MHNS = 0 Handset output driver is not MUTE.MHNS = 1 Handset output driver is MUTE.Mute headset. This bit controls the MUTE function of headset output driver.D2 MHDS 0 MHDS = 0 Headset output driver is not MUTE.MHDS = 1 Headset output driver is MUTE.Mute line output. This bit controls the MUTE function of the 600- Ωoutput driver.D1 MLNO 0 MLNO = 0 The 600- Ωoutput driver is not MUTE.MLNO = 1 The 600- Ωoutput driver is MUTE.Mute 8- Ωspeaker. This bit controls the MUTE function of the 8- Ωspeaker driver.D0 MSPK 0 MSPK = 0 The 8- Ωspeaker driver is not MUTE.MSPK = 1 The 8- Ωspeaker driver is MUTE.
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TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Control Register 3C
(1)
D7 D6 D5 D4 D3 D2 D1 D010 Reserved ICID OSRR/W R/W/S R/W
(1) NOTE: R = Read, W = Write, S = Shadowed
Control Register 3C Bit Summary
RESETBIT NAME FUNCTIONVALUE
D5 Reserved 0
Chip ID. These two bits represent the device version number.ICID = 000 Version 1ICID = 001 Version 2ICID = 010 Version 3D4-D2 ICID 000 ICID = 011 Version 4ICID = 100 Version 5ICID = 101 Version 6ICID = 110 Version 7ICID = 111 Version 8OSR option D1-D0 = X1 OSR for DAC Channel is 512 (Max FS = 8 Ksps)D1-D0 OSR option 00 D1-D0 = 10 OSR for DAC Channel is 256 (Max FS = 16 Ksps)D1-D0 = 00 OSR for DAC Channel is 128 (Max FS = 26 Ksps)
Control Register 3D
(1)
D7 D6 D5 D4 D3 D2 D1 D011 LCDACR/W R/W/S
(1) NOTE: R = Read, W = Write, S = Shadowed
Control Register 3D Bit Summary
RESETBIT NAME FUNCTIONVALUE
D5-D0 LCDAC
(1)
000000 LCD DAC. These bits represent the input value for the 6-bit LCD DAC.
(1) NOTE: See the Electrical Characteristics table for LCD DAC specification.
Control Register 4
(1)
D7 D6 D5 D4 D3 D2 D1 D0FSDIV MNPR/W R/W/S R/W/S R/W/S R/W/S R/W/S R/W/S R/W/S
(1) NOTE: R = Read, W = Write, S = Shadowed
Control Register 4 Bit Summary
RESETBIT NAME FUNCTIONVALUE
Frame sync division factor FSDIV = 0D7 FSDIV 0 To write value of P to bits D2-D0 and value of N to bits D6-D3 FSDIV = 1To write value of M to bits D6-D0
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TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Control Register 4 Bit Summary (continued)
RESETBIT NAME FUNCTIONVALUE
Divider values of M, N, and P to be used in junction with the FSDIV bit for calculation of FS frequencyaccording to the formula: FS = MCLK / (16 x M x N x P) where: M = 1, 2, .., 128Determined by D6-D0 with FSDIV = 1D7-D0 = 10000000 M = 128D7-D0 = 10000001 M = 1D7-D0 = 11111111 M = 127N = 1, 2,.., 16Determined by D6-D3 with FSDIV = 0, D6-D0 M, N, PD6-D0 MNP —
D7-D0 = 00000xxx N = 16D7-D0 = 00001xxx N = 1D7-D0 = 01111xxx N = 15P = 1, 2,.., 8Determined by D2-D0 with FSDIV = 0D7-D0 = 0xxxx000 P = 8D7-D0 = 0xxxx001 P = 1D7-D0 = 0xxxx111 P = 7
Control Register 5A
(1)
D7 D6 D5 D4 D3 D2 D1 D00 0 ADPGAR/W R/W R/W R/W R/W R/W R/W R/W
(1) NOTE: R = Read, W = Write
Table 5. A/D PGA Gain
D5 D4 D3 D2 D1 D0 ADPGA
0 1 1 1 1 1 ADC input PGA gain = MUTE0 1 1 1 1 0 ADC input PGA gain = 54 dB0 1 1 1 0 1 ADC input PGA gain = 48 dB0 1 1 1 0 0 ADC input PGA gain = 42 dB0 1 1 0 1 1 ADC input PGA gain = 40.5 dB0 1 1 0 1 0 ADC input PGA gain = 39 dB0 1 1 0 0 1 ADC input PGA gain = 37.5 dB0 1 1 0 0 0 ADC input PGA gain = 36 dB0 1 0 1 1 1 ADC input PGA gain = 34.5 dB0 1 0 1 1 0 ADC input PGA gain = 33 dB0 1 0 1 0 1 ADC input PGA gain = 31.5 dB0 1 0 1 0 0 ADC input PGA gain = 30 dB0 1 0 0 1 1 ADC input PGA gain = 28.5 dB0 1 0 0 1 0 ADC input PGA gain = 27 dB0 1 0 0 0 1 ADC input PGA gain = 25.5 dB0 1 0 0 0 0 ADC input PGA gain = 24 dB0 0 1 1 1 1 ADC input PGA gain = 22.5 dB0 0 1 1 1 0 ADC input PGA gain = 21 dB0 0 1 1 0 1 ADC input PGA gain = 19.5 dB0 0 1 1 0 0 ADC input PGA gain = 18 dB0 0 1 0 1 1 ADC input PGA gain = 16.5 dB0 0 1 0 1 0 ADC input PGA gain = 15 dB0 0 1 0 0 1 ADC input PGA gain = 13.5 dB0 0 1 0 0 0 ADC input PGA gain = 12 dB0 0 0 1 1 1 ADC input PGA gain = 10.5 dB0 0 0 1 1 0 ADC input PGA gain = 9 dB0 0 0 1 0 1 ADC input PGA gain = 7.5 dB
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TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Table 5. A/D PGA Gain (continued)
D5 D4 D3 D2 D1 D0 ADPGA
0 0 0 1 0 0 ADC input PGA gain = 6 dB0 0 0 0 1 1 ADC input PGA gain = 4.5 dB0 0 0 0 1 0 ADC input PGA gain = 3 dB0 0 0 0 0 1 ADC input PGA gain = 1.5 dB0 0 0 0 0 0 ADC input PGA gain = 0 dB
Control Register 5B
(1)
D7 D6 D5 D4 D3 D2 D1 D00 1 DAPGAR/W R/W R/W R/W R/W R/W R/W R/W
(1) NOTE: R = Read, W = Write
D/A PGA Gain
D5 D4 D3 D2 D1 D0 DAPGA
0 1 1 1 1 1 DAC input PGA gain = MUTE0 1 1 1 1 0 DAC input PGA gain = -54 dB0 1 1 1 0 1 DAC input PGA gain = -48 dB0 1 1 1 0 0 DAC input PGA gain = -42 dB0 1 1 0 1 1 DAC input PGA gain = -40.5 dB0 1 1 0 1 0 DAC input PGA gain = -39 dB0 1 1 0 0 1 DAC input PGA gain = -37.5 dB0 1 1 0 0 0 DAC input PGA gain = -36 dB0 1 0 1 1 1 DAC input PGA gain = -34.5 dB0 1 0 1 1 0 DAC input PGA gain = -33 dB0 1 0 1 0 1 DAC input PGA gain = -31.5 dB0 1 0 1 0 0 DAC input PGA gain = -30 dB0 1 0 0 1 1 DAC input PGA gain = -28.5 dB0 1 0 0 1 0 DAC input PGA gain = -27 dB0 1 0 0 0 1 DAC input PGA gain = -25.5 dB0 1 0 0 0 0 DAC input PGA gain = -24 dB0 0 1 1 1 1 DAC input PGA gain = -22.5 dB0 0 1 1 1 0 DAC input PGA gain = -21 dB0 0 1 1 0 1 DAC input PGA gain = -19.5 dB0 0 1 1 0 0 DAC input PGA gain = -18 dB0 0 1 0 1 1 DAC input PGA gain = -16.5 dB0 0 1 0 1 0 DAC input PGA gain = -15 dB0 0 1 0 0 1 DAC input PGA gain = -13.5 dB0 0 1 0 0 0 DAC input PGA gain = -12 dB0 0 0 1 1 1 DAC input PGA gain = -10.5 dB0 0 0 1 1 0 DAC input PGA gain = -9 dB0 0 0 1 0 1 DAC input PGA gain = -7.5 dB0 0 0 1 0 0 DAC input PGA gain = -6 dB0 0 0 0 1 1 DAC input PGA gain = -4.5 dB0 0 0 0 1 0 DAC input PGA gain = -3 dB0 0 0 0 0 1 DAC input PGA gain = -1.5 dB0 0 0 0 0 0 DAC input PGA gain = 0 dB
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TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Control Register 5C
(1)
D7 D6 D5 D4 D3 D2 D1 D01 0 ASTG DSTGR/W R/W R/W R/W R/W R/W R/W
(1) NOTE: R = Read, W = Write
Analog Sidetone Gain
D5 D4 D3 DSTG
1 1 1 Analog sidetone gain = MUTE1 1 0 Analog sidetone gain = -27 dB1 0 1 Analog sidetone gain = -24 dB1 0 0 Analog sidetone gain = -21 dB0 1 1 Analog sidetone gain = -18 dB0 1 0 Analog sidetone gain = -15 dB0 0 1 Analog sidetone gain = -12 dB0 0 0 Analog sidetone gain = -9 dBDigital Sidetone Gain
D2 D1 D0 DSTG
1 1 1 Digital sidetone gain = MUTE1 1 0 Digital sidetone gain = -27 dB1 0 1 Digital sidetone gain = -24 dB1 0 0 Digital sidetone gain = -21 dB0 1 1 Digital sidetone gain = -18 dB0 1 0 Digital sidetone gain = -15 dB0 0 1 Digital sidetone gain = -12 dB0 0 0 Digital sidetone gain = -9 dB
Control Register 5D
(1)
D7 D6 D5 D4 D3 D2 D1 D01 1 SPKG ReservedR/W R/W R/W/S R/W
(1) NOTE: R = Read, W = Write
Control Register 5D Bit Summary
RESETBIT NAME FUNCTIONVALUE
Speaker GainSPKG = 00 0 dB GainD5-D4 SPKG 00 SPKG = 01 1 dB GainSPKG = 10 2 dB GainSPKG = 11 3 dB GainD3-D0 Reserved 0000
Control Register 6A
(1)
D7 D6 D5 D4 D3 D2 D1 D00 HDSI2O HNSI2O CIDI LINEI MICI HNSI HDSIR/W R/W/S R/W/S R/W R/W R/W R/W R/W
(1) NOTE: R = Read, W = Write
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TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Control Register 6A Bit Summary
RESETBIT NAME FUNCTIONVALUE
Headset input to outputD6 HDSI2O 0 HDSI2O = 0 The headset input is not connected to the headset output.HDSI2O = 1 The headset input is connected to the headset output.Handset input to outputD5 HNSI2O 0 HNSI2O = 0 The handset input is not connected to the handset output.HNSI2O = 1 The handset input is connected to the handset output.Caller ID input selectD4 CIDI 0 CIDI = 0 The caller ID input is not connected to ADC channel.CIDI = 1 The caller ID input is connected to ADC channel.Line input selectD3 LINEI 0 LINEI = 0 The line driver input is not connected to ADC channel.LINEI = 1 The line driver input is connected to ADC channel.MIC input selectD2 MICI 0 MICI = 0 The microphone input is not connected to ADC channel.MICI = 1 The microphone input is connected to ADC channel.Handset input selectD1 HNSI 0 HNSI = 0 The handset input is not connected to ADC channel.HNSI = 1 The handset input is connected to ADC channelHeadset input selectD0 HDSI 0 HDSI = 0 The headset input is not connected to ADC channel.HDSI = 1 The headset input is connected to ADC channel.
Control Register 6B
(1)
D7 D6 D5 D4 D3 D2 D1 D01 Reserved ASTOHD ASTOHN SPKO LINEO HNSO HDSOR/W R R/W R/W R/W R/W R/W R/W
(1) NOTE: R = Read, W = Write
Control Register 6B Bit Summary
RESETBIT NAME FUNCTIONVALUE
D6 Reserved 0
Analog sidetone output select for headset. This bit connects the analog sidetone to headset output.D5 ASTOHD 0 ASTOHD = 0. The analog sidetone is not connected to headset output.ASTOHD = 1. The analog sidetone is connected to headset output.Analog sidetone output select for handset. This bit connects the analog sidetone to handset output.D4 ASTOHN 0 ASTOHN = 0. The analog sidetone is not connected to handset output.ASTOHN = 1. The analog sidetone is connected to handset output.Speaker output select. This bit connects the DAC output to the 8- Ωspeaker driverD3 SPKO 0 SPKO = 0 The speaker driver output is not connected to DAC channel.SPKO = 1 The speaker driver output is connected to DAC channel.Line output select. This bit connects the DAC output to the 600- Ωline driverD2 LINEO 0 LINEO = 0 The line driver output is not connected to DAC channel.LINEO = 1 The line driver output is connected to DAC channel.Handset output select. This bit connects the DAC output to the 150- Ωhandset driverD1 HNSO 0 HNSO = 0 The handset driver output is not connected to DAC channel.HNSO = 1 The handset driver output is connected to DAC channel.Headset output select. This bit connects the DAC output to the 150- Ωheadset driverD0 HDSO 0 HDSO = 0 The headset driver output is not connected to DAC channel.HDSO = 1 The headset driver output is connected to DAC channel.
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Layout and Grounding Guidelines for TLV320AIC2x
TLV320AIC2x-to-DSP Interface
DX
DR
FSX
FSR
CLKX
CLKR
TMS320C54X
TMS320C6X
FS
SCLK
TLV320AIC20
MCLK
DIN
DOUT
M/S
IOVDD
From
Oscillator
Hybrid Circuit External Connections
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
TLV320AIC2x has a built-in analog antialias filter, which provides rejection to external noise at high frequenciesthat may couple into the device. Digital filters with high out-of-band attenuation also reject the external noise. Ifthe differential inputs are used for the ADC channel, then the noise in the common-mode signal is also rejectedby the high CMRR of TLV320AIC2x. Using external common-mode for microphone inputs also helps reject theexternal noise. However to extract the best performance from TLV320AIC2x, care must be taken in board designand layout to avoid coupling of external noise into the device.
TLV320AIC2x supports clock frequencies as high as 100 MHz. To avoid coupling of fast switching digital signalsto analog signals, the digital and analog sections should be separated on the board. In TLV320AIC2x the digitaland analog pins are kept separated to aid such a board layout. A separate analog ground plane must be used forthe analog section of the board. The analog and digital ground planes should be shorted at only one place asclose to TLV320AIC2x as possible. No digital trace should run under TLV320AIC2x to avoid coupling of externaldigital noise into the device. It is suggested to have the analog ground plane running below the TLV320AIC2x.The power-supplies must be decoupled close to the supply pins, preferably, with 0.1 µF ceramic capacitor and10 µF tantalum capacitor following. The ground pin must be connected to the ground plane as close as possibleto the TLV320AIC2x, so as to minimize any inductance in the path. Since the MCLK is expected to be a veryhigh frequency signal, it is advisable to shield it with digital ground. For best performance of ADC in differentialinput mode, the differential signals must be routed close to each other in similar fashion, so that the noisecoupling on both the signals is the same and can be rejected by the device.
Extra care has to be taken for the speaker driver outputs, as any trace resistance can cause a reduction in themaximum swing that can be seen at the speaker.
The TLV320AIC2x interfaces gluelessly to the McBSP port of a C54x or C6x TI DSP. Figure 34 shows a singleTLV320AIC2x connected to a C54x or C6x TI DSP.
Figure 34. TLV320AIC2xs Interface to McBSP Port of C54x or C6x DSP
The TLV320AIC2x connected to the telephone line using the LINEI and LINEO hybrid circuit is shown inFigure 35 .
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600 W
LINEI+
LINEI-
LINEO+
LINEO-
136 kW
136 kW
300 W
300 W
68 kW
Line
68 kW10 kW
10 kW
Microphone, Handset, and Headset External Connections
MIC Preamp
10 kΩ
10 kΩ
MICI+
HEADSET/HANDSET Preamp
10 kΩ
10 kΩ
MICI-
MICBIAS
0.1 µF
0.1 µF(1.35 V)
2 mA max, 2.35 V
HDSI+
HDSI-
0.1 µF
0.1 µF
MIC
AVSS
10 kΩ
MIC
AVSS TLV320AIC20
(1.35 V)
HNSI-
HNSI+
10 kΩ
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Layout and Grounding Guidelines for TLV320AIC2x (continued)
Figure 35. Hybrid Circuit External Connections
The microphone, headset, and handset external connections are shown in Figure 36 . The suggested discretecomponents with their values also are included.
Figure 36. MIC/Handset/Headset External Connections
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CallerID Interface
0-dB Gain, Typ. CIDI+
CIDI-
Rx
365 kΩ
Rx
365 kΩ
Cx
470 pF
Cx
470 pF
To Telephone To RJ11
To Analog
Crosspoint
TLV320AIC20
VCOM
VCOM
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Layout and Grounding Guidelines for TLV320AIC2x (continued)
The callerID amplifier interface to the telephone line is shown in
(A)
.
The value for Rx is 365 k Ω(E96 series, which has 1% tolerance). Cx is 470 pF (10% tolerance) of high-voltagerating. Voltage rating is decided based on the telecommunication standards of the country. The typical value is 1kV. The callerID input can be used as a lower-performance line input. For this application, a larger valuecapacitor is required for Cx.
A. Typical Application Circuit for CallerID Amplifiers
Figure 37. Recommended Power-Supply Decoupling
The recommended power-supply decoupling for the TLV320AIC2x is shown in Figure 38 . Both high frequencyand bulk decoupling capacitors are suggested. The high-frequency capacitors should be X7R type capacitors orbetter. A 1-µF ceramic capacitor should be used to decouple the digital power supply.
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IOVDD
TLV320AIC20
0.01 µF
1 µF
DGND
IOVDD
0.1 µF
AGND
AVDD2
12
13
5
0.1 µF
AGND
DRVDD
27
25
DVDD = Digital Power
DGND = Digital Ground AVDD/AVDD1/AVDD2= Analog
Power
AGND = Analog Ground
DRVDD = Separate Analog Power
0.1 µF
IOVSS
0.01 µF
DGND
DVDD
15
16
0.1 µFDVDD
DVSS
6
AVDD2
AVSS2
DRVDD
DRVSS1
DRVSS2
29
0.1 µF
AGND
33
32
AVDD1
AVSS1
AVDD
0.1 µF
0.1 µF
AGND
42
43
AVDD
AVSS
AVDD
TLV320AIC20, TLV320AIC21TLV320AIC24, TLV320AIC25TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Layout and Grounding Guidelines for TLV320AIC2x (continued)
Figure 38. Recommended Decoupling
48
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV320A20KIPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320A24KIPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC20CPFB NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC20CPFBG4 NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC20CPFBR NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC20CPFBRG4 NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC20IPFB NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC20IPFBG4 NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC20IPFBR NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC20IPFBRG4 NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC20KIPFB ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC20KIPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC20KIPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC21CPFB NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC21CPFBG4 NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC21CPFBR NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC21CPFBRG4 NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC21IPFB NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC21IPFBG4 NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC21IPFBR NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC21IPFBRG4 NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC24CPFB NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC24CPFBG4 NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC24CPFBR NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC24CPFBRG4 NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV320AIC24IPFB NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC24IPFBG4 NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC24IPFBR NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC24IPFBRG4 NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC24KIPFB ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC24KIPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC24KIPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC25CPFB NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC25CPFBG4 NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC25CPFBR NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC25CPFBRG4 NRND TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC25IPFB NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLV320AIC25IPFBG4 NRND TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 3
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV320AIC20CPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TLV320AIC20IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TLV320AIC20KIPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TLV320AIC21CPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TLV320AIC21IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TLV320AIC24CPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TLV320AIC24IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TLV320AIC24KIPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TLV320AIC25CPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV320AIC20CPFBR TQFP PFB 48 1000 367.0 367.0 38.0
TLV320AIC20IPFBR TQFP PFB 48 1000 367.0 367.0 38.0
TLV320AIC20KIPFBR TQFP PFB 48 1000 367.0 367.0 38.0
TLV320AIC21CPFBR TQFP PFB 48 1000 367.0 367.0 38.0
TLV320AIC21IPFBR TQFP PFB 48 1000 367.0 367.0 38.0
TLV320AIC24CPFBR TQFP PFB 48 1000 367.0 367.0 38.0
TLV320AIC24IPFBR TQFP PFB 48 1000 367.0 367.0 38.0
TLV320AIC24KIPFBR TQFP PFB 48 1000 367.0 367.0 38.0
TLV320AIC25CPFBR TQFP PFB 48 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
4073176/B 10/96
Gage Plane
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
0,17
0,27
24
25
13
12
SQ
36
37
7,20
6,80
48
1
5,50 TYP
SQ
8,80
9,20
1,05
0,95
1,20 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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