MC74VHC574DWR2G - ON SEMICONDUCTOR

MC74VHC574

Octal D-Type Flip-Flop

with 3-State Output

The MC74VHC574 is an advanced high speed CMOS octal

flip−flip with 3−state output fabricated with silicon gate CMOS

technology. It achieves high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining CMOS low power

dissipation.

This 8−bit D−type flip−flop is controlled by a clock input and an

output enable input. When the output enable input is high, the eight

outputs are in a high impedance state.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems

to 3 V systems.

•High Speed: fmax = 180 MHz (Typ) at VCC = 5 V

•Low Power Dissipation: ICC = 4 μA (Max) at TA = 25°C

•High Noise Immunity: VNIH = VNIL = 28% VCC

•Power Down Protection Provided on Inputs

•Balanced Propagation Delays

•Designed for 2 V to 5.5 V Operating Range

•Low Noise: VOLP = 1.2 V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300 mA

•ESD Performance: HBM > 2000 V; Machine Model > 200 V

•Chip Complexity: 266 FETs or 66.5 Equivalent Gates

•These Devices are Pb−Free and are RoHS Compliant

May, 2011 − Rev. 6

1Publication Order Number:

MC74VHC574/D

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Device Package Shipping†

ORDERING INFORMATION

MC74VHC574DWR2G SOIC−20 1000 / T&R

MC74VHC574DWG

1

20

MARKING DIAGRAMS

SOIC−20

DW SUFFIX

CASE 751D

VHC574

AWLYYWWG

TSSOP−20

DT SUFFIX

CASE 948E

1

20

1

20

VHC574 = Specific Device Code

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

VHC

574

ALYWG

G

MC74VHC574DTR2G TSSOP−20 2500 / T&R

MC74VHC574DTG TSSOP−20

SOIC−20

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

38 / Rail

75 / Rail

MC74VHC574

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2

Figure 1. LOGIC DIAGRAM

DATA

INPUTS

D0

D1

D2

D3

D4

D5

D6

D7 9

8

7

6

5

4

3

2

1

OE

12

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

13

14

15

16

17

18

19

NONINVERTING

OUTPUTS

11

CP

OE CP Q

L

H

L, H,

X

H

L

No Change

Z

INPUTS OUTPUT

FUNCTION TABLE

D

H

L

X

Figure 2. PIN ASSIGNMENT

D4

D2

D1

D0

OE

GND

D7

D6

D5

D3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q3

Q2

Q1

Q0

VCC

CP

Q7

Q6

Q5

Q4

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

V

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

IIK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Diode Current

ÎÎÎÎÎ

− 20

ÎÎÎ

mA

ÎÎÎÎ

IOK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Diode Current

ÎÎÎÎÎ

±20

ÎÎÎ

mA

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±75

ÎÎÎ

mA

ÎÎÎÎ

PD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, SOIC Packages†

TSSOP Package†

ÎÎÎÎÎ

500

450

ÎÎÎ

mW

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

_C

* Absolute maximum continuous ratings are those values beyond which damage to the device

may occur. Exposure to these conditions or conditions beyond those indicated may

adversely affect device reliability. Functional operation under absolute−maximum−rated

conditions is not implied.

†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎ

2.0

ÎÎ

5.5

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎ

0

ÎÎ

5.5

ÎÎÎ

V

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage

ÎÎÎ

0

ÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature

ÎÎÎ

− 40

ÎÎ

+ 85

ÎÎÎ

_C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 3.3V

VCC = 5.0V

ÎÎÎ

0

ÎÎ

100

20

ÎÎÎ

ns/V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎ

Unit

ÎÎÎÎ

Min

ÎÎÎ

Typ

ÎÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎ

Minimum High−Level

Input Voltage

ÎÎÎÎÎÎÎ

ÎÎÎ

2.0

3.0 to

5.5

ÎÎÎÎ

1.50

VCC x 0.7

ÎÎÎ

ÎÎÎÎ

1.50

VCC x 0.7

ÎÎÎÎ

ÎÎ

V

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎ

Maximum Low−Level

Input Voltage

ÎÎÎÎÎÎÎ

ÎÎÎ

2.0

3.0 to

5.5

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

0.50

VCC x 0.3

ÎÎÎÎ

0.50

VCC x 0.3

ÎÎ

V

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎ

Minimum High−Level

Output Voltage

ÎÎÎÎÎÎÎ

Vin = VIH or VIL

IOH = − 50μA

ÎÎÎ

2.0

3.0

4.5

ÎÎÎÎ

1.9

2.9

4.4

ÎÎÎ

2.0

3.0

4.5

ÎÎÎÎ

1.9

2.9

4.4

ÎÎÎÎ

ÎÎ

V

ÎÎÎÎÎÎÎ

Vin = VIH or VIL

IOH = − 4mA

IOH = − 8mA

ÎÎÎ

3.0

4.5

ÎÎÎÎ

2.58

3.94

ÎÎÎ

ÎÎÎÎ

2.48

3.80

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎ

Maximum Low−Level

Output Voltage

ÎÎÎÎÎÎÎ

Vin = VIH or VIL

IOL = 50μA

ÎÎÎ

2.0

3.0

4.5

ÎÎÎÎ

ÎÎÎ

0.0

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎ

V

ÎÎÎÎÎÎÎ

Vin = VIH or VIL

IOL = 4mA

IOL = 8mA

ÎÎÎ

3.0

4.5

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

0.36

ÎÎÎÎ

0.44

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74VHC574

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4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS

ÎÎ

Unit

ÎÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎ

Unit

ÎÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎ

Typ

ÎÎÎÎ

Min

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎ

Maximum Input

Leakage Current

ÎÎÎÎÎÎÎ

Vin = 5.5V or GND

ÎÎÎ

0 to 5.5

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

±0.1

ÎÎÎÎ

±1.0

ÎÎ

μA

ÎÎÎÎ

IOZ

ÎÎÎÎÎÎÎ

Maximum

Three−State Leakage

Current

ÎÎÎÎÎÎÎ

Vin = VIL or VIH

Vout = VCC or GND

ÎÎÎ

5.5

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

±0.25

ÎÎÎÎ

±2.5

ÎÎ

μA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎ

Maximum Quiescent

Supply Current

ÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎ

5.5

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

4.0

ÎÎÎÎ

40.0

ÎÎ

μA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎ

Unit

ÎÎÎÎ

Min

ÎÎÎ

Typ

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

fmax

ÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency

(50% Duty Cycle)

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3V CL = 15pF

CL = 50pF

ÎÎÎÎ

80

50

ÎÎÎ

125

75

ÎÎÎÎ

—

ÎÎÎ

65

45

ÎÎÎÎ

—

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

ÎÎÎÎ

130

85

ÎÎÎ

180

115

ÎÎÎÎ

—

ÎÎÎ

110

75

ÎÎÎÎ

—

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay,

CP to Q

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3 CL = 15pF

CL = 50pF

ÎÎÎÎ

—

ÎÎÎ

8.5

11.0

ÎÎÎÎ

13.2

16.7

ÎÎÎ

1.0

ÎÎÎÎ

15.5

19.0

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

ÎÎÎÎ

—

ÎÎÎ

5.6

7.1

ÎÎÎÎ

8.6

10.6

ÎÎÎ

1.0

ÎÎÎÎ

10.0

12.0

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎÎ

Output Enable Time,

OE to Q

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3V CL = 15pF

RL = 1kΩCL = 50pF

ÎÎÎÎ

—

ÎÎÎ

8.2

10.7

ÎÎÎÎ

12.8

16.3

ÎÎÎ

1.0

ÎÎÎÎ

15.0

18.5

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 15pF

RL = 1kΩCL = 50pF

ÎÎÎÎ

—

ÎÎÎ

5.9

7.4

ÎÎÎÎ

9.0

11.0

ÎÎÎ

1.0

ÎÎÎÎ

10.5

12.5

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎ

Output Disable Time,

OE to Q

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3V CL = 50pF

RL = 1kΩ

ÎÎÎÎ

—

ÎÎÎ

11.0

ÎÎÎÎ

15.0

ÎÎÎ

1.0

ÎÎÎÎ

17.0

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 50pF

RL = 1kΩ

ÎÎÎÎ

—

ÎÎÎ

7.1

ÎÎÎÎ

10.1

ÎÎÎ

1.0

ÎÎÎÎ

11.5

ÎÎÎÎ

tOSLH,

tOSHL

ÎÎÎÎÎÎÎÎÎ

Output to Output Skew

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3V CL = 50pF

(Note 1)

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

1.5

ÎÎÎ

—

ÎÎÎÎ

1.5

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 50pF

(Note 1)

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

1.0

ÎÎÎ

—

ÎÎÎÎ

1.0

ÎÎ

ns

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎÎÎÎÎ

ÎÎÎÎ

—

ÎÎÎ

4

ÎÎÎÎ

10

ÎÎÎ

—

ÎÎÎÎ

10

ÎÎ

pF

ÎÎÎÎ

Cout

ÎÎÎÎÎÎÎÎÎ

Maximum Three−State Output

Capacitance, Output in

High−Impedance State

ÎÎÎÎÎÎÎÎ

ÎÎÎÎ

—

ÎÎÎ

6

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

—

ÎÎ

pF

CPD Power Dissipation Capacitance (Note 2)

Typical @ 25°C, VCC = 5.0V

pF

28

1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.

2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC /8 (per flip−flop). CPD is used to determine the

no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

MC74VHC574

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5

NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)

Symbol Parameter

TA = 25°C

Unit

Typ Max

VOLP Quiet Output Maximum Dynamic VOL 0.9 1.2 V

VOLV Quiet Output Minimum Dynamic VOL − 0.9 − 1.2 V

VIHD Minimum High Level Dynamic Input Voltage — 3.5 V

VILD Maximum Low Level Dynamic Input Voltage — 1.5 V

TIMING REQUIREMENTS (Input tr = tf = 3.0ns)

Symbol Parameter Test Conditions

TA = 25°C

TA = − 40

to 85°C

Unit

Typ Limit Limit

tsu Minimum Setup Time, D to CP VCC = 3.3 ± 0.3 V

VCC = 5.0 ± 0.5 V

—

3.5

ns

thMinimum Hold Time, CP to D VCC = 3.3 ± 0.3 V

VCC = 5.0 ± 0.5 V

—

1.5

ns

twMinimum Pulse Width, CP VCC = 3.3 ± 0.3 V

VCC = 5.0 ± 0.5 V

—

5.0

5.5

5.0

ns

Figure 3. Switching Waveforms

CP

Q

VCC

GND

50%

50% VCC

tPLH tPHL

tw

1/fmax

Q

50%

50% VCC

tPZL tPLZ

tPZH tPHZ

VCC

GND

HIGH

IMPEDANCE

VOL +0.3V

VOH -0.3V

HIGH

IMPEDANCE

OE

50% VCC

Figure 4. Figure 5.

50%CP

VCC

VALID

GND

VCC

GND

tsu th

50%D

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

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6

Figure 6. Expanded Logic Diagram

C

DQ

2

D0

19 Q0

C

DQ

3

D1

18 Q1

C

DQ

4

D2

17 Q2

C

DQ

5

D3

16 Q3

C

DQ

6

D4

15 Q4

C

DQ

7

D5

14 Q5

C

DQ

8

D6

13 Q6

C

DQ

9

D7

12 Q7

11

CP

1

OE

Figure 7. Test Circuit

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 kΩ

Figure 8. INPUT EQUIVALENT CIRCUIT

INPUT

MC74VHC574

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7

PACKAGE DIMENSIONS

TSSOP−20

CASE 948E−02

ISSUE C

DIM

A

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:

MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS

SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

ÍÍÍÍ

110

1120

PIN 1

IDENT

A

B

−T−

0.100 (0.004)

C

DGH

SECTION N−N

K

K1

JJ1

N

M

F

−W−

SEATING

PLANE

−V−

−U−

S

U

M

0.10 (0.004) V S

T

20X REFK

L

L/2

2X

S

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

--- ---

S

U0.15 (0.006) T

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

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PACKAGE DIMENSIONS

SOIC−20

DW SUFFIX

CASE 751D−05

ISSUE G

20

1

11

10

B20X

H10X

C

L

18X A1

A

SEATING

PLANE

q

hX 45_

E

D

M

0.25 M

B

M

0.25 S

AS

B

T

eT

B

A

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

__

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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