S34ML02G100TFI000 - Spansion

"Spansion, Inc." and "Cypress Semiconductor Corp." have merged together to deliver high-performance, high-quality solutions

at the heart of today's most advanced embedded systems, from automotive, industrial and networking platforms to highly

interactive consumer and mobile devices. The new company "Cypress Semiconductor Corp." will conti nue to offer "Spansion,

Inc." products to new and existing customers.

Continuity of Specifications

There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made

are the result of normal document improvements and are noted in the document history page, wher e supported. Future

revisions will occur when appropriate, and chan ges will be noted in a document history page.

Continuity of Ordering Part Numbers

Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed

in this document.

For More Information

Please contact your local sa les office for additional information about Cypress products and solutions.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 002-00676 Rev. *Q Revised November 02, 2015

S34ML01G1, S34ML02G1, S34ML04G1

1 Gbit, 2 Gbit, 4 Gbit, 3 V

SLC NAND Flash for Embedded

Distinctive Characteristics

Density

– 1 Gbit / 2 Gbit / 4 Gbit

Architecture

– Inpu t / Output Bus Width: 8-bits / 16-bits

– Page Size:

– x8 = 2112 (2048 + 64) bytes; 64 bytes is spare area

– x16 = 1056 (1024 + 32) words; 32 words i s spare area

– Block Size: 64 Pages

– x8 = 128k + 4k bytes

– x16 = 64k + 2k words

– Plane Size:

– 1 Gbit / 2 Gbit: 1024 Blocks per Plane

x8 = 128M + 4M bytes

x16 = 64M + 2M words

– 4 Gbit: 2048 Blocks per Plane

x8 = 256M + 8M bytes

x16 = 128M + 4M words

–Device Size:

– 1 Gbit: 1 Plane per Device or 128 Mbyte

– 2 Gbit: 2 Planes per Device or 256 Mbyte

– 4 Gbit: 2 Planes per Device or 512 Mbyte

NAND Flash Interface

– Open NAND Flash Interface (ONFI) 1.0 compliant

– Address, Data and Commands multiplexed

Supply Voltage

– 3.3V device: Vcc = 2.7V ~ 3.6V

Security

– One Time Programmable (OTP) area

– Hardware program/erase disabled during power transition

Additional Features

– 2 Gb and 4 Gb parts support Multiplane Program and Erase

commands

– Supports Copy Back Program

– 2 Gb and 4 Gb parts support Multiplane Copy Back Program

– Supports Read Cache

Electronic Signature

– Manufacturer ID: 01h

Operating Temperature

– Industrial: -40°C to 85°C

– Automotive: -40°C to 105°C

Performance

Page Read / Program

– Random access: 25 µs (Max)

– Sequential access: 25 ns (Min)

– Program time / Multiplane Program time: 200 µs (Typ)

Block Erase (S34ML01G1)

– Block Erase time: 2.0 ms (Typ)

Block Erase / Multiplane Erase (S34ML02G1, S34ML04G1)

– Block Erase time: 3.5 ms (Typ)

Reliability

– 100,000 Program / Erase cycles (Typ)

(with 1 bit ECC per 528 bytes (x8) or 264 words (x16))

– 10 Year Data retention (Typ)

– Blocks zero and one are valid and will be valid for at least 1000

program-erase cycles with ECC

Package Options

– Lead Free and Low Halogen

– 48-Pin TSOP 12 x 20 x 1.2 mm

– 63-Ball BGA 9 x 11 x 1 mm

Document Number: 002-00676 Rev. *Q Page 3 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Contents

Distinctive Characteristics .................................................. 2

Performance.......................................................................... 2

1. General Description..................................................... 5

1.1 Logic Diagram................................................................ 6

1.2 Connection Diagram...................................................... 7

1.3 Pin Description............ ................................................... 8

1.4 Block Diagram................... .. ... ........................................ 9

1.5 Array Organization....................................................... 10

1.6 Addressing................................................................... 11

1.7 Mode Selection............................................................ 14

2. Bus Operation............................................................ 14

2.1 Command Input ........................................................... 14

2.2 Address Input........ ... ... ................................................. 14

2.3 Data Input ............. ... ... .............. ... ............................ ... . 15

2.4 Data Output.............. ... ................................................. 15

2.5 Write Protect....................... ... ...................................... 15

2.6 Standby........................................................................ 15

3. Command Set............................................................. 16

3.1 Page Read................................................................... 17

3.2 Page Program.............................................................. 17

3.3 Multiplane Program — S34ML02G1

and S34ML04G1.......................................................... 18

3.4 Page Reprogram — S34ML02G1

and S34ML04G1.......................................................... 19

3.5 Block Erase..................................................... ............. 20

3.6 Multiplane Block Erase — S34ML02G1

and S34ML04G1.......................................................... 21

3.7 Copy Back Program..................................................... 21

3.8 EDC Operation — S34ML02G1 and S34ML04G1 ....... 22

3.9 Read Status Register................................................... 24

3.10 Read Status Enhanced — S34ML02G1

and S34ML04G1.......................................................... 24

3.11 Read Status Register Field Definition.......................... 25

3.12 Reset............................................................................ 25

3.13 Read Cache................................................................. 25

3.14 Cache Program............................................................ 26

3.15 Multiplane Cache Program — S34ML02 G1

and S34ML04G1.......................................................... 27

3.16 Read ID........................................................................ 28

3.17 Read ID2...................................................................... 30

3.18 Read ONFI Signature .................................................. 30

3.19 Read Parameter Page................................................. 31

3.20 One-Time Programmable (OTP) Entry........................ 33

4. Signal Descriptions ................................................... 33

4.1 Data Protection and Power On / Off Sequence........... 33

4.2 Ready/Busy.................................................................. 34

4.3 Write Protect Operation ............................................... 35

5. Electrical Characteristics.......................................... 36

5.1 Valid Blocks ................................................................. 36

5.2 Absolute Maximum Ratings......................................... 36

5.3 AC Test Conditions...................................................... 36

5.4 AC Characteristics....................................................... 37

5.5 DC Characteristics.... ... ... ................. ................. ............ 38

5.6 Pin Capacitance ............................................................ 38

5.7 Program / Erase Characteristics................................... 39

6. Timing Diagrams......................................................... 39

6.1 Command Latch Cycle.................................................. 39

6.2 Address Latch Cycle..................................................... 40

6.3 Data Input Cycl e Ti ming................................................ 40

6.4 Data Output Cycle Timing

(CLE=L, WE#=H, ALE=L, WP#=H).. ... ................. .. ... .... 41

6.5 Data Output Cycle Timing

(EDO Type, CLE=L, WE#=H, ALE=L).......................... 41

6.6 Page Read Operation................................................... 42

6.7 Page Read Operation (Interrupted by CE#).................. 43

6.8 Page Rea d Operation Timing with

CE# Don’t Care............................................................. 44

6.9 Page Program Operation.............................................. 44

6.10 Page Program Operation Timing

with CE# Don’t Care . ................. ................. ................. . 45

6.11 Page Program Operation with Random Data Input ...... 45

6.12 Random Data Output In a Page ................................... 46

6.13 Multiplane Page Program

Operation — S34ML02G1 and S34ML04G1................ 46

6.14 Block Erase Operation............ ... ................. .................. 47

6.15 Multiplane Block Erase — S34ML02G1

and S34ML04G1........................................................... 48

6.16 Copy Back Read with Optional Data Readout.............. 49

6.17 Copy Back Program Operation With

Random Data Input....................................................... 49

6.18 Multiplane Copy Back Program — S34ML02G1 and

S34ML04G1.................................................................. 50

6.19 Read Status Register Timing........................................ 51

6.20 Read Status Enhanced Timing..................................... 52

6.21 Reset Operation Timing................................................ 52

6.22 Read Cache.................................................................. 53

6.23 Cache Program............................................................. 55

6.24 Multiplane Cache Program — S34ML02G1 and

S34ML04G1.................................................................. 56

6.25 Read ID Operation Timing............................................ 58

6.26 Read ID2 Operation Timing.......................................... 58

6.27 Read ONFI Signature Timing........................................ 59

6.28 Read Parameter Page Timing ...................................... 59

6.29 OTP Entry Timing ......................................................... 60

6.30 Power On and Data Protection Timing......................... 60

6.31 WP# Handling............................................................... 61

7. Physical Interface ....................................................... 62

7.1 Physical Diagram.......................................................... 62

8. System Interface......................................................... 64

9. Error Management...................................................... 66

9.1 System Bad Block Replacement................................... 66

9.2 Bad Block Management................................................ 67

10. Ordering Information.................................................. 68

11. Revision History.......................................................... 69

Document Number: 002-00676 Rev. *Q Page 5 of 81

S34ML01G1

S34ML02G1, S34ML04G1

1. General Description

The Cypress S34ML01G1, S34ML02G1, and S34ML04G1 series is offered in 3.3 VCC and VCCQ power supply, and with x8 or x16 I/

O interface. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided

into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The page size for x8 is

(2048 + 64 spare) bytes; for x16 (1024 + 32) words.

Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of

NAND flash de vi ces, the implem e n tation of an ECC is mandatory.

The chip supports CE# don't care function. This function allows the direct download of the code from the NAND flash memory device

by a microcontroller, since the CE# transitions do not stop the read operation.

The devices have a Read Cache feature that improves the read throughput for large files. During cache reading, the devices load

the data in a cache register while the previous data is transferred to the I/O bu ffers to be read.

Like all other 2-kB page NAND flash devices, a program op eration typically writes 2112 bytes (x8), or 1056 words (x16) in 200 µs

and an erase operation can typically be performed in 2 ms (S34ML01G1) on a 128-kB block (x8) or 64-kword block (x16). In

addition, thanks to multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at a

time (again, one per plane). The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by

50%.

In multiplane operations, data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as the ports for command

and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards differen t

densities, without any rearrangement of the footprint.

Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control pins.

The on-chip Program/Erase Controller automates all read, pro gram, and erase functions including pulse repetition, where required,

and internal verification and margini ng of data. A WP# pin is available to provide hardware protection against program and erase

operations.

The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if the program/erase/read

controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to connect to a

single pull-up resistor. In a system with multiple memories the

R/B# pins can be connected all together to provide a glob al status signal.

The Reprogram function allows the optimization of defective block management — when a Page Program operation fails the data

can be directly programmed in another page inside th e same array sectio n without the time consuming serial data insertion phase.

The Copy Back operation automatically executes embedded error detection operation: 1-bit error out of every 528 bytes (x8) or 256

words (x16) can be detected. With this feature it is no longer necessary to use an external mechanism to detect Copy Ba ck

operation errors.

Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane cases) is allowed.

In addition, Cache Program and Multiplane Cache Program opera tio ns improve the programing throughput by programing data

using the cache register.

The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page Reprogram re-programs

one page. Normally, this operation is performed after a failed Page Program operation. Similarly, the Multiplane Page Reprogram re-

programs two pages in parallel, one per plane. The first page must be in the first plane while the second page must be in the second

plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The Page

Reprogram and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted during re-

program operations.

Note: The S34ML01G1 device does not support EDC.

Document Number: 002-00676 Rev. *Q Page 6 of 81

S34ML01G1

S34ML02G1, S34ML04G1

The devices come with an OTP (one time prog ra mma b l e) area, which is a restricted access area where sensitive data/code can be

stored permanently. This security feature is subjec t to an NDA (non-disclosure agreement) and is, therefore, not described in the

data sheet. For more details, contact your nearest Cypress sales office.

1.1 Logic Diagram

Figure 1.1 Logic Diagram

Device Density (bits) Number of Planes Number of Blocks

per Plane EDC Support

Main Spare

S34ML01G1 128M x 8

64M x 16 4M x 8

2M x 16 1 1024 No

S34ML02G1 256M x 8

128M x 16 8M x 8

4M x 16 2 1024 Yes

S34ML04G1 512M x 8

256M x 16 16M x 8

8M x 16 2 2048 Yes

Table 1.1 Signal Names

I/O7 - I/O0 (x8) Data Input / Outputs

I/O8 - I/O15 (x16)

CLE Command Latch Enable

ALE Address Latch Enable

CE# Chip Enable

RE# Read Enable

WE# Write Enable

WP# Write Protect

R/B# Read/Busy

VCC Power Supply

VSS Ground

NC Not Connected

VCC

VSS

WP#

CLE

ALE

RE#

WE#

CE# I/O0~I/O7

R/B#

Document Number: 002-00676 Rev. *Q Page 7 of 81

S34ML01G1

S34ML02G1, S34ML04G1

1.2 Connection Diagram

Figure 1.2 48-Pin TSOP1 Contact x8, x16 Devices

Note:

1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.

Figure 1.3 63-BGA Contact, x8 Device (Balls Down, Top View)

Note:

1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.

R/B#

RE#

CE#

VCC

VSS

CLE

ALE

WE#

WP#

VSS

I/O7

I/O6

I/O5

I/O4

VCC

VSS

VCC

I/O3

I/O2

I/O1

I/O0

VSS

481

NAND Flash

TSOP1

x8 x8

R/B#

RE#

CE#

VCC

VSS

CLE

ALE

WE#

WP#

x16 x16

VSS

I/O15

I/O14

I/O13

I/O7

I/O6

I/O5

I/O4

I/O12

VCC

VSS

VCC

I/011

I/O3

I/O2

I/O1

I/O0

I/O10

I/O9

I/O8

VSS

(1)

F3 F4 F5 F6 F7 F8

E3 E4 E5 E6 E7 E8

D3 D4 D5 D6 D7 D8

C3 C4 C5 C6 C7 C8

RB#WE#CE#VSSALEWP#

NCNCNCCLERE#VCC (1)

NCNCNCNCNCNC

G3 G4 G5 G6 G7 G8

NCVSS (1)NCNCNCNC

H3 H4 H5 H6 H7 H8

Vcc

NCNCNCI/O0NC

NCNCNCNCVCC (1)NC

B10

A10

J3 J4 J5 J6 J7 J8

I/O7I/O5VCC

NCI/O1NC

K3 K4 K5 K6 K7 K8

VSS

I/O6I/O4I/O3I/O2VSS

L10

M10

Document Number: 002-00676 Rev. *Q Page 8 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Figure 1.4 63-BGA Contact, x16 Device (Balls Down, Top View)

1.3 Pin Description

Notes:

1. A 0.1 µF capacitor sho uld be connect ed b etween t he V CC Supply Volt age pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB

track widths must be sufficient to carry the currents requ ired during program and erase operations.

2. An internal voltage detector disables all functions whenever VCC is below 1.8V to prot ect the device from any involuntary program/erase during power transitions.

Table 1.2 Pin Description

Pin Name Description

I/O0 - I/O7 (x8) Inputs/Outputs. The I/O pi ns are used for command input, address input, data input, and data output. The

I/O pins float to High-Z when the device is deselected or the outputs are disabled.

I/O8 - I/O15 (x16)

CLE Command Latch Enable. This input activates the latching of the I/O inpu ts inside the Comma nd Register on the rising

edge of Write Enable (WE#).

ALE Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising

edge of Write Enable (WE#).

CE# Chip Enable. This input controls the selection of th e device. When the devi ce is not busy CE# low selects the memory.

WE# Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the risin g edge of WE#.

RE# Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is

valid tREA after the falling edge of RE# which also increments the internal column address counte r by one.

WP# Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification

(program / erase).

R/B# Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.

VCC Supply Voltage. The VCC supplies the power for all the operations (Read, Program, Erase). An internal lock circuit

prevents the insertion of Commands when VCC is less than VLKO.

VSS Ground.

NC Not Connected.

F3 F4 F5 F6 F7 F8

E3 E4 E5 E6 E7 E8

D3 D4 D5 D6 D7 D8

C3 C4 C5 C6 C7 C8

RB#WE#CE#VSSALEWP#

NCNCNCCLERE#VCC

NCNCNCNCNCNC

G3 G4 G5 G6 G7 G8

NCVSSNCNCNCNC

H3 H4 H5 H6 H7 H8

Vcc

I/O14I/O12I/O10I/O0I/O8

NCI/O15I/O13NCVCCNC

B10

A10

J3 J4 J5 J6 J7 J8

I/O7I/O5VCC

I/O11I/O1I/O9

K3 K4 K5 K6 K7 K8

VSS

I/O6I/O4I/O3I/O2VSS

L10

M10

Document Number: 002-00676 Rev. *Q Page 9 of 81

S34ML01G1

S34ML02G1, S34ML04G1

1.4 Block Diagram

Figure 1.5 Functional Block Diagram

Address

Counter

Controller

Command

Interface

Logic

Command

Data

RE#

I/O Buffer

Y Decoder

PAGE Buffer

NAND Flash

Memory Array

WP#

CE#

WE#

CLE

ALE

I/O0~I/O7 (x8)

I/O0~I/O15 (x16)

1024 Mbit + 32 Mbit (1 Gb Device)

Program Erase

HV Generation

2048 Mbit + 64 Mbit (2 Gb Device)

4096 Mbit + 128 Mbit (4 Gb Device)

Document Number: 002-00676 Rev. *Q Page 10 of 81

S34ML01G1

S34ML02G1, S34ML04G1

1.5 Array Organization

Figure 1.6 Array Organization — x8

Figure 1.7 Array Organization — x16

Plane(s)

2048 bytes 64 bytes

I/O

[7:0]

1 Page = (2k + 64) bytes

1 Block = (2k + 64) bytes x 64 pages

= (128k + 4k) bytes

1 Plane = (128k + 4k) bytes x 1024 Blocks

Page Buffer

1024

Blocks

per

Plane

1022

1023

Array Organization (x8)

For 1 Gb and 2 Gb devices there are 1024 Blocks per Plane

For 4 Gb device there are 2048 Blocks per Plane

Note:

2 Gb and 4 Gb devices have two Planes

Plane(s)

1024 words

I/O0~I/O15

1 Page = (1k + 32) words

1 Block = (1k + 32) words x 64 pages

= (64k + 2k) words

1 Plane = (64k + 2k) words x 1024 Blocks

Page Buffer

1024

Blocks

per

Plane

1022

1023

Array Organization (x16)

For 1 Gb and 2 Gb devices there are 1024 Blocks per Plane

For 4 Gb device there are 2048 Blocks per Plane

Note:

2 Gb and 4 Gb devices have two Planes

32 words

Document Number: 002-00676 Rev. *Q Page 11 of 81

S34ML01G1

S34ML02G1, S34ML04G1

1.6 Addressing

1.6.1 S34ML01G1

Notes:

1. CAx = Column Address bit.

2. PAx = Page Address bit.

3. BAx = Block Address bit.

4. Block address concatenated with page address = actual page address, also known as the row address.

5. I/O[15:8] are not used during the addressing sequence and should be driven Low.

For the x8 address bits, the following rules apply:

A0 - A11: column address in the page

A12 - A17: page address in the block

A18 - A27: block address

For the x16 address bits, the following rules apply:

A0 - A10: column address in the page

A11 - A16: page address in the block

A17 - A26: block address

Table 1.3 Address Cycle Map — 1 Gb Device

Bus Cy cl e I/O [15: 8] (5) I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

1st / Col. Add. 1 — A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)

2nd / Col. Add. 2 — A8 (CA8) A9 (CA9) A10 (CA10) A11 (CA11) Low Low Low Low

3rd / Row Add. 1 — A12 (PA0) A13 (PA1) A14 (PA2) A15 (PA3) A16 (PA4) A17 (PA5) A18 (BA0) A19 (BA1)

4th / Row Add. 2 — A20 (BA2) A21 (BA3) A22 (BA4) A23 (BA5) A24 (BA6) A25 (BA7) A26 (BA8) A27 (BA 9 )

x16

1st / Col. Add. 1 Low A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)

2nd / Col. Add. 2 Low A8 (CA8) A9 (CA9) A10 (CA10) Low Low Low Low Low

3rd / Row Add. 1 Low A11 (PA0) A12 (PA1) A13 (PA2) A14 (PA3) A15 (PA4) A16 (PA5) A17 (BA0) A18 (BA1)

4th / Row Add. 2 Low A19 (BA2) A20 (BA3) A21 (BA4) A22 (BA5) A23 (BA6) A24 (BA7) A25 (BA8) A26 (BA9)

Document Number: 002-00676 Rev. *Q Page 12 of 81

S34ML01G1

S34ML02G1, S34ML04G1

1.6.2 S34ML02G1

Notes:

1. CAx = Column Address bit.

2. PAx = Page Address bit.

3. PLA0 = Plane Address bit zero.

4. BAx = Block Address bit.

5. Block address concatenated with page address and plane address = actual page address, also known as the row address.

6. I/O[15:8] are not used during the addressing sequence and should be driven Low.

For the x8 address bits, the following rules apply:

A0 - A11: column address in the page

A12 - A17: page address in the block

A18: plane address (for multiplane operations) / block address (for normal operations)

A19 - A28: block address

For the x16 address bits, the following rules apply:

A0 - A10: column address in the page

A11 - A16: page address in the block

A17: plane address (for multiplane operations) / block address (for normal operations)

A18 - A27: block address

Table 1.4 Address Cycle Map — 2 Gb Device

Bus Cycle I/O [15:8] (6) I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

1st / Col. A dd . 1 — A0 (CA0) A1 (CA1) A2 (CA 2 ) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)

2nd / Col. Add. 2 — A8 (CA8) A9 (CA9) A10 (CA10) A11 (CA11) Low Low Low Low

3rd / Row Add. 1 — A12 (PA0) A13 (PA1) A14 (PA2) A15 (PA3) A16 (PA4) A17 (PA5) A18

(PLA0) A19 (BA0)

4th / Row Add. 2 — A20 (BA1) A21 (BA2) A22 (BA3) A23 (BA4) A24 (BA5) A25 (BA6) A26 (BA7) A27 (BA8)

5th / Row Add. 3 — A28 (BA9) Low Low Low Low Low Low Low

x16

1st / Col. A dd . 1 Low A0 (C A0) A1 (C A1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)

2nd / Col. Add. 2 Low A8 (CA8) A9 (CA9) A10 (CA10) Low Low Low Low Low

3rd / Row Add. 1 Low A11 (PA0) A12 (PA1) A13 (PA2) A14 (PA3) A15 (PA4) A16 (PA5) A17

(PLA0) A18 (BA0)

4th / Row Add. 2 Low A19 (BA1) A20 (BA2) A21 (BA3) A22 (BA4) A23 (BA5) A24 (BA6) A25 (BA 7) A26 (BA8)

5th / Row Add. 3 Low A27 (BA9) Low Low Low Low Low Low Low

Document Number: 002-00676 Rev. *Q Page 13 of 81

S34ML01G1

S34ML02G1, S34ML04G1

1.6.3 S34ML04G1

Notes:

1. CAx = Column Address bit.

2. PAx = Page Address bit.

3. PLA0 = Plane Address bit zero.

4. BAx = Block Address bit.

5. Block address concatenated with page address and plane address = actual page address, also known as the row address.

6. I/O[15:8] are not used during the addressing sequence and should be driven Low.

For the x8 address bits, the following rules apply:

A0 - A11: column address in the page

A12 - A17: page address in the block

A18: plane address (for multiplane operations) / block address (for normal operations)

A19 - A29: block address

For the x16 address bits, the following rules apply:

A0 - A10: column address in the page

A11 - A16: page address in the block

A17: plane address (for multiplane operations) / block address (for normal operations)

A18 - A28: block address

Table 1.5 Address Cycle Map — 4 Gb Device

Bus Cycle I/O [15:8] (6) I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

1st / Col. Add. 1 — A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)

2nd / Col. A dd. 2 — A8 (CA8) A9 (CA9) A10 (CA10) A11 (CA11) Low Low Low Low

3rd / Row Add. 1 — A12 (PA0) A13 (PA1) A14 (PA2) A15 (PA3) A16 (PA4) A17 (PA5) A18

(PLA0) A19 (BA0)

4th / Row Add. 2 — A20 (BA1) A21 (BA2) A22 (BA3) A23 (BA4) A24 (BA5) A25 (BA6) A26 (BA7) A27 (BA8)

5th / Row Add. 3 — A28 (BA9) A29

(BA10) Low Low Low Low Low Low

x16

1st / Col. Add. 1 Low A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)

2nd / Col. A dd. 2 Low A8 (CA8) A9 (CA9) A10 (CA10) Low Low Low Low Low

3rd / Row Add. 1 Low A11 (PA0) A12 (PA1) A13 (PA2) A14 (PA3) A15 (PA4) A16 (PA5) A17

(PLA0) A18 (BA0)

4th / Row Add. 2 Low A19 (BA1) A20 (BA2) A21 (BA3) A22 (BA4) A23 (BA5) A24 (BA6) A25 (BA7) A26 (BA8)

5th / Row Add. 3 Low A27 (BA9) A28

(BA10) Low Low Low Low Low Low

Document Number: 002-00676 Rev. *Q Page 14 of 81

S34ML01G1

S34ML02G1, S34ML04G1

1.7 Mode Selection

Notes:

1. X can be VIL or VIH. High= Logic level high. Low = Logic level low.

2. WP# should be biased to CMOS high or CMOS low for stand-by mode.

3. During Busy Time in Read, RE# must be held high to prevent unintended data out.

2. Bus Operation

There are six standard bus operations that control the device: Command Input, Address Input, Data Input, Data Output, Write

Protect, and Standby. (See Table 1.6.)

Typically glitches less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory and do not affect bus

operations.

2.1 Command Input

The Command Input bus operation is used to give a command to the memory device. Co mmands are accepted with Chip Enable

low, Command Latch Enable high, Address Latch Enable low, and Read Enable high and latched on the rising edge of Write Enable.

Moreover, for commands that start a modify operation (program/erase) the Write Protect pin must be high. See Figure 6.1

on page 39 and Table 5.4 on page 37 for details of the timing requirements. Command codes are always applied on I/O7:0

regardless of the bus configuration (x8 or x16).

2.2 Address Input

The Address Input bus operation allows the insertion of the memory address. For the S34ML02G1 and S34ML04G1 devices, fi ve

write cycles are needed to input the addresses. For the S34ML01G1, four write cycles are needed to input the addresses. If

necessary, a 5th dummy address cycle can be issued to S34ML01G1, which will be ignored by the NAND device without causing

problems. Addresses are accepted with Chip Enable low, Address Latch Ena ble high, Command Latch Enable low, and Read

Enable high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/erase)

the Write Protect pin must be high. See Figure 6.2 on page 40 and Table 5.4 on page 37 for details of the timing requirements.

Addresses are always applied on I/O7:0 regardless of the bus configuration (x8 or x16). Refer to Table 1.3 through Table 1.5

on page 13 for more detailed information.

Table 1.6 Mode Selection

Mode CLE ALE CE# WE# RE# WP#

Read Mode Command Input High Low Low Rising High X

Address Input Low High Low Rising High X

Program or Erase Mode Command Input High Low Low Rising High High

Address Input Low High Low Rising High High

Data Input Low Low Low Rising High High

Data Output (on going) Low Low Low High Falling X

Data Output (suspended) X X X High High X

Busy T ime in Read X X X High High (3) X

Busy Ti me in Program X X X X X High

Busy Time in Erase X X X X X High

Write Protect X X X X X Low

Stand By X X High X X 0V / VCC (2)

Document Number: 002-00676 Rev. *Q Page 15 of 81

S34ML01G1

S34ML02G1, S34ML04G1

2.3 Data Input

The Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is serial and timed by

the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read

Enable high, and Write Protect high and latched on the rising edge of Write Enable. See Figure 6.3 on page 40 and Table 5.4

on page 37 for details of the timing requirements.

2.4 Data Output

The Data Output bus operation allows data to be read from the memory array and to check the Status Register content, the EDC

register content, and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip Enable low, Write

Enable high, Address Latch Enable low, and Command Latch Enable low. See Figure 6.4 on page 41 and Table 5.4 on page 37 for

details of the ti mi n gs re qu i re m en t s .

2.5 Write Protect

The Hardware Write Protection is activated when the Write Protect pin is low. In this condition, modify operations do not start and the

content of the memory is not altered. The Write Protect pin is not latched by Write Enable to ensure the protection even during power

up.

2.6 Standby

In Standby, the device is deselected, outputs are disabled, and power consumption is re duced.

Document Number: 002-00676 Rev. *Q Page 16 of 81

S34ML01G1

S34ML02G1, S34ML04G1

3. Command Set

Table 3.1 Command Set

Command 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle Acceptable

Command

during Busy

Supported on

S34ML01G1

Page Read 00h 30h No Yes

Page Program 80h 10h No Yes

Random Data Input 85h No Yes

Random Data Output 05h E0h No Yes

Multiplane Program 80h 11h 81h 10h No No

ONFI Multiplane Program 80h 11h 80h 10h No No

Page Reprogram 8Bh 10h No No

Multiplane Page Reprogram 8Bh 11h 8Bh 10h No No

Block Erase 60h D0h No Yes

Multiplane Block Erase 60h 60h D0h No No

ONFI Multiplane Block Erase 60h D1h 60h D0h No No

Copy Back Read 00h 35h No Yes

Copy Back Program 85h 10h No Yes

Multiplane Copy Back Program 85h 11h 81h 10h No No

ONFI Multiplane Copy Back Program 85h 11h 85h 10h No No

Special Read For Copy Back 00h 36h No No

Read EDC Status Register 7Bh Yes No

Read Status Register 70h Yes Yes

Read Status Enhanced 78h Yes No

Reset FFh Yes Yes

Read Cache 31h No Yes

Read Cache Enhanced 00h 31h No No

Read Cache End 3Fh No Yes

Cache Program (End) 80h 10h No Yes

Cache Program (Start) / (Continue) 80h 15h No Yes

Multiplane Cache Program (Start/Continue) 80h 11h 81h 15h No No

ONFI Multiplane Cache Program (Start/Continue) 80h 11h 80h 15h No No

Multiplane Cache Program (End) 80h 11h 81h 10h No No

ONFI Multiplane Cache Program (End) 80h 11h 80h 10h No No

Read ID 90h No Yes

Read ID2 30h-65h-00h 30h No Yes

Read ONFI Signature 90h No Yes

Read Parameter Page ECh No Yes

One-time Programmable (OTP) Area Entry 29h-17h-04h-19h No Yes

Document Number: 002-00676 Rev. *Q Page 17 of 81

S34ML01G1

S34ML02G1, S34ML04G1

3.1 Page Read

Page Read is initiated by writing 00h and 30h to the command register along with five address cycles (four or five cycles for

S34ML01G1). Two types of operations are available: random read and serial page read. Random read mode is enabled when the

page address is changed. All data within the selected page are transferred to the data registers. The system controller may detect

the completion of this data transfer (tR) by analyzing the output of the R/B pin. Once the data in a page is loaded into the data

registers, they may be read out in 25 ns cycle time by sequentially pulsing RE#. The repetitive high to low transitions of the RE#

signal makes the device output the data, starting fro m the selected column address up to the last column address.

The device may output random data in a page instead of the sequential data by writing Random Data Output command. The column

address of next data, which is going to be out, may be changed to the address that follows Random Data Output command. Random

Data Output can be performed as many times as needed.

After power up, the device is in read mode, so 00h command cycle is not necessary to start a read operation. Any operation other

than read or Random Data Output causes the device to exit read mode .

See Figure 6.6 on page 42 and Figure 6.12 on page 46 as references.

3.2 Page Program

A page program cycle consists of a serial data loading period in which up to 2112 bytes (x8) or 1056 words (x1 6) of data may be

loaded into the data register, followed by a non-volati le programming period where the loaded data is programmed into the

appropriate ce ll.

The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle address inputs

(four cycles for S34ML01G1) and then serial data. The words other than those to be programmed do not need to be loaded. The

device supports Random Data Input with in a page. The column address of next data, which will be entered, may be changed to the

address that follows the Random Data Input command (85h). Random Data Input may be performed as many times as needed.

The Page Program confirm command (10h) initiates the programming process. The internal write state controller automatically

executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks.

Once the program process starts, the Read Status Register commands (70h or 78h) may be issued to read the Status Register. The

system controller can detect the completion of a program cycle by monitoring the

R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status commands (70h or 78h) or Reset command are

valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O0) may be checked. The

internal write verify detects only errors for 1’s that are not successfully programmed to 0’s. The command register remains in Read

Status command mode until another valid command is written to the command register. Figure 6.9 on page 44 and Figure 6.11

on page 45 detail the sequence.

The device is programmable by page, but it also allows multiple partial page programming of a word or consecutive bytes up to 2112

bytes (x8) or 1056 words (x16) in a single page program cycle.

The number of consecutive partial page programming operations (NOP) withi n the same page must not exceed the number

indicated in Table 5.7 on page 39. Pages may be programmed in any order within a block.

Users who use “EDC check” (for S34ML02G1 and S34ML04G1 only) in copy back must comply with some limitations related to data

handling during one page pr ogram sequence. Refer to Section 3.8 on page 22 for details.

If a Page Program operation is interrupted by hardware reset, power failure or other means, the host mu st ensure that the

interrupted page is not used for further read ing or programming operations until the next uninterrupted block erase is complete.

Document Number: 002-00676 Rev. *Q Page 18 of 81

S34ML01G1

S34ML02G1, S34ML04G1

3.3 Multiplane Program — S34ML02G1 and S34ML04G1

The S34ML02G1 and S34ML04G1 devices support Multiplan e Program, making it possible to program two pages in parallel, one

page per plane.

A Multiplane Program cycle consists of a double serial data loading period in which up to 4224 bytes (x8) or 2112 words (x16) of

data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into

the appropriate cell. The serial data loading period begins with inputting the Serial Data Input command (80h), followed by the five

cycle address inputs and serial data for the 1st page. The address for this page must be in the 1st plane (PLA0 = 0). The device

supports Random Data Input exactly the same as in the case of page program operation. The Dummy Page Program Confirm

command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again,

the ‘81h’ command must be issued, followed by 2nd page address (5 cycles) and its serial data input. The address for this page

must be in the 2nd plane (PLA0 = 1). The Program Confirm command (10h) starts parallel programming of both pages.

Figure 6.13 on page 46 describes the sequences using the legacy protocol. In this case, the block address bits for the first plane are

all zero and the second address issued selects the block for both planes. Figure 6.14 on page 47 describes the sequences using the

ONFI protocol. For both addresses issued in this protocol, th e block address bits must be the same except for the bit(s) that select

the plane.

The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or 78h). The Read Status

Register command is also available during Dummy Busy time (tDBSY). In case of failure in either page program, the fail bit of the

Status Register will be set. Refer to Section 3.9 on page 24 for further info.

The number of consecutive partial page programming operations (NOP) withi n the same page must not exceed the number

indicated in Table 5.7 on page 39. Pages may be programmed in any order within a block.

If a Multiplane Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the

interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete

for the applicable blocks.

Document Number: 002-00676 Rev. *Q Page 19 of 81

S34ML01G1

S34ML02G1, S34ML04G1

3.4 Page Reprogram — S34ML02G1 and S34ML04G1

Page Program may result in a fail, which can be detected by Read Status Register. In this event, the host may call Page Reprogram.

This command allows the reprogramming of the same pattern of the last (failed) page into another memory locatio n. The command

sequence initiates with reprogram setup (8Bh), followed by the fi ve cycle address inp uts of the target page. If the target pattern for

the destination page is not changed compared to the last page, the program confirm can be issued (10h) without any data input

cycle, as described in Figure 3.1.

Figure 3.1 Page Reprogram

On the other hand, if the pattern bound for the target page is different from that of the previous page, data in cycles can be issued

before program confirm ‘10h’, as described in Figure 3.2.

Figure 3.2 Page Reprogram with Data Manipulation

SR[6]

I/Ox

Cycle Type

As defined for Page

Program A

I/Ox

SR[6]

Cycle Type CMD ADDR ADDR ADDR

00h C2 R1 R3

Page N

Din Din Din Din CMD

D0 D1 . . . Dn 10h

CMD Dout

70h E1

FAIL ! Page M

CMD

10h

tADL

tWB

tPROG

tWB

tPROG

ADDR

CMD ADDR ADDR ADDR ADDR

ADDR

8Bh C1 C2 R1 R3

IOx

SR[6]

Cycle Type

I/Ox

Cycle Type

As defined for Page

Program A

CMD ADDR ADDR ADDR ADDR

80h C2 R1 R3

Page N

Din Din Din Din CMD

D0 D1 . . . Dn 10h

CMD ADDR ADDR ADDR ADDR

8Bh C1 C2 R1 R3

FAIL !

Page M

CMD

10h

tADL

tWB tPROG

tWB

tPROG

CMD Dout

70h E1

Din Din Din Din

D0 D1 . . . Dn

tADL

ADDR

Document Number: 002-00676 Rev. *Q Page 20 of 81

S34ML01G1

S34ML02G1, S34ML04G1

The device supports Random Data Input within a page. The column address of next data, which will be entered, may be changed to

the address which follows the Random Data Input command (85h). Random Data In put may be operated multiple times regardless

of how many times it is done in a page.

The Program Confirm command (10h) initiates the re-programming process. The internal write sta te controller automatically

executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks.

Once the program process starts, the Read Status Register command may be issued to read the Status Register. The system

controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status R egister.

Only the Read Status command and Reset command are valid when programming is in progress. When the Page Program is

complete, the Write Status Bit (I/O0) may be checked. The internal write verify detects only errors for 1’s tha t ar e no t su cce s sfully

programmed to 0’s. The command register remains in Read Status command mode until anoth er valid command is written to the

command register.

The Page Reprogram must be issued in the same plane as the Page Program that failed. In order to program the data to a different

plane, use the Page Program operation instead. The Multiplane Page Reprogram can re-program two pages in para llel, one per

plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The command

sequence is very similar to Figure 6.13 on page 46, except that it requires the Page Reprogram Command (8Bh) instead of 80h and

81h.

If a Page Reprogram operation is interrupted by hardware reset, power failure or other means, the host must ensure that the

interrupted page is not used for further read ing or programming operations until the next uninterrupted block erase is complete.

3.5 Block Erase

The Block Erase operation is done on a block basis. Block address loadi ng is accomplished in three cycles (two cycles for

S34ML01G1) initiated by an Erase Setup command (60h). Only the block address bits are valid while the page address bits are

ignored.

The Erase Confirm command (D0h) following the block address loading initia tes the internal erasing process. This two-step

sequence of setup followed by the execution command ensures that memory contents are not accidentally erased due to external

noise conditions.

At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and erase verify. Once

the erase process starts, the Read Status Register commands (70h or 78h) may be issued to read the Status Register.

The system controller can detect the com pletion of an erase by monitoring the R/B# output, or the Status bit

(I/O6) of the Status Register. Only the Read Status commands (70h or 78h) and Reset command are valid while erasing is in

progress. When the erase operation is completed, the Write Status Bit (I/O0) may be checked. Figure 6.15 on page 47 details the

sequence.

If a Block Erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted

block is erased under continuous power conditions before that block can be trusted for further programming and reading operations.

Document Number: 002-00676 Rev. *Q Page 21 of 81

S34ML01G1

S34ML02G1, S34ML04G1

3.6 Multiplane Block Erase — S34ML02G1 and S34ML04G1

Multiplane Block Erase allows the erase of two blocks in parallel, one block per memory plane.

The Block erase setup command (60h) must be repeated two times, followed by 1st and 2nd block address respectively (3 cycles

each). As for block erase, D0h command makes embedded operation start. In this case, multipl ane erase does not need any

Dummy Busy Time between 1st and 2nd block insertion. See Table 5.7 on page 39 for performance information.

For the Multiplane Block Erase operation, the address of the first block must be within the first plane

(PLA0 = 0) and the address of the second block in the second plane (PLA0 = 1). See Figure 6.16 on page 48 for a description of the

legacy protocol. In this case, the block address bits for the first plane are all zero and the second address issued selects the block

for both planes. Figure 6.17 on page 48 describes the sequences using the ONFI protocol. For both addresses issued in this

protocol, the block address bits must be the same except for the bit(s) that select the plane.

The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or 78h). The Read Status

Register command is also available during Dummy Busy time (tDBSY). In case of failure in either erase, the fail bit of the Status

If a Multiplane Block Erase operation is inte rrupted by hardware reset, power failure or other means, the host must ensure that the

interrupted blocks are erased under continuous power conditions before those blocks can be trusted for further programming and

reading operations.

3.7 Copy Back Program

The copy back feature is intended to quickly and efficiently rewrite data stored in one page without utilizing an exte rnal memory.

Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is greatly improved.

The benefit is especially obvious when a portion of a block needs to be updated and the rest of the block also needs to be copied to

the newly assigned free block. The operation for performing a copy back is a sequential execution of page-read (without mandatory

serial access) and Copy Back Program with the address of destination page. A read operation with the ‘35h’ command and the

address of the source page moves the whole page of data into the internal data register. As soon as the device returns to the Ready

state, optional data read-out is allowed by toggling RE# (see Figure 6.18 on page 49), or the Copy Back Program command (85h)

with the address cycles of the destination page may be written. The Program Confirm command (10h) is required to actually begin

programming.

The source and the destination pages in the Copy Back Program sequence must belong to the same device plane (same PLA0 fo r

S34ML02G1 and S34ML04G1). Copy Back Read and Copy Back Program for a given plane must be between odd address pages or

between even address pages for the device to meet the program time (tPROG) specification . Cop y Back Program may not meet this

specification when copying from an odd address page (source page) to an even address page (target page) or from an even

address page (source page) to an odd addre s s page (target page).

The data input cycle for modifying a portion or multipl e distinct portions of the source page is allowed as shown in Figure 6.19

on page 49. As noted in Section 1. on page 5 the device may include an automatic EDC (for S34ML02G1 and S34ML04G1) check

during the copy back operation, to detect single bit errors in EDC units contain ed within the source page. More details on EDC

operation and limitations related to data input ha ndling during one Copy Back Program sequence are available in Section 3.8

on page 22.

If a Copy Back Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the

interrupted page is not used for further read ing or programming operations until the next uninterrupted block erase is complete.

Document Number: 002-00676 Rev. *Q Page 22 of 81

S34ML01G1

S34ML02G1, S34ML04G1

3.7.1 Multiplane Copy Back Program — S34ML02G1 and S34ML04G1

The device suppo rts Multiplane Copy Back Program with exactly the same sequence and limitations as the Page Program.

Multiplane Copy Back Program must be preceded by two single page Copy Back Read command seq uences (1st page must be

read from the 1st plane and 2nd page from the 2nd plane).

Multiplane Copy Back cannot cross plane boundaries — the contents of the source page of one device plane can be copied only to

a destination page of the same plane. EDC check is available also for Multiplane Copy Back Program only for S34ML02G1 and

S34ML04G1.

When “EDC check” is used in copy back, it must comply with some limitations related to data handling during one Multiplane Copy

Back Program sequence. Please refer to Section 3.8 on page 22 for details on EDC operation. The Multiplane Copy Back Program

sequence represented in Figure 6.20 on page 50 shows the legacy protocol. In this case, the block address bits for the first plane

are all zero and the second address issued selects the block for both planes. Figure 6.21 on page 51 describes the sequence using

the ONFI protocol. For both addresses issued in this proto c ol, the block address bits must be the same except for the bit(s) that

select the plane.

If a Multiplane Copy Back Program operation is interrupted by hardw are reset, power failure or other means, the host must ensure

that the interrupted pages are not used for furth er reading or programming operations until the next uninterrupted block erases are

complete for the applicable blocks.

3.7.2 Special Read for Copy Back — S34ML02G1 and S34ML04G1

The S34ML02G1 and S34ML04G1 devices support Special Read for Copy Back. If Cop y Back Read (described in Section 3.7 and

Section 3.7.1 on page 22) is triggered with confirm command ‘36h’ instead ‘35h’, Copy Back Read from target page(s) will be

executed with an increased intern al (VPASS) voltage.

This special feature is used in order to minimize the number of read errors due to over-program or read disturb — it shall be used

only if ECC read errors have occurred in the source page using Page Read or Copy Back Read sequences.

Excluding the Copy Back Read confirm comman d, all other features described in Section 3.7 and Section 3.7.1 for standard copy

back remain valid (including the figures referred to in those sections).

3.8 EDC Operation — S34ML02G1 and S34ML04G1

Error Detection Code check is a feature that can be used during the copy back operation (both single and multiplane) to detect

single bit errors occurring in the source page(s).

Note: The S34ML01G1 device does not support EDC.

EDC check allows detection of up to 1 single bit error every 52 8 bytes, where each 528 byte group is composed of 512

bytes of main array and 16 bytes of spare area (see Table 3.3 and Table 3.4 on pa ge 24). The described 528-byte area is

called an “EDC unit.”

In the x16 device, EDC allows detection of up to 1 single bit error every 264 words, where each 264 word group is

composed by 256 words of main array and 8 words of spare area see Table 3.3 and Table 3.4 on page 24). The described

264-word area is called “EDC unit.”

EDC results can be checked through a specific Read EDC register command, available only after issuing a Copy Back Program or a

Multiplane Copy Back Program. The EDC register can be queried during the copy back program busy time (tPROG).

For the “EDC check” feature to operate correctly, specific conditions on data input handling apply for program operations.

For the case of Page Program, Multiplane Page Program, Page Reprogram, Multiplane Page Reprogram, Cache Program, and

Multiplane Cache Program operations:

In Section 3.2 on page 17 it was explained that a number of consecutive partial program operations (NOP) is allowed within

the same page. In case this feature is used, the number of partial program operations occurring in the same EDC unit must

not exceed 1. In other words, page program operations must be performed on the whole page, or on whole EDC unit at a

time.

“Random Data Input” in a given EDC unit can be executed several times during one page program sequence, but data

cannot be written to any column address more than once before the program is initiated.

For the case of Copy Back Program or Multiplane Copy Back Program operations:

Document Number: 002-00676 Rev. *Q Page 23 of 81

S34ML01G1

S34ML02G1, S34ML04G1

If Random Data Input is applied in a given EDC unit, the entire EDC unit must be written to the page buff er. In other words,

the EDC check is possible only if the whole EDC unit is modified during one Copy Back Program sequence.

“Random Data Input” in a given EDC unit can be executed several times during one Copy Back Program sequen ce, but

data insertion in each column address of the EDC unit must not exceed 1.

If you use copy back without EDC check, none of the limitations described above apply.

After a Copy Back Program operation, the host can use Read EDC Status Register to check the status of both the program

operation and the Copy Back Read. If the EDC was valid and an error was reported in the EDC (see Table 3.2 on page 23), the host

may perform Special Read For Copy Back on the source page and attempt the Copy Back Program again. If this also fails, the host

can execute a Page Read operation in order to correct a single bit error with external ECC software or hardware.

3.8.1 Read EDC Status Register — S34ML02G1 and S34ML04G1

This operation is available only after issuing a Copy Back Progra m and it al lows the detection of errors during Copy Back Read. In

the case of multiplane copy back, it is not possible to know which of the two read operations caused the error.

After writing the Read EDC Status Register command (7Bh) to the command register, a read cycle outpu ts th e co ntent of the EDC

The operation is the same as the Read Status Register command. Refer to Table 3.2 for specific EDC Register definitions:

Table 3.2 EDC Register Coding

ID Copy Back Program Coding

0 Pass / Fail Pass: 0; Fail: 1

1 EDC status No error: 0; Error: 1

2 EDC validity Invalid: 0; Valid: 1

3NA —

4NA —

5 Ready / Busy Busy: 0; Ready: 1

6 Ready / Busy Busy: 0; Ready: 1

7 Write Protect Protected: 0; Not Protected: 1

Table 3.3 Page Organization in EDC Units

Main Field (2048 Byte) Spare Field (64 Byte)

“A” area

(1st sector) “B” area

(2nd sector) “C” area

(3rd sector) “D” area

(4th sector) “E” area

(1st sector) “F” area

(2nd sector) “G” area

(3rd sector) “H” area

(4th sector)

512 byte 512 byte 512 byte 512 byte 16 byte 16 byte 16 byte 16 byte

x16

256 words 256 words 256 words 256 words 8 words 8 words 8 words 8 words

Document Number: 002-00676 Rev. *Q Page 24 of 81

S34ML01G1

S34ML02G1, S34ML04G1

3.9 Read Status Register

The Status Register is used to retrieve the status value for the last operation issued. After writing 70 h command to the command

register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs

last. This two-line control allows the system to poll the progress of each device in multiple memory connections even when R/B#

pins are common-wired. Refer to Section 3.5 on page 25 for specific Status Register definition, and to Figure 6.22 on page 51 for

timings.

If the Read Status Register command is issued du ring multiplane operations then Status Register polling will return the combined

status value related to the ou t c ome of the operation in the two planes according to the following table:

In other words, the Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.

The command register remains in Status Read mode until further commands are issued. Therefore, if the Status Register is read

during a random read cycle, the read command (00h) must be issued before starting read cycles.

Note: The Read Status Register command shall not be used for concurrent operations in multi-die stack configurations (single CE#).

“Read Status Enhanced” shall be used instead.

3.10 Read Status Enhanced — S34ML02G1 and S34ML04G1

Read Status Enhanced is used to retrieve the status value for a previous operation in the specified plane.

Figure 6.23 on page 52 defines the Read Status Enhanced behavior and timings. The plane and die address must be specified in

the command sequence in order to retrieve the status of the die and the plane of interest.

Refer to Table 3.5 for specific Status Register definitions. The command register remain s in Status Read mode until further

commands are issued.

The Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.

Table 3.4 Page Organization in EDC Units by Address

Sector Main Field (Column 0-2047) Spare Field (Column 2048-2111)

Area Name Column Address Area Name Column Address

1st 528-byte Sector A 0-511 E 2048-2063

2nd 528-byte Sector B 512-1023 F 2064-2079

3rd 528-byte Sector C 1024-1535 G 2080-2095

4th 528-byte Sector D 1536-2047 H 2096-2111

x16

1st 256-word Sector A 0-255 E 1024-1031

2nd 256-word Sector B 256-511 F 1032-1039

3rd 256-word Sector C 512-767 G 1040-1047

4th 256-word Sector D 768-1023 H 1048-1055

Status Register Bit Composite Status Value

Bit 0, Pass/Fail OR

Bit 1, Cache Pass/Fail OR

Document Number: 002-00676 Rev. *Q Page 25 of 81

S34ML01G1

S34ML02G1, S34ML04G1

3.11 Read Status Register Field Definition

Table 3.5 below lists the meaning of each bit of the Read Status Register and Read Status Enhanced (S34ML02G1 and

S34ML04G1).

3.12 Reset

The Reset feature is executed by writing FFh to the command register. If th e device is in the Busy state during random read,

program, or erase mode, the Reset operation will abort these operations. The contents of memory cells being altered are no long er

valid, as the data may be partially programmed or erased. The command register is cleared to wait for the next command, and the

Status Register is cleared to value E0h when WP# is high or value 60h when WP# is low. If the device is already in reset state a new

Reset command will not be accepted by the command register. The R/B# pi n tra nsi ti o n s to l o w fo r tRST after the Reset command is

written. Refer to Figure 6.24 on page 52 for further detail s. Th e Status Register can also be read to determine the status of a Reset

operation.

3.13 Read Cache

Read Cache can be used to increase the read operation speed, as defined in Section 3.1 on page 17, and it cannot cross a block

boundary. As soon as the user starts to read one page, the device automatically loads the next page into the cache register. Serial

data output may be ex ecuted while data in the memory is read into the cache register. Read Cache is initiated by the Page Read

sequence (00-30h) on a page M.

After random access to the first page is complete (R/B# returned to high, or Read Status Register I/O6 switches to high), two

command sequences can be used to continue read cache:

Read Cache (command ‘31h’ only): once the command is latched into the command register (see Figure 6.26 on page 53),

device goes busy for a short time (tCBSYR), during which data of the first page is transferred from the data register to the

cache register. At the end of this phase, the cache register data can be output by toggling RE# while the next page (page

address M+1) is read from the memory array into the data register.

Read Cache Enhanced (seque nce ‘00h’ <page N address> ‘31’): once the command is latched into th e command register

(see Figure 6.27 on page 54), device goes busy for a short time (tCBSYR), during which data of the first page is transferred

from the data register to the cache register. At the end of this phase, cache register data can be output by toggling RE#

while page N is read from the memory array into the data register.

Note: The S34ML01G1 device does not support Read Cache Enhanced .

Table 3.5 Status Register Codin g

Page

Program /

Page

Reprogram

Block Erase Read Read Cache

Cache

Program /

Cache

Reprogram

Coding

0 Pass / Fail Pass / Fail NA NA Pass / Fail N Page

Pass: 0

Fail: 1

1NA NA NA NAPass / FailN - 1 Page

Pass: 0

Fail: 1

2NA NA NANANA —

3NA NA NANANA —

4NA NA NANANA —

5 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy Internal Data Operation

Active: 0

Idle: 1

6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy

Busy: 0

Ready: 1

7 Writ e Protect Write Protect NA NA W rite Protect Protected: 0

Not Protected: 1

Document Number: 002-00676 Rev. *Q Page 26 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Subsequent pages are read by issuing additional Read Cache or Read Cache Enhanced command sequences. If serial data output

time of one page exceeds random access time (tR), the random access time of the next page is hidden by data downloading of the

previous page.

On the other hand, if 31h is issued prior to completing the random access to the next page, the device will stay busy as long as

needed to complete rando m access to this page, transfer its contents into the cache register, and trigger the random access to the

following page.

To terminate the Read Cache operation, 3Fh command should be issued (see Figure 6.28 on page 54). This command transfers

data from the data register to the cache register without issuing next page read.

During the Read Cache operation, the device doesn't allow any other command except for 00h, 31h, 3Fh, Read SR, or Reset (FFh).

To carry out other operations, Read Cache must be terminated by the Read Cache End command (3Fh) or the device must be reset

by issuing FFh.

Read Status command (70h) may be issued to check the status of the different reg isters and the busy/ready status of the cached

read operations.

The Cache-Busy status bit I/O6 indicates when the cache register is ready to output new data.

The status bit I/O5 can be used to determine when the cell reading of the current data register contents is complete.

Note: The Read Cache and Read Cache End commands reset the column counter, thus, when RE# is toggled to output the data of

a given page, the first output data is related to the first byte of the page (column address 00h). Random Data Outp ut command can

be used to switch column address.

3.14 Cache Program

Cache Program can improve the program throughput by using the cache regi ster. The Cache Program operation cannot cross a

block boundary. The cache register allows new data to be input while the previous data that was transferred to the data re gister is

programmed into the memory array.

After the serial data input command (80h) is loaded to the command register, followed by five cycles of address, a full or partial page

of data is latched into the cache register.

Once the cache write command (15h) is loaded to the command register, the data in the cache register is transferred into the data

register for cell programming. At this time the device remains in the Busy state for a short time (tCBSYW). After all data of the cache

register is transferred into the data register, the device returns to the Ready state and allows loading the next data into the cache

The Busy time following the first sequence 80h - 15h equals the time needed to transfer the data from the cache register to the data

register. Cell programming the data of the data reg ister and loading of the next data into the cache register is consequen tly

processed through a pipeline model.

In case of any subsequent sequence 80h - 15h, transfer from the cache register to the data register is held off until cell programming

of current data register contents is complete; till this moment the device will stay in a busy state (tCBSYW).

Read Status commands (70h or 78h) may be issued to check the status of the different registers, and the pass/fail status of the

cached program operations.

The Cache-Busy status bit I/O6 indicates when the cache register is ready to accept new data.

The status bit I/O5 can be used to determine when the cell programming of the current data register contents is complete.

The Cache Program error bit I/O1 can be used to identify if the previous page (page N-1) has been successfully

programmed or not in a Cache Program operation. The status bit is valid upon I/O6 status bit changing to 1.

The error bit I/O0 is used to identify if any error has been detected by the program/erase controller while programming page

N. The status bit is valid upon I/O5 status bit changing to 1.

I/O1 may be read together with I/O0.

If the system monitors the progress of the operation only with R/B#, the last page of the target program sequence must be

programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O5

Document Number: 002-00676 Rev. *Q Page 27 of 81

S34ML01G1

S34ML02G1, S34ML04G1

must be polled to find out if the last programming is finished before starting any other operation. See Tab le 3.5 on page 25 and

Figure 6.29 on page 55 for more details.

If a Cache Program operation is interrupted by hardware reset, power failure or other means, the host must ensure th at the

interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete

for the applicable blocks.

3.15 Multiplane Cache Program — S34ML02G1 and S34ML04G 1

The Multiplane Cache Program enables high program throughput by prog ramming two pages in parallel, while exploiting the data

and cache registers of both planes to implement cache.

The command sequence can be summarized as follows:

Serial Data Input command (80h), followed by the five cycle address inputs and then serial data for the 1st page. Address

for this page must be within 1st plane (PLA0 = 0). The data of 1st page other than those to be programmed do not need to

be loaded. The device supports Random Data Input exactly like Page Program operation.

The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short

time (tDBSY).

Once device returns to ready again, 81h command must be issue d, followed by 2nd page address

(5 cycles) and its serial data input. Address for this page must be within 2nd plane (PLA0 = 1). The data of 2nd page other

than those to be programmed do not need to be loaded.

Cache Program confirm command (15h). Once the cache write command (15h) is loaded to the command register , the data

in the cache registers is transferred into the data registers for cell programming. At this time the device remains in the Busy

state for a short time (tCBSYW). After all data from the cache registers are transferred into the data registers, the device

returns to the Ready state, and allows loading the next data into the cache register through another Cache Program

command sequence.

The sequence 80h-...- 11h...-...81h...-...15h can be iterated, and each time the device will be busy for the tCBSYW time needed to

complete programming the current data register contents, and transferring the new data from the cache registers. The sequence to

end Multiplane Cache Program is 80h-...- 11h...-...81 h...-...10h.

The Multiplane Cache Program is available only within two paired blocks in separate planes. Figure 6.30 on page 56 shows the

legacy protocol for the Multiplane Cach e Program operation. In this case, the block address bits for the first plane are all zero and

the second address issued selects the block for both planes. Figure 6.31 on page 57 shows the ONFI protocol for the Multiplane

Cache Program operation. For both addresses issued in this protocol, the block address bits must be the same excep t fo r the bit(s)

that select the plane.

The user can check operation status by R/B# pin or Read Status Register commands (70h or 78h). If the user opts for 70h, Read

Status Register will provide “global” information about the operation in the two planes.

I/O6 indicates when both cache registers are ready to accept new data.

I/O5 indicates when the cell programming of the current data registers is complete.

I/O1 identifies if the previous pages in both planes (pages N-1) have been successfully programmed or not. This status bit

is valid upon I/O6 status bit changing to 1.

I/O0 identifies if any error has been detected by the program/erase controller while programming the two pages N. This

status bit is valid upon I/O5 status bit changing to 1.

See Table 3.5 on page 25 for more details.

If the system monitors the progress of the operation only with R/B#, the last pages of the target program sequence must be

programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O5

must be polled to find out if the last programming is finished before starting any other operation. Refer to Section 3.9 on page 24 for

further information.

If a Multiplane Cache Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that

the interrupted pages are not used for further read ing or programming operations until the next uninterrupted block erases are

complete for the applicable blocks.

Document Number: 002-00676 Rev. *Q Page 28 of 81

S34ML01G1

S34ML02G1, S34ML04G1

3.16 Read ID

The device contains a prod uct identification mode, initiated by writing 90h to the command register, followed by an address input of

00h.

Note: If you want to execute Read Status command (0x70) after Read ID sequence, you should input dummy command (0x00)

before Read Status command (0x70).

For the S34ML02G1 and S34ML04G1 devices, five read cycles sequentially output the manufacturer code (01h), and the device

code and 3rd, 4th, and 5th cycle ID, respectively. For the S34ML01G1 device, four read cycles sequentially output the manufacturer

code (01h), device id (F1h), 3rd cycle (00h), and 4th cycle ID of 1Dh respectively. The command register remains in Read ID mode

until further commands are issued to it. Figure 6.32 on page 58 shows the operation sequence, while Table 3.6 to Table 3.11 explain

the byte meaning.

Table 3.6 Read ID for Supported Configurations

Density Org VCC 1st 2nd 3rd 4th 5th

1 Gb

3.3V

01h F1h 00h 1Dh —

2 Gb 01h DAh 90h 95h 44h

4 Gb 01h DCh 90h 95 h 54h

1 Gb

x16

01h C1h 00h 5Dh —

2 Gb 01h CAh 90h D5h 44h

4 Gb 01h CCh 90h D5h 54h

Table 3.7 Read ID Bytes

Device Identifier Byte Description

1st Manufacturer Code

2nd Device Identifier

3rd Internal chip number, cell type, etc.

4th Page Size, Block Size, Spare Size, Serial Access Time, Organization

5th (S34ML02G1, S34ML04G1) ECC, Multiplane information

Document Number: 002-00676 Rev. *Q Page 29 of 81

S34ML01G1

S34ML02G1, S34ML04G1

3rd ID Data

4th ID Data

Table 3.8 Read ID Byte 3 Description

Descript ion I/O7 I/O6 I/ O5 I/O 4 I/O3 I/O2 I/O1 I/O 0

Internal Chip Number

0 0

0 1

1 0

1 1

Cell type

2-level cell

4-level cell

8-level cell

16-level cell

0 0

0 1

1 0

1 1

Number of simultaneously

programmed pages

0 0

0 1

1 0

Interleave program

Between multiple chips Not supported

Supported 0

Cache Program Not supported

Supported 0

Table 3.9 Read ID Byte 4 Description — S34ML01G1

Description I/ O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/ O0

Page Size

(without spare area)

1 kB

2 kB

4 kB

8 kB

0 0

0 1

1 0

1 1

Block Size

(without spare area)

64 kB

128 kB

256 kB

512 kB

0 0

0 1

1 0

1 1

Spare Area Size

(byte / 512 byte) 8

16 0

Serial Access Time

45 ns

25 ns

Reserved

Organization x8 0

x16 1

Document Number: 002-00676 Rev. *Q Page 30 of 81

S34ML01G1

S34ML02G1, S34ML04G1

5th ID Data

3.17 Read ID2

The device contains an alternate identification mode, initiated by writing 30h-65h-00h to the command register, followed by address

inputs, followed by command 30h. The address for S34ML01G1 will be

00h-02h-02h-00h. The address for S34ML02G1 and S34ML04G1 will be 00h-02h-02h-00h-00h. The ID2 data can then be read from

the device by pulsing RE#. The command register remains in Read ID2 mode until furth er commands are issued to it. Figure 6.33

on page 58 shows the Read ID2 command sequence. Read ID2 values are all 0xFs, unless specific values are requested when

ordering from Cypress.

3.18 Read ONFI Signature

To retrieve the ONFI signature, the command 90h together with an address of 20h shall be entered (i.e. it is not valid to enter an

address of 00h and read 36 bytes to get the ONFI signature). The ONFI signature is the ASCII encoding of 'ONFI' where 'O' = 4Fh,

'N' = 4Eh, 'F' = 46h, and 'I' = 49h. Reading beyond four bytes yields indeterminate values. Figure 6.34 on page 59 shows the

operation sequence.

Table 3.10 Read ID Byte 4 Description — S34ML02G1 and S34ML04G1

Description I/ O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/ O0

Page Size

(without spare area)

1 kB

2 kB

4 kB

8 kB

0 0

0 1

1 0

1 1

Block Size

(without spare area)

64 kB

128 kB

256 kB

512 kB

0 0

0 1

1 0

1 1

Spare Area Size

(byte / 512 byte) 8

16 0

Serial Access Time

50 ns / 30 ns

25 ns

Reserved

Organization x8 0

x16 1

Table 3.11 Read ID Byte 5 Description — S34ML02G1 and S34ML04G1

Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

Plane Number

0 0

0 1

1 0

1 1

Plane Size

(without spare area)

64 Mb

128 Mb

256 Mb

512 Mb

1 Gb

2 Gb

4 Gb

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

Reserved 0 0 0

Document Number: 002-00676 Rev. *Q Page 31 of 81

S34ML01G1

S34ML02G1, S34ML04G1

3.19 Read Parameter Page

The device suppo rts the ONFI Read Parameter Page operation, initiated by writing ECh to the command register, followed by an

address input of 00h. The host may monitor the R/B# pin or wait for the maximum data transfer time (tR) before reading the

Parameter Page data. The command register remains in Parameter Page mode until further commands are issued to it. If the Status

Figure 6.35 on page 59 shows the operation sequence, while Table 3.12 explains the parameter fields.

For x16 devices, the upper eight I/Os are not used and are 0xFF.

Table 3.12 Parameter Page Description (Sh eet 1 of 3)

Byte O/M Description Values

Revision Information and Features Block

0-3 M

Parameter page signature

Byte 0: 4Fh, “O”

Byte 1: 4Eh, “N”

Byte 2: 46h, “F”

Byte 3: 49h, “I”

4Fh, 4Eh, 46h, 49h

4-5 M

Revision number

2-15 Reserved (0)

1 1 = supports ONFI version 1.0

0 Reserved (0)

02h, 00h

6-7 M

Features supported

5-15 Reserved (0)

4 1 = supports odd to even page Copyback

3 1 = supports interleaved operations

2 1 = supports non-sequential page programming

1 1 = supports multiple LUN operations

0 1 = supports 16-bit data bus width

S34ML01G100 (x8): 14h, 00h

S34ML02G100 (x8): 1Ch, 00h

S34ML04G100 (x8): 1Ch, 00h

S34ML01G104 (x16): 15h, 00h

S34ML02G104 (x16): 1Dh, 00h

S34ML04G104 (x16): 1Dh, 00h

8-9 M

Optional commands supported

6-15 Reserved (0)

5 1 = supports Read Unique ID

4 1 = supports Copyback

3 1 = supports Read Status Enhanced

2 1 = supports Get Feat ures and Set Features

1 1 = supports Read Cache commands

0 1 = supports Page Cache Program command

S34ML01G1: 13h, 00h

S34ML02G1: 1Bh, 00h

S34ML04G1: 1Bh, 00h

10-31 Reserved (0) 00h

Manufacturer Information Block

32-43 M Device manufacturer (12 ASCII characte rs) 53h, 50h, 41h, 4Eh, 53h, 49h,

4Fh, 4Eh, 20h, 20h, 20h, 20h

44-63 M Device model (20 ASCII characters)

S34ML01G1: 53h, 33h, 34h,

4Dh, 4Ch, 30h, 31h, 47h, 31h,

20h, 20h, 20h, 20h, 20h, 20h,

20h, 20h, 20h, 20h, 20h

S34ML02G1: 53h, 33h, 34h,

4Dh, 4Ch, 30h, 32h, 47h, 31h,

20h, 20h, 20h, 20h, 20h, 20h,

20h, 20h, 20h, 20h, 20h

S34ML04G1: 53h, 33h, 34h,

4Dh, 4Ch, 30h, 34h, 47h, 31h,

20h, 20h, 20h, 20h, 20h, 20h,

20h, 20h, 20h, 20h, 20h

64 M JEDEC manufacturer ID 01h

65-66 O Date code 00h

67-79 Reserved (0) 00h

Document Number: 002-00676 Rev. *Q Page 32 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Memory Organization Block

80-83 M Number of data bytes per page 00h, 08h, 00h, 00h

84-85 M Number of spare bytes per page 40h, 00h

86-89 M Number of data bytes per partial page 00h, 02h, 00h, 00h

90-91 M Number of spare bytes per partial page 10h, 00h

92-95 M Number of pages per block 40h, 00h, 00h, 00h

96-99 M Number of blocks per logical unit (LUN) S34ML01G1: 00h, 04h, 00h, 00h

S34ML02G1: 00h, 08h, 00h, 00h

S34ML04G1: 00h, 10h, 00h, 00h

100 M Number of logical units (LUNs) 01h

101 M

Number of address cycles

4-7 Column address cycles

0-3 Row address cycles

S34ML01G1: 22h

S34ML02G1: 23h

S34ML04G1: 23h

102 M Number of bit s per cell 01h

103-104 M Bad blocks maximum per LUN S34ML01G1: 14h, 00h

S34ML02G1: 28h, 00h

S34ML04G1: 50h, 00h

105-106 M Block endurance 01h, 05h

107 M Guaranteed valid blocks at beginning of target 01h

108-109 M Block endurance for guaranteed valid blocks 01h, 03h

110 M Number of programs per page 04h

111 M

Partial programming attributes

5-7 Reserved

4 1 = partial page layout is partial page data followed by

partial page spare

1-3 Reserved

0 1 = partial page programming has constraints

00h

112 M Number of bits ECC correctability 01h

113 M

Number of interleaved address bits

4-7 Reserved (0)

0-3 Number of interleaved address bits

S34ML01G1: 00h

S34ML02G1: 01h

S34ML04G1: 01h

114 O

Interleaved operation attributes

4-7 Reserved (0)

3 Address restrictions for program cache

2 1 = program cache supported

1 1 = no block address restrictions

0 Overlapped / concurrent interleaving support

S34ML01G1: 00h

S34ML02G1: 04h

S34ML04G1: 04h

115-127 Reserved (0) 00h

Electrical Parameters Block

128 M I/O pin capacitance 0Ah

129-130 M

Timing mode support

6-15 Reserved (0)

5 1 = suppor ts timing mode 5

4 1 = suppor ts timing mode 4

3 1 = suppor ts timing mode 3

2 1 = suppor ts timing mode 2

1 1 = suppor ts timing mode 1

0 1 = supports timing mode 0, shall be 1

1Fh, 00h

131-132 O

Program cache timing mo de support

6-15 Reserved (0)

5 1 = suppor ts timing mode 5

4 1 = suppor ts timing mode 4

3 1 = suppor ts timing mode 3

2 1 = suppor ts timing mode 2

1 1 = suppor ts timing mode 1

0 1 = suppor ts timing mode 0

1Fh, 00h

Table 3.12 Parameter Page Description (Sh eet 2 of 3)

Byte O/M Description Values

Document Number: 002-00676 Rev. *Q Page 33 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Note:

1. O” Stands for Optional, “M” for Mandatory.

3.20 One-Time Programmable (OTP) Entry

The device contains a one-time programmable (OTP) area, which is accessed by writing 29h-17h-04h-19h to the command register.

The device is then ready to accept Page Read and Page Program commands (refer to Page Read and Page Program on page 17).

The OTP area is of a single erase block size (64 pages), and hence only row addresses between 00h and 3Fh are allowed. The host

must issue the Reset command (refer to Reset on page 25) to exit the OTP area and access the normal flash array. The Block Erase

command is not allowed in the OTP area. Refer to Figure 6.36 on page 60 for more detail on the OTP Entry command sequence.

Note: The OTP feature in the S34ML01G1 does not have non-volatile protection.

4. Signal Descriptions

4.1 Data Protection and Power On / Off Sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector

disables all functions whenever VCC is below about 1.8V.

The power-up and power-down sequence is shown in Figure 6.37 on page 60, in this case VCC and VCCQ on the one hand (and VSS

and VSSQ on the other hand) are shorted together at all tim es.

The Ready/Busy signal shall be valid within 100 µs after the power supplies have reached the minimum values (as specified on),

and shall return to one with in 5 ms (max).

During this busy time, the device executes the initialization process (cam reading), and dissipates a current ICC0 (30 mA max), in

addition, it disregards all commands excluding Read Status Register (70h).

At the end of this busy time, the device defaults into “read setup”, thus if the user decides to issue a page re ad command, the 00h

command may be skipped.

The WP# pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time

of minimum 100 µs is required before the internal circuit gets ready for any co mmand sequences as shown in Figure 6.37

133-134 M tPROG Maximum page program time (µs) BCh, 02h

135-136 M tBERS Maximum block erase time (µs) S34ML01G1: B8h, 0Bh

S34ML02G1: 10h, 27h

S34ML04G1: 10h, 27h

137-138 M tR Maximum page read time (µs) 19h, 00h

139-140 M tCCS Minimum Change Column setup time (ns) 64h, 00h

141-163 Reserved (0) 00h

Vendor Block

164-165 M Vendor specific Revision number 00h

166-253 Vendor specific 00h

254-255 M Integrity CRC

S34ML01G100 (x8): FFh, 63h

S34ML02G100 (x8): 3Bh, C5h

S34ML04G100 (x8): 45h, 8Eh

S34ML01G104 (x16): 8Dh, 15h

S34ML02G104 (x16): 49h, B3h

S34ML04G104 (x16): 37h, F8h

Redundant Parameter Pages

256-511 M Value of bytes 0-255 Repeat Value of bytes 0-255

512-767 M Value of bytes 0-255 Repeat Value of bytes 0-255

768+ O Additional redundant parameter pages FFh

Table 3.12 Parameter Page Description (Sh eet 3 of 3)

Byte O/M Description Values

Document Number: 002-00676 Rev. *Q Page 34 of 81

S34ML01G1

S34ML02G1, S34ML04G1

on page 60. The two-step command sequence for

program/erase provides additional software protection.

4.2 Ready/Busy

The Ready/Busy output provides a method of indicating the completion of a page progra m, erase, copyback, or read completion.

The R/B# pin is normally high and goes to low when the device is busy (after a reset, read, program, or erase operation). It returns to

high when the internal controller has finished the operati on. The pin is an open-drain driver thereby all owing two or more R/B#

outputs to be Or-tied. Because the pull-u p resistor value is related to tr (R/B#) and the current drain during busy (ibusy), and output

load capacitance is related to tf an appropriate value can be obtained with the reference chart shown in Figure 4.1.

For example, for a particular system with 20 pF of output load, tf from VCC to VOL at 10% to 90% will be 10 ns, whereas for a

particular load of 50 pF, Cypress measured it to be 20 ns as shown in Figure 4.1.

Figure 4.1 Ready/Busy Pin Electrical Application

Rp vs. tr, tf and Rp vs. ibusy

Rp ibusy

Busy

Ready V

VOL

: 0.4V, VOH : 2.4V

Vcc

GND

Device

open drain output

R/B#

300n

200n

100n

= t

f (ns)

20 20 20 20

= t

r (ns)

ibusy [A]

[s]

1k 2k 3k 4k

= ibusy (

)

1.2

2.4

100

150

200

0.8

0.6

Rp (ohm)

@ Vcc = 3.3V, Ta = 25°C, C

=50 pF

Rp value guidence

Rp (min.) = =

Vcc (Max.) - V

(Max.) 3.2V

8mA + ∑I

OL +

∑

Rp(max) is determined by maximum permissible limit of tr.

where is the sum of the input currents of all devices tied to the R/B# pin.

Legend

Document Number: 002-00676 Rev. *Q Page 35 of 81

S34ML01G1

S34ML02G1, S34ML04G1

4.3 Write Protect Operation

Erase and program operations are aborted if WP# is driven low during busy time, and kept low for about

100 ns. Switching WP# low during this time is equivalent to issuing a Reset command (FFh). The contents of memory cells being

altered are no longer valid, as the data will be partially programmed or erased. The

R/B# pin will stay low for tRST (similarly to Figure 6.24 on page 52). At the end of this time, the command register is ready to process

the next command, and the Status Register bit I/O6 will be cleared to 1, while I/O7 value will be related to the WP# value. Refer to

Table 3.5 on page 25 for more information on device status.

Erase and program operations are enabled or disabled by setting WP# to high or low respectively, prior to issuing the setup

commands (80h or 60h). The level of WP# shall be set tWW ns prior to raising the WE# pin for the set up command, as explained in

Figure 6.38 and Figure 6.39 on page 61.

Figure 4.2 WP# Low Timing Requirements during Program/Erase Command Sequence

WE#

I/O[7:0]

WP#

Valid

> 100 ns

Sequence

Aborted

Document Number: 002-00676 Rev. *Q Page 36 of 81

S34ML01G1

S34ML02G1, S34ML04G1

5. Electrical Characteristics

5.1 Valid Blocks

5.2 Absolute Maximum Ratings

Notes:

1. Except for the rating “Operating Temperature Range”, stresses above those listed in the table Absolute Maximum Ratings “Absolute Maximum Ratings” may cause

permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating

sections of thi s specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reli ability.

2. Minimum Voltage may undershoot to -2V during transition and for less than 20 ns during transitions.

3. Maximum Voltage may overshoot to VCC+2.0V during transition and for less than 20 ns during transitions.

5.3 AC Test Conditions

Table 5.1 Valid Blocks

Device Symbol Min Typ Max Unit

S34ML01G1 NVB 1004 — 1024 Blocks

S34ML02G1 NVB 2008 — 2048 Blocks

S34ML04G1 NVB 4016 — 4096 Blocks

Table 5.2 Absolute Maximum Ratings

Parameter Symbol Value Unit

Ambient Operating Temperature (Industrial Temperature Range) TA-40 to +85 °C

Temperature under Bias TBIAS -50 to +125 °C

Storage Temperature TSTG -65 to +150 °C

Input or Output Voltage VIO (2) -0.6 to +4.6 V

Supply Voltage VCC -0.6 to +4.6 V

Table 5.3 AC Test Conditions

Parameter Value

Input Pulse Levels 0.0V to VCC

Input Rise And Fall Times 5 ns

Input And Output Timing Levels VCC / 2

Output Load (2.7V - 3.6V) 1 TTL Gate and CL = 50 pF

Document Number: 002-00676 Rev. *Q Page 37 of 81

S34ML01G1

S34ML02G1, S34ML04G1

5.4 AC Characteristics

Notes:

1. The time to Ready depends on the value of the pull-up resistor tied to R/B# pin.

2. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5 µs.

3. CE# low to high or RE# low to high can be at different times and produce three cases. Depending on which signal comes high first, either tCOH or tRHOH will be met.

4. During data output, tCEA depends partly on tCR (CE# low to RE# low). If tCR exceeds the minimum value specified, then the maximum time for tCEA may also be

exceeded (tCEA = tCR + tREA).

Table 5.4 AC Characteristics

Parameter Symbol Min Max Unit

ALE to RE# delay tAR 10 — ns

ALE hold time tALH 5—ns

ALE setup time tALS 10 — ns

Address to data loading time tADL 70 — ns

CE# low to RE# low tCR 10 — ns

CE# hold time tCH 5—ns

CE# high to output High-Z tCHZ —30ns

CLE hold time tCLH 5—ns

CLE to RE# delay tCLR 10 — ns

CLE setup time tCLS 10 — ns

CE# access time tCEA (4) —25ns

CE# high to output hold tCOH (3) 15 — ns

CE# high to ALE or CLE don't care tCSD 10 — ns

CE# setup time tCS 20 — ns

Data hold time tDH 5—ns

Data setup time tDS 10 — ns

Data transfer from cell to register tR—25µs

Output High-Z to RE# low tIR 0—ns

Read cycle time tRC 25 — ns

RE# access time tREA —20ns

RE# high hold time tREH 10 — ns

RE# high to output hold tRHOH (3) 15 — ns

RE# high to WE# low tRHW 100 — ns

RE# high to output High-Z tRHZ — 100 ns

RE# low to output hold tRLOH 5—ns

RE# pulse width tRP 12 — ns

Ready to RE# low tRR 20 — ns

Device resetting time (Read/Program/Erase) tRST —5/10/500µs

WE# high to busy tWB — 100 ns

Write cycle time tWC 25 — ns

WE# high hold time tWH 10 — ns

WE# high to RE# low tWHR 60 — ns

WE# pulse widt h tWP 12 — ns

Write protect time tWW 100 — ns

Document Number: 002-00676 Rev. *Q Page 38 of 81

S34ML01G1

S34ML02G1, S34ML04G1

5.5 DC Characteristics

Notes:

1. All VCCQ and VCC pins, and VSS and VSSQ pins respectively are shorted together.

2. Values listed in this table refe r to the complete voltag e range for VCC and VCCQ and to a single device in case of device stacking.

3. All current measurements are performed with a 0.1 µF capacitor connected between the VCC Supply Voltage pin and the VSS Ground pin.

4. Standby current measurement can be performed after the device has completed the initialization process at power up. Refer to Section 4.1 for more deta ils.

5.6 Pin Capacitance

Note:

1. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips].

Table 5.5 DC Characteristics and Operating Conditi ons

Parameter Symbol Test Conditions Min Typ Max Units

Power-On Current

(S34ML02G1, S34ML04G1 ) ICC0 Power-Up Current

(Refer to Section 4.1)—1530mA

Operating Current

Sequential

Read ICC1 tRC = see Table 5.4

CE#=VIL, IOUT = 0 mA —1530mA

Program ICC2

Normal (S34ML01G1) —1530mA

Normal (S34ML02G1) —1530mA

Normal (S34ML04G1) ——30mA

Cache (S34ML02G1) —2040mA

Cache (S34ML04G1) ——40mA

Erase ICC3

— (S34ML01G1) —1530mA

— (S34ML02G1) ——30mA

— (S34ML04G1) —1530mA

Standby Current, (TTL) ICC4 CE# = VIH,

WP# = 0V/Vcc —— 1mA

Standby Current, (CMOS) ICC5 CE# = VCC –0.2,

WP# = 0/VCC —1050µA

Input Leakage Current ILI VIN = 0 to 3.6V — — ±10 µA

Output Leakage Current ILO VOUT = 0 to 3.6V — — ±10 µA

Input High Voltage VIH —V

CC x 0.8 — VCC + 0.3 V

Input Low Voltage VIL —-0.3—V

CC x 0.2 V

Output High Voltage VOH IOH = –400 µA 2.4 — — V

Output Low Voltage VOL IOL = 2.1 mA — — 0.4 V

Output Low Current (R/B#) IOL(R/B#) VOL = 0.4V 8 10 — mA

VCC Supply Voltage

(erase and program locko ut) VLKO ——1.8—V

Table 5.6 Pin Capacitance (TA = 25°C, f=1.0 MHz)

Parameter Symbol Test Condition Min Max Unit

Input CIN VIN = 0V — 10 pF

Input / Output CIO VIL = 0V — 10 pF

Document Number: 002-00676 Rev. *Q Page 39 of 81

S34ML01G1

S34ML02G1, S34ML04G1

5.7 Program / Erase Characteristics

Notes:

1. Typical program time is defined as the time within which more than 50% of the whol e pages are programmed (VCC = 3.3V, 25°C).

2. Copy Back Read and Copy Back Program for a given plane must be between odd address pages or between even address pages for the device to meet the program

time (tPROG) specification. Copy Back Prog ram may not meet this specification when copying from an odd address page (source page) to an even address page

(target page) or from an even address page (source pa ge) to an odd address page (target page).

6. Timing Diagrams

6.1 Command Latch Cycle

Command Input bus opera tion is used to give a command to the memory device. Commands are accepted with Chip Enable low,

Command Latch Enable High, Address Latch Enable low, and Read Enable High and latched on the rising edge of Write Enable.

Moreover for commands that starts a modify operation (write/ erase) the Write Protect pin must be high.

Figure 6.1 Command Latch Cycle

Table 5.7 Program / Erase Characteristics

Parameter Description Min Typ Max Unit

Program Time / Multiplane Program Time (2) tPROG — 200 700 µs

Dummy Busy Ti me for Multiplane Program (S34ML02G1, S34ML04G1) tDBSY —0.5 1 µs

Cache Program short busy time (S34ML02G1, S34ML04G1) tCBSYW —5t

PROG µs

Number of partial Program Cycles in the same page Main + Spare NOP — — 4 Cycle

Block Erase T ime / Multiplane Erase Time (S34ML02G1, S34ML04G1) tBERS —3.510ms

Block Erase T ime (S34ML01G1) tBERS —2 3ms

Read Cache busy time tCBSYR —3t

Rµs

tCL

tCS

tWP

Command

CLE

CE#

WE#

ALE

I/Ox

tDH tDS

tALS tALH

tCLH

tCH

= Don’t Care

Document Number: 002-00676 Rev. *Q Page 40 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.2 Address Latch Cycle

Address Input bus operation allows the insertion of the memory address. To insert the 27 (x8 Device) addresses needed to access

the 1 Gb, four write cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch

Enable low, and Read Enable High and latched on the rising edge o f Wri te Ena ble. Moreover, fo r commands that start a modify

operation (write/ erase) the Write Protect pin must be hi gh.

Figure 6.2 Address Latch Cycle

6.3 Data Input Cycle Timing

Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is serially, and timed by the

Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read

Enable High, and Write Protect High and latched on the rising edge of Wri te Enable.

Figure 6.3 Input Data Latch Cycle

tCLS

tCS

tWC

tALS tALS tALS tALS tALStALHtALHtALHtALH

tWC tWC tWC

tWP tWP

tWH

tWP tWP

tWH

tWH tWH

tDS

Col.

Add1

CLE

CE#

WE#

ALE

I/Ox

tDS tDS tDS tDS

tDHtDHtDHtDHtDH

Col.

Add2

Row.

Add2

Row.

Add1

Row.

Add3

tALH

= Don’t Care

tWC

tCLH

tCH

tWP

tWH

Din

tWH

tDH tDH tDH

tDS

tDS tDS

tWP tWP

CLE

ALE

CE#

I/Ox

WE#

tALS

Din 0

Din final

= Don’t Care

Document Number: 002-00676 Rev. *Q Page 41 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.4 Data Output Cycle Timing (CLE=L, WE#=H, ALE=L, WP#=H)

Figure 6.4 Data Output Cycle Timing

Notes:

1. Transition is measured at ± 200 mV from steady state voltage with load.

2. This parameter is sampled and not 100% tested.

3. tRHOH starts to be valid when f r equency is lower than 33 MHz.

6.5 Data Output Cycle Timing (EDO Type, CLE=L, WE#=H, ALE=L)

Figure 6.5 Data Output Cycle Timing (EDO)

Notes:

1. Transition is measured at ± 200 mV from steady state voltage with load.

2. This parameter is sampled and not 100% tested.

3. tRLOH is valid when frequency is higher than 33 MHz.

4. tRHOH starts to be valid when f r equency is lower than 33 MHz.

tRC

CE#

RE#

I/Ox

R/B#

tREA

tRR

tuoDtuoDtuoD

tREA

tRHZ

tREA

tCHZ

tCOH

tRHOH

tREH

tRHZ

tRC

tRP tREH

tREA

tCR

tRLOH

tRR

tREA

tCHZ

tCOH

tRHZ

tRHOH

DoutDout

CE#

RE#

I/Ox

R/B#

= Don’t Care

Document Number: 002-00676 Rev. *Q Page 42 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.6 Page Read Operation

Figure 6.6 Page Read Operation (Read On e Page)

Note:

1. If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data can be read from the page

buffer.

CE#

WE#

I/Ox

CLE

RE#

R/B#

ALE

00h Col.

Add. 1

Col.

Add. 2

Row

Add. 1

Row

Add. 2 Row

Add. 3 30h Dout N Dout

N +1

Column Address Row Address

tCSD

tWB

tCLR

tR tRC

tRR

Busy

tAR

Dout

tRHZ

tWC

= Don’t Care

Document Number: 002-00676 Rev. *Q Page 43 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.7 Page Read Operation (Interrupted by CE#)

Figure 6.7 Page Read Operation Interrupted by CE#

CE#

WE#

I/Ox

CLE

RE#

R/B#

ALE

00h Col.

Add. 1

Col.

Add. 2

Row

Add. 1

Row

Add. 2

Row

Add. 3 30h Dout N Dout

N +1

Column Address Row Address

tCSD

tWB

tCLR

tR tRC

tRR

Busy

tAR

tCHZ

tCOH

Dout

N +2

= Don’t Care

Document Number: 002-00676 Rev. *Q Page 44 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.8 Page Read Operation Timing with CE# Don’t Care

Figure 6.8 Page Read Operation Timing with CE# Don’t Care

6.9 Page Program Operation

Figure 6.9 Page Program Operation

Note:

1. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first dat a cycle.

00h

Col.

Add. 1 Col.

Add. 2 Row

Add. 1 Row

Add. 2

Dout

N + 1

: Don’t Care (VIH or VIL)

CE#

RE# tREA

tCR

CE# don’t care

CE#

CLE

ALE

WE#

RE#

I/Ox

30h

Dout

N + 2

Dout

N + 3

Dout

N + 4 Dout

N + 5

Dout

M + 1

Dout

M + 2

R/B# tR

tRR

tRC

I/Ox

Dout

Row

Add. 3

CLE

ALE

CE#

RE#

R/B#

I/Ox

WE#

tWC

Serial Data

Input Command Column Address

Row Address Read Status

Command

Program

Command

I/O0=0 Successful Program

I/O0=1 Error in Program

1 up to m byte

Serial Input

Din

N Din

tWC

tWB tPROG

tWHR

tWC

tADL

80h Col.

Add1

Col.

Add2

Row.

Add1

Row.

Add2 h07h01 I/O0

Row.

Add3

= Don’t Care

Document Number: 002-00676 Rev. *Q Page 45 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.10 Page Program Operation Timing with CE# Don’t Care

Figure 6. 10 Page Program Operation Timing with CE# Don’t Care

6.11 Page Program Operation with Random Data Input

Figure 6. 11 Random Data Input

Notes:

1. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first dat a cycle.

2. For EDC operation only one Random Data Inpu t is allowed at each EDC Unit.

80h Col.

Add. 1 Col.

Add. 2 Row

Add. 1 Row

Add. 2 Din

Din

N + 1

Din

P + 1

Din

R10h

: Don’t Care

CE#

WE# tWP

tCS tCH

CE# don’t care

CE#

CLE

ALE

WE#

RE#

I/Ox Row

Add. 3

CLE

ALE

CE#

RE#

R/B#

I/Ox

WE#

80h Din

Din

MDin

JDin

85h 10h 70h

Serial Data

Input Command

Random Data

Input Command

Column Address Column Address Serial Input Program

Command

Read Status

Command

tPROG

IO0

tWB

Col.

Add1

Col.

Add2

Row

Add1

Row

Add2

Row

Add3

Col.

Add1

Col.

Add2

tADL

Row Address

tWC tWC

tADL

tWC

tWHR

= Don’t Care

Document Number: 002-00676 Rev. *Q Page 46 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.12 Random Data Output In a Page

Figure 6.12 Random Data Output

6.13 Multiplane Page Program Operation — S34ML02G1 and S34ML04G1

Figure 6.13 Multiplane Page Program

Notes:

1. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.

2. A18 is the plane address bit for x8 devices. A17 is the plane address bit for x16 devices.

CE#

WE#

I/Ox

CLE

RE#

R/B#

ALE

00h Col.

Add. 1

Col.

Add. 2

Row

Add. 1

Row

Add. 2

Row

Add. 3 30h Dout N Dout

N +1 05h Col.

Add. 1

Col.

Add. 2 Dout M Dout

M +1

E0h

Column Address Row Address Column Address

tCLR

tWHR

tREA

tWB tAR tRHW

tR tRC

tRR

Busy

= Don’t Care

CLE

ALE

CE#

RE#

R/B#

I/Ox

WE#

R/B#

I/O0~7

Ex.) Address Restriction for Multiplane Page Program

81h 70h IO

Program Confirm

Command (True)

tDBSY

Col Add 1,2 and Row Add 1,2,3

(2112 byte data)

A0 ~ A11: Valid

A12 ~ A17: Fixed ‘Low’

A18: Fixed ‘Low’

A19 ~ A28: Fixed ‘Low’

Serial Data

Input Command Column Address Page Row Address 1 up to 2112 byte

Data Serial Input

Program

Command

(Dummy)

11h 10h

Din

NDin

MDin

NDin

Col.

Add1

80h Col.

Add2

Row

Add1

Row

Add2 Row

Add3

tWB tPROG

tWB tDBSY

Col.

Add1 Col.

Add2

Row

Add1

Row

Add2 Row

Add3

tWC

Read Staus

Command

tWHR

tPROG

80h Address & Data Input 11h

Col Add 1,2 and Row Add 1,2,3

(2112 byte data)

A0 ~ A11: Valid

A12 ~ A17: Valid

A18: Fixed ‘High’

A19 ~ A28: Valid

tADL

81h Address & Data Input 10h 70h

(Note 1)

Document Number: 002-00676 Rev. *Q Page 47 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Figure 6.14 Multiplane Page Program (ONFI 1.0 Protocol)

Notes:

1. C1A-C2A Column address for page A. C1A is the least significant byte.

2. R1A-R3A Row address for page A. R1A is the least significant byte.

3. D0A-DnA Data to program for page A.

4. C1B-C2B Column address for page B. C1B is the least significant byte.

5. R1B-R3B Row address for page B. R1B is the least significant byte.

6. D0B-DnB Data to program for page B.

7. The block address bits must be the same except for the bit(s) that select the plane.

6.14 Block Erase Operation

Figure 6.15 Block Erase Operation (Erase One Block)

CMD ADDR ADDR ADDRADDR

ADDR

CMD ADDR ADDR ADDRADDR

ADDR

DIN DIN DIN DIN

DIN DIN DIN DIN CMD

CMD

80h C1AC2AD0AR3AR2A

R1AD1A... DnA11h

80h C1BC2BD0B

R3BR2B

R1BD1B... DnB10h

Cycle Type

DQx

SR[6]

Cycle Type

DQx

SR[6]

tADL

tIPBSY

tADL

tPROG

tWC

CLE

CE#

WE#

ALE

RE#

I/Ox

R/B#

tWB tBERS

BUSY

Auto Block Erase

Setup Command I/O0=0 Successful Erase

I/O0=1 Error in Erase

Row Address

D0h

60h 70h I/O0

Erase Command Read Status

Command

Row Add1 Row Add2 Row Add3

tWHR

= Don’t Care

Document Number: 002-00676 Rev. *Q Page 48 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.15 Multiplane Block Erase — S34ML02G1 and S34ML04G1

Figure 6.16 Multiplane Blo ck Erase

Note:

1. A18 is the plane address bit for x8 devices. A17 is the plane address bit for x16 devices.

Figure 6.17 Multiplane Block Erase (ONFI 1.0 Protocol)

Notes:

1. R1A-R3A Row address for block on plane 0. R1A is the least significant byte.

2. R1B-R3B Row address for block on plane 1. R1B is the least significant byte.

3. The block address bits must be the same except for the bit(s) that select the plane.

Row Address

Block Erase Setup Command1 Block Erase Setup Command2 Erase Confirm Command

Read Status Command

Busy

Row Address

Ex.) Address Restriction for Multiplane Block Erase Operation

ALE

CLE

CE#

RE#

R/B#

I/Ox

WE#

R/B#

I/O0~7

tWC

60h

Row Add1,2,3 Row Add1,2,3

A12 ~ A17 : Fixed ‘Low’

A18 : Fixed ‘Low’

A19 ~ A28 : Fixed ‘Low’

A12 ~ A17 : Fixed ‘Low’

A18 : Fixed ‘High’

A19 ~ A28 : Valid

Address Address h07h06 D0h

h0Dh06 70h I/O0

Row Add1 Row Add1

Row Add2 Row Add2 3ddA woR3ddA woR

tWC

tWB tBERS

tBERS

tWHR

I/O 1 = 0 Successful Erase

I/O 1 = 1 Error in plane

60h

CLE

WE#

ALE

RE#

IOx R1AR2AR3AD1h 60h R1BR2B

SR[6]

tIEBSY

R3BD0h

tBERS

Document Number: 002-00676 Rev. *Q Page 49 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.16 Copy Back Read with Optional Data Readout

Figure 6.18 Copy Back Read with Optional Data Readout

6.17 Copy Back Program Operation With Random Data Input

Figure 6.19 Copy Back Program with Random Data Input

I/O

R/B#

Busy

(Read Busy time)

Busy

tPROG

(Program Busy time)

00h Source

Add Inputs 35h Data Outputs 85h Target

Add Inputs 10h 70h/

7Bh

SR0/

EDC Reg

Read Status Register/

EDC Register

I/O

R/B#

Busy

(Read Busy time)

Busy

tPROG

(Program Busy time)

00h Source

Add Inputs 35h 85h 2 Cycle

Add Inputs 10h

Unlimited number of repetitions

70h SR0

Read Status Register

85h Target

Add Inputs Data Data

Document Number: 002-00676 Rev. *Q Page 50 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.18 Multiplane Copy Back Program — S34ML02G1 and S34ML04G1

Figure 6.20 Multiplane Copy Back Program

Notes:

1. Copy Back Program operation is allowed only within the same memory plane.

2. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.

3. A18 is the plane address bit for x8 devices. A17 is the plane address bit for x16 devices.

I/Ox

R/B#

I/Ox

tR tR

tDBSY tPROG

00h Add. (5 cycles) 35h

Col. Add. 1, 2 and Row Add. 1, 2, 3

Source Address on Plane 0

00h Add. (5 cycles) 35h

Col. Add. 1, 2 and Row Add. 1, 2, 3

Source Address on Plane 1

85h Add. (5 cycles) 11h

Col. Add. 1, 2 and Row Add. 1, 2, 3

Destination Address

A0 ~ A11 : Fixed ‘Low’

A12 ~ A17 : Fixed ‘Low’

A18 : Fixed ‘Low’

A19 ~ A28 : Fixed ‘Low’

81h Add. (5 cycles)

Col. Add. 1, 2 and Row Add. 1, 2, 3

Destination Address

A0 ~ A11 : Fixed ‘Low’

A12 ~ A17 : Valid

A18 : Fixed ‘High’

A19 ~ A28 : Valid

10h 70h

Plane 0

(1) (3)

Data Field Spare Field

Plane 1

(2) (3)

Data Field Spare Field

Source Page

Target Page

Target Page (1) : Copy Back Read on Plane 0

(2) : Copy Back Read on Plane 1

(3) : Multiplane Copy Back Program

(Note 2)

Document Number: 002-00676 Rev. *Q Page 51 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Figure 6.21 Multiplane Copy Back Program (ONFI 1.0 Protocol)

Notes:

1. C1A-C2A Column address for page A. C1A is the least significant byte.

2. R1A-R3A Row address for page A. R1A is the least significant byte.

3. C1B-C2B Column address for page B. C1B is the least significant byte.

4. R1B-R3B Row address for page B. R1B is the least significant byte.

5. The block address bits must be the same except for the bit(s) that select the plane.

6.19 Read Status Register Timing

Figure 6.22 Status / EDC Read Cycl e

85h

CLE

WE#

ALE

RE#

IOx C1AC2 AR1AR2AR3A11h 85h C1BC2B

SR[6]

tIPBSY

R1BR2

BR3B10h

tPROG

tCLS

tCLR

tCLH

tCS

tCH

tWP

tWHR

tCEA

tDS tREA

tCHZ

tCOH

tRHZ

tRHOH

70h or 7Bh Status Output

tDH tIR

CE#

WE#

I/Ox

CLE

RE#

= Don’t Care

Document Number: 002-00676 Rev. *Q Page 52 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.20 Read Status Enhanced Timing

Figure 6.23 Read Status Enhanced Ti ming

6.21 Reset Operation Timing

Figure 6.24 Reset Operation Timing

CLE

ALE

WE#

I/O0-7

RE#

78h R1 R2 SR

tWHR

tAR

tRST

WE#

ALE

CLE

RE#

I/O7:0

R/B#

Document Number: 002-00676 Rev. *Q Page 53 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.22 Read Cache

Figure 6.25 Read Cache Operation Timing

Figure 6. 26 “Sequential” Read Cache Timing, Start (and Continuation) of Cache Operation

Page N

Page N + 1

Page N + 2

Page N + 1

Page N + 3

Page N + 2 Page N + 3

Data Cache

Page Buffer

Cell Array

Page N Page N + 1 Page N + 2 Page N + 3

789

CE#

CLE

ALE

WE#

RE#

I/Ox

R/B#

CE#

CLE

ALE

WE#

RE#

I/Ox

R/B#

123

78 96

00h Col.

Add 1

Col.

Add 2

Column Address 00h

Row

Add 1

Row

Add 2

Page Address N

30h 31h Dout

Dout

1Dout 31h Dout

Dout

Col. Add. 0

Page N + 2

3Fh Dout

Dout

1Dout

31h Dout

Dout Dout

1Dout

tWC

tWB

tR tCBSYR

tWB

tRR

tWB

Col. Add. 0 Page N Col. Add. 0

Page N + 1

tRC tRC

tRR

tCBSYR

tWB

tRR

tRC

tCBSYR

tWB

tRR

tRC

Col. Add. 0

Page N + 3

= Don’t Care

Row

Add 3

CMD CMD Dout Dout Dout CMD Dout

0Dh03 31h ... Dn 31h D0

Cycle Type

I/Ox

SR[6]

tRR

As defined for

Read

tRR

tWB

tCBSYR

tWB

tCBSYR

Document Number: 002-00676 Rev. *Q Page 54 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Figure 6.27 “Random” Read Cache Timing, Start (and Continuation) of Cache Operation

Figure 6.28 Read Cache Timing, End Of Cache Operation

Cycle Type

I/Ox

SR[6]

Cycle Type

I/Ox

SR[6]

As defined

for Read

CMD ADDR ADDR ADDR ADDR

tWB

ADDR CMD

00h C1 C2 R1 R2 R3 31h

CMD

30h

Dout Dout Dout

D0 . . . Dn

Page N

Page R

CMD ADDR ADDR ADDR ADDR ADDR CMD

00h C1 C2 R1 R2 R3 31h

Dout

tRR tWB

tCBSYR

tRR

tWB

tCBSYR

tRR

Cycle Type

I/Ox

SR[6]

As defined for

Read Cache

(Sequential or Random)

Dout Dout Dout CMD

tWB

tCBSYR

D0 . . . Dn 3Fh

CMD

31h

Dout Dout Dout

D0 . . . Dn

tRR tWB

tCBSYR

tRR

Document Number: 002-00676 Rev. *Q Page 55 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.23 Cache Program

Figure 6. 29 Cache Program

Column Address Row Address

tWB

Column Address Row Address

tCBSYW

CLE

ALE

CE#

RE#

R/B#

I/Ox

WE#

tCBSYW

Din

NDin

MDin

NDin

Column Address Row Address

10h

Din

NDin

M70h

tPROG

80h

Col.

Add1

Col.

Add2

Row.

Add1

Row.

Add2

Row.

Add3

15h 80h 15h

80h

Col.

Add1

Col.

Add2

Row.

Add1

Row.

Add2

Row.

Add3

tADL

Status

tWC

Col.

Add1

Col.

Add2

Row.

Add1

Row.

Add2

Row.

Add3

tWC

CLE

ALE

CE#

RE#

R/B#

I/Ox

WE#

Document Number: 002-00676 Rev. *Q Page 56 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.24 Multiplane Cache Program — S34ML02G1 and S34ML04G 1

Figure 6.30 Multiplane Cache Program

Notes:

1. Read Status Register (70h) is used in the figure. Read Status Enhanced (78h) can be also used.

2. A18 is the plane address bit for x8 devices. A17 is the plane address bit for x16 devices.

CLE

ALE

CE#

RE#

R/B#

I/Ox

WE#

Column Address Row Address

tWB

tWC

Column Address Row Address

tCBSYW

tDBSY

80h Col.

Add1 Col.

Add2

Row

Add1

Row

Add2 Row

Add3

81h Col.

Add1 Col.

Add2

Row

Add1

Row

Add2 Row

Add3

15h

Din

NDin

11h

Din

NDin

Column Address Row Address

tWC

Column Address Row Address

tPROG

tDBSY

11h

Din

NDin

80h 81h Col.

Add1 Col.

Add2

Row

Add1

Row

Add2 Row

Add3

10h

Din

NDin

tWB

tADL tADL

tWB

Status

70h

80h Address Input Data Input 11h 81h Address Input Data Input 15h

Command Input

A13~A17: Fixed ‘Low’

A18: Fixed ‘Low’

A19~A31: Fixed ‘Low’

A13~A17: Valid

A18: Fixed ‘High’

A19~A31: Valid

tDBSY

Return to 1

Repeat a max of 63 times

80h Address Input Data Input 11h 81h Address Input Data Input 10h

Command Input

A13~A17: Fixed ‘Low’

A18: Fixed ‘Low’

A19~A31: Fixed ‘Low’

A13~A17: Valid

A18: Fixed ‘High’

A19~A31: Valid

tDBSY tPROG

tCBSYW

RY/BY#

CLE

ALE

CE#

RE#

R/B#

I/Ox

WE#

Col.

Add1 Col.

Add2

Row

Add1

Row

Add2 Row

Add3

Document Number: 002-00676 Rev. *Q Page 57 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Figure 6.31 Multiplane Cache Program (ONFI 1.0 Protocol)

Notes:

1. The block address bits must be the same except for the bit(s) that select the plane.

2. Read Status register (70 h) is used in the f igure. Read Status Enhanced (78h) can be also used.

CLE

ALE

CE#

RE#

R/B#

IOx

WE#

Column Address Row Address

tWB

tWC

Column Address Row Address

tCBSYW

CLE

ALE

CE#

RE#

R/B#

IOx

WE#

tDBSY

11h

Din

NDin

80h Col.

Add1 Col.

Add2

Row

Add1

Row

Add2 Row

Add3

80h Col.

Add1 Col.

Add2

Row

Add1

Row

Add2 Row

Add3

15h

Din

NDin

Column Address Row Address

tWC

Column Address Row Address

tPROG

tDBSY

11h

Din

NDin

80h Col.

Add1 Col.

Add2

Row

Add1

Row

Add2 Row

Add3

80h Col.

Add1 Col.

Add2

Row

Add1

Row

Add2 Row

Add3

10h

Din

NDin

tWB

tADL tADL

tWB

Status

70h

80h Address Input Data Input 11h 80h Address Input Data Input 15h

Command Input

DBSY

Return to 1

Repeat a max of 63 times

80h Address Input Data Input 11h 80h Address Input Data Input 10h

Command Input

DBSY

PROG

CBSYW

RY/BY#

Document Number: 002-00676 Rev. *Q Page 58 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.25 Read ID O peration Timing

Figure 6.32 Read ID Operation Timing

6.26 Read ID2 Operation Timing

Figure 6.33 Read ID2 Operation Timing

Notes:

1. 4-cycle address is shown for the S34ML01G1. For S34ML02G1 and S34ML04G1, insert an additional address cycle of 00h.

2. If Status Register polling is used to determine completion of the Read ID2 operation, the Read Command (00h) must be i ssued before ID2 data can be read from the

flash.

CE#

WE#

CLE

RE#

ALE

tWHR

tAR

tREA

I/Ox

01h F1h 00h 1Dh

1 Gb Device

I/Ox

01h DAh 90h 95h

2 Gb Device

44h

I/Ox

01h DCh 90h 95h

4 Gb Device

54h

Read ID

Command

Address 1

Cycle

Maker

Code

Device

Code

3rd Cycle 4th Cycle 5th Cycle

90h

09h

00h

CE#

WE#

CLE

RE#

ALE

Read ID2

Commands

4 Cycle Address 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle

I/Ox

Read ID2

Confirm

Command

30h 65h 00h 00h 02h 02h 00h 30h ID2 Data ID2 Data ID2 Data ID2 Data ID2 Data

R/B#

Busy

(Note 1)

Document Number: 002-00676 Rev. *Q Page 59 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.27 Read ONFI Signature Timing

Figure 6.34 ONFI Signature Timing

6.28 Read Parameter Page Timing

Figure 6.35 Read Parameter Page Timing

Note:

1. If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data can be read from the page

buffer.

90h

CLE

WE#

ALE

RE#

IO0~7 20h 4Fh

4Eh 46h

WHR

49h

tREA

00h

CLE

WE#

ALE

RE#

IO0-7 P1

R/B#

......

P01

P10

P00

ECh

Document Number: 002-00676 Rev. *Q Page 60 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.29 OTP Entry Timing

Figure 6.36 OTP Entry Timing

6.30 Power On and Data Protection Timing

Figure 6. 37 Power On and Data Protec ti on Ti mi ng

Note:

1. VTH = 1.8 Vo lts.

CLE

ALE

WE#

I/O0-7

29h 17h 19h04h

VCC

Vcc(min)

100 µs max

Invalid

Operation

5 ms max

Ready/Busy

don’t

care

don’t

care

don’t

care

Vcc(min)

VTH TH

Document Number: 002-00676 Rev. *Q Page 61 of 81

S34ML01G1

S34ML02G1, S34ML04G1

6.31 WP# Handling

Figure 6.38 Program Enabling / Disabling Through WP# Handling

Figure 6.39 Erase Enabling / Disabling Through WP# Handling

80h 10h

WE#

I/Ox

WP#

R/B#

80h 10h

WE#

I/Ox

WP#

R/B#

60h D0h

WE#

I/Ox

WP#

R/B#

WE#

WP#

R/B#

I/Ox

Document Number: 002-00676 Rev. *Q Page 62 of 81

S34ML01G1

S34ML02G1, S34ML04G1

7. Physical Interface

7.1 Physical Diagram

7.1.1 48-Pin Thin Small Outline Package (TSOP1)

Figure 7. 1 TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline

5006 \ f16-038 \ 6.5.13

PACKAGE TS/TSR 48

JEDEC MO-142 (D) DD

SYMBOL MIN NOM MAX

A --- --- 1.20

A1 0.05 --- 0.15

A2 0.95 1.00 1.05

b1 0.17 0.20 0.23

b 0.17 0.22 0.27

c1 0.10 --- 0.16

c 0.10 --- 0.21

D 19.80 20.00 20.20

D1 18.30 18.40 18.50

E 11.90 12.00 12.10

e 0.50 BASIC

L 0.50 0.60 0.70

O0˚ --- 8

R 0.08 --- 0.20

N48

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS (mm).

(DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1994).

2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.

4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS

DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS

ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD

PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.

6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.

MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR THE

FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07mm.

7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10mm AND 0.25mm FROM THE LEAD TIP.

8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM

THE SEATING PLANE.

9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

Document Number: 002-00676 Rev. *Q Page 63 of 81

S34ML01G1

S34ML02G1, S34ML04G1

7.1.2 63-Pin Ball Grid Array (BGA)

Figure 7.2 VBM063 — 63-Pin BGA, 11 mm x 9 mm Package

g5011\ 16-038.25 \ 6.5.13

NOTES:

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JEP95, SECTION

3, SPP-020.

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE

"D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

n IS THE TOTAL NUMBER OF POPULATED SOLDER

BALL POSITIONS FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 “SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW “SD” OR “SE” = 0.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, “SD” = eD/2 AND “SE” = eE/2.

8. "+" INDICATES THE THEORETICAL CENTER OF

DEPOPULATED BALLS.

9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

PACKAGE VBM 063

JEDEC M0-207(M)

11.00 mm x 9.00 mm NOM

PACKAGE

SYMBOL MIN NOM MAX NOTE

A --- --- 1.00 PROFILE

A1 0.25 --- --- BALL HEIGHT

D 11.00 BSC. BODY SIZE

E 9.00 BSC. BODY SIZE

D1 8.80 BSC. MATRIX FOOTPRINT

E1 7.20 BSC. MATRIX FOOTPRINT

MD 12 MATRIX SIZE D DIRECTION

ME 10 MATRIX SIZE E DIRECTION

n 63 BALL COUNT

b 0.40 0.45 0.50 BALL DIAMETER

eE 0.80 BSC. BALL PITCH

eD 0.80 BSC. BALL PITCH

SD 0.40 BSC. SOLDER BALL PLACEMENT

SE 0.40 BSC. SOLDER BALL PLACEMENT

A3-A8,B2-B8,C1,C2,C9,C10 DEPOPULATED SOLDER BALLS

D1,D2,D9,D10,E1,E2,E9,E10

F1,F2,F9,F10,G1,G2,G9,G10

H1,H2,H9,H10,J1,J2,J9,J10

K1,K2,K9,K10

L3-L8,M3-M8

Document Number: 002-00676 Rev. *Q Page 64 of 81

S34ML01G1

S34ML02G1, S34ML04G1

8. System Interface

To simplify system interface, CE# may be unasserted during data loading or sequential data reading as shown in Figure 8.1. By

operating in this way, it is possible to connect NAND flash to a microprocessor.

Figure 8.1 Program Operation with CE# Don't Care

Figure 8.2 Read Operation with CE# Don't Care

CE# don’t care

h01 tupnI ataD (5 Cycle).ddA tratS h08 Data Input

CLE

CE#

WE#

ALE

I/Ox

CE# don’t care

h03h00

CLE

CE#

RE#

ALE

R/B#

WE#

I/Ox )laitneuqes(tuptuO ataD(5 Cycle).ddA tratS

Document Number: 002-00676 Rev. *Q Page 65 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Figure 8.3 Page Programming Within a Block

Page 63

Page 31

Page 2

Page 1

Page 0

Page 63

Page 31

Page 2

Page 1

Page 0

(64)

(32)

(3)

(2)

(1)

(64)

(1)

(3)

(32)

(1)

Data Register Data Register

From the LSB page to MSB page

DATA IN : Data (1) Data (64)

Ex.) Random page program (Optional)

DATA IN : Data (1) Data (64)

Document Number: 002-00676 Rev. *Q Page 66 of 81

S34ML01G1

S34ML02G1, S34ML04G1

9. Error Management

9.1 System Bad Block Replacement

Over the lifetime of the device, additional Bad Blocks may develop. In this case, each bad block has to be replaced by copying any

valid data to a new block. These additional Bad Blocks can be identified whenever a program or erase operation reports “Fail” in the

Status Register.

The failure of a page program operation does not affect the data in other pages in the same block, thus the block can be replaced by

re-programming the current data and copying the rest of the replaced block to an available valid block. Refer to Table 9.1 and

Figure 9.1 for the recommended procedure to follow if an error occurs during an operation.

Figure 9.1 Bad Block Replacement

Notes:

1. An error occurs on the Nth pag e of Block A during a program operation.

2. Data in Block A is copied to the same location in Block B, which is a valid block.

3. The Nth page of block A, which is in controller buff er memory, is copied into the Nth page of Block B.

4. Bad block table sh ould be updated to preve nt from erasing or programming Block A.

Table 9.1 Block Failure

Operation Recommended Procedure

Erase Block Replacement

Program Block Replacement

Read ECC (1 bit / 512+16 byte)

Data

buffer memory of the controller

N page

FFh

Data

FFh

Failure

N page

Block A Block B

(1)

(2)

(3)

Document Number: 002-00676 Rev. *Q Page 67 of 81

S34ML01G1

S34ML02G1, S34ML04G1

9.2 Bad Block Management

Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are

valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by

a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad Block Information is

written prior to shipping. Any block where the 1st byte in the spare area of the 1st or 2nd or last page does not contain FFh is a Bad

Block. That is, if the first page has an FF value and should have been a non-FF value, then the non-FF value in the second page or

the last page will indicate a bad block.The Bad Block Information must be read before any erase is attemp ted, as the Bad Block

Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information, it is

recommended to create a Bad Block table following the flowchart shown in Figure 9.2. The host is responsible to detect and track

bad blocks, both factory bad blocks and blocks that may go bad during operation. Once a block is found to be bad, data should not

be written to tha t bl o ck.The 1st block, wh i c h is placed on 00h block address is guaranteed to be a valid block.

Figure 9.2 Bad Block Management Flowchart

Note:

1. Check for FFh at the 1st byte in the spare area of the 1st, 2nd, and last pages.

Yes

Start

Block Address=

Block 0

Data

=FFh?

Last

Block?

End

Increment

Block Address

Update

Bad Block Table

(1)

Document Number: 002-00676 Rev. *Q Page 68 of 81

S34ML01G1

S34ML02G1, S34ML04G1

10. Ordering Information

The ordering part number is formed by a valid combination of the follo wing:

Valid Combinations

Valid Combinations list configuration s pl anned to be supported in volume for this device. Consult your local sales office to confirm

availability of specific valid combinations and to check on newly released combination s.

Notes:

1. BGA package marking omits the leading “S34” and the Packing Type designator from the ordering pa rt number .

2. A, V, B: 4G x16 (04 in bus width) available, but for other X16 versions contact factory.

S34ML 04G 1 00 T F I 00 0 Packing Type

0 = Tray

3 = 13” Tape and Reel

Model Number

00 = Standard Interface / ONFI (x8)

00 = Standard Interface (x16)

01 = ONFI (x16)

Temperature Range

I = Industrial (–40°C to + 85°C)

A = –40°C to + 85°C, GT-grade

V = Automotive (–40°C to + 105°C)

B = –40°C to + 105°C, GT-grade

Materials Set

F = Lead (Pb)-free

H = Lead (Pb)-free and Low Halogen

Package

B=BGA

T = TSOP

Bus Width

00 = x8 NAND, single die

04 = x16 NAND, single die

Technology

1 = Cypress NAND Revision 1 (4x nm)

Density

01G=1 Gb

02G=2 Gb

04G=4 Gb

Device Family

S34ML - 3V

Cypress SLC NAND Flash Memory for Embedded

Valid Combinations

Device

Family Density Technology Bus

Width Package

Type Temperature

Range Additional

Ordering Options Packing

Type Package

Description

S34ML

01G

1 00, 04 TF, BH I

A, V, B (2) 00, 01 0, 3 TSOP, BGA (1)02G

04G

Document Number: 002-00676 Rev. *Q Page 69 of 81

S34ML01G1

S34ML02G1, S34ML04G1

11. Revision History

Spansion Publication Number: S34ML01G1_04G1

Section Description

Revision 01 (April 16, 2012)

Initial release

Revision 02 (May 4, 2012)

Global Removed Sp ansion Confidential designation

Read Status Enhanced Updated text

Command Set Updated table: Command Set

Read ID Updated table: Read ID for Supported Configuratio ns

Legacy Read ID Removed section heading : Leg acy Read ID

Valid Blocks Updated table: Valid Blocks

Revision 03 (May 23, 2012)

Global Changed Cache Read to Read Cache

General Description Updated text

Block Diagram Combined three block diagrams into one

Addressing Updated Address Cycle Map tables

Mode Selection Updated table: Busy Time in Read; updated note

Command Set Updated table

Added ‘Supported in S34ML01G1 ’ column

Copy Back Program Updated text

Multiplane Copy Back Program Updated text

Special Read for Copy Back Updated text

Read EDC Status Register Updated text

Read ID Read ID Byte 4 Description — S34ML01G1 table: changed Number of I/O to Sp are Area Size

(byte / 512 byte)

Absolute Maximum Ratings Updated Input or Output Voltage and Supply Voltage rows

Program / Erase Characteristics Updated table

Revision 04 (May 24, 2012)

Performance Updated Perfor mance section

Read ID

Updated Read ID for Supported Configurations table

Modified tables: Read ID Byte 3 Description, Read ID Byte 4 Description – S34ML01G1,

Read ID Byte 4 Description – S34ML02G1 and S34ML 04G1, Read ID Byte 5 Description –

S34ML02G1 and S34ML04G1

AC Test Conditions Updated table

Revision 05 (May 31, 2012)

Global Data Sheet designation updated from Advance Information to Preliminary

Distinctive Characteristics/

Performance Updated Distinctive Characteristics and Performance section

Pin Description Updated Pin Description table

Addressing Updated Address Cycle Map — 1 Gb Device table

Updated Address Cycle Map — 2 Gb Device table

Updated Address Cycle Map — 4 Gb Device table

Command Set Updated Command Set table

Revision 06 (July 13, 2012)

Document Number: 002-00676 Rev. *Q Page 70 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Performance Corrected Page Read/Program - Sequential access: from 25ns (Max) to 25 ns (Min)

Connection Diagram Corrected figure: 48-Pin TSOP1 Contact x8 Device

Mode Selection Mode selection table: corrected Busy Time in Read, WE# from High to X; corrected Notes

Command Set Command Set table: added ONFI, Extended Read Status, and Read ID2 commands

Note that all ONFI information is in the Advan ced Informatio n designation

Copy Back Program Updated section

Multiplane Copy Back Program —

S34ML02G1 and S34ML04G1 Updated section

Read ID2 Added section

Read ONFI Signature Added Section

Note that all ONFI information is in the Advan ced Informatio n designation

Read Parameter Page Added section

Note that all ONFI information is in the Advan ced Informatio n designation

One-Time Programmable (OTP)

Entry Added section

Note that all ONFI information is in the Advan ced Informatio n designation

Program/Erase Characteristics Added note to table

Timing Diagrams

Rearranged section

Added timing diagrams: Multiplane Bloc k Erase (ONFI 1.0 Protocol), Multiplane Cache

Program (ONFI 1.0 Protocol), Read ID2 Operation Timing, ONFI Signature Timing, Read

Parameter Page Timing, Read ID2 Operation Timing, OTP Entry Timing

Updated timi ng diagrams: Page Read Operation (Read One Page), Page Read Operation

Intercepted by CE#, Page Read Operation Timing with CE# Don’t Care, Page Program

Operation, Page Program Operation Timing with CE# Don’t Care, Random Data Input,

Random Data Output, Multiplane Page Program, Block Erase Operation (Erase One Block),

Reset Operation Timing, Read Cache Operation Timing, Cache Program, Multiplane Cache

Program, Read ID Operation Timing

Note that all ONFI information is in the Advan ced Informatio n designation

Revision 07 (July 23, 2012)

Command Set Command Set table: changed Read ONFI Signature to ‘Yes’ for Supported on S34ML01G1

Read Parameter Page Parameter Page Description table: changed Byte 254-255 Values

Valid Blocks Valid Blocks table: removed Note 1 and Note 3

DC Characteristics DC Characteristics and Operating Conditions table:

corrected Output low voltage Test Conditions

corrected Output low current (R/B#) Typ and Max values

Revision 08 (August 2, 2012)

Global Note that all ONFI information is now in the Prelim inary designation

Read Parameter Page Parameter Page Description table: updated values for bytes 6-7, 108-109, 254-255

Physical Interface Added TSOP (2 CE 8 Gb) diagram

Added BGA diagram

Ordering Information Updated data

Appendix A Added Errata

Revision 09 (August 29, 2012)

Global Removed 8 Gb data

Added x16 I/O bus width data

Revision 10 (September 6, 2012)

Section Description

Document Number: 002-00676 Rev. *Q Page 71 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Connection Diagram 48-Pin TSOP1 Contact x8, x16 Devices figure: corrected pinouts

63-VFBGA Contact, x16 Device (Balls Down, Top View) figure: corrected pinouts, removed

note

Command Set Reorganized section

AC Characteristics Corrected TALS Min and TDS Min

Revision 11 (October 1, 2012)

Addressing Address Cycle Map — 1 Gb Device: corrected data

Address Cycle Map — 2 Gb Device: corrected data

Address Cycle Map — 4 Gb Device: corrected data

Multiplane Program — S34ML02G1

and S34ML04G1 Added text

Block Erase Added text

Multiplane B lock Erase —

S34ML02G1 and S34ML04G1 Added text

Copy Back Program Added text

Multiplane Copy Back Program —

S34ML02G1 and S34ML04G1 Added text

Multiplane Cache Program —

S34ML02G1 and S34ML04G1 Added text

Read Parameter Page Parameter Page Description table:

corrected Electrical Parameters Block values for bytes 129-130 and bytes 131-132

corrected Vendor Block values for bytes 254-255

Multiplane Page Progra m

Operation — S34ML02G1 and

S34ML04G1

Added note to Multiplane Page Program figure

Added note to Multiplane Page Pr ogram (ONFI 1.0 Protocol) figure

Multiplane B lock Erase —

S34ML02G1 and S34ML04G1 Added note to Multiplane Block Erase figure

Updated note to Multiplane Block Erase (ONFI 1.0 Protocol) figure

Multiplane Copy Back Program —

S34ML02G1 and S34ML04G1

Added note to Multiplane Copy Back Program figure

Multiplane Copy Back Program (ONFI 1.0 Protocol) figure: corrected IOx values

Updated note

Multiplane Cache Program —

S34ML02G1 and S34ML04G1

Added note to Multiplane Cache Program figure

Multiplane Cache Program (ONFI 1.0 Protocol) figure:

removed address values from RY/BY#

changed IOx value from F1h to 70h

updated note

AC Characteristics AC Characteristics table: added CE# access time

Revision 12 (November 2, 2012)

Global Data Sheet designation updated from Preliminary to Full Production

Absolute Maximum Ratings Added note

Ordering Information Valid Combinations table: added to Additional Orde ring Options

Revision 13 (December 19, 2012)

Command Set Added Page Reprogram command

Changed ReadID2 to be “Supported on S34ML0 1G1”

Page Reprogram Moved section

Added paragraph

Copy Back Program Added paragraph

Section Description

Document Number: 002-00676 Rev. *Q Page 72 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Reset Updated paragraph

ReadID2 Updated paragraph

Read Parameter Page Parameter Page Description table:

fixed Values of Bytes 6-7 and 254-255

fixed Description of Bytes 129-130 and 131-132

DC Characteristics

DC Characteristics and Operating Conditions table:

Power-On Reset Current (S34ML01G1): removed row

Operating Current: removed ICC1: tRC = tRC (min); ICC2: removed Cache (S34ML01G1)

Input Leakage Current: removed VIN = 0 to VCC (max)

Output Leakage Current: remove d VOUT = 0 to VCC (max)

Output High Voltage: removed IOH = -100 µA, IOH = 100 µA, and IOH = 400 µA rows

Output Low Voltage: removed IOL = -100 µA row

Output Low Current (R/B#): removed VOL = 0.1V row

AC Characteristics AC Characteristics table: added note

Page Read Operation Page Read Operation (Read One Page) figure: added note

Read ID2 Operation Timing Read ID2 Operation Timing figure:

replaced tWHR with tR and added R/B# timing signal

added note

Bad Block Management Added text

Bad Block Management Flowchart: updated note

Revision 14 (February 28, 2013)

Command Set Command Set table: removed ‘Nth Page’ entries

Page Program Added paragraph

Multiplane Program — S34ML02G1

and S34ML04G1 Added paragraph

Page Reprogram — S34ML02G1

and S34ML04G1 Added paragraph

Block Erase Added paragraph

Multiplane B lock Erase —

S34ML02G1 and S34ML04G1 Added paragraph

Copy Back Program Added paragraph

Multiplane Copy Back Program —

S34ML02G1 and S34ML04G1 Added paragraph

Cache Program — S34ML02G1

and S34ML04G1 Added paragraph

Multiplane Cache Program —

S34ML02G1 and S34ML04G1 Added paragraph

Read Parameter Page Added paragraph

Electrical Characteristics Valid Blocks table: updated table

AC Characteristics AC Characteristics table: corrected Min value for tCLS and Max value for tCEA

Read Status Cycle Timing Status / EDC Read Cycle figure: removed Note

Revision 15 (March 7, 2013)

Ready/Busy Updated section

Corrected Ready/Busy Pin Electrical Application figure

Revision 16 (August 9, 2013)

Section Description

Document Number: 002-00676 Rev. *Q Page 73 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Distinctive Characteristics Security: removed Serial number (uniqu e ID)

Operating Temperature: removed Commercial and Extended temperatures

Performance Updated Reliabil ity

General Description Updated section

Removed bullet: Serial number (unique identifier)

Addressing Appended Note in all Address Cycle Map tables

Added text to Bus Cycle column in all Address Cycle Map tables

Mode Selection Updated Mode Selection table

Command Set

Command Set table:

updated Acceptable Command during Busy column

Changed status of Cache Program (End) and Cache Program (Start) / (Continue) to

‘Supported on S34ML01G1’

Page Read Updated section

Page Program Changed sentence “In addition, pages must be sequentially programmed within a blo ck.” to

“Pages may be programmed in any order within a block.”

Multiplane Program — S34ML02G1

and S34ML04G1 Changed sentence “In addition, pages must be programmed sequentially within a block.” to

“Pages may be programmed in any order within a block.”

Page Reprogram — S34ML02G1

and S34ML04G1 Corrected Page Reprogram figure

Corrected Page Reprogram with Data Manipulation figure

Copy Back Program Updated section

Read Status Enhanced —

S34ML02G1 and S34ML04G1 Updated section

Read Status Register Field

Definition Updated Status Register Coding table

Cache Program Removed S34ML02G1 and S34ML04 G1 from heading

Read ID Read ID Bytes: updated Description

Read Parameter Page Parameter Page Description table: corrected Values for Bytes 8-9 and 254-255

Absolute Maximum Ratings Updated Absolute Maximum Ratings table

Multiplane Page Progra m

Operation — S34ML02G1 and

S34ML04G1

Updated Multiplane Page Program figure

Updated Multiplane Page Program (ONFI 1.0 Protoco l)

Copy Back Read with Optional

Data Readout Corrected Copy Back Read with Optional Data Readout figure

Copy Back Program Operation

With Random Data Input Updated Copy Back Program Operation With Random Data Input figure

Read Status Register Timing Removed Read Status Enhanced Cycle figure

Read Status Enhanced Timin g Removed Read Status Timing figure

Read Cache Updated Read Cache Operation Timing figure

Removed Cache Timing heading

Cache Program Updated Cache Program figure

Multiplane Cache Program —

S34ML02G1 and S34ML04G1 Update d Multiplane Cache Program figure

Updated Multiplane Cache Program (ONFI 1.0 Protocol) figure

Read Parameter Page Timing Added Note to Read Parameter Page Timing figure

One-Time Programmable (OTP)

Entry Added Note stating that the OTP feature in the S34ML01G1 does not have non-volatile

protection

Section Description

Document Number: 002-00676 Rev. *Q Page 74 of 81

S34ML01G1

S34ML02G1, S34ML04G1

Electrical Characteristics Absolute Maximum Ratings table: removed Ambient Operating Temperature (Commercial

Temperature Range) an d Ambient Operating Temperature (Extended Temperature Range)

Physical Interface Updated figures:

TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline

VBM063 — 63-Pin BGA, 11 mm x 9 mm Package

System Interface Updated Read Operation with CE# Don't Care figure

Ordering Information Updated Mate rials Set: H = Low Halogen to H = Lead (Pb)-free and Low Halo gen

Added Note to Valid Combinations table

Revision 17 (February 10, 2014)

Distinctive Characteristics Operating Temperature: Added Automotive

Read ID Updated secti on

Ordering Information Temperature Range: Added A, V, B

Valid Combinations Temperature Range: Added A, V, B

Added Note

Document History Page

Document Title: S34ML01G1, S34ML02G1, S34ML04G1 1 Gbit, 2 Gbit, 4 Gbit, 3 V SLC NAND Flash for Embedded

Document Number: 002-00676

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

** - XILA 04/16/2012 Initial release

*A - XILA 05/04/2012

Global: Removed Spansion Confidential designation

Read Status Enhanced: Updated text

Command Set: Updated table: Command Set

Read IDUpdated table: Read ID for Supported Configurations

Legacy Read ID: Removed section heading: Legacy Read ID

Valid BlocksUpdated table: Valid Blocks

*B - XILA 05/23/2012

Global: Changed C ache Read to Read Cache

General Description: Updated text

Block Diagram: Combined three block diagrams into one

Addressing: Updated Address Cycle Map tables

Mode Selection: Updated table: Busy Time in Read; updated note

Command Set: Updated table

Added ‘Supported in S34ML01G1’ column

Copy Back Program: Updated text

Multiplane Copy Back Program: Updated text

Special Read for Copy Back: Updated text

Read EDC Status Register: Updated text

Read ID: Read ID Byte 4 Description — S3 4ML01G1 table: changed Number

of I/O to Spare Area Size (byte / 512 byte)

Absolute Maximum Ratings: Updated Input or Output Voltage and Supply Volt-

age rows

Program / Erase Characteristics: Updated table

Section Description

Document Number: 002-00676 Rev. *Q Page 75 of 81

S34ML01G1

S34ML02G1, S34ML04G1

*C - XILA 05/24/2012

Performance: Updated Performance section

Read ID: Updated Read ID for Supported Configurations table

Modified tables: Read ID Byte 3 Description, Read ID Byte 4 Description –

S34ML01G1, Read ID Byte 4 Description – S34ML02G1 and S34ML04G1,

Read ID Byte 5 Description – S34ML02G1 and S34ML04G1

AC Test Conditions: Updated table

*D - XILA 05/31/2012

Global: Data Sheet designation updated fr om Advance Information to Prelimi-

nary

Distinctive Characteristics/PerformanceUpdated Distinctive Characteristics and

Performance section

Pin Description: Updated Pin Description table

Addressing: Updated Address Cycle Map — 1 Gb Device table

Updated Address Cycle Map — 2 Gb Device table

Updated Address Cycle Map — 4 Gb Device table

Command Se: Updated Command Set table

*E - XILA 07/13/2012

Performance: Corrected Page Read/Progra m - Sequential access: from 25ns

(Max) to 25 ns (Min)

Connection DiagramCorrected figure: 48-Pin TSOP1 Contact x8 Device

Mode Selection: Mode selection table: corrected Busy Time in Read, WE# from

High to X; corrected Notes

Command Set: Command Set table: added ONFI, Extende d Read Status, and

Read ID2 commands

Note that all ONFI informati on is in the Advanced Information designation

Copy Back Program: Updated section

Multiplane Copy Back Program — S34ML02G1 and S34ML04G1Updated sec-

tion

Read ID2: Added section

Read ONFI Signature: Added Section

Note that all ONFI informati on is in the Advanced Information designation

Read Parameter Page: Added section

Note that all ONFI informati on is in the Advanced Information designation

One-Time Programmable (OTP) Entry: Added section

Note that all ONFI informati on is in the Advanced Information designation

Program/Erase Characteristics: Added note to table

Timing DiagramsRearranged section

Added timing diagrams: Multiplane Block Erase (ONFI 1.0 Protocol), Multiplane

Cache Prog ram (ONFI 1. 0 Protoc ol), Read ID2 Operation T iming, ONFI Signa-

ture Timing, Read Parame ter Page Timing, Read ID2 Operation Timing, OTP

Entry Timing

Updated timing diagrams: Page Read Operation (Read One Page), Page Read

Operation Intercepted by CE#, Page Read Operation Timing with CE# Don’t

Care, Page Program Operation, Page Program Operation Timing with CE#

Don’t Care, Random Data Input, Random Data Output, Multiplane Page Pro-

gram, Block Erase Operation (Erase One Block), Reset Operation Timing, Read

Cache Operation Timing, Cache Program, Multiplane Cache Program, Read ID

Operation Timing

Note that all ONFI informati on is in the Advanced Information designation

Document History Page (Continued)

Document Title: S34ML01G1, S34ML02G1, S34ML04G1 1 Gbit, 2 Gbit, 4 Gbit, 3 V SLC NAND Flash for Embedded

Document Number: 002-00676

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

Document Number: 002-00676 Rev. *Q Page 76 of 81

S34ML01G1

S34ML02G1, S34ML04G1

*F - XILA 07/23/2012

Command Set: Command Set table: changed Read ONFI Signature to ‘Yes’ for

Supported on S34ML01G1

Read Parameter Page: Parameter Page Descrip ti on table: changed Byte 254-

255 Values

Valid Blocks: Valid Blocks table: removed No te 1 and Note 3

DC Characteristics: DC Characteristics and Operating Conditions table:

corrected Output low voltage Test Conditions

corrected Output low current (R/B#) Typ and Max values

*G - XILA 08/02/2012

Global: Note that all ONFI information is now in the Preliminary designation

Read Parameter Page: Para meter Page Descripti on table: updated values for

bytes 6-7, 108-109, 254-255

Physical Interface: Added TSOP (2 CE 8 Gb) diagram

Added BGA diagram

Ordering Information: Updated data

Appendix A: Added Errata

*H - XILA 08/29/2012

Global: Removed 8 Gb data

Added x16 I/O bus width data

Revision 10 (September 6, 2012)

Connection Diagram: 48-Pin TSOP1 Contact x8, x16 Devices figure: corrected

pinouts

63-VFBGA Contact, x16 Device (Balls Down, Top View) figure: corrected pin-

outs, removed note

Command Set: Reorganized section

AC Characteristics: Corrected TALS Min and TDS Min

Document History Page (Continued)

Document Title: S34ML01G1, S34ML02G1, S34ML04G1 1 Gbit, 2 Gbit, 4 Gbit, 3 V SLC NAND Flash for Embedded

Document Number: 002-00676

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

Document Number: 002-00676 Rev. *Q Page 77 of 81

S34ML01G1

S34ML02G1, S34ML04G1

*I - XILA 09/06/2012

AddressingAddress Cycle Map -1 Gb Device: corrected data

Address Cycle Map -2 Gb Device: corrected data

Address Cycle Map -4 Gb Device: corrected data

Multiplane Program -S34ML02G1 and S34ML04G: Added text

Block EraseAdded text

Multiplane Block Erase -S34ML02G1 and S34ML04G1: Added text

Copy Back Program: Added text

Multiplane Copy Back Program — S34ML02G1 and S34ML04G: Added text

Multiplane Cache Program — S34ML 02G1 and S34ML04G1: Added text

Read Parameter Page: Parameter Page Description table:

corrected Electrical Parameters Block values for bytes 129-130 and bytes 131-

132

corrected Vendor Block values for bytes 254-255

Multiplane Page Program Operation — S34ML02G1 and S34ML04G1Added

note to Multiplane Page Program figure

Added note to Multiplane Page Program (ONFI 1.0 Protocol) figu re

Multiplane Block Erase — S34ML02G1 and S34ML04G1: Added note to Multi-

plane Block Erase figure

Updated note to Multiplane Block Erase (ONFI 1.0 Protocol) figure

Multiplane Copy Back Program — S34ML02G1 and S34ML04G1: Added note

to Multipl ane Copy Back Program figure

Multiplane Copy Back Program (ONFI 1.0 Protocol) figure: corrected IOx values

Updated note

Multiplane Cache Program — S34ML02G1 and S34ML04G1Added note to Mul-

tiplane Cache Program figure

Multiplane Cache Program (ONF I 1.0 Protocol) figure:

removed address values from RY/BY#

changed IOx value from F1h to 70h

updated note

AC Characteristics: AC Characteristics table: added CE# access time

*J - XILA 10/01/2012 Connection Diagram: 48-Pin TSOP1 Contact x8, x16 Devices figure: corrected

pinouts

63-VFBGA Contact, x16 Device (Balls Down, Top View) figure: corrected pin-

outs, removed note

*K - XILA 11/02/2012

Global: Data Sheet designa tion updated from Preliminary to Full Produ ction

Absolute Maximum Ratings: Added note

Ordering Information: Valid Combinations table: added to Additional Ordering

Options

Document History Page (Continued)

Document Title: S34ML01G1, S34ML02G1, S34ML04G1 1 Gbit, 2 Gbit, 4 Gbit, 3 V SLC NAND Flash for Embedded

Document Number: 002-00676

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

Document Number: 002-00676 Rev. *Q Page 78 of 81

S34ML01G1

S34ML02G1, S34ML04G1

*L - XILA 12/19/2012

Command Set: Added Page Reprogram command

Changed ReadID2 to be “Supported on S34ML01G1”

Page Reprogram: Moved section

Added paragraph

Copy Back ProgramAdded paragraph

Reset: Updated paragraph

ReadID2: Updated paragraph

Read Parameter Page: Parameter Page Description table:

fixed Values of Bytes 6-7 and 254-255

fixed Description of Bytes 129-130 and 131-132

DC CharacteristicsDC Characteristics and Operating Co nditions table:

Power-On Reset Current (S34ML01G1): removed row

Operating Current: removed ICC1: tRC = tRC (min); ICC2: removed Cache

(S34ML01G1)

Input Leakage Current: removed VIN = 0 to VCC (max)

Output Leakage Current: removed VOUT = 0 to VCC (max)

Output High Voltage: removed IOH = -100 µA, IOH = 100 µA, and IOH = 400

µA rows

Output Low Voltage: removed IOL = -100 µA row

Output Low Current (R/B#): removed VOL = 0.1V row

AC Characteristics: AC Characteristics table: added note

Page Read Operation: Page Read Oper ation (Read One Page) figure : added

note

Read ID2 Operation Timin: Read ID2 Operation Timing figure:

replaced tWHR with tR and added R/B# timing signal

added note

Bad Block Management: Added text

Bad Block Management Flowchart: updated note

*M - XILA 02/28/2013

Command Set: Command Set table: removed ‘Nth Page’ entries

Page Program: Added paragraph

Multiplane Program — S34ML02G1 and S34ML04 G1: Added paragraph

Page Reprogram — S34ML02G1 and S34ML04G1: Added paragraph

Block Eras: Added paragraph

Multiplane Block Erase — S34ML02G1 and S34ML04G1: Added paragraph

Copy Back Program: Added paragraph

Multiplane Copy Back Program — S34ML02G1 and S34ML04G1: Added para-

graph

Cache Program — S34ML02G1 and S34ML04G: Added paragraph

Multiplane Cache Program — S34ML02G1 and S34ML04G1Added paragraph

Read Parameter Page: Added paragraph

Electrical Characteristics: Valid Blocks table: updated table

AC Characteristics: AC Characteristics table: corrected Min value for tCLS and

Max value for tCEA

Read Status Cycle Timing: status / EDC Read Cycle figure: removed Note

*N - XILA 03/07/2013 Ready/Busy: Update d section

Corrected Ready/Busy Pin Electrical Appli ca ti on figure

Document History Page (Continued)

Document Title: S34ML01G1, S34ML02G1, S34ML04G1 1 Gbit, 2 Gbit, 4 Gbit, 3 V SLC NAND Flash for Embedded

Document Number: 002-00676

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

Document Number: 002-00676 Rev. *Q Page 79 of 81

S34ML01G1

S34ML02G1, S34ML04G1

*O - XILA 08/09/2013

Distinctive Characteristi cs: Security -removed Serial number (unique ID)

Operating Temperature: removed Commercial and Extended temperature s

Performance: Updated Reliability

General Description: Updated section

Removed bullet: Serial number (unique identifier)

Addressing: Appended Note in all Address Cycle Map tables

Added text to Bus Cycle column in all Addr ess C ycl e Ma p tables

Mode Selection: Updated Mode Selection table

Command Set: Command Set table:

updated Acceptable Command during Busy column

Changed status of Cache Program (End) and Cache Program (S t art) / (Contin-

ue) to ‘Supported on S34ML01G1’

Page Read: Updated section

Page Program: Changed sentence “In addition, pages must be sequentially

programmed within a block.” to “Pages may be programmed in any order within

a block.”

Multiplane Program — S34ML02G1 and S34ML04G1 : Changed sentence “In

addition, pages must be programmed sequentially within a block.” to “Pages

may be programmed in any order within a block.”

Page Reprogram — S34ML02G1 and S34ML04G1: Corrected Page Repro-

gram figure

Corrected Page Reprogram with Data Manipulation figure

Copy Back Program: Updated section

Read Status Enhanced — S34ML02G1 and S34ML04G1: Updated section

Read Status Register Field Definition: Updated Status Register Coding table

Cache Program: Removed S34ML02G1 and S34ML04G1 from heading

Read ID: Read ID Bytes: updated Description

Read Parameter Page: Parameter Page Description table: corrected Values for

Bytes 8-9 and 254-2 55

Absolute Maximum Ratings: Updated Absolute Maximum Ratings table

Multiplane Page Program Operation — S34ML02G1 and S34ML04G1: Updated

Multiplane Page Program figure

Updated Multiplane Page Program (ONFI 1.0 Proto col)

Copy Back Read with Optional Data Readout: Corrected Copy Back Read with

Optional Data Readout figure

Copy Back Program Operation With Random Data Input: Updated Co py Back

Program Operation With Rando m Data Input figure

Read Status Register Timing: Removed Read Status Enhanced Cycle figure

Read Status Enhanced Timing: Removed Read Status Timing figure

Read Cache: Updated Read Cache Operation Timing figure

Removed Cache Timing heading

Cache Program:Updated Cache Program figure

Multiplane Cache Program — S34ML02G1 and S34ML04G1Updated Multi-

plane Cache Program figure

Updated Multiplane Cach e Program (ONFI 1.0 Pro tocol) figure

Read Parameter Page Timing: Added Note to Read Parameter Page Timing

figure

One-Time Programmable (OTP) Entry: Added Note stating that the OTP feature

in the S34ML01G1 does not have non-volatile protection

Document History Page (Continued)

Document Title: S34ML01G1, S34ML02G1, S34ML04G1 1 Gbit, 2 Gbit, 4 Gbit, 3 V SLC NAND Flash for Embedded

Document Number: 002-00676

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

Document Number: 002-00676 Rev. *Q Page 80 of 81

S34ML01G1

S34ML02G1, S34ML04G1

*O (Cont’d) - XILA 08/09/2013

Operating Temperature (Commercial Temperature Range) and Ambient Op er-

ating Temperature (Extended Tempe ra tu r e Range)

Physical Interface: Updated figures:

TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline

VBM063 — 63-Pin BGA, 11 mm x 9 mm Package

System Interface: Updated Read Operation with CE# Don't Care figure

Ordering Information: Updated Materials Set: H = Low Halogen to H = Lead

(Pb)-free and Low Halogen

Added Note to Valid Combinations table

*P - XILA 02/10/2014

Distinctive Characteristic: Operating Temperature: Added Automotive

Read ID: Updated section

Ordering Information: Temperature Range: Added A, V, B

Valid Combinations: Temperature Range: Added A, V, B

*Q 496 3050 XILA 11 /02/2015 Upda ted to Cypress template

Document History Page (Continued)

Document Title: S34ML01G1, S34ML02G1, S34ML04G1 1 Gbit, 2 Gbit, 4 Gbit, 3 V SLC NAND Flash for Embedded

Document Number: 002-00676

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

Document Number: 002-00676 Rev. *Q Revised November 02, 2015 Page 81 of 81

Cypress®, Spansi on®, MirrorBit®, MirrorBit® E clipse™ , ORNAND™, Hype rBus™, HyperFl ash™, and com binations ther eof, are trad emarks and re gistered tradema rks of Cypress Se miconductor Corp.

All products and company names mentioned in this document may be the trademarks of their respective holders.

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress prod uc ts are n ot war r ant ed no r inte nd ed to be used fo r

medical, life supp or t, l if e savin g, cr it ical control or safety ap pl i cations, unless pur suan t to an express written ag re em en t w it h C ypr ess. Fu rth erm ore, Cyp ress doe s not auth ori ze i t s pr o ducts for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress produ cts in life-supp ort systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress again s t all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protecti on (United States and fore ign),

United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only i n conjunction with a Cy press

integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials de scribed herei n. Cypress d oes not

assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

S34ML01G1

S34ML02G1, S34ML04G1

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

Automotive..................................cypress.com/go/automotive

Clocks & Buffers................................cypress.com/go/clocks

Interface......................................... cypress.com/go/interface

Lighting & Power Control............cypress.com/go/powerpsoc

Memory...........................................cypress.com/go/memory

PSoC....................................................cypress.com/go/psoc

Touch Sensing.................................... cypress.com/go/touch

USB Controllers....................................cypress.com/go/USB

Wireless/RF....................................cypress.com/go/wireless

PSoC® Solutions

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Cypress Developer Community

Community | Forums | Blogs | Video | Training

Technical Support

cypress.com/go/support

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Spansion Inc.:

S34ML01G100TFI000 S34ML01G100TFI003 S34ML02G100TFI000 S34ML02G100TFI003 S34ML04G100TFI000

S34ML04G100TFI003 S34ML01G100BHI000 S34ML02G100BHI000 S34ML04G100BHI000 S34ML04G100BHI003

S34ML02G100BHI003 S34ML02G100TFA000 S34ML02G104TFI010 S34ML01G100TFI503 S34ML01G100TFI500

S34ML01G100TFI900 S34ML02G104TFI013 S34ML04G100TFI903