3.3V 16K/32K/64K x 16/18
Synchron ous Dual-Por t Static RAM
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06056 Rev. ** Revised September 21, 2001
25/0251
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 6 Flow-Through/Pipelined devices
—16K x 16/18 organization (CY7C09269V/369V)
—32K x 16/18 organization (CY7C09279V/379V)
—64K x 16/18 organization (CY7C09289V/389V)
•3 Modes
—Flow-Through
—Pipelined
—Burst
• Pipelined output mode on both ports allows fast
100-MHz opera tion
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5[1, 2]/7.5[2]/9/12 ns
(max.)
• 3.3V low operating power
—Active = 115 mA (typical)
—Standby = 10 µA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
—Shorten cycle times
—Minimize bus noise
—Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
• Commercial and Indus trial tem peratu re ranges
• Available in 100-pin TQFP
Notes:
1. Call for availability.
2. See page 6 for Load Conditions.
3. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
4. I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices.
5. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices.
Logic Block Diagram
R/WL
1
0
0/1
CE0L
CE1L
LBL
OEL
UBL
1b
0/1 0b 1a 0a
ba
FT/PipeL
I/O8/9L–I/O15/17L
I/O0L–I/O7/8L
I/O
Control
Counter/
Address
Register
Decode
A0L–A13/14/15L
CLKL
ADSL
CNTENL
CNTRSTL
True Dual-Ported
RAM Array
R/WR
1
0
0/1
CE0R
CE1R
LBR
OER
UBR
1b0/1
0b1a0a ba FT/PipeR
I/O
Control
Counter/
Address
Register
Decode
14/15/16
8/9
8/9 I/O8/9R–I/O15/17R
I/O0R–I/O7/8R
A0R–A13/14/15R
CLKR
ADSR
CNTENR
CNTRSTR
14/15/16
8/9
8/9
[3]
[4]
[3]
[4]
[5] [5]
For the most recent information, visit the Cypress web site at www.cypress.com
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 2 of 19
Functional Description
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are
high-speed 3.3V synchronous CMOS 16K, 32K, and 64K x
16/18 dual-port static RAMs. Two ports are provided, permit-
ting inde pendent, si multaneous acce ss for reads an d writes to
any location in memory.[6] Registers on control, address, and
data line s allow for minim al set-up and hol d times. In pipeline d
output mode, data is registered for decreased cycle time.
Clock to d ata valid tCD2 = 6 .5 ns[1 , 2] (pi peline d). Flow-th rough
mode ca n also be used to b ypass the pipe lined output reg ister
to elimi nate acc es s latency. In flow-throu gh mod e dat a w ill be
available tCD1 = 18 ns after the address is clocked into the
device. Pipelined output or flow-through mode is selected via
the FT/Pipe pin.
Each po rt con tains a bu rst co unter on the inpu t a ddress re gis-
ter. The internal write pulse width is independent of the LOW
to HIGH trans iti on of the cloc k si gna l. The intern al w rite puls e
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clo ck cy cle wil l po wer
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelin ed mod e, one c ycl e is require d wi th CE0 LO W and CE 1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal add ress generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW to HIGH tran-
sition of that port’s clock signal. This will read/write one word
from/into each successive address location until CNTEN is
deasse rted. The coun ter can address th e entire memory array
and will loop back to the start. Counter Reset (CNTRST) is
used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Pin Configurations
Notes:
6. When writing simultaneously to the same location, the final value cannot be guaranteed.
7. This pin is NC for CY7C09269V.
8. This pin is NC for CY7C09269V and CY7C09279V.
9. For CY7C09269V and CY7C09279V , pin #18 connected to VCC is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin
compatible to an IDT 5V x16 flow-through device.
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A9R
A10R
A11R
A12R
A13R
A14R
UBR
NC
LBR
CE1R
CNTRSTR
OER
FT/PIPER
NC
A15R
GND
R/WR
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
CE0R
58
57
56
55
54
53
52
51
CY7C09279V (32K x 16)
CY7C09269V (16K x 16)
A9L
A10L
A11L
A12L
A13L
A14L
UBL
NC
LBL
CE1L
CNTRSTL
OEL
FT/PIPEL
NC
A15L
VCC
R/WL
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
CE0L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8L
A7L
A6L
A5L
A4L
A3L
CLKL
A1L
CNTENL
GND
ADSR
A0R
A1R
A0L
A2L
CLKR
CNTENR
A2R
A3R
A4R
A5R
A6R
A7R
A8R
ADSL
34 35 36 424139 403837 43 44 45 5048 494746
NC
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/01R
I/O4R
I/O2R
GND
I/O0L
I/O2L
I/O3L
I/O3R
I/O5R
I/O1L
GND
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
I/O0R
3332313029282726
CY7C09289V (64K x 16)
100-Pin TQFP (Top View)
[7]
[8]
[9][9]
[7]
[8]
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 3 of 19
Pin Configurations (continued)
Notes:
10. This pin is NC for CY7C09369V.
11. This pin is NC for CY7C09369V and CY7C09379V.
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A8R
A9R
A10R
A11R
A12R
A13R
CE0R
A15R
UBR
CNTRSTR
R/WR
FT/PIPER
I/O17R
LBR
A14R
GND
OER
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
CE1R
58
57
56
55
54
53
52
51
CY7C09379V (32K x 18)
CY7C09369V (16K x 18)
A9L
A10L
A11L
A12L
A13L
A14L
CE1L
LBL
CE0L
R/WL
OEL
I/O17L
I/O16L
UBL
A15L
VCC
FT/PIPEL
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O11L
I/O10L
CNTRSTL
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8L
A7L
A6L
A5L
A4L
A3L
CLKL
A1L
CNTENL
GND
GND
CNTENR
A0R
A0L
A2L
ADSR
CLKR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
ADSL
34 35 36 424139 403837 43 44 45 5048 494746
I/10R
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/01R
I/O4R
I/O2R
GND
I/O0L
I/O2L
I/O3L
I/O3R
I/O5R
I/O1L
GND
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
I/O0R
3332313029282726
CY7C09389V (64K x 18)
100-Pin TQFP (T op View)
[10]
[11]
[10]
[11]
Selection Guide
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-6[1, 2]
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-7[2]
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-9
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-12
fMAX2 (MHz) (Pip eli ned ) 100 83 67 50
Max. Access Time (ns)
(Clock to Data,
Pipelined)
6.5 7.5 9 12
Typical Operating
Current ICC (mA) 175 155 135 115
Typical Standby Current
for ISB1 (mA) (Both
Ports TTL Level)
25 25 20 20
Typical Standby Current
for ISB3 (µA) (Both Ports
CMOS Level)
10 µA10 µA10 µA10 µA
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 4 of 19
Maximum Ratings
(Above w hi ch the useful life may be impaired. For user g uid e-
lines, not tes ted .)
Storage Temperature................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to VCC+0.5V
DC Input Voltage......................................–0.5V to VCC+0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage........................................... >1100V
Latch-Up Current......................................................>200mA
Pin Definitions
Left Port Right Port Description
A0L–A15L A0R–A15R Address Inputs (A0–A14 for 32K, A0–A13 for 16K devices).
ADSLADSRAddress Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part usin g an external ly supplied address. Ass erting this s ignal LOW als o loads the
burst counter with the address present on the address pins.
CE0L,CE1L CE0R,CE1R Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted
to their active sta tes (CE0 ≤ VIL and CE1 ≥ VIH).
CLKLCLKRClock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENLCNTENRCounter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTLCNTRSTRCounter R eset Inpu t. Ass erting this sig nal LOW resets the b urst addre ss c ounter of its re spec-
tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O17L I/O0R–I/O17R Data Bus Input/Output (I/O0–I/O15 for x16 devices).
LBLLBRLower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte . (I/O0–I/O8 for x18, I/O0–I/O7 for x1 6) of the memory array . For read operations both
the LB and OE signals must be asserte d to driv e output data on the lower byte of the data pin s.
UBLUBRUpper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L).
OELOEROutput Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WLR/WRRead/Write Enable Inp ut. Thi s s ign al is asserte d LO W to wr ite to the du al po rt me mo ry arra y.
For read operations, assert this pin HIGH.
FT/PIPELFT/PIPERFlow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND Ground Input.
NC No Connect.
VCC Power Input.
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 3.3V ± 300 mV
Industrial –40°C to +85°C 3.3V ± 300 mV
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 5 of 19
Note:
12. CEL and CER are internal signals. To select either the left or right port, both CE0 and CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
Electrical Characteristics Ov er the Op erating Range
Parameter Description
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Unit
-6[1, 2] -7[2] -9 -12
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
VOH Output HIGH Voltage (VCC = Min.
lOH = –4.0 mA) 2.4 2.4 2.4 2.4 V
VOL Output LOW Voltage (VCC = Min.
lOH = +4.0 mA) 0.4 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.0 2.0 2.0 2.0 V
VIL Input LOW Voltage 0.8 0.8 0.8 0.8 V
IOZ Output Leakage Current –10 10 –10 10 –10 10 –10 10 µA
ICC Operating Current
(VCC = Max, IOUT = 0 mA)
Outputs Disabled
Com’l. 175 320 155 275 135 230 115 180 mA
Indust. 275 390 185 300 mA
ISB1 Standby Current (Both
Ports TTL Level)[12] CEL &
CER ≥ VIH, f = fMAX
Com’l. 25 95 25 85 20 75 20 70 mA
Indust. 85 120 35 85 mA
ISB2 Standby Current (One Port
TTL Level)[12] CEL | CER ≥
VIH, f = fMAX
Com’l. 115 175 105 165 95 155 85 140 mA
Indust. 165 210 105 165 mA
ISB3 Standby Current (Both
Ports CMOS Level)[12] CEL
& CER ≥ VCC – 0.2V, f = 0
Com’l. 10 250 10 250 10 250 10 250 µA
Indust. 10 250 10 250 µA
ISB4 Standby Current (One Port
CMOS Level)[12] CEL | CER
≥ VIH, f = fMAX
Com’l. 105 135 95 125 85 115 75 100 mA
Indust. 125 170 95 125 mA
Capacitance
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 2 5°C, f = 1 MHz,
VCC = 3.3 V 10 pF
COUT Output Capacitance 10 pF
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 6 of 19
AC Test Loads (Applicable to -6 and -7 only)[13]
Note:
13. Test Conditions: C = 10 pF.
AC Test Loads
(a) Normal Load (Load 1)
R1 = 590Ω
3.3V
OUTPUT
R2 = 435Ω
C= 30pF
VTH =1.4V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay(Load 2)
R1 = 590Ω
R2 = 435Ω
3.3V
OUTPUT
C= 5pF
RTH = 250Ω
(Used for tCKLZ, tOLZ, & tOHZ
including scope and jig)
V
TH
=1.4V
OUTPUT
C
(a) Load 1 (-6 and -7 o nly)
R = 50
Ω
Z
0
= 50
Ω
3.0V
GND 90% 90%
10%
3ns 3ns
10%
ALL INPUTPULSES
≤≤
0.00
0.1 0
0.20
0.30
0.40
0.50
0.60
1 0 1 5 20 25 30 35
(b) Load Derating Curve
Capacitance (pF)
∆
(ns) for all -7 access times
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 7 of 19
Notes:
14. Test conditions used are Load 2.
15. This parameter is guaranteed by design, but it is not production tested.
Switching Characteristics Over the Operating Range
Parameter Description
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Unit
-6[1, 2] -7[2] -9 -12
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
fMAX1 fMax Flow-Through 53454033MHz
fMAX2 fMax Pipe lined 100 83 67 50 MHz
tCYC1 Clock Cycle Time - Flow-Through 19 22 25 30 ns
tCYC2 Clock Cycle Time - Pipelin ed 10 12 15 20 ns
tCH1 Clock HIG H Time - Flow-Throu gh 6.5 7.5 12 12 ns
tCL1 Clock LOW Time - Flow-Through 6.5 7.5 12 12 ns
tCH2 Clock HIGH Time - Pipelined 4568ns
tCL2 Clock LOW Time - Pipelined 4568ns
tRClock Rise Time 3 3 3 3 ns
tFClock Fal l Time 3 3 3 3 ns
tSA Address Set-Up Time 3.5 4 4 4 ns
tHA Address Hold Time 0011ns
tSC Chip Enable Set-Up Time 3.5 4 4 4 ns
tHC Chip Enable Hold Time 0011ns
tSW R/W Set-Up Time 3.5 4 4 4 ns
tHW R/W Hold Time 0011ns
tSD Input Data Set-Up Time 3.5 4 4 4 ns
tHD Input Data Hold Time 0011ns
tSAD ADS Set-Up Time 3.5444ns
tHAD ADS Hold Time 0011ns
tSCN CNTEN Set-Up Time 3.5 4.5 5 5 ns
tHCN CNTEN Hold Time 0011ns
tSRST CNTRST Set-Up Time 3.5 4 4 4 ns
tHRST CNTRST Hold Time 0011ns
tOE Output Enable to Data Valid 8 9 10 12 ns
tOLZ[14,15] OE to Low Z 2222ns
tOHZ[14,15] OE to High Z 17171717ns
tCD1 Clock to Data Valid - Flow- Through 15 18 20 25 ns
tCD2 Clock to Data Valid - Pipelined 6.5 7.5 9 12 ns
tDC Data Output Hold After Clock HIGH2222ns
tCKZ[14,15] Clock HIGH to Output High Z 2 9 2 9 2 9 2 9 ns
tCKZ[14,15] Clock HIGH to Output Low Z 2222ns
Port to Port Delays
tCWDD Write Port Clock HIGH to Read Data Delay 30 35 40 40 ns
tCCS Clock to Clock Set-Up Time 9 10 15 15 ns
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 8 of 19
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = VIL)[16, 17, 18, 19]
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[16, 17, 18, 19]
Notes:
16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
17. ADS = VIL, CNTEN and CNTRST = VIH.
18. The o utput is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock.
19. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only .
tCH1 tCL1
tCYC1
tSC tHC
tDC
tOHZ
tOE
tSC tHC
tSW tHW
tSA tHA
tCD1 tCKHZ
tDC
tOLZ
tCKLZ
AnAn+1 An+2 An+3
QnQn+1 Qn+2
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
tCH2 tCL2
tCYC2
tSC tHC
tSW tHW
tSA tHA
AnAn+1
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
An+2 An+3
tSC tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
QnQn+1 Qn+2
1 Latency
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 9 of 19
Bank Select Pipelined Read[20, 21]
Left Port Write to Flow-Through Right Port Read[22, 23, 24, 25]
Notes:
20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
ADDRESS(B1) = ADDRESS(B2).
21. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
22. The same waveforms apply for a right port write to flow-through left port read.
23. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
24. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
25. It t CCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid
until tCCS + tCD1. tCWDD does not apply in this case.
Switching Waveforms (continued)
D3
D1
D0
D2
A0A1A2A3A4A5
D4
A0A1A2A3A4A5
tSA tHA
tSC tHC
tSA tHA
tSC tHC
tSC tHC
tSC tHC tCKHZ
tDC
tDC
tCD2
tCKLZ
tCD2 tCD2 tCKHZ
tCKLZ
tCD2 tCKHZ
tCKLZ
tCD2
tCH2 tCL2
tCYC2
CLKL
ADDRESS(B1)
CE0(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE0(B2)
tSA tHA
tSW tHW
tSD tHD
MATCH
VALID
tCCS
tSW tHW
tDC
tCWDD
tCD1
MATCH
tSA tHA
MATCH
NO
MATCH
NO
VALID VALID
tDC
tCD1
CLKL
R/WL
ADDRESSL
DATAINL
ADDRESSR
DATAOUTR
CLKR
R/WR
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 10 of 19
Pipelined Read-to-Write-to-Read (OE = VIL)[19, 26, 27, 28]
Pipelined Read-to-Write-to-Read (OE Controlled)[19, 26, 27, 28]
Notes:
26. Output state (High, LOW, or high impedance) is determined by the previous cycle control signals.
27. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
28. During “No Operation”, data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Switching Waveforms (continued)
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
tHW
tSW
tCD2 tCKHZ
tSD tHD
tCKLZ tCD2
NO OPERATIO N WRITEREAD READ
CLK
CE0
CE1
R/W
ADDRESS
DATAIN
DATAOUT
AnAn+1 An+2 An+2
Dn+2
An+3 An+4
QnQn+3
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
AnAn+1 An+2 An+3 An+4 An+5
tHW
tSW
tSD tHD
Dn+2
tCD2
tOHZ
READ READWRITE
Dn+3 tCKLZ tCD2
QnQn+4
CLK
CE0
CE1
R/W
ADDRESS
DATAIN
DATAOUT
OE
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 11 of 19
Flow-Through Read-to-Write-to-Read (OE = VIL)[17, 19, 27, 28]
Flow-Through Read-to-Write-to-Read (OE Controlled)[17, 19, 26, 27, 28]
Switching Waveforms (continued)
tCH1 tCL1
tCYC1
tSC tHC
tSW tHW
tSA tHA
tSW tHW
tSD tHD
AnAn+1 An+2 An+2 An+3 An+4
Dn+2
QnQn+1 Qn+3
tCD1 tCD1
tDC tCKHZ
tCD1 tCD1
tCKLZ tDC
READ NO
OPERATION WRITE READ
CLK
CE0
CE1
ADDRESS
R/W
DATAIN
DATAOUT
Qn
tCH1 tCL1
tCYC1
tSC tHC
tSW tHW
tSA tHA
tCD1 tDC
tOHZ
READ
AnAn+1 An+2 An+3 An+4 An+5
Dn+2 Dn+3
tSW tHW
tSD tHD
tCD1 tCD1
tCKLZ tDC
Qn+4
tOE
WRITE READ
CLK
CE0
CE1
ADDRESS
R/W
DATAIN
DATAOUT
OE
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 12 of 19
Pipelined Read with Address Counter Advance[29]
Flow-Through Read with Address Counter Advance[29]
Note:
29. CE0 and O E = VIL; CE1, R/W and CNTRST = VIH.
Switching Waveforms (continued)
COUNTER HOLD
READ WITH COUNTER
tSA tHA
tSAD tHAD
tSCN tHCN
tCH2 tCL2
tCYC2
tSAD tHAD
tSCN tHCN
Qx-1 QxQnQn+1 Qn+2 Qn+3
tDC
tCD2
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
CLK
ADDRESS
ADS
DATAOUT
CNTEN
An
tCH1 tCL1
tCYC1
tSA tHA
tSAD tHAD
tSCN tHCN
QxQnQn+1 Qn+2 Qn+3
An
tSAD tHAD
tSCN tHCN
tDC
tCD1
COUNTER HOLD
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
CLK
ADDRESS
ADS
DATAOUT
CNTEN
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 13 of 19
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[30, 31]
Notes:
30. CE0, UB, LB, and R/ W = VIL; CE1 and CNTRST = VIH.
31. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
AnAn+1 An+2 An+3 An+4
Dn+1 Dn+1 Dn+2 Dn+3 Dn+4
An
Dn
tSAD tHAD
tSCN tHCN
tSD tHD
WRIT E EX TERNA L WRITE WITH COUNTER
ADDRESS WRITE WITH
COUNTER WRITE COUNTER
HOLD
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
tSA tHA
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 14 of 19
Counter Reset (Pipelined Outputs)[19, 26, 32, 33]
Notes:
32. CE0, UB, and LB = VIL; CE1 = VIH.
33. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
CNTRST
R/W
DATAOUT Q0Q1Qn
D0
AX01A
nAn+1
tSAD tHAD
tSCN tHCN
tSRST tHRST
tSD tHD
tSW tHW
AnAn+1
tSA tHA
COUNTER
RESET WRITE
ADDRESS 0 READ
ADDRESS 0 READ
ADDR ES S 1 READ
ADDRESS n
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 15 of 19
Notes:
34. “X” = “Don’t Care”, “H” = VIH, “L” = VIL.
35. ADS, CNTEN, CNTRST = “Don’t Care”.
36. OE is an asynchronous input signal.
37. When C E changes state In the pipelined mode, deselection and read happen in the following clock cycle.
38. CE0 and O E = VIL; CE1 and R/W = VIH.
39. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
40. Counter operation is independent of CE0 and CE1.
Read/Write and Enable Operation[34, 35, 36]
Inputs Outputs
OE CLK CE0CE1R/W I/O0–I/O17 Operation
X H X X High-Z Deselected[37]
X X L X High-Z Deselected[37]
X L H L DIN Write
L L H H DOUT Read[35]
H X L H X High-Z Outputs Disabled
Address Counter Control Operation[34, 38, 39, 40]
Address Previous
Address CLK ADS CNTEN CNTRST I/O Mode Operation
X X X X L Dout(0) Reset Counter Reset to Address 0
AnX L X H Dout(n) Load Address Load into Counter
X AnH H H Dout(n) Hold External Address Blocked—Counter
Disabled
X AnH L H Dout(n+1) Increment Counter Enabled —Internal Address
Generation
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 16 of 19
Ordering Information
16K x16 3.3V Synchronous Dual-Port SRAM
Speed (ns) Ordering Code Package Name Package Type Opera ting Range
6.5[1, 2] CY7C09269V-6AC A100 100-Pin Thin Quad Flat Pack Commercial
7.5[2] CY7C09269V-7AC A100 100-Pin Thin Quad Flat Pack Commercial
9CY7C09269V-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09269V-9AI A100 100-Pin Thin Quad Flat Pack Industrial
12 CY7C09269V-12AC A100 100-Pin Thin Quad Flat Pack Commercial
32K x16 3.3V Synchronous Dual-Port SRAM
Speed (ns) Ordering Code Package Name Package Type Operating Range
6.5[1, 2] CY7C09279V-6AC A100 100-Pin Thin Quad Flat Pack Commercial
7.5[2] CY7C09279V-7AC A100 100-Pin Thin Quad Flat Pack Commercial
9 CY7C09279V-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09279V-9AI A100 100-Pin Thin Quad Flat Pack Industrial
12 CY7C09279V-12AC A100 100-Pin Thin Quad Flat Pack Commercial
64K x16 3.3V Synchronous Dual-Port SRAM
Speed (ns) Ordering Code Package Name Package Type Operating Range
6.5[1, 2] CY7C09289V-6AC A100 100-Pin Thin Quad Flat Pack Commercial
7.5[2] CY7C09289V-7AC A100 100-Pin Thin Quad Flat Pack Commercial
9 CY7C09289V-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09289V-9AI A100 100-Pin Thin Quad Flat Pack Industrial
12 CY7C09289V-12AC A100 100-Pin Thin Quad Flat Pack Commercial
16K x18 3.3V Synchronous Dual-Port SRAM
Speed (ns) Ordering Code Package Name Package Type Operating Range
6.5[1, 2] CY7C09369V-6AC A100 100-Pin Thin Quad Flat Pack Commercial
7.5[2] CY7C09369V-7AC A100 100-Pin Thin Quad Flat Pack Commercial
7.5[2] CY7C09369V-7AI A100 100-Pin Thin Quad Flat Pack Industrial
9 CY7C09369V-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09369V-9AI A100 100-Pin Thin Quad Flat Pack Industrial
12 CY7C09369V-12AC A100 100-Pin Thin Quad Flat Pack Commercial
32K x18 3.3V Synchronous Dual-Port SRAM
Speed (ns) Ordering Code Packa ge Name Package Type Operating Range
6.5[1, 2] CY7C09379V-6AC A100 100-Pin Thin Quad Flat Pack Commercial
7.5[2] CY7C09379V-7AC A100 100-Pin Thin Quad Flat Pack Commercial
9 CY7C09379V-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09379V-9AI A100 100-Pin Thin Quad Flat Pack Industrial
12 CY7C09379V-12AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 17 of 19
64K x18 3.3V Synchronous Dual-Port SRAM
Speed (ns) Ordering Code Package Name Package Type Operating Range
6.5[1, 2] CY7C09389V-6AC A100 100-Pin Thin Quad Flat Pack Commercial
7.5[2] CY7C09389V-7AC A100 100-Pin Thin Quad Flat Pack Commercial
9 CY7C09389V-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09389V-9AI A100 100-Pin Thin Quad Flat Pack Industrial
12 CY7C09389V-12AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 18 of 19
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-B
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 19 of 19
Document T itle: CY7C0926 9V/79V/89V CY7C09 369V/79V/89 V 3.3V 16K/32K/64K X 16/18 Synchronous Dual Port Static
RAM
Document Number: 38-06056
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 110215 12/18/01 SZV Change from Spec number: 38-00668 to 38-06056
