General Description
The MAX1778/MAX1880–MAX1885 multiple-output
DC-DC converters provide the regulated voltages required
by active matrix thin-film transistor (TFT) liquid crystal
displays (LCD) in a low-profile TSSOP package. One
high-power step-up converter and two low-power charge
pumps convert the 2.7V to 5.5V input voltage into three
independent output voltages. A built-in linear regulator and
VCOM buffer complete the power-supply requirements.
The main step-up converter accurately generates an
externally set output voltage up to 13V that can supply the
display’s row/column drivers. The converter’s high switch-
ing frequency and current-mode PWM architecture provide
fast transient response and allow the use of small low-
profile inductors and ceramic capacitors. The low-power
BiCMOS control circuitry and internal 14V switch (0.35Ω
N-channel MOSFET) enable efficiencies up to 91%.
The dual low-power charge pumps (MAX1778/MAX1880/
MAX1881/MAX1882 only) independently regulate one
positive output (VPOS) and one negative output (VNEG).
These low-power outputs use external diode and capaci-
tor stages (as many stages as required) to regulate output
voltages up to +40V and -40V. A unique control scheme
minimizes output ripple as well as capacitor sizes for both
charge pumps.
A resistor-programmable, 40mA, low-dropout linear
regulator (MAX1778/MAX1881/MAX1883/MAX1884 only)
provides preregulation or postregulation for any of the
supplies. For higher current applications, an external
transistor can be added. Additionally, the VCOM buffer
provides a high current output that is ideal for driving the
capacitive backplane of TFT LCD panels. The VCOM
buffer’s output voltage is preset with an internal 50%
resistive-divider or can be externally adjusted for other
voltages.
The MAX1778/MAX1880–MAX1885 are protected against
output undervoltage and thermal overload conditions by a
latched fault detection circuit that shuts down the device.
All devices are available in the ultrathin TSSOP package
(1.1mm max height).
Applications
●TFT LCD Notebook Displays
●TFT LCD Desktop Monitor Panels
Features
●500kHz/1MHz Current-Mode PWM Step-Up
Regulator
• Up to +13V Main High-Power Output
±1% Accurate
• High Efficiency (91%)
●Dual Regulated Charge-Pump Outputs (MAX1778/
MAX1880–MAX1882 only)
• Up to +40V Positive Charge-Pump Output
• Up to -40V Negative Charge-Pump Output
●Low-Dropout 40mA Linear Regulator (MAX1778/
MAX1881/MAX1883/MAX1884 only)
• Up to +15V LDO Input
●Optional Higher Current with External Transistor
●2.7V to 5.5V Input Supply
●Internal Supply Sequencing and Soft-Start
●Power-Ready Output
●Adjustable Fault-Detection Latch
●Thermal Protection (+160°C)
● 0.1μA Shutdown Current
●0.7mA IN Quiescent Current
●Ultra-Small External Components
●Thin TSSOP Package (1.1mm max height)
Typical operating Circuit appears at end of data sheet.
Pin Configurations and Selector Guide appear at end of
data sheet.
19-1979; Rev 3; 4/15
+Denotes lead(Pb)-free/RoHS-compliant package.
PART TEMP RANGE PIN-PACKAGE
MAX1778EUG -40°C to +85°C 24 TSSOP
MAX1778EUG+ -40°C to +85°C 24 TSSOP
MAX1880EUG -40°C to +85°C 24 TSSOP
MAX1881EUG -40°C to +85°C 24 TSSOP
MAX1882EUG -40°C to +85°C 24 TSSOP
MAX1883EUP -40°C to +85°C 20 TSSOP
MAX1884EUP -40°C to +85°C 20 TSSOP
MAX1885EUP -40°C to +85°C 20 TSSOP
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
Ordering Information
IN, SHDN, TGND, FLTSET to GND...........................-0.3V to +6V
DRVN to GND........................................-0.3V to (VSUPN + 0.3V)
DRVP to GND........................................-0.3V to (VSUPP + 0.3V)
PGND to GND.....................................................................±0.3V
RDY, SUPB to GND................................................-0.3V to +14V
LX, SUPP, SUPN to PGND .....................................-0.3V to +14V
SUPL to GND..........................................................-0.3V to +18V
LDOOUT to GND....................................-0.3V to (VSUPL + 0.3V)
INTG, REF, FB, FBN, FBP to GND...............-0.3V to (VIN + 0.3V)
FBL to GND.............-0.3V to the lower of (VSUPL + 0.3V) or +6V
BUFOUT, BUF+, BUF- to GND..............-0.3V to (VSUPB + 0.3V)
Continuous Power Dissipation (TA = +70°C)
20-Pin TSSOP (derate 10.9mW/°C above +70°C)......879mW
24-Pin TSSOP (derate 12.2mW/°C above +70°C)......975mW
Operating Temperature Range
MAX1778EUG, MAX1883EUP.........................-40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range..............................-65°C to +150°C
Lead Temperature (soldering, 10s)...................................+300°C
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
PGND = GND, CREF = 0.22μF, CBUF = 1μF, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Supply Range VIN 2.7 5.5 V
Input Undervoltage Threshold VUVLO VIN rising, 40mV hysteresis (typ) 2.2 2.4 2.6 V
IN Quiescent Supply Current IIN
VFB = VFBP =
1.5V, VFBN =
-0.2V
MAX1778/MAX1880/
MAX1883 (fOSC = 1MHz) 0.7 1
mA
MAX1881/MAX1882/
MAX1884/MAX1885
(fOSC = 500kHz)
0.6 1
SUPP Quiescent Current ISUPP VFBP = 1.5V
MAX1778/MAX1880
(fOSC = 1MHz) 0.4 0.7
mA
MAX1881/MAX1882
(fOSC = 500kHz) 0.3 0.5
SUPN Quiescent Current ISUPN VFBN = -0.2V
MAX1778/MAX1880
(fOSC = 1MHz) 0.4 0.7
mA
MAX1881/MAX1882
(fOSC = 500kHz) 0.3 0.5
IN Shutdown Current VSHDN = 0, VIN = 5V 0.1 10 µA
SUPP Shutdown Current VSHDN = 0, VSUPP = 13V,
MAX1778/MAX1880/MAX1881/MAX1882 0.1 10 µA
SUPN Shutdown Current VSHDN = 0, VSUPN = 13V,
MAX1778/MAX1880/MAX1881/MAX1882 0.1 10 µA
SUPL Shutdown Current VSHDN = 0, VSUPL = 13V
MAX1778/MAX1881/MAX1883/MAX1884 0.1 10 µA
SUPB Shutdown Current VSHDN = 0, VSUPB = 13V 6 13 µA
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
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Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
PGND = GND, CREF = 0.22μF, CBUF = 1μF, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAIN STEP-UP CONVERTER
Main Output Voltage Range VMAIN VIN 13 V
FB Regulation Voltage VFB
Integrator enabled, CINTG = 1000pF 1.234 1.247 1.260 V
Integrator disabled (INTG = REF) 1.220 1.280
FB Input Bias Current IFB VFB = 1.25V, INTG = GND -50 +50 nA
Operating Frequency fOSC
MAX1778/MAX1880/MAX1883 0.85 1 1.15 MHz
MAX1881/MAX1882/MAX1884/MAX1885 425 500 575 kHz
Oscillator Maximum Duty Cycle 80 85 91 %
Load Regulation ILX = 0 to 200mA,
VMAIN = 10V
Integrator enabled,
CINTG = 1000pF 0.01
%
Integrator disabled
(INTG = REF) 0.2
Line Regulation 0.1 %/V
Integrator Transconductance 317 µS
LX Switch On-Resistance RLX(ON) ILX = 100mA 0.35 0.7 Ω
LX Leakage Current ILX VLX = 13V 0.01 20 µA
LX Current Limit ILIM
Phase I = soft-start (1024/fOSC) 0.275 0.38 0.5
A
Phase II = soft-start (1024/fOSC) 0.75
Phase III = soft-start (1024/fOSC) 1.12
Phase IV = fully on (after 3072/fOSC) 1.15 1.5 1.85
Maximum RMS LX Current 1 A
Soft-Start Period tSS Power-up to the end of Phase III 3072 / fOSC s
FB Fault Trip Level Falling edge, FLTSET = GND 1.07 1.1 1.14 V
Falling edge, FLTSET = 1V 0.955 0.99 1.025
POSITIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only)
SUPP Input Supply Range VSUPP 2.7 13 V
Operating Frequency fCHP 0.5 x fOSC Hz
FBP Regulation Voltage VFBP 1.2 1.25 1.3 V
FBP Input Bias Current IFBP VFBP = 1.5V -50 +50 nA
DRVP PCH On-Resistance RPCH(ON) 5 10 Ω
DRVP NCH On-Resistance RNCH(ON)
VFBP = 1.2V 2 4 Ω
VFBP = 1.3V 20 kΩ
Maximum RMS DRVP Current 0.1 A
FBP Power-Ready Trip Level Rising edge 1.09 1.125 1.16 V
FBP Fault Trip Level Falling edge, FLTSET = GND 1.08 1.11 1.16 V
Falling edge, FLTSET = 1V 0.955 0.99 1.025
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
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Electrical Characteristics (continued)
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
PGND = GND, CREF = 0.22μF, CBUF = 1μF, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
NEGATIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only)
SUPN Input Supply Range VSUPN 2.7 13 V
Operating Frequency fCHP 0.5 x fOSC Hz
FBN Regulation Voltage VFBN -50 0 +50 mV
FBN Input Bias Current IFBN VFBN = 0 -50 +50 nA
DRVN PCH On-Resistance RPCH(ON) 5 10 Ω
DRVN NCH On-Resistance RNCH(ON)
VFBN = +50mV 2 4 Ω
VFBN = -50mV 20 kΩ
Maximum RMS DRVN Current 0.1 A
FBN Power-Ready Trip Level Falling edge 80 125 165 mV
FBN Fault Trip Level Rising edge 80 140 190 mV
LOW-DROPOUT LINEAR REGULATOR (MAX1778/MAX1881/MAX1883/MAX1884 only)
SUPL Input Supply Range VSUPL 4.5 15 V
SUPL Undervoltage Lockout Rising edge, 50mV hysteresis (typ) 3.8 4 4.3 V
SUPL Quiescent Current ISUPL ILDO = 100µA 120 220 µA
Dropout Voltage (Note 1) VDROP LDO is set to
regulate at 9V
ILDO = 40mA 130 300 mV
ILDO = 5mA 70
FBL Regulation Voltage VFBL VSUPL = 10V, LDO regulating at 9V,
ILDO = 15mA 1.235 1.25 1.265 V
LDO Load Regulation VSUPL = 10V, LDO regulating at 9V,
ILDO = 100µA to 40mA 1.2 %
LDO Line Regulation VSUPL = 4.5V to 15V, FBL = LDOOUT,
ILDO = 15mA 0.02 %/V
FBL Input Bias Current IFBL VFBL = 1.25V -0.8 +0.8 µA
LDO Current Limit ILDOLIM VSUPL = 10V, VLDOOUT = 9V, VFBL = 1.2V 40 130 220 mA
VCOM BUFFER
SUPB Input Supply Range VSUPB 4.5 13 V
SUPB Quiescent Current ISUPB VSUPB = 13V 420 850 µA
BUFOUT Leakage Current -10 +10 µA
Power-Supply Rejection Ratio PSRR VSUPB = 4.5V to 13V, VCM = 2.25V 85 98 dB
Input Common-Mode Voltage
Range VCM |VOS| < 10mV 1.2 8.8 V
Common-Mode Rejection Ratio CMRR VCM = 1.2V to 8.8V 75 dB
Input Bias Current IBIAS VCM = 5V -100 -10 +100 nA
Input Offset Current IOS VCM = 5V -100 +100 nA
Gain Bandwidth Product GBW CBUF = 1µF 13 kHz
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
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Electrical Characteristics (continued)
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
PGND = GND, CREF = 0.22μF, CBUF = 1μF, TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
Dual Mode is a trademark of Maxim Integrated Products, Inc.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Voltage VBUFOUT BUF+ = GND
IBUFOUT = 0 4.99 5.01
IBUFOUT = ±5mA 4.97 5.03 V
IBUFOUT = ±45mA 4.93 5.07
Input Offset Voltage VOS
VSUPB = 4.5V to
13V, VCM = 1.2V to
(VSUPB - 1.2V)
IBUFOUT = ±5mA -30 +30
mV
IBUFOUT = ±45mA -70 +70
Output Voltage Swing High VOH IBUFOUT = -45mA, ∆VOS = 1V 9 9.6 V
Output Voltage Swing Low VOL IBUFOUT = +45mA, ∆VOS = 1V 0.4 1 V
Peak Buffer Output Current ±150 mA
BUF+ Dual Mode™ Threshold
Voltage Falling edge, 20mV hysteresis (typ) 80 125 170 mV
REFERENCE
Reference Voltage VREF -2µA < IREF < 50µA 1.231 1.25 1.269 V
Reference Undervoltage
Threshold 0.9 1.05 1.2 V
LOGIC SIGNALS
SHDN Input Low Voltage 0.9 V
SHDN Input High Voltage 2.1 V
SHDN Input Current ISHDN 0.01 1 µA
FLTSET Input Voltage Range 0.67 x
VREF
0.85 x
VREF V
FLTSET Threshold Voltage Rising edge, 25mV hysteresis (typ) 80 125 170 mV
FLTSET Input Current VFLTSET = 1V 0.1 50 nA
RDY Output Low Voltage ISINK = 2mA 0.25 0.5 V
RDY Output High Leakage VRDY = 13V 0.01 1 µA
Thermal Shutdown Rising temperature 160 °C
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
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Electrical Characteristics (continued)
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
PGND = GND, CREF = 0.22μF, CBUF = 1μF, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
Input Supply Range VIN 2.7 5.5 V
Input Undervoltage Threshold VUVLO VIN Rising, 40mV hysteresis (typ) 2.2 2.6 V
IN Quiescent Supply Current IIN
VFB =
VFBP = 1.5V,
VFBN = -0.2V
MAX1778/MAX1880/
MAX1883 (fOSC = 1MHz) 1
mA
MAX1881/MAX1882/MAX1884/
MAX1885 (fOSC = 500kHz) 1
SUPP Quiescent Current ISUPP VFBP = 1.5V
MAX1778/MAX1880
(fOSC = 1MHz) 0.7
mA
MAX1881/MAX1882
(fOSC = 500kHz) 0.5
SUPN Quiescent Current ISUPN VFBN = -0.2V
MAX1778/MAX1880
(fOSC = 1MHz) 0.7
mA
MAX1881/MAX1882
(fOSC = 500kHz) 0.5
IN Shutdown Current VSHDN = 0, VIN = 5V 10 µA
SUPP Shutdown Current VSHDN = 0, VSUPP = 13V,
MAX1778/MAX1880/MAX1881/MAX1882 10 µA
SUPN Shutdown Current VSHDN = 0, VSUPN = 13V,
MAX1778/MAX1880/MAX1881/MAX1882 10 µA
SUPL Shutdown Current VSHDN = 0, VSUPL = 13V,
MAX1778/MAX1881/MAX1883/MAX1884 10 µA
SUPB Shutdown Current VSHDN = 0, VSUPB = 13V 13 µA
MAIN STEP-UP CONVERTER
Main Output Voltage Range VMAIN VIN 13 V
FB Regulation Voltage VFB
Integrator enabled, CINTG = 1000pF 1.223 1.269 V
Integrator disabled (INTG = REF) 1.21 1.29
FB Input Bias Current IFB VFB = 1.25V, INTG = GND -50 +50 nA
Operating Frequency FOSC
MAX1778/MAX1880/MAX1883 0.75 1.25 MHz
MAX1881/MAX1882/MAX1884/MAX1885 375 625 kHz
Oscillator Maximum Duty
Cycle 79 91 %
LX Switch On-Resistance RLX(ON) ILX = 100mA 0.7 Ω
LX Leakage Current ILX VLX = 13V 20 µA
LX Current Limit ILIM
Phase I = soft-start (1024/fOSC) 0.275 0.525 A
Phase IV = fully on (after 3072/fOSC) 1.1 2.05
FB Fault Trip Level Falling edge, FLTSET = GND 1.07 1.14 V
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
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Electrical Characteristics
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
PGND = GND, CREF = 0.22μF, CBUF = 1μF, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
POSITIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only)
SUPP Input Supply Range VSUPP 2.7 13 V
FBP Regulation Voltage VFBP 1.2 1.3 V
FBP Input Bias Current IFBP VFBP = 1.5V -50 +50 nA
DRVP PCH On-Resistance RPCH(ON) 10 Ω
DRVP NCH On-Resistance RNCH(ON)
VFBP = 1.2V 4 Ω
VFBP = 1.3V 20 kΩ
FBP Power-Ready Trip Level Rising edge 1.09 1.16 V
NEGATIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only)
SUPN Input Supply Range VSUPN 2.7 13 V
FBN Regulation Voltage VFBN -50 +50 mV
FBN Input Bias Current IFBN VFBN = 0 -50 +50 nA
DRVN PCH On-Resistance RPCH(ON) 10 Ω
DRVN NCH On-Resistance RNCH(ON)
VFBN = +50mV 4 Ω
VFBN = -50mV 20 kΩ
FBN Power-Ready Trip Level Falling edge 80 165 mV
LOW DROPOUT LINEAR REGULATOR (MAX1778/MAX1881/MAX1883/MAX1884 only)
SUPL Input Supply Range VSUPL 4.5 15 V
SUPL Undervoltage Lockout Rising edge, 50mV hysteresis (typ) 3.8 4.3 V
SUPL Quiescent Current ISUPL ILDO = 100µA 240 µA
Dropout Voltage (Note 1) VDROP LDO regulating to 9V, ILDO = 40mA 330 mV
FBL Regulation Voltage VFBL VSUPL = 10V, LDO regulating to 9V,
ILDO = 15mA 1.222 1.265 V
LDO Load Regulation VSUPL = 10V, LDO regulating to 9V,
ILDO = 100µA to 40mA 1.2 %
LDO Line Regulation VSUPL = 4.5V to 15V, FBL = LDOOUT,
ILDO = 15mA 0.02 %/V
FBL Input Bias Current IFBL VFBL = 1.25V -1.2 +1.2 µA
LDO Current Limit ILDOLIM VSUPL = 10V, VLDOOUT = 9V, VFBL = 1.2V 40 260 mA
VCOM BUFFER
SUPB Input Supply Range VSUPB 4.5 13 V
SUPB Quiescent Current ISUPB VSUPB = 13V 850 µA
BUFOUT Leakage Current -10 +10 µA
Input Common-Mode Voltage
Range VCM |VOS| < 10mV 1.2 8.8 V
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
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Electrical Characteristics (continued)
(VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND =
PGND = GND, CREF = 0.22μF, CBUF = 1μF, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
Note 1: Dropout voltage is defined as the VSUPL - VLDOOUT, when VSUPL is 100mV below the set value of VLDOOUT.
Note 2: Specifications to -40°C are guaranteed by design, not production tested.
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
Input Bias Current IBIAS VCM = 5V -500 +500 nA
Input Offset Current IOS VCM = 5V -500 +500 nA
Output Voltage VBUFOUT BUF+ = GND
IBUFOUT = 0 4.988 5.012
VIBUFOUT = ±5mA 4.97 5.03
IBUFOUT = ±45mA 4.93 5.07
Input Offset Voltage VOS
VSUPB = 4.5V to 13V
VCM = 1.2V to
(VSUPB - 1.2V)
IBUFOUT = ±5mA -30 +30
mV
IBUFOUT = ±45mA -70 +70
Output Voltage Swing High VOH IBUFOUT = -45mA, ∆VOS = 1V 9 V
Output Voltage Swing Low VOL IBUFOUT = +45mA, ∆VOS = 1V 1 V
BUF+ Dual-Mode
Threshold Voltage Falling edge, 20mV hysteresis (typ) 80 170 mV
REFERENCE
Reference Voltage VREF -2µA < IREF < 50µA 1.223 1.269 V
Reference Undervoltage
Threshold 0.9 1.2 V
LOGIC SIGNALS
SHDN Input Low Voltage 0.9 V
SHDN Input High Voltage 2.1 V
SHDN Input Current ISHDN 1 µA
FLTSET Input Voltage
Range
0.74 x
VREF
0.85 x
VREF V
FLTSET Threshold Voltage Rising edge, 25mV hysteresis (typ) 80 170 mV
FLTSET Input Current VFLTSET = 1V 50 nA
RDY Output Low Voltage ISINK = 2mA 0.5 V
RDY Output High Leakage VRDY = 13V 1 µA
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
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Electrical Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET =
TGND = PGND = GND, TA = +25°C.)
40
50
60
70
80
90
100
0 200 400 600 800
MAIN 8V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX1778 toc02
IOUT (mA)
EFFICIENCY (%)
VIN = 3.3V
VOUT = 8V
RCOMP = 24kΩ
CCOMP = 470pF
CINTG = 470pF
VIN = 5V
11.76
11.92
11.84
12.08
12.00
12.16
12.24
0 200 300100 400 500 600
MAIN 12V OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX1778 toc03
IOUT (mA)
VOUT (V)
FIGURE 8
CINTG = 470pF
VIN = 3.3V
VIN = 5V
40
60
50
80
70
90
100
0 200 300100 400 500 600
MAIN 12V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX1778 toc04
IOUT (mA)
EFFICIENCY (%)
FIGURE 8
VOUT = 12V
CINTG = 470pF
VIN = 3.3V
VIN = 5V
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
2.5 3.53.0 4.0 4.5 5.0 5.5
STEP UP CONVERTERS
SWITCHING FREQUENCY vs. INPUT VOLTAGE
MAX1778 toc05
VIN (V)
SWITCHING FREQUENCY (MHz)
MAX1778
19.2
19.4
19.8
19.6
20.0
20.2
POSITIVE CHARGE-PUMP OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX1778 toc06
IPOS (mA)
VPOS (V)
0 105 15 20
VSUPP = 10V
VSUPP = 8V
VSUPP = 7.5V
VSUPP = 7V
30
80
70
90
100
POSITIVE CHARGE-PUMP EFFICIENCY
vs. LOAD CURRENT
MAX1778 toc07
INEG (mA)
EFFICIENCY (%)
0 105 15 20
VPOS = 20V
VSUPP = 7.5V
VSUPP = 7V
VSUPP = 8V
VSUPP = 10V
60
50
40
7.88
7.92
7.96
8.00
8.04
8.08
8.12
0 200 400 600 800
MAIN 8V OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX1778 toc01
IOUT (mA)
VOUT (V)
VIN = 5V
CINTG = 470pF
RCOMP = 24kΩ
CCOMP = 470pF
VIN = 3.3V
5
15
10
25
20
35
30
40
2 6 84 10 12 14
MAXIMUM POSITIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
MAX1778 toc08
VSUPP (V)
VPOS (V)
IPOS = 10mA
IPOS = 1mA
-5.04
-5.00
-5.02
-4.96
-4.98
-4.92
-4.94
-4.90
NEGATIVE CHARGE-PUMP OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX1778 toc09
INEG (mA)
VNEG (V)
0 10 20 30 40
VSUPN = 7V
V
SUPN
= 8V
VSUPN = 6V
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MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics
(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET =
TGND = PGND = GND, TA = +25°C.)
30
50
40
70
60
90
80
100
NEGATIVE CHARGE-PUMP EFFICIENCY
vs. LOAD CURRENT
MAX1778 toc10
INEG (mA)
EFFICIENCY (%)
0 10 20 30 40
VSUPN = 7V
VSUPN = 8V
VSUPN = 6V
VNEG = -5V
-14
-10
-12
-6
-8
-4
-2
2 6 84 10 12 14
MAXIMUM NEGATIVE CHARGE-PUMP
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
MAX1778 toc11
VSUPN (V)
VNEG (V)
INEG = 10mA
INEG = 1mA
1.23
1.24
1.25
1.26
1.27
0 20 40 60 80 100
REFERENCE VOLTAGE
vs. REFERENCE LOAD CURRENT
MAX1778 toc12
IREF (µA)
VREF (V)
STEP-UP CONVERTER LOAD-TRANSIENT
RESPONSE
MAX1778 toc13
200mA
0
8.1V
8.0V
7.9V
1A
0
40µs/div
A. IMAIN = 20mA to 200mA, 200mA/div
B. VMAIN = 8V, 100mV/div
C. INDUCTOR CURRENT, 1A/div
CINTG = 1000pF
C
B
A
STEP-UP CONVERTER LOAD-TRANSIENT
RESPONSE WITHOUT INTEGRATOR
MAX1778 toc14
200mA
0
8.1V
8.0V
7.9V
1A
0
40µs/div
A. IMAIN = 20mA to 200mA, 200mA/div
B. VMAIN = 8V, 100mV/div
C. INDUCTOR CURRENT, 1A/div
INTG = REF
C
B
A
STEP-UP CONVERTER LOAD-TRANSIENT
RESPONSE (1µs PULSES)
MAX1778 toc15
0.5A
0
8.0V
7.9V
1A
0.5A
0
4µs/div
A. IMAIN = 0 to 500mA, 500mA/div
B. VMAIN = 8V, 100mV/div
C. INDUCTOR CURRENT, 500mA/div
C
B
A
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MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET =
TGND = PGND = GND, TA = +25°C.)
RIPPLE VOLTAGE WAVEFORMS
MAX1778 toc16
8V
-5V
20V
1µs/div
A. VMAIN = 8V, IMAIN = 200mA, 10mV/div
B. VNEG = -5V, INEG = 10mA, 20mV/div
C. VPOS = 20V, IPOS = 5mA, 20mV/div
C
B
A
STEP-UP CONVERTER
SOFT-START (LIGHT LOAD)
MAX1778 toc17
0
6V
0.5A
1ms/div
A. VSHDN = O TO 2V, 2V/div
B. VMAIN = 8V, 2V/div
C. INDUCTOR CURRENT, 500mA/div
RLOAD = 400Ω
C
B
A
2V
8V
4V
0
STEP-UP CONVERTER
SOFT-START (HEAVY LOAD)
MAX1778 toc18
0
6V
1.0A
1ms/div
A. VSHDN = O TO 2V, 2V/div
B. VMAIN = 8V, 2V/div
C. INDUCTOR CURRENT, 500mA/div
RLOAD = 20Ω
C
B
A
2V
8V
4V
0.5A
0
POWER-UP SEQUENCE
MAX1778 toc19
0
0
10V
2ms/div
A. VSHDN = O TO 2V, 2V/div
B. RDY, 5V/div
C. POSITIVE CHARGE PUMP = VPOS = 20V, RLOAD = 4kΩ, 10V/div
D. STEP-UP CONVERTER: VMAIN = 8V, RLOAD = 40Ω, 10V/div
E. NEGATIVE CHARGE PUMP: VNEG = -5V, RLOAD = 500Ω, 10V/div
E
B
A
2V
5V
20V
0
-10V
C
D
POWER-UP SEQUENCE
(CIRCUIT OF FIGURE 10)
MAX1778 toc20
0
10V
0
1ms/div
A. RDY, 2V/div
B. POSITIVE CHARGE PUMP, VPOS(SYS) = 20V, 10V/div
C. STEP-UP CONVERTER: VMAIN(SYS) = 8V, 10V/div
D. NEGATIVE CHARGE PUMP, VNEG = -5V, -5V/div
B
A
2V
20V
0
-5V
C
D
4V
MAX1778 toc21
C
B
A
10V
5V
4V
5V
2V
0
0
0
100µs/div
POWER-UP INTO SHORT-CIRCUIT
(CIRCUIT OF FIGURE 10)
A. RDY, 2V/div
B. GATE OF N-CH MOSFET, 5V/div
C. STEP-UP CONVERTER, VMAIN(START) = 8V, 5V/div
VMAIN(SYS) = GND
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MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET =
TGND = PGND = GND, TA = +25°C.)
4.75
4.80
4.85
4.90
4.95
5.00
5.05
MAX1778 toc22
VSUPL (V)
VLDOOUT (V)
LDO OUTPUT VOLTAGE
vs. LDO INPUT VOLTAGE
(INTERNAL LINEAR REGULATOR)
4 86 10 12
ILDOOUT = 0
ILDOOUT = 40mA
5.04
5.02
4.90
0.01 0.1 10 100
4.92
4.96
4.94
5.00
4.98
MAX1778 toc23
ILDOOUT (mA)
VLDOOUT (V)
1
LDO OUTPUT VOLTAGE
vs. LDO OUTPUT CURRENT
(INTERNAL LINEAR REGULATOR)
4.90
4.96
4.94
4.92
4.98
5.00
5.02
5.04
5.06
5.08
5.10
-40 10-15 35 60 85
LDO OUTPUT VOLTAGE vs. TEMPERATURE
(INTERNAL LINEAR REGULATOR)
MAX1778 toc24
TEMPERATURE (°C)
V
LDO
(V)
ILDOOUT = 0
ILDOOUT = 40mA
0
40
120
80
160
200
MAX1778 toc25
ILDOOUT (mA)
VSUPL - VLDOOUT (mV)
0 2010 30 40
DROPOUT VOLTAGE
vs. LDO LOAD CURRENT
(INTERNAL LINEAR REGULATOR)
VLDOOUT = 5V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0 10 20 30 40
MAX1778 toc26
ILDOOUT (mA)
ISUPL - ILDOOUT (mA)
LDO SUPPLY CURRENT
vs. LDO OUTPUT CURRENT
(INTERNAL LINEAR REGULATOR)
VLDOOUT = 5V
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MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET =
TGND = PGND = GND, TA = +25°C.)
0
1 100010010
100
40
20
80
60
MAX1778 toc27
FREQUENCY (kHz)
PSRR (dB)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
CLDOOUT = 4.7µF
ILDOOUT = 40mA
0 40
REGION OF STABLE CLDOOUT ESR
vs. LOAD CURRENT
MAX1778 toc28
ILDOOUT (mA)
CLDOOUT ESR (Ω)
10 20 30
100
0.01
0.1
10
1
CLDOOUT = 1µF
STABLE REGION
MAX1778 toc29
B
A
4.96V
40mA
0
5.00V
100µs/div
LOAD-TRANSIENT RESPONSE
(INTERNAL LINEAR REGULATOR)
A. ILDO = 100µA TO 40mA, 40mA/div
B. VLDO = 5V, 20mV/div
VSUPL = VLDO + 500mV
MAX1778 toc30
B
A
4.94V
40mA
0
5.00V
100µs/div
LOAD-TRANSIENT RESPONSE NEAR
DROPOUT (INTERNAL LINEAR REGULATOR)
A. ILDO = 100µA TO 40mA, 40mA/div
B. VLDO = 5V, 20mV/div
VIN = VLDO + 100mV
MAX1778 toc31
C
B
A
0.5A
0
5.0V
8.0V
1.0A
10µs/div
INTERNAL LINEAR-REGULATOR
RIPPLE REJECTION
A. VLDOOUT = 5V, ILDOOUT = 40mA, 10mV/div
B. VMAIN = VSUPL = 8V, 200mV/div
C. IMAIN = 0 TO 750mA, 500mA/div
MAX1778 toc32
C
B
A
4V
2V
2V
0
2V
4V
0
400µs/div
INTERNAL LINEAR-REGULATOR
STARTUP
A. V
S
HDN = 0 TO 2V, 2V/div
B. VLDOOUT = 5V, RLDOOUT = 125Ω, 2V/div
C. VMAIN = 8V, RMAIN = 40Ω, 2V/div
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MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET =
TGND = PGND = GND, TA = +25°C.)
2.45
2.47
2.49
2.51
2.53
2.55
2.5 3.53.0 4.0 4.5 5.0 5.5
MAX1778 toc33
VIN (V)
VLDO (V)
LINEAR-REGULATOR OUTPUT VOLTAGE
vs. INPUT VOLTAGE
(EXTERNAL LINEAR REGULATOR)
ILDO = 0
ILDO = 750mA
FIGURE 7
2.55
2.45
0.1 1 10 100 1000
2.47
MAX1778 toc34
ILDO (mA)
VLDO (V)
2.49
2.51
2.53
LINEAR-REGULATOR OUTPUT VOLTAGE
vs. LOAD CURRENT
(EXTERNAL LINEAR REGULATOR)
FIGURE 7
MAX1778 toc35
B
A
2.45V
250mA
2.55V
50mA
2.50V
100µs/div
EXTERNAL LINEAR-REGULATOR
LOAD-TRANSIENT RESPONSE
A. ILDO = 50mA TO 250mA, 200mA/div
B. VLDO = 2.5V, 50mV/div
FIGURE 7
MAX1778 toc36
C
B
A
0.5A
0
2.5V
7.8V
8.0V
1A
10µs/div
EXTERNAL LINEAR-REGULATOR
RIPPLE REJECTION
A. VLDO = 2.5V, ILDO = 200mA, 10mV/div
B. VMAIN = VSUPL = 8V, 200mV/div
C. IMAIN = 0 TO 750mA, 500mA/div
FIGURE 7
-2.5
-1.5
-0.5
1.5
0.5
2.5
0 2 4 6 8 10 12 14
MAX1778 toc37
VCM (V)
∆VOS (mV)
INPUT OFFSET VOLTAGE DEVIATION
vs. COMMON-MODE VOLTAGE
VSUPB = 4.5V VSUPB = 13V
-1.0
-0.6
-0.2
0.2
0.6
1.0
4 86 10 12 14
MAX1778 toc38
VSUPB (V)
∆V
OS
(mV)
INPUT OFFSET VOLTAGE DEVIATION
vs. BUFFER SUPPLY VOLTAGE
VCM = VSUPB / 2
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MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET =
TGND = PGND = GND, TA = +25°C.)
0
-0.6
-0.2
0.2
0.6
1.0
-40 10-15 35 60 85
MAX1778 toc39
TEMPERATURE (°C)
∆VOS (mV)
INPUT OFFSET VOLTAGE DEVIATION
vs. TEMPERATURE
VSUPB = 13V
VCM = VSUPB/2
0.0
1.0
0.5
2.5
2.0
1.5
4.0
3.5
3.0
4.5
-45 -15-30 0 15 30 45
MAX1778 toc40
IBUFOUT (mA)
gm (S)
BUFFER TRANSCONDUCTANCE
vs. BUFFER OUTPUT CURRENT
TA = +25°C
TA = -40°C
TA = +85°C TA = +85°C
VCM = VSUPB/2
0
2
6
4
8
10
0 42 6 8 10 12 14
MAX1778 toc41
VCM (V)
IBIAS (nA)
BUFFER INPUT BIAS CURRENT
vs. COMMON-MODE VOLTAGE
VSUPB = 4.5V
VSUPB = 13V
4
6
8
10
4 86 10 12 14
MAX1778 toc42
VSUPB (V)
IBIAS (nA)
BUFFER INPUT BIAS CURRENT
vs. BUFFER SUPPLY VOLTAGE
VCM = VSUPB / 2
4
5
6
7
8
9
10
11
12
-40 -15 10 35 60 85
MAX1778 toc43
TEMPERATURE (°C)
IBIAS (nA)
BUFFER INPUT BIAS CURRENT
vs. TEMPERATURE
VCM = VSUPB/2
0.30
0.34
0.42
0.38
0.46
0.50
0 42 6 8 10 12 14
MAX1778 toc44
VCM (V)
ISUPB (mA)
BUFFER SUPPLY CURRENT
vs. COMMON-MODE VOLTAGE
VSUPB = 4.5V
VSUPB = 13V
0.30
0.34
0.38
0.42
0.46
0.50
4 86 10 12 14
MAX1778 toc45
VSUPB (V)
ISUPB (mA)
BUFFER SUPPLY CURRENT
vs. BUFFER SUPPLY VOLTAGE
VCM = VSUPB/2
0
0.3
0.2
0.1
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-40 10-15 35 60 85
ISUPB (mA)
MAX1778 toc46
TEMPERATURE (°C)
NO-LOAD BUFFER SUPPLY CURRENT
vs. TEMPERATURE
VSUPB = 13V
VCM = VSUPB/2
MAX1778 toc47
B
A
4.00V
3.95V
4.05V
4.00V
3.95V
4.05V
4µs/div
VCOM BUFFER
SMALL-SIGNAL RESPONSE
A. VBUF+ = 3.95V TO 4.05V, 50mV/div
B. BUFOUT = BUF-, 50mV/div
CBUF = 1µF, VSUPB = 8V
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MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = +3.3V, SHDN = IN, VMAIN = VSUPP = VSUPN = VSUPB = VSUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET =
TGND = PGND = GND, TA = +25°C.)
MAX1778 toc48
B
A
4.00V
3.50V
4.50V
4.00V
3.50V
4.50V
10µs/div
VCOM BUFFER
LARGE-SIGNAL RESPONSE
A. VBUF+ = 3.50V TO 4.50V, 0.5V/div
B. BUFOUT = BUF-, 0.5V/div
CBUF = 1µF, VSUPB = 8V
MAX1778 toc49
C
B
A
3.8V
8.0V
200mA
4.2V
0
-200mA
4.0V
4µs/div
VCOM BUFFER
LOAD-TRANSIENT RESPONSE
A. IBUFOUT = 200mA PULSES, 200mA/div
B. BUFOUT = BUF-, 200mV/div
C. VMAIN = 8V, 50mV/div
VSUPB = VMAIN, BUF+ = GND, CBUF = 1µF
MAX1778 toc50
C
B
A
3.5V
8.0V
500mA
4.5V
0
-500mA
4.0V
4µs/div
VCOM BUFFER
LOAD-TRANSIENT RESPONSE
A. IBUFOUT = 400mA PULSES, 500mA/div
B. BUFOUT = BUF-, 0.5V/div
C. VMAIN = 8V, 100mV/div
VSUPB = VMAIN, BUF+ = GND, CBUF = 1µF
MAX1778 toc51
C
B
A
8.1V
7.8V
2V
4V
2V
0
4V
0
100µs/div
VCOM BUFFER STARTUP
A. RDY, 2V/div
B. BUFOUT = BUF-, CBUF = 1µF, 2V/div
C. VSUPB = VMAIN = 8V, IMAIN = 20mA, 200mV/div
BUF+ = GND
MAX1778 toc52
C
B
A
8.2V
8.0V
7.9V
2V
4V
2V
0
4V
0
1µs/div
A. RDY, 2V/div
B. BUFOUT = BUF-, CBUF = 1µF, 2V/div
C. VSUPB = VMAIN = 8V, IMAIN = 20mA, 200mV/div
FIGURE 11
VCOM BUFFER STARTUP
(PRECHARGED BUFOUT)
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Converters with Buffer
Typical Operating Characteristics (continued)
PIN
NAME FUNCTION
MAX1778
MAX1881
MAX1880
MAX1882
MAX1883
MAX1884 MAX1885
1 1 1 1 FB
Main Step-Up Regulator Feedback Input. Regulates to 1.25V
nominal. Connect a resistive divider from the output (VMAIN) to FB
to analog ground (GND).
2 2 2 2 INTG
Main Step-Up Integrator Output. When using the integrator,
connect 1000pF to analog ground (GND). To disable the integrator,
connect INTG to REF.
3 3 3 3 IN
Main Supply Voltage. The supply voltage powers the control
circuitry for all the regulators and can range from 2.7V to 5.5V.
Bypass with a 0.1µF capacitor between IN and GND, as close to
the pins as possible.
4 4 4 4 BUF+
VCOM Buffer (Operational Transconductance Amplier) Positive
Feedback Input. Connect to GND to select the internal resistive
divider that sets the positive input to half the amplier’s supply
voltage (VBUF+ = VSUPB /2).
5 5 5 5 BUF- VCOM Buffer (Operational Transconductance Amplier) Negative
Feedback Input
6 6 6 6 SUPB VCOM Buffer (Operational Transconductance Amplier) Supply
Voltage
7 7 7 7 BUFOUT VCOM Buffer (Operational Transconductance Amplier) Output
8 8 8 8 GND Analog Ground. Connect to power ground (PGND) underneath the
IC.
9 9 9 9 REF
Internal Reference Bypass Terminal. Connect a 0.22µF ceramic
capacitor from REF to analog ground (GND). External load
capability up to 50µA.
10 10 — — FBP
Positive Charge-Pump Regulator Feedback Input. Regulates
to 1.25V nominal. Connect a resistive divider from the positive
charge-pump output (VPOS) to FBP to analog ground (GND).
11 11 — — FBN
Negative Charge-Pump Regulator Feedback Input. Regulates to
0V nominal. Connect a resistive divider from the negative charge-
pump output (VNEG) to FBN to the reference (REF).
12 12 10 10 SHDN
Active-Low Shutdown Control Input. Pull SHDN low to force the
controller into shutdown. If unused, connect SHDN to IN for normal
operation. A rising edge on SHDN clears the fault latch.
13 — 11 — SUPL
Low-Dropout Linear Regulator Input Voltage. Can range from
4.5V to 15V. Bypass with a 1µF capacitor to GND (see Capacitor
Selection and Regulator Stability). Connect both input pins together
externally.
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
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Pin Description
PIN
NAME FUNCTION
MAX1778
MAX1881
MAX1880
MAX1882
MAX1883
MAX1884 MAX1885
14 — 12 — LDOOUT
Linear Regulator Output. Sources up to 40mA. Bypass to GND with
a ceramic capacitor determined by:
15 — 13 — FBL Voltage Setting Input. Connect a resistive divider from the linear
regulator output (VLDOOUT) to FBL to analog ground (GND).
16 16 14 14 FLTSET
Fault Trip-Level Set Input. Connect to a resistive divider between
REF and GND to set the main step-up converter’s and positive
charge pump’s fault thresholds between 0.67 x VREF and 0.85 x
VREF. Connect to GND for the preset fault threshold (0.9 x VREF).
17 17 — — SUPN Negative Charge-Pump Driver Supply Voltage. Bypass to power
ground (PGND) with a 0.1µF capacitor.
18 18 — — DRVN Negative Charge-Pump Driver Output. Output high level is VSUPN
and low level is PGND.
19 19 — — SUPP Positive Charge-Pump Driver Supply Voltage. Bypass to power
ground (PGND) with a 0.1µF capacitor.
20 20 — — DRVP Positive Charge-Pump Driver Output. Output high level is VSUPP
and low level is PGND
21 21 17 17 PGND Power Ground. Connect to analog ground (GND) underneath the
IC.
22 22 18 18 LX Main Step-Up Regulator Power MOSFET N-Channel Drain. Place
output diode and output capacitor as close as possible to PGND.
23 23 19 19 TGND Must be connected to ground.
24 24 20 20 RDY Active-Low, Open-Drain Output. Indicates all outputs are ready.
On-resistance is 125Ω (typ).
— 13–15 15, 16 11–13,
15, 16 N.C. No Connection. Not internally connected.
LDOOUT(MAX)
LDOOUT LDOOUT
I
C 0.5ms X V
≥
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
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Pin Description (continued)
Detailed Description
The MAX1778/MAX1880–MAX1885 are highly efficient
multiple-output power supplies for thin-film transistor
(TFT) liquid crystal display (LCD) applications. The
devices contain one high-power step-up converter, two
low-power charge pumps, an operational transconduc-
tance amplifier (VCOM buffer), and a low-dropout linear
regulator. The primary step-up converter uses an internal
N-channel MOSFET to provide maximum efficiency and
to minimize the number of external components. The out-
put voltage of the main step-up converter (VMAIN) can be
set from VIN to 13V with external resistors.
The dual charge pumps (MAX1778/MAX1880–MAX1882
only) independently regulate a positive output (VPOS) and
a negative output (VNEG). These low-power outputs use
external diode and capacitor stages (as many stages as
required) to regulate output voltages from - 40V to +40V.
A unique control scheme minimizes output ripple as well
as capacitor sizes for both charge pumps.
A resistor-programmable 40mA linear regulator (MAX1778/
MAX1881/MAX1883/MAX1884 only) can provide preregu-
lation or postregulation for any of the supplies. For higher
current applications, an external transistor can be added.
Additionally, the VCOM buffer provides a high current
output that is ideal for driving capacitive loads, such as
the backplane of a TFT LCD panel. The positive feedback
input features dual-mode operation, allowing this input to
be connected to an internal 50% resistive-divider between
the buffer’s supply voltage and ground, or externally
adjusted for other voltages.
Also included in the MAX1778/MAX1880–MAX1885 is a
precision 1.25V reference that sources up to 50μA, logic
shutdown, soft-start, power-up sequencing, adjustable
fault detection, thermal shutdown, and an active-low,
open-drain ready output.
Figure 1. Typical Application Circuit
IN
BUFFER OUTPUT
VBUFOUT = VSUPB/2
POSITIVE
VPOS = 20V
CBUF
1.0µF
CLDO
4.7µF
CREF
0.22µF
C7
1.0µF
C5
1.0µF
C4
0.1µF
L1
6.8µH
C4
0.1µF
C2
0.1µF
C1
0.22µF
CIN
4.7µF
SHDN
RDY
SUPL
LDOOUT SUPN
SUPP
DRVP
FBP
R3
750kΩ
R5
200kΩ
R7
150kΩ
R4
49.9kΩ
R6
49.9kΩ
R8
49.9kΩ
R2
49.9kΩ
R2
274kΩ
LX
INPUT
VIN = 3.3V
LDO
VLDOOUT = 5V
NEGATIVE
VNEG = -5V
TO LOGIC
FB
BUFOUT
BUF-
BUF+
GND
TGND
FBL
DRVN
FBN
REF
FLTSET
INTG
PGND
SUPB
MAX1778
MAIN
VMAIN = 8V
MAIN
(8V)
COUT
(2) 4.7µF
C3
1.0µF
RRDY
100kΩ
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Main Step-up Controller
During normal pulse-width modulation (PWM) operation,
the MAX1778/MAX1880–MAX1885 main step-up control-
lers switch at a constant frequency of 500kHz or 1MHz
(see the Selector Guide), allowing the use of low-profile
inductors and output capacitors. Depending on the input-
to-output voltage ratio, the controller regulates the output
voltage and controls the power transfer by modulating the
duty cycle (D) of each switching cycle:
MAIN IN
MAIN
V - V
D V
≈
On the rising edge of the internal clock, the controller sets
a flip-flop when the output voltage is too low, which turns
on the n-channel MOSFET (Figure 2). The inductor cur-
rent ramps up linearly, storing energy in a magnetic field.
Once the sum of the feedback voltage error amplifier,
slope-compensation, and current-feedback signals trip
the multi-input comparator, the MOSFET turns off, the flip-
flop resets, and the diode (D1) turns on. This forces the
current through the inductor to ramp back down, transfer-
ring the energy stored in the magnetic field to the output
capacitor and load. The MOSFET remains off for the rest
of the clock cycle.
Changes in the feedback voltage-error signal shift the
switch-current trip level, consequently modulating the
MOSFET duty cycle.
Under very light loads, an inherent switchover to pulse-
skipping takes place (Figure 3). When this occurs, the
controller skips most of the oscillator pulses in order to
reduce the switching frequency and gate charge losses.
When pulse-skipping, the step-up controller initiates a
new switching cycle only when the output voltage drops
too low. The n-channel MOSFET turns on, allowing the
inductor current to ramp up until the multi-input compara-
tor trips. Then, the MOSFET turns off and the diode turns
on, forcing the inductor current to ramp down. When the
inductor current reaches zero, the diode turns off, so
the inductor stops conducting current. This forces the
threshold between pulse-skipping and PWM operation
to coincide with the boundary between continuous and
discontinuous inductor-current operation:
2
IN MAIN IN
LOAD(CROSSOVER)
MAIN OSC
V V - V
1
I
2V f L
≈
Figure 2. Main Step-Up Converter Block Diagram
MAX1778
MAX1880
MAX1881
MAX1882
MAX1883
MAX1884
MAX1885
VMAIN = 1 + VREF
VREF = 1.25V
R1
R2
( )
S
R
ILIM
Q
CREF
VREF
1.25V
gm
L1
D1
R1
R2
INTG
CINTG
RCOMP
(OPTIONAL)
CCOMP
(OPTIONAL)
CIN
COUT
VMAIN
(UP TO 13V)
VIN
(2.7V TO 5.5V)
OSC
(80% DUTY)
REF
GND
LX
FB
PGND
PWM
COMPARATOR
ERROR
AMPLIFIER
ILIM
COMPARATOR
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The switching waveforms appear noisy and asynchro-
nous when light loading causes pulse-skipping operation;
this is a normal operating condition that improves light-
load efficiency.
Dual Charge-Pump Regulator (MAX1778/
MAX1880–MAX1882 Only)
The MAX1778/MAX1880–MAX1882 controllers contain
two independent low-power charge pumps (Figure 4).
One charge pump inverts the input voltage and provides
a regulated negative output voltage. The second charge
pump doubles the input voltage and provides a regulated
positive output voltage. The controllers contain internal
p-channel and n-channel MOSFETs to control the power
transfer. The internal MOSFETs switch at a constant
frequency (fCHP = fOSC/2).
Positive Charge Pump
During the first half-cycle, the n-channel MOSFET turns
on and charges flying capacitor CX(POS) (Figure 4). This
initial charge is controlled by the variable n-channel on-
resistance. During the second half-cycle, the n-channel
MOSFET turns off and the p-channel MOSFET turns
on, level shifting CX(POS) by VSUPP volts. This con-
nects CX(POS) in parallel with the reservoir capacitor
COUT(POS). If the voltage across COUT(POS) plus a diode
drop (VPOS + VDIODE) is smaller than the level-shifted fly-
ing capacitor voltage (VCX(POS) + VSUPP), charge flows
from CX(POS) to COUT(POS) until the diode (D3) turns off.
Figure 4. Low-Power Charge Pump Block Diagram
Figure 3. Discontinuous-to-Continuous Conduction Crossover
Point
MAX1778
MAX1880
MAX1881
MAX1882
VNEG = - VREF
VREF = 1.25V
( )
R5
R6
R5
R6
COUT(NEG)
CX(NEG)
VSUPN
2.7V TO 13V
OSC
REF
PGNDGND
SUPN
DRVN
FBN
SUPP
DRVP
FBP
D4
D5
VPOS = 1 + VREF
VREF = 1.25V
R3
R4
( )
VSUPP
2.7V TO 13V
VSUPD
D2
D3
CREF
0.22µF
VREF
1.25V
R4
CX(POS)
COUT(POS)
VPOS VNEG
R3
INDUCTOR CURRENT
ILOAD
tON tOFF
TIME
IPEAK
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Negative Charge Pump
During the first half-cycle, the p-channel MOSFET turns
on, and flying capacitor CX(NEG) charges to VSUPN minus
a diode drop (Figure 4). During the second half-cycle, the
p-channel MOSFET turns off, and the n-channel MOSFET
turns on, level shifting CX(NEG). This connects CX(NEG) in
parallel with reservoir capacitor COUT(NEG). If the voltage
across COUT(NEG) minus a diode drop is greater than the
voltage across CX(NEG), charge flows from COUT(NEG)
to CX(NEG) until the diode (D5) turns off. The amount
of charge transferred to the output is controlled by the
variable n-channel on-resistance.
Low-Dropout Linear Regulator (MAX1778/
MAX1881/MAX1883/MAX1884 Only)
The MAX1778/MAX1881/MAX1883/MAX1884 contain a
low-dropout linear regulator (Figure 5) that uses an
internal pnp pass transistor (QP) to supply loads up to
40mA. As illustrated in Figure 5, the 1.25V reference is
connected to the error amplifier, which compares this
reference with the feedback voltage and amplifies the
difference. If the feedback voltage is higher than the refer-
ence voltage, the controller lowers the base current of QP,
which reduces the amount of current to the output. If the
feedback voltage is too low, the device increases the pass
transistor base current, which allows more current to pass
to the output and increases the output voltage. However,
the linear regulator also includes an output current limit to
protect the internal pass transistor against short circuits.
The low-dropout linear regulator monitors and controls the
pass transistor’s base current, limiting the output current
to 130mA (typ). In conjunction with the thermal overload
protection, this current limit protects the output, allowing
it to be shorted to ground for an indefinite period of time
without damaging the part.
VCOM Buffer
The MAX1778/MAX1880–MAX1885 include a VCOM
buffer, which uses an operational transconductance
amplifier (OTA) to provide a current output that is ideal for
driving capacitive loads, such as the backplane of a TFT
LCD panel. The unity-gain bandwidth of this current-
output buffer is:
GBW = gm/COUT
where gm is the amplifier’s transconductance. The band-
width is inversely proportional to the output capacitor, so
large capacitive loads improve stability; however, lower
bandwidth decreases the buffer’s transient response time.
Figure 5. Low-Dropout Linear Regulator Block Diagram
SUPL
CSUPL
VSUPL
4.5V TO 15V
CLDOOUT
LDOOUT
VLDOOUT
1.25V TO (VSUPL - 0.3V)
FBL
VREF
1.25V
ERROR
AMPLIFIER
GND
R8
R7
QP
CURRENT
LIMIT
THERMAL
SENSOR
VLDOOUT = (1 + )VREF
VREF = 1.25V
R7
R8
MAX1778
MAX1881
MAX1883
MAX1884
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To improve the transient response times, the amplifier’s
transconductance increases as the output current increas-
es (see the Typical Operating Characteristics).
The VCOM buffer’s positive feedback input features
dual mode operation. The buffer’s output voltage can be
internally set by a 50% resistive divider connected to the
buffer’s supply voltage (SUPB), or the output voltage can
be externally adjusted for other voltages.
Shutdown (SHDN)
A logic-low level on SHDN shuts down all of the con-
verters and the reference. When shut down, the supply
current drops to 0.1μA to maximize battery life, and the
reference is pulled to ground. The output capacitance,
feedback resistors, and load current determine the rate
at which each output voltage decays. A logic-level high
on SHDN power activates the MAX1778/MAX1880–
MAX1885 (see the Power-Up Sequencing section). Do
not leave SHDN floating. If unused, connect SHDN to IN.
A logic-level transition on SHDN clears the fault latch.
Power-Up Sequencing
Upon power-up or exiting shutdown, the MAX1778/
MAX1880–MAX1885 start a power-up sequence. First,
the reference powers up. Then, the main DC-DC step-up
converter powers up with soft-start enabled. The linear
regulator powers up at the same time as the main step-up
converter; however, the power sequence and ready out-
put signal are not affected by the regulation of the linear
regulator. While the main step-up converter powers up,
the output of the PWM comparator remains low (Figure
2), and the step-up converter charges the output capaci-
tors, limited only by the maximum duty cycle and current-
limit comparator. When the step-up converter approaches
its nominal regulation value and the PWM comparator’s
output changes states for the first time, the negative
charge pump turns on. When the negative output voltage
reaches approximately 90% of its nominal value (VFBN <
110mV), the positive charge pump starts up. Finally, when
the positive output voltage reaches 90% of its nominal
value (VFBP > 1.125V), the active-low ready signal (RDY)
goes low (see the Power Ready section), and the VCOM
buffer powers up. The MAX1883–MAX1885 do not con-
tain the charge pumps, but the power-up sequence still
contains the charge pumps’ startup logic, which appears
as a delay (2 x 4096/fOSC) between the step-up converter
reaching regulation and when the ready signal and VCOM
buffer are activated.
Soft-Start
For the main step-up regulator, soft-start allows a gradual
increase of the current-limit level during startup to reduce
input surge currents. The MAX1778/MAX1880–MAX1885
divide the soft-start period into four phases. During the
first phase, the controller limits the current limit to only
0.38A (see the Electrical Characteristics), approximately
Figure 6. VCOM Buffer Block Diagram
SUPB VSUPB
4.5V TO 13V
CBUF
BUFOUT
BUF-
VBUFOUT
1.2V TO (VSUPB - 1.2V)
BUF+
125mV
GND
R12
R
R
R11
VBUFOUT = ( )VSUPB
R12
R11 + R12
MAX1778
MAX1880
MAX1881
MAX1882
MAX1883
MAX1884
MAX1885
gm
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a quarter of the maximum current limit (ILX(MAX)). If
the output does not reach regulation within 1ms, soft-
start enters phase II, and the current limit is increased
by another 25%. This process is repeated for phase III.
The maximum 1.5A (typ) current limit is reached within
3072 clock cycles or when the output reaches regulation,
whichever occurs first (see the startup waveforms in the
Typical Operating Characteristics).
For the charge pumps (MAX1778/MAX1880–MAX1882
only), soft-start is achieved by controlling the rate of rise
of the output voltage. Both charge-pump output volt-
ages are controlled to be in regulation within 4096 clock
cycles, regardless of output capacitance and load, limited
only by the charge pump’s output impedance. Although
the MAX1883–MAX1885 controllers do not include the
charge pumps, the soft-start logic still contains the 4096
clock cycle startup periods for both charge pumps.
Fault Trip Level (FLTSET)
The MAX1778/MAX1880–MAX1885 feature dual-mode
operation to allow operation with either a preset fault trip
level or an adjustable trip level for the step-up converter
and positive charge-pump outputs. Connect FLTSET to
GND to select the preset 0.9 x VREF fault threshold. The
fault trip level can also be adjusted by connecting a volt-
age-divider from REF to FLTSET (Figure 8). For greatest
accuracy, the total load on the reference (including current
through the negative charge-pump feedback resistors)
should not exceed 50μA so that VREF is guaranteed
to be in regulation (see the Electrical Characteristics).
Therefore, select R10 in the 100kΩ to 1MΩ range, and
calculate R9 with the following equation:
R9 = R10 [(VREF/VFLTSET) - 1]
where VREF = 1.25V, and VFLTSET can range from 0.67
x VREF to 0.85 x VREF. FLTSET’s input bias current has
a maximum value of 50nA. For 1% error, the current
through R10 should be at least 100 times the FLTSET
input bias current (IFLTSET).
Fault Condition
Once RDY is low, if the output of the main regulator
or either low-power charge pump falls below its fault
detection threshold, or if the input drops below its under-
voltage threshold, then RDY goes high impedance and
all outputs shut down; however, the reference remains
active. After removing the fault condition, toggle shutdown
(below 0.8V) or cycle the input voltage (below 0.2V) to
clear the fault latch and reactivate the device.
The reference fault threshold is 1.05V. For the step-up
converter and positive charge-pump, the fault trip level is
set by FLTSET (see the Fault Trip Level (FLTSET) sec-
tion). For the negative charge pump, the fault threshold
measured at the charge-pump’s feedback input (FBN) is
140mV (typ).
Power Ready (RDY)
RDY is an open-drain output. When the power-up
sequence for the main step-up converter and low-power
charge pumps has properly completed, the 14V MOSFET
turns on and pulls RDY low with a 125Ω (typ) on-
resistance. If a fault is detected on any of these three
outputs, the internal open-drain MOSFET appears as
a high impedance. Connect a 100kΩ pullup resistor
between RDY and IN for a logic-level output.
Voltage Reference (REF)
The voltage at REF is nominally 1.25V. The reference
can source up to 50μA with good load regulation (see
the Typical Operating Characteristics). Connect a 0.22μF
ceramic bypass capacitor between REF and GND.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation
in the MAX1778/MAX1880–MAX1885. When the junction
temperature exceeds TJ = +160°C, a thermal sensor acti-
vates the fault protection, which shuts down the controller,
allowing the IC to cool. Once the device cools down by
15°C, toggle shutdown (below 0.8V) or cycle the input
voltage (below 0.2V) to clear the fault latch and reactivate
the controller. Thermal-overload protection protects the
controller in the event of fault conditions. For continuous
operation, do not exceed the absolute maximum junction-
temperature rating of TJ = +150°C.
Operating Region and Power Dissipation
The MAX1778/MAX1880–MAX1885s’ maximum power
dissipation depends on the thermal resistance of the IC
package and circuit board, the temperature difference
between the die junction and ambient air, and the rate of
any airflow. The power dissipated in the device depends on
the operating conditions of each regulator and the buffer.
The step-up controller dissipates power across the inter-
nal n-channel MOSFET as the controller ramps up the
inductor current. In continuous conduction, the power dis-
sipated internally can be approximated by:
2
2
MAIN MAIN IN
STEP UP IN OSC
DS(ON)
I V VD
1
P
V 12 f L
RD
−
≈+
×
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where IMAIN includes the primary load current and the
input supply currents for the charge pumps (see the
Charge-Pump Input Power and Efficiency Considerations
section), linear regulator, and VCOM buffer.
The linear regulator generates an output voltage by dis-
sipating power across an internal pass transistor, so the
power dissipation is simply the load current times the
input-to-output voltage differential:
LDO(INT) LDO SUPL LDO
P I (V - V )=
When driving an external transistor, the internal linear
regulator provides the base drive current. Depending on
the external transistor’s current gain (β) and the maximum
load current, the power dissipated by the internal linear
regulator can still be significant:
( )
LDO
LDO(INT) SUPL LDO
LDOOUT SUPL LDOOUT
I
P V - V 0.7V
I (V - V )
= +
β
=
The charge pumps provide regulated output voltages by
dissipating power in the low-side n-channel MOSFET, so
they could be modeled as linear regulators followed by
unregulated charge pumps. Therefore, their power dis-
sipation is similar to a linear regulator:
( )
( )
NEG NEG SUPN DIODE NEG
POS POS SUPP DIODE SUPD POS
P I V - 2V N - V
P I V - 2V N V - V
=
= +
where N is the number of charge-pump stages, VDIODE
is the diodes’ forward voltage, and VSUPD is the positive
charge-pump diode supply (Figure 4).
The VCOM buffer’s power dissipation depends on the
capacitive load (CLOAD) being driven, the peak-to-peak
voltage change (VP-P) across the load, and the load’s
switching rate:
BUF P- P LOAD LOAD SUPB
P VC f V=
To find the total power dissipated in the device, the power
dissipated by each regulator and the buffer must be
added together:
TOTAL STEP- UP LDO(INT)
NEG POS BUF
P P P
P P P
= +
+++
The maximum allowed power dissipation is 975mW
(24-pin TSSOP)/879mW (20-pin TSSOP) or:
MAX J(MAX) A JB BA
P (T T ) / ( )= − θ +θ
where TJ - TA is the temperature difference between the
controller’s junction and the surrounding air, θJB (or θJC)
is the thermal resistance of the package to the board,
and θBA is the thermal resistance from the PCB to the
surrounding air.
Design Procedure
Main Step-Up Converter
Output-Voltage Selection
Adjust the output voltage by connecting a voltage-divider
from the output (VMAIN) to FB to GND (see the Typical
Operating Circuit). Select R2 in the 10kΩ to 50kΩ range.
Calculate R1 with the following equations:
R1 = R2 [(VMAIN/VREF) - 1]
where VREF = 1.25V. VMAIN can range from VIN to 13V.
Inductor Selection
Inductor selection depends upon the minimum required
inductance value, saturation rating, series resistance, and
size. These factors influence the converter’s efficiency,
maximum output load capability, transient response time,
and output-voltage ripple. For most applications, values
between 4.7μH and 22μH work best with the controller’s
switching frequency (Tables 1 and 2).
The inductor value depends on the maximum output load
the application must support, input voltage, output volt-
age, and switching frequency. With high inductor values,
the MAX1778/MAX1880–MAX1885 source higher output
currents, have less output ripple, and enter continuous
conduction operation with lighter loads; however, the
circuit’s transient response time is slower. On the other
hand, low-value inductors respond faster to transients,
remain in discontinuous conduction operation, and typi-
cally offer smaller physical size for a given series resis-
tance and current rating. The equations provided here
include a constant LIR, which is the ratio of the peak-
to-peak AC inductor current to the average DC inductor
current. For a good compromise between the size of the
inductor, power loss, and output-voltage ripple, select an
LIR of 0.3 to 0.5. The inductance value is then given by:
2
IN(MIN) MAIN IN(MIN)
MIN MAIN MAIN(MAX) OSC
V V - V 1
L
V I f LIR
= η
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where η is the efficiency, fOSC is the oscillator frequency
(see the Electrical Characteristics), and IMAIN includes
the primary load current and the input supply currents for
the charge pumps (see the Charge-Pump Input Power
and Efficiency Considerations section), linear regulator,
and VCOM buffer. Considering the typical application
circuit, the maximum average DC load current (IMAIN(MAX))
is 300mA with an 8V output. Based on the above
equations and assuming 85% efficiency, the inductance
value is then chosen to be 4.7μH.
The inductor’s saturation current rating should exceed the
peak inductor current throughout the normal operating
range. The peak inductor current is then given by:
MAIN(MAX) MAIN
PEAK IN(MIN)
IV
LIR 1
I 1
V2
= +
η
Under fault conditions, the inductor current can reach up
to 1.85A (ILIM(MAX)), see the Electrical Characteristics).
However, the controller’s fast current-limit circuitry allows
the use of soft-saturation inductors while still protecting
the IC.
The inductor’s DC resistance can significantly affect
efficiency due to the power loss in the inductor. The power
loss due to the inductor’s series resistance (PLR) can be
approximated by the following equation:
2
MAIN MAIN
LR L
IN
I X V
P R V
≅
where RL is the inductor’s series resistance. For best per-
formance, select inductors with resistance less than the
internal n-channel MOSFET on-resistance (0.35Ω typ).
Use inductors with a ferrite core or equivalent. To
minimize radiated noise in sensitive applications, use a
shielded inductor.
Output Capacitor
Output capacitor selection depends on circuit stability and
output-voltage ripple. A 10μF ceramic capacitor works
well in most applications (Tables 1 and 2). Additional
feedback compensation is required (see the Feedback
Compensation section) to increase the margin for stability
by reducing the bandwidth further. In cases where the out-
put capacitance is sufficiently large, additional feedback
compensation is not necessary.
Output-voltage ripple has two components: variations in
the charge stored in the output capacitor with each LX
pulse, and the voltage drop across the capacitor’s equiva-
lent series resistance (ESR) caused by the current into
and out of the capacitor:
RIPPLE RIPPLE(C) RIPPLE(ESR)
RIPPLE(ESR) PEAK ESR(COUT)
MAIN IN MAIN
RIPPLE(C)
MAIN OUT OSC
V V V
V I R , AND
V V I
V V Cf
= +
≈
−
≈
where IPEAK is the peak inductor current (see the Inductor
Selection section). For ceramic capacitors, the output-
voltage ripple is typically dominated by VRIPPLE( C). The
voltage rating and temperature characteristics of the out-
put capacitor must also be considered.
Feedback Compensation
For stability, add a pole-zero pair from FB to GND in the
form of a compensation resistor (RCOMP) in series with
a compensation capacitor (CCOMP), as shown in Figure
2. Select RCOMP to be half the value of R2, the low-side
feedback resistor.
Integrator Capacitor
The MAX1778/MAX1880–MAX1885 contain an internal
current integrator that improves the DC load regulation
but increases the peak-to-peak transient voltage (see
the load-transient waveforms in the Typical Operating
Characteristics). For highly accurate DC load regulation,
enable the current integrator by connecting a 470pF
(ƒOSC = 1MHz)/1000pF (ƒOSC = 500kHz) capacitor to
INTG. To minimize the peak-to-peak transient voltage
at the expense of DC regulation, disable the integrator
by connecting INTG to REF. When using the MAX1883–
MAX1885, connect a 100kΩ resistor to GND when dis-
abling the integrator.
Input Capacitor
The input capacitor (CIN) in step-up designs reduces the
current peaks drawn from the input supply and reduces
noise injection. The value of CIN is largely determined by
the source impedance of the input supply. High source
impedance requires high input capacitance, particularly
as the input voltage falls. Since step-up DC-DC converters
act as “constant-power” loads to their input supply, input
current rises as input voltage falls. A good starting point is
to use the same capacitance value for CIN as for COUT.
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Rectier Diode
Use a Schottky diode with an average current rating equal
to or greater than the peak inductor current, and a voltage
rating at least 1.5 times the main output voltage (V
MAIN
).
Charge Pumps (MAX1778/ MAX1880/
MAX1881/MAX1882 Only)
Selecting the Number of Charge-Pump Stages
The number of charge-pump stages required to regulate
the output voltage depends on the supply voltage, output
voltage, load current, switching frequency, the diode’s for-
ward voltage drop, and ceramic capacitor values.
For positive charge-pump outputs, the number of required
stages can be determined by:
POS SUPD
POS
SUPP DIODE TX LOAD
V - V
N
V - 1 . 1( 2 V R I )
≥
+
where V
SUPD
is the positive charge-pump diode supply
(Figure 4), V
DIODE
is the diode’s forward voltage drop,
and R
TX
is the charge pump’s output impedance. The
charge pump’s output impedance can be approximated
using the following equation:
TX PCH(ON) NCH(ON) X CHP
OUT CHP
1
R 2(R R ) Cf
1
Cf
= ++
+
where the charge pump’s switching frequency (f
CHP
) is
equal to 0.5 x f
OSC
, the p-channel MOSFET’s on-resis-
tance (R
PCH(ON)
) is 10Ω, and the n-channel MOSFET’s
on-resistance (R
NCH(ON)
) is 4Ω (see the Electrical
Characteristics).
For negative charge-pump outputs, the number of required
stages can be determined by:
NEG
NEG
SUPN DROP TX LOAD
V
N
V - 1 . 1( 2 V R I )
≥
+
where N
NEG
is rounded up to the nearest integer.
*RCOMP and CCOMP are connected between the step-up converter’s output (VMAIN) and FB.
Table 1. MAX1778/MAX1880/MAX1883 Component Values (fOSC = 1MHz)
CIRCUIT 1 CIRCUIT 2 CIRCUIT 3 CIRCUIT 4 CIRCUIT 5
VIN 3.3V 3.3V 3.3V 5V 5V
VMAIN 9V 9V 9V 12V 12V
IMAIN(MAX) 100mA 200mA 200mA 220mA 220mA
VNEG -5V -5V -5V -5V -5V
INEG 2mA 5mA 5mA 5mA 5mA
VPOS 24V 24V 24V 24V 24V
IPOS 2mA 5mA 5mA 5mA 5mA
L 2.2µH 4.7µH 4.7µH 6.8µH 6.8µH
IPEAK >1A >1A >1A >1A >1A
COUT 4.7µF 10µF 20µF 10µF 20µF
R1 309kΩ 309kΩ 309kΩ 429kΩ 429kΩ
R2 49.9kΩ 49.9kΩ 49.9kΩ 49.9kΩ 49.9kΩ
RCOMP None None 39kΩ* None 20kΩ*
CCOMP None None 100pF* None 200pF*
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Charge-Pump Input Power and
Efciency Considerations
The charge pumps in the MAX1778/MAX1880–MAX1882
provide regulated output voltages by controlling the volt-
age drop across the low-side n-channel MOSFET, so
they can be modeled as linear regulators followed by an
unregulated charge pump when determining the input
power requirements and efficiency.
The charge pump only provides charge to the output
capacitor during half the period (50% duty cycle), so the
input current is a function of the number of stages and the
load current:
SUPP POS
I I (N 1)= +
for the positive charge pump, and:
SUPP POS
I I (N 1) = +
for the negative charge pump, where N is the number of
charge-pump stages.
The efficiency characteristics of the MAX1778/MAX1880–
MAX1882 regulated charge pumps are similar to a linear
regulator. It is dominated by quiescent current at low
*RCOMP and CCOMP are connected between the step-up converter’s output (VMAIN) and FB.
Table 2. MAX1881/MAX1882/MAX1884/MAX1885 Component Values (fOSC = 500kHz)
Table 3. Component Suppliers
CIRCUIT 6 CIRCUIT 7 CIRCUIT 8 CIRCUIT 9
VIN 3.3V 3.3V 3.3V 3.3V
VMAIN 9V 9V 9V 9V
IMAIN(MAX) 100mA 100mA 200mA 200mA
VNEG -5V -5V -5V -5V
INEG 2mA 2mA 5mA 5mA
VPOS 24V 24V 24V 24V
IPOS 2mA 2mA 5mA 5mA
L 4.7µH 10µH 10µH 10µH
IPEAK >1A >1A >1A >1A
COUT 4.7µF 10µF 10µF 20µF
R1 309kΩ 309kΩ 309kΩ 309kΩ
R2 49.9kΩ 49.9kΩ 49.9kΩ 49.9kΩ
RCOMP None None None 20kΩ*
CCOMP None None None 200pF*
SUPPLIER PHONE FAX
INDUCTORS
Coilcraft 847-639-6400 847-639-1469
Coiltronics 561-241-7876 561-241-9339
Sumida USA 847-956-0666 847-956-0702
TOKO 847-297-0070 847-699-1194
CAPACITORS
AVX 803-946-0690 803-626-3123
KEMET 408-986-0424 408-986-1442
SANYO 619-661-6835 619-661-1055
Taiyo Yuden 408-573-4150 408-573-4159
DIODES
Central
Semiconductor 516-435-1110 516-435-1824
International
Rectier 310-322-3331 310-322-3332
Motorola 602-303-5454 602-994-6430
Nihon 847-843-7500 847-843-2798
Zetex 516-543-7100 516-864-7630
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output currents and by the input voltage at higher output
currents (see the Typical Operating Characteristics). So
the maximum efficiency can be approximated by:
POS
POS
SUPD SUPP
V
V VN
η≅ +
for the positive charge pump, and:
NEG
NEG
SUPN
V
VN
η≅
for the negative charge pump, where VSUPD is the
positive charge pump’s diode supply (Figure 4).
Output-Voltage Selection
Adjust the positive output voltage by connecting a
voltage-divider from the output (VPOS) to FBP to GND
(see the Typical Operating Circuit). Adjust the negative
output voltage by connecting a voltage-divider from the
output (VNEG) to FBN to REF. Select R4 and R6 in the
50kΩ to 100kΩ range. Higher resistor values improve
efficiency at low output current but increase output-
voltage error due to the feedback input bias current. For the
negative charge pump, higher resistor values also reduce
the load on the reference, which should not exceed
50μA for greatest accuracy (including current through
the FLTSET resistors) to guarantee that VREF remains in
regulation (see the Electrical Characteristics). Calculate
the remaining resistors with the following equations:
R3 = R4 [(VPOS/VREF) - 1]
R5 = R6 |VNEG/VREF|
where VREF = 1.25V. VPOS can range from VSUPP to
40V, and VNEG can range from 0V to -40V.
Flying Capacitor
Increasing the flying capacitor (CX) value increases the
output current capability. Above a certain point, increasing
the capacitance has a negligible effect because the out-
put current capability becomes dominated by the internal
switch resistance and the diode impedance. The flying
capacitor’s voltage rating must exceed the following:
CXN(POS) SUPD SUPP
V 1.5 V V ( N -1)>+
for the positive charge pump, and:
CXN(NEG) SUPN
V 1.5(V N)>
for the negative charge pump, where N is the stage
number in which the flying capacitor appears, and VSUPD
is the positive charge pump’s diode supply (Figure 4).
For example, the two-stage positive charge pump in the
typical application circuit (Figure 1) where VSUPP =
VSUPD = 8V contains two flying capacitors. The flying
capacitor in the first stage (C4) requires a voltage rating
over 12V. The flying capacitor in the second stage (C6)
requires a voltage rating over 24V.
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the ESR
reduces the output ripple voltage and the peak-to-peak
transient voltage. With ceramic capacitors, the output-
voltage ripple is dominated by the capacitance value.
Use the following equation to approximate the required
capacitor value:
LOAD
OUT
CHP RIPPLE
I
C
fV
≥
where fCHP is typically fOSC/2 (see the Electrical
Characteristics).
Charge-Pump Input Capacitor
Use a bypass capacitor with a value equal to or greater than
the flying capacitor. Place the capacitor as close as pos-
sible to the IC. Connect directly to power ground (PGND).
Charge-Pump Rectier Diodes
Use Schottky diodes with a current rating equal to or
greater than two times the average charge-pump input
current, and a voltage rating at least 1.5 times VSUPP
for the positive charge pump and VSUPN for the negative
charge pump.
Low-Dropout Linear Regulator (MAX1778/
MAX1881/MAX1883/MAX1884 Only)
Output-Voltage Selection
Adjust the linear-regulator output voltage by connecting a
voltage-divider from LDOOUT to FBL to GND (Figure 5).
Select R8 in the 5kΩ to 50kΩ range. Calculate R7 with the
following equation:
R7 = R8 [(VLDOOUT/VFBL) - 1]
where VFBL = 1.25V, and VLDOOUT can range from 1.25V
to (VSUPL - 300mV). FBL’s input bias current is 0.8μA
(max). For less than 0.5% error due to FBL input bias
current (IFBL), R8 must be less than 8kΩ.
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Capacitor Selection and Regulator Stability
Capacitors are required at the input and output of
the MAX1778/MAX1881/MAX1883/MAX1884 for stable
operation over the full temperature range and with
load currents up to 40mA. Connect a 1μF input bypass
capacitor (CSUPL) between SUPL and ground to lower
the source impedance of the input supply. Connect a
ceramic capacitor between LDOOUT and ground, using
the following equation to determine the lowest value
required for stable operation:
LDOOUT(MAX)
LDOOUT LDOOUT
I
C 0.5ms X V
≥
For example, with a 5V linear regulator output voltage
and a maximum 40mA load, use at least 4μF of output
capacitance. Applications that experience high-current
load pulses may require more output capacitance.
The ESR of the linear regulator’s output capacitor
(CLDOOUT) affects stability and output noise. Use output
capacitors with an ESR of 0.1Ω or less to ensure stability
and optimum transient response. Surface-mount ceramic
capacitors are good for this purpose. Place CSUPL and
CLDOOUT as close as possible to the linear regulator to
minimize the impact of PCB trace inductance.
External Pass Transistor
For applications where the linear regulator currents
exceed 40mA or where the power dissipation in the IC
needs to be reduced, an external npn transistor can be
used. In this case, the internal LDO only provides the
necessary base drive while the external npn transistor
supports the load, so most of the power dissipation occurs
across the external transistor’s collector and emitter.
Selection of the external npn transistor is based on three
factors: the package’s power dissipation, the current
gain (β), and the collector-to-emitter saturation voltage
(VCE(SAT)). First, the maximum power dissipation should
not exceed the transistor’s package rating:
COLLECTOR LDO LOAD(MAX)
P (V V ) x I= −
Once the appropriate package type is selected, consider
the npn transistor’s current gain. Since the internal LDO
cannot source more than 40mA (min), the transistor’s
current gain must be high enough at the lowest collector-
to-emitter voltage to support the maximum output load:
LOAD(MAX)
MIN
I - 40mA
40mA
β≥
For stable operation, place a capacitor (CLDOOUT) and
a minimum load resistor (R5) at the output of the internal
linear regulator (the base of the external transistor) to set
the dominant pole:
LDOOUT LDO
LOAD(MAX)
LDO
MIN
1
C 0.5ms
V
I
V 0.7V
x
R5
≥
++
β
Since the LDO cannot sink current, a minimum pull-
down resistor (R5) is required at the base of the npn
transistor to sink leakage currents and improve the high-
to-low load-transient response. Under no-load conditions,
leakage currents from the internal pass transistor supply
the output capacitor (CLDOOUT), even when the transistor
is off. As the leakage currents increase over temperature,
charge can build up on CLDOOUT, making the linear
regulator’s output rise above its set point. Therefore, R5
must sink at least 100μA to guarantee proper regulation.
Additionally, the minimum load current provided by R5
improves the high-to-low load transients by lowering the
impedance seen by CLDOOUT after the transient occurs.
Therefore, if large load transients are expected, select R5
so that the minimum load current is 10% of the transistor’s
maximum base current:
LDO LDO MIN
LDOOUT(MIN) LOAD(MAX)
V 0.7V (V 0.7V)
R 5 0 . 1
II
+ +β
= =
Alternatively, output capacitance placed on the external
linear regulator’s output (the emitter) adds a second pole
that could destabilize the regulator. A capacitive-divider
from the transistor’s base to the feedback input (C2 and
C3, Figure 7) circumvents this second pole by adding a
pole-zero pair. Furthermore, to minimize excessive over-
shoot, the capacitive-divider’s ratio must be the same as
the resistive-divider’s ratio. Once the output capacitor is
selected, using the following equations to determine the
required capacitive-divider values:
LDO
REF
LDO
CR4
C 2 C 3 1
100 R3
V
C2 R4
C2 C3 R3 R4 V
+≥ +
= =
++
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Input-to-Output (Dropout) Voltage and Startup
A linear regulator’s minimum input-to-output voltage
differential (dropout voltage) determines the lowest
useable supply voltage. Because the MAX1778/MAX1881/
MAX1883/MAX1884 use an internal pnp transistor (or
external npn transistor), their dropout voltage is a function
of the transistor’s collector-to-emitter saturation voltage
(see the Typical Operating Characteristics). The linear
regulator’s quiescent current increases when in dropout.
The internal linear regulator tries to start up once its
supply voltage (VSUPL) exceeds 4V. When the linear
regulator powers up, the linear regulator may be in
dropout if the linear regulator’s output set voltage is
higher than its input supply voltage. Therefore, during this
brief period, the linear regulator draws additional supply
current until the input supply voltage exceeds the output
set voltage plus the pass transistor’s saturation voltage
(VLDO(SET) + VCE(SAT)).
VCOM Buffer (Operational Transconductance
Amplier)
Buffer Output Voltage and Capacitor Selection
The positive input (BUF+) features dual-mode operation.
Connect BUF+ to GND for the preset VSUPB/2 output
voltage, set by an internal 50% resistive-divider. Adjust
the amplifier’s output voltage by connecting a voltage-
divider from SUPB to BUF+ to GND (Figure 6). Select
R12 in the 10kΩ to 100kΩ range. Calculate R11 with the
following equation:
SUPB
BUF
V
R11 R12 - 1
V+
=
where VSUPB can range from 4.5V to 13V, and VBUF+
can range from 1.2V to (VSUPB - 1.2V). Connect a
minimum 1μF ceramic capacitor from BUFOUT to ground.
PCB Layout and Grounding
Careful PCB layout is extremely important for proper
operation. Follow the following guidelines for good PCB
layout:
1) Place the main step-up converter output diode and
output capacitor less than 0.2in (5mm) from the LX
and PGND pins with wide traces and no vias.
2) Separate analog ground and power ground. The
ground connections for the step-up converter’s and
charge pump’s input and output capacitors should be
connected to the power ground plane. The linear regu-
lator’s and VCOM buffer’s input and output capacitors
should be connected to a separate power-ground
path, star-connected to the PGND pin to minimize
voltage drops. When using multi-layer boards, the top
Figure 7. External Linear Regulator
IN
SHDN
LDOOUT
LX
L1
6.8µH
INPUT
VIN = 3.3V
C1
0.22µF
COUT
(2) 4.7µF
CIN
4.7µF R1
274kΩ
R2
49.9kΩ
FB
GND
FBL
REF
Q1
INTG
PGND
CREF
0.22µF
MAX1778
MAX1883
(MAX1881)*
(MAX1884)*
R3
49.9kΩ
R4
49.9kΩ
CLDO
1µF
C3
0.01µF
C2
0.01µF
CLDOOUT
4.7µF
CLDOIN
1µF
R5
1.5kΩ
MAIN
VMAIN = 8V
LDO
VLDO = 2.5V
SUPL
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layer should contain the boost regulator and charge-
pump power ground plane, and the inner layer should
contain the analog ground plane and power-ground
plane/path for the VCOM buffer and LDO. Connect all
three ground planes together at one place near the
PGND pin.
3) Locate all feedback resistive-dividers as close as pos-
sible to their respective feedback pins. The voltage-
divider’s center trace should be kept short. Avoid run-
ning any feedback trace near the LX switching node or
the charge-pump drivers. The resistive-dividers’ ground
connections should be to analog ground (GND).
4) When using multilayer boards, separate the top signal
layer and bottom signal layer with a ground plane
between to eliminate capacitive coupling between fast-
charging nodes on the top layer and high-impedance
nodes on the bottom layer. The fast-charging nodes,
such as the LX and charge-pump driver nodes, should
not have any other traces or ground planes near by.
5) Keep the charge-pump circuitry as close as possible
to the IC, using wide traces and avoiding vias when
possible. Place 0.1μF ceramic bypass capacitors near
the charge-pump input pins (SUPP and SUPN) to the
PGND pin.
6) To maximize output power and efficiency and minimize
output ripple voltage, use extra-wide, power-ground
traces, and solder the IC’s power-ground pin directly
to it.
Refer to the MAX1778/MAX1880–MAX1885 evaluation
kit for an example of proper board layout.
Figure 8. 5V Input Monitor Application
IN
BUFFER OUTPUT
VBUFOUT = VSUPB/2
POSITIVE
VPOS = 20V
SHDN
RDY
SUPL
LDOOUT SUPN
SUPP
DRVP
FBP
LX
L1
10µH
INPUT
VIN = 5V
C1
0.22µF
C6
1µF C6
0.01µF
C7
0.01µF
C3
1.0µF
CREF
0.22µF
C2
0.1µF
CBUF
1.0µF
C5
1.0µF
CCOMP
470pF
COUT
(2) 10µF
C4
0.1µF
CIN
(2) 4.7µF
CLDOOUT
4.7µF
RRDY
100kΩ
R8
1.5kΩ
R8
10kΩ
R5
316kΩ R9
30kΩ
R3
750kΩ
R4
49.9kΩ
R1
86.6kΩ
R2
10kΩ
RCOMP
4.7kΩ
R10
100kΩ
R6
49.9kΩ
R7
16.4kΩ
NEGATIVE
VNEG = -8V
TO LOGIC
FB
BUFOUT
BUF-
BUF+
FLTSET
GND
TGND
FBL
DRVN
FBN
REF
INTG
PGND
SUPB
MAX1778
LDO
VLDO = 3.3V
Q1
REF
MAIN
VMAIN = 12V
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Applications Information
Low-Prole Components
Notebook applications generally require low-profile com-
ponents, potentially limiting the circuit’s performance. For
example, low-profile inductors typically have lower satu-
ration ratings and more series resistance, limiting output
current and efficiency. Low-profile capacitors have lower
voltage ratings for a given capacitance value, so 3.3μF
low-profile capacitors with voltage ratings greater than
10V were not available at the time of publication.
Desktop Monitors
Monitor applications do not have the same component
height restrictions associated with laptops, allowing more
flexibility in component selection (Figure 8). Larger output
capacitors with higher voltage ratings allow configurations
with output voltages above 10V. Additionally, physically
larger inductors with less series resistance and higher
saturation ratings provide more output current and higher
efficiency.
Input Voltage Above and
Below the Output Voltage
Combining the step-up converter and linear regulator
as shown in Figure 9 provides output-voltage regula-
tion above and below the input voltage. Supplied by the
step-up converter, the linear regulator output provides a
constant output voltage (VLDO). When the input voltage
exceeds the main step-up converter’s nominal output volt-
age, the controller stops switching but the linear regula-
tor maintains the output voltage. When the input voltage
drops below the output voltage, the step-up converter
Figure 9. Input Voltage Above and Below the Output Voltage
IN
BUFFER OUTPUT
VBUFOUT = VSUPB/2
POSITIVE
VPOS = 24V
SHDN
RDY
BUF-
BUFOUT
SUPN
SUPP
LX
L1
6.8µH
POWER INPUT
VBATT = 10V TO 15V
INPUT
VIN = 3.3V TO 5V C1
0.1µF
CLDO
(2) 3.3µF
C6
0.1µF
C7
0.1µF
C3
1.0µF
CBUF
1.0µF
CINTG
470pF
C2
0.1µF
COUT
(3) 3.3µF
C4
0.1µF
CIN
4.7µF
CLDOOUT
3.3µF
RRDY
100kΩ
R10
100kΩ
R5
475kΩ
R3
909kΩ
R8
49.9kΩ
R1
511kΩ
R2
49.9kΩ
R4
49.9kΩ
R7
470kΩ
R6
49.9kΩ
R9
6.8kΩ
NEGATIVE
VNEG = -12V
TO LOGIC
FB
FBL
SUPL
LDOOUT
BUF+
FBP
DRVP
GND
TGND
FBN
DRVN
REF
FLTSET
INTG
PGND
SUPB
CREF
0.22µF
MAX1778
LDO
VLDO = 13V
Q1
C5
1.0µF
R9
30kΩ
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steps up the input voltage so that the linear regulator will
not drop out. Therefore, to guarantee that the external
pass transistor does not saturate, the step-up converter’s
output voltage must be set above the linear regulator’s
output voltage plus the transistor’s saturation rating
(VMAIN ≥ VLDO + VSAT).
Power-Up Sequencing and Fault Protection
The MAX1778/MAX1880–MAX1885’s fault pro-
tection cannot be activated until the power-up sequence
is successfully completed and the power-ready out-
put goes low. Therefore, faults on the main output or
positive charge-pump output could damage the controller
or external components. Additional fault protection can be
added as shown in Figure 10. The external MOSFET and
pnp transistor isolate the positive outputs during startup.
When the controller finishes the power-up sequence,
the power-ready output goes low, turning on the pnp
transistor. Any fault on the positive charge-pump output
pulls down the charge pump’s output voltage and triggers
the fault protection; otherwise, the MOSFET’s gate slow
charges. Once the MOSFET turns on, any faults on the
main step-up converter’s output pull down the main output
voltage and trigger the fault protection.
VCOM Buffer Startup
The VCOM buffer does not include soft-start. Therefore,
once the VCOM buffer turns on, it draws high surge cur-
rents while charging the output capacitance. In some
applications, the buffer’s high startup surge current could
potentially trip the fault-detection circuit, forcing the con-
troller to shut down. In these cases, adding a soft-start
resistive-divider between SUPB and BUFOUT reduces the
startup surge current and voltage drops associated with
Figure 10. Power-Up Sequencing and Fault Protection
IN
SYSTEM
POSITIVE
VPOS(SYS) = 20V
STARTUP
POSITIVE
VPOS(START) = 20V
INPUT
VIN = 3.3V
SHDN
SUPP
LX
L1
6.8µH
INPUT
VIN = 3.3V
C1
0.22µF
C5
1.0µF
C7
1.0µF
Q2
Q3
COUT
(2) 3.3µF
C4
0.1µF
CIN
4.7µF
R10
100kΩ
RRDY
5.1kΩ
R1
274kΩ
R2
49.9kΩ
R7
10kΩ
FB
RDY
FBP
DRVP
GND
TGND
REF
FLTSET
INTG
PGND
CREF
0.22µF
MAX1778
C8
3.3µF
SYSTEM MAIN
VMAIN(SYS) = 8V
STARTUP MAIN
VMAIN(START) = 8V
C10
0.1µF
C6
0.1µF
R8
100kΩ
R3
750kΩ
R4
49.9kΩ
R9
30kΩ
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this load (Figure 11), as shown in the Typical Operating
Characteristics. Set the resistive divider to precharge
BUFOUT, matching the buffer’s output set voltage:
SUPB
BUFOUT
V
R3 R4 1
V
= −
These resistor values are selected to charge the output
capacitor close to the output set voltage before the buffer
starts up:
BUFOUT
OSC
5000
C (R3 || R 4 )
f
≈
Figure 11. VCOM Buffer Soft-Start
PART
STEP-UP
SWITCHING
FREQUENCY
(Hz)
DUAL
CHARGE
PUMPS
LINEAR
REGULATOR
MAX1778 1M Yes Yes
MAX1880 1M Yes No
MAX1881 500k Yes Yes
MAX1882 500k Yes No
MAX1883 1M No Yes
MAX1884 500k No Yes
MAX1885 500k No No
IN
BUFFER OUTPUT
VBUFOUT = VSUPB/2
SHDN
SUPB
LX
L1
6.8µH
INPUT
VIN = 3.3V
C1
0.22µF
COUT
(2) 4.7µF
CIN
4.7µF R1
274kΩ
R2
49.9kΩ
FB
BUFOUT
GND
BUF+
BUF-
REF
INTG
PGND
CREF
0.22µF
MAX1778
CSUPB
1.0µF
CBUF
1.0µF
R3
10kΩ
R4
10kΩ
MAIN
VMAIN = 8V
R3 = R4[( ) -1]
VSUPB
VBUFOUT
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Selector Guide
IN
BUFFER OUTPUT
POSITIVE
SHDN
RDY
SUPL
LDOOUT
SUPN
SUPP
DRVP
FBP
LX
INPUT
LDO OUTPUT
NEGATIVE
TO LOGIC
FB
BUFOUT
BUF-
BUF+
FLTSET
GND
TGND
FBL
DRVN
FBN
REF
INTG
PGND
SUPB
MAX1778
MAIN
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Typical Operating Circuit
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
TGND
LX
PGNDBUF+
IN
INTG
FB
TOP VIEW
DRVP
SUPP
DRVN
SUPNGND
BUFOUT
SUPB
BUF-
16
15
14
13
9
10
11
12
FLTSET
FBL
LDOOUT
SUPL
FBN
FBP
REF
TSSOP
MAX1778
MAX1881
RDY
SHDN
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
TGND
LX
PGNDBUF+
IN
INTG
FB
DRVP
SUPP
DRVN
SUPNGND
BUFOUT
SUPB
BUF-
16
15
14
13
9
10
11
12
FLTSET
N.C.
N.C.
N.C.
FBN
FBP
REF
TSSOP
MAX1880
MAX1882
RDY
SHDN
++
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
TGND
LX
PGNDBUF+
IN
INTG
FB
TOP VIEW
N.C.
N.C.
FLTSET
FBLGND
BUFOUT
SUPB
BUF-
12
11
9
10
LDOOUT
SUPL
REF
MAX1883
MAX1884
TSSOP
RDY
SHDN
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
TGND
LX
PGNDBUF+
IN
INTG
FB
N.C.
N.C.
FLTSET
N.C.GND
BUFOUT
SUPB
BUF-
12
11
9
10
N.C.
N.C.
REF
MAX1885
TSSOP
RDY
SHDN
++
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
www.maximintegrated.com Maxim Integrated
│
37
Pin Congurations
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 TSSOP U20-2 21-0066 90-0116
24 TSSOP U24-1 21-0066 90-0118
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
www.maximintegrated.com Maxim Integrated
│
38
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Chip Information
TRANSISTOR COUNT: 3739
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
2 10/12 Added MAX1880EUG/V+ to Ordering Information 1
3 4/15 Deleted MAX1880EUG/V+ from Ordering Information 1
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc.
│
39
MAX1778/MAX1880–MAX1885 Quad-Output TFT LCD DC/DC
Converters with Buffer
Revision History
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
