74LVCH32373AEC,551 - NXP Semiconductors / Philips Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of 1999 Nov 24 2004 May 19

INTEGRATED CIRCUITS

74LVCH32373A

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state

2004 May 19 2

Philips Semiconductors Product speciﬁcation

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state 74LVCH32373A

FEATURES

•5 V tolerant inputs/outputs for interfacing with 5 V logic

•Wide supply voltage range from 1.2 V to 3.6 V

•CMOS low power consumption

•MULTIBYTE flow-trough standard pin-out architecture

•Low inductance multiple power and ground pins for

minimum noise and ground bounce

•Direct interface with TTL levels

•Inputs accept voltages up to 5.5 V

•All data inputs have bushold

•Complies with JEDEC standard JESD8-B/JESD36

•ESD protection:

HBM EIA/JESD22-A114-B exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

•Specified from −40 °C to +85 °C

•Packaged in plastic fine-pitch ball grid array package.

DESCRIPTION

The 74LVCH32373A is a high-performance, low-power,

low-voltage, Si-gate CMOS device superior to most

advanced CMOS compatible TTL families.

The inputs can be driven from either 3.3 V or 5 V devices.

In 3-state operation, outputs can handle 5 V. These

features allow the use of these devices in a mixed

3.3 V and 5 V environment.

The 74LVCH32373A is a 32-bit transparent D-type latch

featuring separate D-type inputs for each latch and 3-state

outputs for bus oriented applications. One latch enable

input (nLE) and one output enable input (nOE) are

provided for each octal. Inputs can be driven from either

3.3 V or 5 V devices.

The74LVCH32373Aconsistsof4 sectionsofeightD-type

transparent latches with 3-state true outputs. When input

nLE is HIGH, data at the nDn inputs enter the latches. In

this condition the latches are transparent, i.e. a latch

output will change each time its corresponding D-input

changes.

When input nLE is LOW, the latches store the information

thatwaspresentattheD-inputsoneset-uptimepreceding

the HIGH-to-LOW transition of nLE. When input nOE is

LOW, the contents of the eight latches are available at the

outputs. When input nOE is HIGH, the outputs go to the

high-impedance OFF-state. Operation of the nOE input

does not affect the state of the latches.

The 74LVCH32373A bushold data input circuits eliminate

the need for external pull-up resistors to hold unused

inputs.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25°C; tr=t

f≤2.5 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD=C

PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

tPHL/tPLH propagation delay nDn to nQn CL= 50 pF; VCC = 3.3 V 3.0 ns

propagation delay nLE to nQn CL= 50 pF; VCC = 3.3 V 3.4 ns

tPZH/tPZL 3-state output enable time nOE to nQn CL= 50 pF; VCC = 3.3 V 3.5 ns

tPHZ/tPLZ 3-state output disable time nOE to nQn CL= 50 pF; VCC = 3.3 V 3.9 ns

CIinput capacitance 5.0 pF

CPD power dissipation per latch VCC = 3.3 V; notes 1 and 2

outputs enabled 15 pF

outputs disabled 11 pF

2004 May 19 3

Philips Semiconductors Product speciﬁcation

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state 74LVCH32373A

CL= output load capacity in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

Σ(CL×VCC2×fo) = sum of the outputs.

2. The condition is VI= GND to VCC.

FUNCTION TABLE

See note 1.

Note

1. H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;

Z = high-impedance OFF-state.

ORDERING INFORMATION

OPERATING MODE INPUT INTERNAL

LATCH OUTPUT

nOE nLE nDn nQn

Enable and read register

(transparent mode) LHLLL

LHHHH

Latch and read register L L l L L

LLhHH

Latch register and disable

outputs HL l LZ

HLhHZ

TYPE NUMBER PACKAGE

TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE

74LVCH32373AEC −40 °C to +85 °C 96 LFBGA96 plastic SOT536-1

PINNING

BALL SYMBOL DESCRIPTION

A1 1Q1 data output

A2 1Q0 data output

A3 1OE output enable input (active LOW)

A4 1LE latch enable input (active HIGH)

A5 1D0 data input

A6 1D1 data input

B1 1Q3 data output

B2 1Q2 data output

B3 GND ground (0 V)

B4 GND ground (0 V)

B5 1D2 data input

B6 1D3 data input

C1 1Q5 data output

C2 1Q4 data output

C3 VCC supply voltage

C4 VCC supply voltage

C5 1D4 data input

C6 1D5 data input

D1 1Q7 data output

D2 1Q6 data output

D3 GND ground (0 V)

BALL SYMBOL DESCRIPTION

2004 May 19 4

Philips Semiconductors Product speciﬁcation

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state 74LVCH32373A

D4 GND ground (0 V)

D5 1D6 data input

D6 1D7 data input

E1 2Q1 data output

E2 2Q0 data output

E3 GND ground (0 V)

E4 GND ground (0 V)

E5 2D0 data input

E6 2D1 data input

F1 2Q3 data output

F2 2Q2 data output

F3 VCC supply voltage

F4 VCC supply voltage

F5 2D2 data input

F6 2D3 data input

G1 2Q5 data output

G2 2Q4 data output

G3 GND ground (0 V)

G4 GND ground (0 V)

G5 2D4 data input

G6 2D5 data input

H1 2Q6 data output

H2 2Q7 data output

H3 2OE output enable input (active LOW)

H4 2LE latch enable input (active HIGH)

H5 2D7 data input

H6 2D6 data input

J1 3Q1 data output

J2 3Q0 data output

J3 3OE output enable input (active LOW)

J4 3LE latch enable input (active HIGH)

J5 3D0 data input

J6 3D1 data input

K1 3Q3 data output

K2 3Q2 data output

K3 GND ground (0 V)

K4 GND ground (0 V)

K5 3D2 data input

K6 3D3 data input

L1 3Q5 data output

L2 3Q4 data output

BALL SYMBOL DESCRIPTION

L3 VCC supply voltage

L4 VCC supply voltage

L5 3D4 data input

L6 3D5 data input

M1 3Q7 data output

M2 3Q6 data output

M3 GND ground (0 V)

M4 GND ground (0 V)

M5 3D6 data input

M6 3D7 data input

N1 4Q1 data output

N2 4Q0 data output

N3 GND ground (0 V)

N4 GND ground (0 V)

N5 4D0 data input

N6 4D1 data input

P1 4Q3 data output

P2 4Q2 data output

P3 VCC supply voltage

P4 VCC supply voltage

P5 4D2 data input

P6 4D3 data input

R1 4Q5 data output

R2 4Q4 data output

R3 GND ground (0 V)

R4 GND ground (0 V)

R5 4D4 data input

R6 4D5 data input

T1 4Q6 data output

T2 4Q7 data output

T3 4OE output enable input (active LOW)

T4 4LE latch enable input (active HIGH)

T5 4D7 data input

T6 4D6 data input

BALL SYMBOL DESCRIPTION

2004 May 19 5

Philips Semiconductors Product speciﬁcation

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state 74LVCH32373A

mna492

1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D6 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6

1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D7 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7

1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q7 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7

1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q6 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6

1LE 2LE 3LEGND GND GND GND 4LE

VCC

GND GND GND GND

1OE

3 2OE 3OEGND GND GND GND 4OEGND GND GND GND

AHJBDEG TCF KMNRLP

Fig.1 Pin configuration.

mna493

LE LE

1Q0

LATCH 1

to 7 other channels

1OE

1D0

1LE

LE LE

2Q0

LATCH 9

to 7 other channels

2OE

2D0

2LE

LE LE

3Q0

LATCH 17

to 7 other channels

3OE

3D0

3LE

LE LE

4Q0

LATCH 25

to 7 other channels

4OE

4D0

4LE

Fig.2 Logic symbol.

2004 May 19 6

Philips Semiconductors Product speciﬁcation

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state 74LVCH32373A

handbook, halfpage

MNA473

VCC

data

input to internal circuit

Fig.3 Bushold circuit.

RECOMMENDED OPERATING CONDITIONS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. All supply and ground pins connected externally to one voltage source.

3. Above 70 °C the value of Ptot derates linearly with 1.8 mW/K.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCC supply voltage for maximum speed performance 2.7 3.6 V

for low-voltage applications 1.2 3.6 V

VIinput voltage 0 5.5 V

VOoutput voltage output HIGH or LOW state 0 VCC V

output 3-state 0 5.5 V

Tamb ambient temperature in free air −40 +85 °C

tr,t

finput rise and fall times VCC = 1.2 V to 2.7 V 0 20 ns/V

VCC = 2.7 V to 3.6 V 0 10 ns/V

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCC supply voltage −0.5 +6.5 V

IIK input diode current VI<0V −−50 mA

VIinput voltage note 1 −0.5 +6.5 V

IOK output diode current VO>V

CC or VO<0V −±50 mA

VOoutput voltage output HIGH or LOW state; note 1 −0.5 VCC + 0.5 V

output 3-state; note 1 −0.5 +6.5 V

IOoutput source or sink current VO=0VtoV

CC −±50 mA

ICC,I

GND VCC or GND current note 2 −±200 mA

Tstg storage temperature −65 +150 °C

Ptot power dissipation Tamb =−40 °C to +85 °C; note 3 −1000 mW

2004 May 19 7

Philips Semiconductors Product speciﬁcation

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state 74LVCH32373A

DC CHARACTERISTICS

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Notes

1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.

2. For bushold parts, the bushold circuit is switched off when VI>V

CC allowing 5.5 V on the input pin.

3. For data inputs only, control inputs do not have a bushold circuit.

4. The specified sustaining current at the data inputs holds the input below the specified VI level.

5. The specified overdrive current at the data input forces the data input to the opposite logic input state.

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT

OTHER VCC (V)

Tamb =−40 °C to +85 °C; note 1

VIH HIGH-level input voltage 1.2 VCC −−V

2.7 to 3.6 2.0 −−V

VIL LOW-level input voltage 1.2 −−GND V

2.7 to 3.6 −−0.8 V

VOH HIGH-level output voltage VI=V

IH or VIL

IO=−100 µA 2.7 to 3.6 VCC −0.2 VCC −V

IO=−12 mA 2.7 VCC −0.5 −−V

IO=−18 mA 3.0 VCC −0.6 −−V

IO=−24 mA 3.0 VCC −0.8 −−V

VOL LOW-level output voltage VI=V

IH or VIL

IO= 100 µA 2.7 to 3.6 −GND 0.20 V

IO=12mA 2.7 −−0.40 V

IO=24mA 3.0 −−0.55 V

ILI input leakage current VI= 5.5 Vor GND;

note 2 3.6 −±0.1 ±5µA

IOZ 3-state output OFF-state

current VI=V

IH or VIL;

VO= 5.5 Vor GND;

note 2

3.6 −0.1 ±5µA

Ioff power-off leakage supply

current VIor VO= 5.5 V 0.0 −0.1 ±10 µA

ICC quiescent supply current VI=V

CC or GND;

IO=0A 3.6 −0.1 40 µA

∆ICC additionalquiescentsupply

current per input pin VI=V

CC −0.6 V;

IO=0A 2.7 to 3.6 −5 500 µA

IBH bushold LOW sustaining

current VI= 0.8 V;

notes 3 and 4 3.0 75 −−µA

IBHH bushold HIGH sustaining

current VI= 2.0 V;

notes 3 and 4 3.0 −75 −−µA

IBHLO bushold LOW overdrive

current notes 3 and 5 3.6 500 −−µA

IBHHO bushold HIGH overdrive

current notes 3 and 5 3.6 −500 −−µA

2004 May 19 8

Philips Semiconductors Product speciﬁcation

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state 74LVCH32373A

AC CHARACTERISTICS

GND = 0 V; tr=t

f≤2.5 ns; CL= 50 pF; RL= 500 Ω.

Notes

1. All typical values are measured at Tamb =25°C.

2. Measured at VCC = 3.3 V.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

WAVEFORMS VCC (V)

Tamb =−40 °C to +85 °C; note 1

tPHL/tPLH propagation delay nDn to nQn see Fig 4 and 8 1.2 −12 −ns

2.7 1.5 −4.9 ns

3.0 to 3.6 1.0 3.0(2) 4.4 ns

propagation delay nLE to nQn see Fig 5 and 8 1.2 −14 −ns

2.7 1.5 −5.3 ns

3.0 to 3.6 1.5 3.4(2) 4.8 ns

tPZH/tPZL 3-state output enable time nOE to nQn see Fig 7 and 8 1.2 −18 −ns

2.7 1.5 −5.7 ns

3.0 to 3.6 1.0 3.5(2) 4.9 ns

tPHZ/tPLZ 3-state output disable time nOE to nQn see Fig 7 and 8 1.2 −11 −ns

2.7 1.5 −6.3 ns

3.0 to 3.6 1.5 3.9(2) 5.4 ns

tWnLE pulse width HIGH see Fig 5 1.2 −−−ns

2.7 3.0 −−ns

3.0 to 3.6 3.0 2.0(2) −ns

tsu set-up time nDn to nLE see Fig 6 1.2 −−−ns

2.7 2.0 −−ns

3.0 to 3.6 2.0 1.0(2) −ns

thhold time nDn to nLE see Fig 6 1.2 −−−ns

2.7 0.9 −−ns

3.0 to 3.6 0.9 −1.0(2) −ns

tsk(0) skew 3.0 to 3.6 −−1.0 ns

2004 May 19 9

Philips Semiconductors Product speciﬁcation

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state 74LVCH32373A

AC WAVEFORMS

mna494

nDn input

nQn output

tPHL tPLH

GND

VOH

VOL

Fig.4 Input (nDn) to output (nQn) propagation delay times.

VM= 1.5 V at VCC ≥2.7 V;

VM= 0.5 ×VCC at VCC < 2.7 V;

VOL and VOH are typical output voltage drop that occur with the output load.

mna495

nLE input

nQn output

tPHL tPLH

VOH

GND

VOL

VMVM

Fig.5 Latch enable inputs (nLE) pulse width and the latch enable input to outputs (nQn) propagation delay times.

VM= 1.5 V at VCC ≥2.7 V;

VM= 0.5 ×VCC at VCC < 2.7 V;

VOL and VOH are typical output voltage drop that occur with the output load.

2004 May 19 10

Philips Semiconductors Product speciﬁcation

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state 74LVCH32373A

mna496

tsu

GND

nLE input

nDn input

Fig.6 Set-up and hold times for inputs (nDn) to inputs (nLE).

VM= 1.5 V at VCC ≥2.7 V;

VM= 0.5 ×VCC at VCC < 2.7 V.

Fig.7 3-state output enable and disable times.

VM= 1.5 V at VCC ≥2.7 V;

VM= 0.5 ×VCC at VCC < 2.7 V. VX=V

OL +0.3VatV

CC ≥2.7 V;

VX=V

OL +0.1VatV

CC < 2.7 V;

VY=V

OH −0.3VatV

CC ≥2.7 V;

VY=V

OH −0.1VatV

CC < 2.7 V.

handbook, full pagewidth

MNA478

tPLZ

tPHZ

outputs

disabled outputs

enabled

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

nOE input

VOL

VOH

VCC

GND

tPZL

tPZH

VOL and VOH are typical output voltage drop that occur with

the output load.

2004 May 19 11

Philips Semiconductors Product speciﬁcation

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state 74LVCH32373A

handbook, full pagewidth

VEXT

VCC

VIVO

MNA616

D.U.T.

PULSE

GENERATOR

Fig.8 Load circuitry for switching times.

Definitions for test circuits:

RL= Load resistor.

CL= Load capacitance including jig and probe capacitance.

RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.

Note

1. The circuit performs better when RL= 1000 Ω.

VCC VICLRLVEXT

tPLH/tPHL tPZH/tPHZ tPZL/tPLZ

1.2 V VCC 50 pF 500 Ω(1) open GND 2 ×VCC

2.7 V 2.7 V 50 pF 500 Ωopen GND 2 ×VCC

3.0 V to 3.6 V 2.7 V 50 pF 500 Ωopen GND 2 ×VCC

2004 May 19 12

Philips Semiconductors Product speciﬁcation

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state 74LVCH32373A

PACKAGE OUTLINE

0.8

UNIT Dye

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

00-03-04

03-02-05

IEC JEDEC JEITA

mm 1.5 0.41

0.31 1.2

0.9 5.6

5.4

13.6

13.4

0.51

0.41 0.1 0.2

DIMENSIONS (mm are the original dimensions)

SOT536-1

0.15

0.1

0 5 10 mm

scale

SOT536-1

LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm

max.

detail X

246135

ball A1

index area

ball A1

index area

y1C

∅

1/2

2004 May 19 13

Philips Semiconductors Product speciﬁcation

32-bit transparent D-type latch with

5 V tolerant inputs/outputs; 3-state 74LVCH32373A

DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

LEVEL DATA SHEET

STATUS(1) PRODUCT

STATUS(2)(3) DEFINITION

I Objective data Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Relevant changes will

be communicated via a Customer Product/Process Change Notiﬁcation

(CPCN).

DEFINITIONS

Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

attheseorat anyotherconditionsabovethose given inthe

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Application information  Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

norepresentationorwarrantythatsuchapplicationswillbe

suitable for the specified use without further testing or

modification.

DISCLAIMERS

Life support applications  These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductorscustomersusingorselling theseproducts

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes  Philips Semiconductors

reserves the right to make changes in the products -

including circuits, standard cells, and/or software -

described or contained herein in order to improve design

and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be

communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these

products, conveys no licence or title under any patent,

makes no representations or warranties that these

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right infringement, unless otherwise specified.

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Contact information

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Printed in The Netherlands R20/02/pp14 Date of release: 2004 May 19 Document order number: 9397 750 13227