SN74V245-15PAGEP - Texas Instruments

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4096 × 18 DSP-SYNC™ FIRST-IN, FIRST-OUT MEMORY

Check for Samples: SN74V245-EP

1FEATURES

2• 4096 × 18-Bit Organization Array • Provide a DSP Glueless Interface to Texas

Instruments TMS320™ DSPs

• 7.5-ns Read and Write Cycle Time • Packaged in 64-Pin Thin Quad Flat Package

• 3.3-V VCC, 5-V Input Tolerant

• First-Word or Standard Fall-Through Timing SUPPORTS DEFENSE, AEROSPACE,

• Single or Double Register-Buffered Empty and AND MEDICAL APPLICATIONS

Full Flags • Controlled Baseline

• Easily Expandable in Depth and Width • One Assembly and Test Site

• Asynchronous or Coincident Read and Write • One Fabrication Site

Clocks • Available in Military (–55°C to 125°C)

• Asynchronous or Synchronous Programmable Temperature Range

Almost-Empty and Almost-Full Flags With • Extended Product Life Cycle

Default Settings • Extended Product-Change Notification

• Half-Full Flag Capability • Product Traceability

• Output Enable Puts Output Data Bus in High-

Impedance State

• High-Performance Submicron CMOS

Technology

• DSP and Microprocessor Interface Control

Logic

DESCRIPTION/ORDERING INFORMATION

The SN74V245 is a very high-speed, low-power CMOS clocked first-in first-out (FIFO) memory. It supports clock

frequencies up to 133 MHz and has read-access times as fast as 5 ns. This DSP-Sync FIFO memory features

read and write controls for use in applications such as DSP-to-processor communication, DSP-to-analog front

end (AFE) buffering, network, video, and data communications.

The SN74V245 is a synchronous FIFO, which means each port employs a synchronous interface. All data

transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable

signals. The continuous clocks for each port are independent of one another and can be asynchronous or

coincident. The enables for each port are arranged to provide a simple interface between DSPs,

microprocessors, and/or buses controlled by a synchronous interface. An output-enable (OE) input controls the

3-state output.

The synchronous FIFO has two fixed flags, empty flag/output ready (EF/OR) and full flag/input ready (FF/IR), and

two programmable flags, almost-empty (PAE) and almost-full (PAF). The offset loading of the programmable

flags is controlled by a simple state machine, and is initiated by asserting the load pin (LD). A half-full flag (HF) is

available when the FIFO is used in a single-device configuration.

Two timing modes of operation are possible with the SN74V245: first-word fall-through (FWFT) mode and

standard mode.

In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three

transitions of the RCLK signal. A read enable (REN) does not have to be asserted for accessing the first word.

In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a

specific read operation is performed. A read operation, which consists of activating REN and enabling a rising

RCLK edge, shifts the word from internal memory to the data output lines.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2DSP-SYNC, TMS320 are trademarks of Texas Instruments.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Write-Control

Logic

RAM ARRAY

512 ×18, 1024 ×18,

2048 ×18, 4096 ×18

Offset

Input

Flag

Logic

Read

Pointer

Read-Control

Logic

Output

Write

Pointer

Expansion

Logic

Reset

Logic

(HF)/WXO

WXI

RXI

RXO

WEN

WCLK

D0–D17

HF/(WXO)

PAE

EF/OR

PAF

FF/IR

Q0–Q17

OE RENRCLK

58 61 60

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The SN74V245 is depth expandable, using a daisy-chain technique or FWFT mode. The XI and XO pins are

used to expand the FIFOs. In depth-expansion configuration, first load (FL) is grounded on the first device and

set to high for all other devices in the daisy chain.

The SN74V245 is characterized for operation from –55°C to 125°C.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION(1)

TJPACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER

–55°C to 125°C 64-pin TQFP (PAG) SN74V245-15PAGEP V245-15EP V62/13606-01XE

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

FUNCTIONAL BLOCK DIAGRAM

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PAG PACKAGE

(TOP VIEW)

D15

D14

D13

D12

D11

D10

Q14

Q13

GND

Q12

Q11

VCC

Q10

GND

VCC

D16

D17

GND

WEN

WXI

PAE

WCLK

REN

Q17

GND

Q15

RCLK

RXO

PAF

RXI

WXO/HF

GND

Q16

GND

FF/IR

EF/OR

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DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL I/O DESCRIPTION

NAME NO.

D0–D17 1-16, 63, 64 I Data inputs. Data inputs for an 18-bit bus.

Memory-empty/valid-data-available flag. In the standard mode, the EF function is selected.

EF/OR 54 O EF indicates whether the FIFO memory is empty. In FWFT mode, the OR function is

selected. OR indicates whether there is valid data available at the outputs.

Memory-full/space-available flag. In the standard mode, the FF function is selected. FF

FF/IR 25 O indicates whether the FIFO memory is full. In the FWFT mode, the IR function is selected. IR

indicates whether there is space available for writing to the FIFO memory.

Mode selection. In the single-device or width-expansion configuration, FL, together with WXI

and RXI, determines if the mode is standard mode or first-word fall-through (FWFT) mode,

FL 18 I as well as whether the PAE/PAF flags are synchronous or asynchronous (see Table 5). In

the daisy-chain depth-expansion configuration, FL is grounded on the first device (first-load

device) and set to high for all other devices in the daisy chain.

30, 35, 40, 46, 51,

GND Ground

55, 62 Read/write control. When LD is low, data on the inputs D0–D11 is written to the offset and

depth registers on the low-to-high transition of the WCLK, when WEN is low. When LD is

LD 59 I low, data on the outputs Q0–Q11 is read from the offset and depth registers on the low-to-

high transition of RCLK when REN is low.

Output enable. When OE is low, the data output bus is active. If OE is high, the output data

OE 58 I bus is in the high-impedance state.

Programable almost-empty flag. When PAE is low, the FIFO is almost empty, based on the

PAE 17 O offset programmed into the FIFO. The default offset at reset is 127 from empty.

Programable almost-full flag. When PAF is low, the FIFO is almost full, based on the offset

PAF 23 O programmed into the FIFO. The default offset at reset is 127 from full.

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TERMINAL FUNCTIONS (continued)

TERMINAL I/O DESCRIPTION

NAME NO.

28, 29, 31, 32, 34,

36–39, 41, 42, 44,

Q0–Q17 O Data outputs. Data outputs for an 18-bit bus.

45, 47, 48, 50, 52,

53 Read clock. When REN is low, data is read from the FIFO on a low-to-high transition of

RCLK 61 I RCLK, if the FIFO is not empty.

Read enable. When REN is low, data is read from the FIFO on every low-to-high transition of

REN 60 I RCLK. When REN is high, the output register holds the previous data. Data is not read from

the FIFO if EF is low.

Reset. When RS is set low, internal read and write pointers are set to the first location of the

RS 57 I RAM array, FF and PAF go high, and PAE and EF go low. A reset is required before an

initial write after power up.

Read expansion. In the single-device or width-expansion configuration, RXI, together with FL

and WXI, determines if the mode is standard mode or FWFT mode, as well as whether the

RXI 24 I PAE/PAF flags are synchronous or asynchronous (see Table 5). In the daisy-chain depth-

expansion configuration, RXI is connected to RXO (read expansion out) of the previous

device.

Last-location-read flag. In the depth-expansion configuration, a pulse is sent from RXO to

RXO 27 O RXI of the next device when the last location in the FIFO is read.

VCC 22, 33, 43, 49, 56 Supply voltage. +3.3-V power-supply pins.

Write clock. When WEN is low, data is written into the FIFO on a low-to-high transition of

WCLK 19 I WCLK if the FIFO is not full.

Write enable. When WEN is low, data is written into the FIFO on every low-to-high transition

WEN 20 I of WCLK. When WEN is high, the FIFO holds the previous data. Data is not written into the

FIFO if FF is low.

Width expansion. In the single-device or width-expansion configuration, WXI, together with

FL and RXI, determines if the mode is standard mode or FWFT mode, as well as whether

WXI 21 I the PAE/PAF flags are synchronous or asynchronous (see Table 5). In the daisy-chain

depth-expansion configuration, WXI is connected to WXO (write expansion out) of the

previous device.

Half-full flag. In the single-device or width-expansion configuration, the device is more than

WXO/HF 26 O half full when HF is low. In the depth-expansion configuration, a pulse is sent from WXO to

WXI of the next device when the last location in the FIFO is written.

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)(1)

VALUE

Supply voltage range, VCC –0.5 V to 5 V

Continuous output current, IO(VO= 0 to VCC) ±50 mA

Maximum junction temperature, Tj 150°C

Storage temperature range, Tstg –65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS(1)

MIN TYP MAX UNIT

VCC Supply voltage 3 3.3 3.6 V

VIH High-level input voltage 2 5 V

VIL Low-level input voltage 0.8 V

TJOperating junction temperature –55 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

THERMAL INFORMATION SN74V245

THERMAL METRIC(1) PAG UNITS

64 PINS

θJA Junction-to-ambient thermal resistance(2) 46.1

θJCtop Junction-to-case (top) thermal resistance(3) 5.8

θJB Junction-to-board thermal resistance(4) 19.7 °C/W

ψJT Junction-to-top characterization parameter(5) 0.2

ψJB Junction-to-board characterization parameter(6) 19.4

θJCbot Junction-to-case (bottom) thermal resistance(7) N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

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100

1000

10000

100000

120 130 140 150 160 170

Life (Hrs)

Operating Junction Temperature (°C)

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ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOH High-level output voltage VCC = 3 V, IOH = -2 mA 2.4 V

VOL Low-level output voltage VCC = 3 V, IOL = 8 mA 0.4 V

IIInput current VCC = 3.6 V, VI= VCC to 0.4 V ±1 µA

IOZ High-impedance output current VCC = 3.6 V, OE ≥VIH, VO= VCC to 0.4 V ±10 µA

ICC1 Supply current VCC = 3.3 V, See (1),(2) and (3) 35 mA

ICC2 VCC = 3.6 V, See (1) and (4) 5 mA

CIN Input capacitance VI= 0, TA= 25°C, f = 1 MHz 10 pF

VO= 0, TA= 25°C, f = 1 MHz, Output

COUT 10 pF

deslected, (OE ≥VIH)

(1) Tested with outputs disabled (IOUT = 0).

(2) RCLK and WCLK switch at 20 MHz and data inputs switch at 10 MHz.

(3) Typical ICC1 = 2.04 + 0.88 × fSW + 0.02 × CL × fSW (in mA). These equations are valid under the following conditions:

VCC = 3.3 V, TA= 25°C, fSW = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fSW/2, CL= capacitive

load (in pF).

(4) All inputs = (VCC – 0.2 V) or (GND + 0.2 V), except RCLK and WCLK, which switch at 20 MHz.

xxx

(1) See datasheet for absolute maximum and minimum recommended operating conditions.

(2) Silicon operating life design goal is 100,000 hrs at 106°C junction temperature (does not include package interconnect

life).

(3) The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the

dominant failure mechanism affecting device wearout for the specific device process and design characteristics.

Figure 1. Electromigration Fail Mode Derating Chart

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TIMING REQUIREMENTS MIN MAX UNIT

fclock Clock cycle frequency 66.7 MHz

tAData access time 1 11 ns

tCLK Clock cycle time 16 ns

tCLKH Clock high time 7 ns

tCLKL Clock low time 7 ns

tDS Data setup time 5 ns

tDH Data hold time 2 ns

tENS Enable setup time 5 ns

tENH Enable hold time 2 ns

tLDS Load setup time 5 ns

tLDH Load hold time 2 ns

tRS Reset pulse width(1) 16 ns

tRSS Reset setup time 10.5 ns

tRSR Reset recovery time 10.5 ns

tRSF Reset to flag and output time 16 ns

tOLZ Output enable to output in low Z 0 ns

tOE Output enable to output valid 1.5 9 ns

tOHZ Output enable to output in high Z 1.5 9 ns

tWFF Write clock to Full flag 11 ns

tREF Read clock to Empty flag 11 ns

tPAFA Clock to asynchronous programmable Almost-Full flag 21 ns

tPAFS Write clock to synchronous programmable Almost-Full flag 11 ns

tPAEA Clock to asynchronous programmable Almost-Empty flag 21 ns

tPAES Read clock to synchronous programmable Almost-Empty flag 11 ns

tHF Clock to Half-Full flag 21 ns

tXO Clock to expansion out 11 ns

tXI Expansion in pulse duration 7 ns

tXIS Expansion in setup time 6 ns

tSKEW1 Skew time between read clock and write clock for FF/IR and EF/OR 6.5 ns

tSKEW2 Skew time between read clock and write clock for PAE and PAF (synchronous only) 18.5 ns

(1) Pulse durations less than minimum values are not allowed.

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From Output

Under Test

30 pF

(see Note A)

510 Ω

330 Ω

3.3 V

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load for tCLK = 10 ns, 15 ns

Output Load for tCLK = 7.5 ns

GND to 3.0 V

3 ns

1.5 V

See A

See B and C

AC TEST CONDITIONS

50 Ω

VCC/2

ZO= 50 Ω

I/O

B. AC TEST LOAD FOR 7.5 SPEED GRADE

A. OUTPUT LOAD CIRCUIT

FOR 10, 15, AND 20 SPEED GRADES

0 20 40 60 80 100 120 140 160 180 200

C. LUMPED CAPACITIVE LOAD, TYPICAL DERATING

Capacitance – pF

Typical – t∆CD – ns

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PARAMETER MEASUREMENT INFORMATION

A. Includes probe and jig capacitance

Figure 2. Load Circuits

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DETAILED DESCRIPTION

INPUTS:

DATA IN (D0–D17)

Data inputs for 18-bit-wide data.

CONTROLS:

RESET (RS)

Reset is accomplished when RS is taken low. During reset, both internal read and write pointers are set to the

first location. A reset is required after power up before a write operation can take place. The half-full flag (HF)

and programmable almost-full flag (PAF) is reset to high after tRSF. The programmable almost-empty flag (PAE)

is reset to low after tRSF. The full flag (FF) resets to high. The empty flag (EF) resets to low in standard mode, but

resets to high in FWFT mode. During reset, the output register is initialized to all zeros, and the offset registers

are initialized to their default values.

WRITE CLOCK (WCLK)

A write cycle is initiated on the low-to-high transition of WCLK. Data setup and hold times must be met with

respect to the low-to-high transition of WCLK.

The write and read clocks can be asynchronous or coincident.

WRITE ENABLE (WEN)

When WEN is low, data can be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the

device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation.

When WEN is high, no new data is written in the RAM array on each WCLK cycle.

To prevent data overflow in the standard mode, FF goes low, inhibiting further write operations. Upon completion

of a valid read cycle, FF goes high, allowing a write to occur. The FF flag is updated on the rising edge of WCLK.

To prevent data overflow in the FWFT mode, IR goes high, inhibiting further write operations. Upon completion of

a valid read cycle, IR goes low, allowing a write to occur. The IR flag is updated on the rising edge of WCLK.

WEN is ignored when the FIFO is full in either FWFT or standard mode.

READ CLOCK (RCLK)

Data can be read on the outputs on the low-to-high transition of RCLK when OE is low.

The write and read clocks can be asynchronous or coincident.

READ ENABLE (REN)

When REN is low, data is loaded from the RAM array into the output register on the rising edge of every RCLK

cycle if the device is not empty.

When REN is high, the output register holds the previous data and no new data is loaded into the output register.

Data outputs Q0–Qn maintain the previous data value.

In the standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be

requested using REN. When the last word has been read from the FIFO, the empty flag (EF) goes low, inhibiting

further read operations. REN is ignored when the FIFO is empty. After a write is performed, EF goes high,

allowing a read to occur. The EF flag is updated on the rising edge of RCLK.

In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third

valid low-to-high transition of RCLK + tSKEW after the first write. REN need not be asserted low. To access all

other words, a read must be executed using REN. The RCLK low-to-high transition after the last word has been

read from the FIFO, output ready (OR) goes high with a true read (RCLK with REN low), inhibiting further read

operations. REN is ignored when the FIFO is empty.

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OUTPUT ENABLE (OE)

When OE is low, the parallel output buffers transmit data from the output register. When OE is high, the Q-output

data bus is in the high-impedance state.

LOAD (LD)

The SN74V245 contains two 12-bit offset registers with data on the inputs, or read on the outputs. When LD is

low and WEN is low, data on the inputs D0–D11 is written into the empty offset register on the first low-to-high

transition of the write clock (WCLK). When LD and WEN are held low, data is written into the full offset register

on the second low-to-high transition of WCLK (see Table 1,Table 2 and Table 3). The third transition of WCLK

again writes to the empty-offset register.

However, writing to all offset registers need not occur at one time. One or two offset registers can be written and

then, by bringing LD high, the FIFO is returned to normal read/write operation. When LD is low, and WEN is low,

the next offset register in sequence is written.

Table 1. Writing to Offset Registers

LD WEN WCLK SELECTION(1)

Writing to offset registers:

L L ↑Empty offset

Full offset

L H ↑No operation

H L ↑Write into FIFO

H H ↑No operation

(1) The same selection sequence applies to reading from the registers.

REN is enabled and read is performed on the low-to-high transition

of RCLK.

Table 2. Empty Offset Register Location and Default Values(1)

17 12 11 0

Empty Offset Register

Not used Default value

007FH

(1) Any bits of the offset register not being programmed should be set to zero.

Table 3. Full Offset Register Location and Default Values(1)

17 12 11 0

Full Offset Register

Not used Default value

007FH

(1) Any bits of the offset register not being programmed should be set to zero.

When LD is low and WEN is high, the WCLK input is disabled; then, a signal at this input can neither increment

the write-offset-register pointer, nor execute a write.

The contents of the offset registers can be read on the output lines when LD is low and REN is low; then, data

can be read on the low-to-high transition of RCLK. Reading the control registers employs a dedicated read-

offset-register pointer (the read and write pointers operate independently). Offset register content can be read out

in the standard mode only. It is inhibited in the FWFT mode.

A read from and a write to the offset registers should not be performed simultaneously.

FIRST LOAD (FL)

For the single-device mode, see Table 6 for additional information. In the daisy-chain depth-expansion

configuration, FL is grounded to indicate it is the first device loaded and is set high for all other devices in the

daisy chain (see Operating Configurations for further details).

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WRITE EXPANSION INPUT (WXI)

This is a dual-purpose pin. For single-device mode, see Table 6 for additional information. WXI is connected to

write expansion out (WXO) of the previous device in the daisy-chain depth-expansion mode.

READ EXPANSION INPUT (RXI)

This is a dual-purpose pin. For single-device mode, see Table 6 for additional information. RXI is connected to

read expansion out (RXO) of the previous device in the daisy-chain depth-expansion mode.

OUTPUTS:

FULL FLAG/INPUT READY (FF/IR)

This is a dual-purpose pin. In FWFT mode, the input ready (IR) function is selected. IR goes low when memory

space is available for writing data. When there is no free space left, IR goes high, inhibiting further write

operations.

In standard mode, the FF function is selected. When the FIFO is full, FF goes low, inhibiting further write

operations. When FF is high, the FIFO is not full. If no reads are performed after a reset, FF goes low after D

writes to the FIFO. D = 4096.

IR goes high after D writes to the FIFO. D = 4097. The additional word in FWFT mode is due to the capacity of

the memory plus output register.

FF/IR is synchronous and updated on the rising edge of WCLK.

EMPTY FLAG/OUTPUT READY (EF/OR)

This is a dual-purpose pin. In FWFT mode, the OR function is selected. OR goes low at the same time the first

word written to an empty FIFO appears valid on the outputs. OR stays low after the RCLK low-to-high transition

that shifts the last word from the FIFO memory to the outputs. OR goes high only with a true read (RCLK with

REN low). The previous data stays at the outputs, indicating that the last word was read. Further data reads are

inhibited until OR goes low again.

In the standard mode, the EF function is selected. When the FIFO is empty, EF goes low, inhibiting further read

operations. When EF is high, the FIFO is not empty.

EF/OR is synchronous and updated on the rising edge of RCLK.

PROGRAMMABLE ALMOST-FULL FLAG (PAF)

PAF goes low when the FIFO reaches the almost-full condition. In FWFT mode, if no reads are performed, PAF

goes low after 4097 - m. Default values for m are in Table 4 and Table 5.

In standard mode, if no reads are performed after reset (RS), PAF goes low after 4096 – m writes. The offset m

is defined in Table 3.

If asynchronous PAF configuration is selected, PAF is asserted low on the low-to-high transition of WCLK. PAF is

reset to high on the low-to-high transition of RCLK. If synchronous PAF configuration is selected (see Table 6),

PAF is updated on the rising edge of WCLK.

PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)

PAE goes low when the FIFO reaches the almost-empty condition. In FWFT mode, PAE goes low when there

are n + 1 words, or fewer, in the FIFO. In standard mode, PAE goes low when there are n words or fewer in the

FIFO. The offset n is defined as the empty offset. The default values for n are noted in Table 4 and Table 5.

If there is no empty offset specified, PAE is low when the device is 127 away from completely empty.

If asynchronous PAE configuration is selected, PAE is asserted low on the low-to-high transition of the read clock

(RCLK). PAE is reset to high on the low-to-high transition of the write clock (WCLK). If synchronous PAE

configuration is selected (see Table 6), PAE is updated on the rising edge of RCLK.

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WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF)

This is a dual-purpose output. In the single-device and width-expansion mode, when write expansion in (WXI)

and/or read expansion in (RXI) are grounded, this output acts as an indication of a half-full memory.

After one-half of the memory is filled, and at the low-to-high transition of the next write cycle, the half-full flag

(HF) goes low and remains set until the difference between the write pointer and read pointer is less than or

equal to one-half of the total memory of the device. HF is then reset to high by the low-to-high transition of the

read clock (RCLK). HF is asynchronous.

In the daisy-chain depth-expansion mode, WXI is connected to WXO of the previous device. This output acts as

a signal to the next device in the daisy chain by providing a pulse when the previous device writes to the last

location of memory.

READ EXPANSION OUT (RXO)

In the daisy-chain depth-expansion configuration, read expansion in (RXI) is connected to read expansion out

(RXO) of the previous device. This output acts as a signal to the next device in the daisy chain by providing a

pulse when the previous device reads from the last location of memory.

DATA OUTPUTS (Q0–Q17)

Q0–Q17 are data outputs for 18-bit-wide data.

FUNCTIONAL DESCRIPTION

TIMING MODES:

STANDARD vs FIRST-WORD FALL-THROUGH (FWFT) MODE

The SN74V245 supports two different timing modes. The selection of the mode of operation is determined during

configuration at reset (RS). During an RS operation, the first load (FL), read expansion input (RXI), and write-

expansion input (WXI) pins are used to select the timing mode as shown in Table 6. In standard mode, the first

word written to an empty FIFO does not appear on the data output lines unless a specific read operation is

performed. A read operation, which consists of activating read enable (REN) and enabling a rising read clock

(RCLK) edge, shifts the word from internal memory to the data output lines. In FWFT mode, the first word written

to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN

does not have to be asserted to access the first word.

Various signals, both input and output signals, operate differently, depending on which timing mode is in effect.

FIRST-WORD FALL-THROUGH MODE (FWFT)

In this mode, status flags IR, PAF, HF, PAE, and OR operate in the manner outlined in Table 4. To write data

into the FIFO, WEN must be low. Data presented to the data-in lines is clocked into the FIFO on subsequent

transitions of WCLK. After the first write is performed, the output ready (OR) flag goes low. Subsequent writes

continue to fill the FIFO. PAE goes high after n + 2 words have been loaded into the FIFO, where n is the empty

offset value. The default setting for this value is stated in the footnote of Table 4. This parameter also is user

programmable. See the Programmable Flag Offset Loading section.

If data continues to be written into the FIFO, and no read operations are taking place, HF switches to low when

the 2050th word is written into the FIFO. Continuing to write data into the FIFO causes PAF to go low. Again, if

no reads are performed, PAF goes low after 4097 – m writes, where m is the full offset value. The default setting

for this value is stated in the footnote of Table 4.

When the FIFO is full, the input ready (IR) flag goes high, inhibiting further write operations. If no reads are

performed after a reset, IR goes high after D writes to the FIFO. D = 4097. The additional word in FWFT mode is

due to the capacity of the memory plus output register.

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If the FIFO is full, the first read operation causes the IR flag to go low. Subsequent read operations cause PAF

and HF to go high at the conditions described in Table 4. If further read operations occur without write

operations, PAE goes low when there are n + 1 words in the FIFO, where n is the empty offset value. If there is

no empty offset specified, PAE is low when the device is 128 away from empty. Continuing read operations

cause the FIFO to be empty. When the last word has been read from the FIFO, OR goes high, inhibiting further

read operations. REN is ignored when the FIFO is empty.

Table 4. Status Flags for FWFT Mode

NUMBER OF WORDS IN FIFO IR PAF HF PAE OR

0 L H H L H

1 to (n+1)(1) L H H L L

(n+2) to 2049 L H H H L

2050 to [4097–(m+1)](2) L H L H L

(4097–m) to 4096 L L L H L

4097 H L L H L

(1) n = Empty offset = 127

(2) m = Full offset = 127

STANDARD MODE

In this mode, status flags FF, PAF, HF, PAE, and EF operate in the manner outlined in Table 5. To write data

into the FIFO, write enable (WEN) must be low. Data presented to the data-in lines is clocked into the FIFO on

subsequent transitions of the write clock (WCLK). After the first write is performed, the empty flag (EF) goes high.

Subsequent writes continue to fill the FIFO. The programmable almost-empty flag (PAE) goes high after n + 1

words have been loaded into the FIFO, where n is the empty offset value. The default setting for this value is

stated in the footnote of Table 5. This parameter also is user programmable. See the Programmable Flag Offset

Loading section.

If data continues to be written into the FIFO, and no read operations are taking place, the half-full flag (HF)

switches to low when the 2049th word is written into the FIFO. Continuing to write data into the FIFO causes the

programmable almost-full flag (PAF) to go low. Again, if no reads are performed, PAF goes low after 4096 – m

writes. Offset m is the full offset value. This parameter also is user programmable. See the Programmable Flag

Offset Loading section. If there is no full offset specified, PAF is low when the device is 127 away from full.

When the FIFO is full, the full flag (FF) goes low, inhibiting further write operations. If no reads are performed

after a reset, FF goes low after D writes to the FIFO. D = 4096.

If the FIFO is full, the first read operation causes FF to go high. Subsequent read operations cause PAF and the

half-full flag (HF) to go high under the conditions described in Table 5. If further read operations occur, without

write operations, the programmable almost-empty flag (PAE) goes low when there are n words in the FIFO,

where n is the empty offset value. If there is no empty offset specified, PAE is low when the device is 127 away

from completely empty. Continuing read operations cause the FIFO to be empty. When the last word has been

read from the FIFO, EF goes low, inhibiting further read operations. REN is ignored when the FIFO is empty.

Table 5. Status Flags for Standard Mode

NUMBER OF WORDS IN FIFO FF PAF HF PAE EF

0 H H H L L

1 to n(1) H H H L H

(n+1) to 2048 H H H H H

2049 to [4096–(m+1)](2) H H L H H

(4096–m) to 4095 H L L H H

4096 L L L H H

(1) n = Empty offset = 127

(2) m = Full offset = 127

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PROGRAMMABLE FLAG LOADING

Full- and empty-flag offset values can be user programmable. The SN74V245 has internal registers for these

offsets. Default settings are stated in the footnotes of Table 4 and Table 5. Offset values are loaded into the

FIFO using the data input lines D0–D11. To load the offset registers, the load (LD) pin and WEN pin must be

held low. Data present on D0–D11 is transferred to the empty offset register on the first low-to-high transition of

WCLK. By continuing to hold the LD and WEN pins low, data present on D0–D11 is transferred into the full offset

to all offset registers does not have to occur at the same time. One or two offset registers can be written and

then, by bringing the LD pin high, the FIFO is returned to normal read/write operation. When the LD pin and

WEN again are set low, the next offset register in sequence is written.

The contents of the offset registers can be read on the data output lines Q0–Q11 when the LD pin is set low, and

REN is set low. Data then can be read on the next low-to-high transition of RCLK. The first transition of RCLK

presents the empty offset value to the data output lines. The next transition of RCLK presents the full offset

value. Offset register content can be read in the standard mode only. It cannot be read in the FWFT mode.

SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION

The SN74V245 can be configured during the configuration-at-reset cycle (see Table 6) with either asynchronous

or synchronous timing for PAE and PAF flags.

If asynchronous PAE/PAF configuration is selected (see Table 6), the PAE is asserted low on the low-to-high

transition of RCLK. PAE is reset to high on the low-to-high transition of WCLK. Similarly, the PAF is asserted low

on the low-to-high transition of WCLK, and PAF is reset to high on the low-to-high transition of RCLK. For

detailed timing diagrams, see Figure 11 for asynchronous PAE timing and Figure 12 for asynchronous PAF

timing.

If synchronous PAE/PAF configuration is selected, PAE is asserted and updated on the rising edge of RCLK

only, but not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only, but not RCLK. For

detailed timing diagrams, see Figure 20 for synchronous PAE timing and Figure 21 for synchronous PAF timing.

Table 6. Truth Table for Configuration at Reset

FL RXI WXI EF/OR FF/IR PAE, PAF FIFO TIMING MODE

Single register-buffered full

0 0 0 Single register-buffered empty flag Asynchronous Standard

flag

Triple register-buffered output- Double register-buffered input

0 0 1 Asynchronous FWFT

ready flag ready flag

Double register-buffered full

0 1 0 Double register-buffered empty flag Asynchronous Standard

flag

Single register-buffered full

0(1) 1 1 Single register-buffered empty flag Asynchronous Standard

flag

Single register-buffered full

1 0 0 Single register-buffered empty flag Synchronous Standard

flag

Triple register-buffered output- Double register-buffered input

1 0 1 Synchronous FWFT

ready flag ready flag

Double register-buffered full

1 1 0 Double register-buffered empty flag Synchronous Standard

flag

Single register-buffered full

1(2) 1 1 Single register-buffered empty flag Asynchronous Standard

flag

(1) In daisy-chain depth expansion, FL is held low for the first-load device. The RXI and WXI inputs are driven by the corresponding RXO

and WXO outputs of the preceding device.

(2) In daisy-chain depth expansion, FL is held high for members of the expansion other than the first-load device. The RXI and WXI inputs

are driven by the corresponding RXO and WXO outputs of the preceding device.

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The SN74V245 can be configured during the configuration-at-reset cycle (see Table 8) with single, double, or

triple register-buffered flag output signals. The various combinations available are described in Table 7 and

Table 8. In general, going from single to double or triple register-buffered flag outputs removes the possibility of

metastable flag indications on boundary states (empty or full conditions). The tradeoff is the addition of clock-

cycle delays for the respective flag to be asserted. Not all combinations of register-buffered flag outputs are

supported. Register-buffered outputs apply to the empty flag and full flag only. Partial flags are not affected.

Table 7 and Table 8 summarize the options available.

Table 7. Register-Buffered Flag Output Options, FWFT Mode

PROGRAMMING AT RESET

OUTPUT READY INPUT READY FLAG TIMING

PARTIAL FLAGS

(OR) (IR) DIAGRAMS

FL RXI WXI

Triple Double Asynchronous 0 0 1 Figure 25

Triple Double Synchronous 1 0 1 Figure 18,Figure 19

Table 8. Register-Buffered Flag Output Options, Standard Mode

EMPTY FLAG FULL FLAG PROGRAMMING AT RESET

(EF) (FF) PARTIAL FLAGS FLAG TIMING

BUFFERED BUFFERED TIMING MODE DIAGRAMS

FL RXI WXI

OUTPUT OUTPUT

Single Single Asynchronous 0 0 0 Figure 7,Figure 8

Single Single Synchronous 1 0 0 Figure 7,Figure 8

Double Double Asynchronous 0 1 0 Figure 22,Figure 24

Double Double Synchronous 1 1 0 Figure 22,Figure 24

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REN, WEN, LD

tRS

tRSR

tRSS tRSR

Configuration Setting

tRSF

FL, RXI, WXI

(see Note A)

RCLK, WCLK

(see Note B)

FF/IR

EF/OR

PAF,

WXO/HF, RXO

PAE

Q0–Q17

Standard Mode

FWFT Mode

Standard Mode

OE = 1

OE = 0

(see Note C)

NOTES: A. Single-device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC

or GND).

B. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.

C. In FWFT mode, IR goes low based on the WCLK edge after reset.

D. After reset, the outputs are low if OE = 0 and 3-state if OE = 1.

(see Note D)

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Figure 3. Reset Timing

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WCLK

tCLKH tCLKL

tCLK

tDH

tDS

Data

Invalid

tENH

tENS

D0–D17

WEN No Operation

tWFF tWFF

tSKEW1 (see Note A)

RCLK

REN

NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high during the current

clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, FF might not change

state until the next WCLK edge.

B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.

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Figure 4. Write-Cycle Timing With Single Register-Buffered FF (Standard Mode)

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tCLK

tCLKH tCLKL

RCLK

tENH

tENS

No Operation

REN

tREF tREF

tOE

tOLZ tOHZ

tSKEW1

(see Note A)

Q0–D17

WCLK

WEN

NOTES: A. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that EF goes high during the current

clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, EF might not change

state until the next RCLK edge.

B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.

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Figure 5. Read-Cycle Timing With Single Register-Buffered EF (Standard Mode)

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tDS

D0 (First Valid Write) D1 D2 D3 D4

WCLK

D0–D17

WEN

tENS

tFRL

(see Note A)

tSKEW1

RCLK

tREF

tENS

tAtA

D0 D1

tOLZ

tOE

REN

Q0–Q17

NOTES: A. When tSKEW1 is at the minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 is less than the

minimum specification, tFRL (maximum) = either (2 ×t CLK) + tSKEW1 or tCLK + tSKEW1. The latency timing applies only at the

empty boundary (EF is low).

B. The first word always is available the cycle after EF goes high.

C. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.

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Figure 6. First-Data-Word Latency with Single Register-Buffered EF (Standard Mode)

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Data Write Data

Write

Data ReadData In Output Register Next Data Read

WCLK

D0–D17

tDS

tSKEW1

(see Note A)

tWFF tWFF tWFF

tSKEW1

(see Note A) tDS

WEN

RCLK

tENS

tENH

tENS

tENH

REN

Low

tAtA

Q0–Q17

NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high during the current

clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, FF might not change

state until the next WCLK edge.

B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.

No Write

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Figure 7. Single Register-Buffered Full-Flag Timing (Standard Mode)

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Data Write 1 Data Write 2

Data ReadData In Output Register

WCLK

D0–D17

WEN

RCLK

REN

Q0–Q17

tDS tDS

tENS

tENH

tENS

tENH

tSKEW1

tFRL

(see Note A)

tFRL

(see Note A)

tSKEW1

tREF tREF tREF

Low

NOTES: A. When tSKEW1 is at the minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 is less than the minimum

specification, tFRL (maximum) = either (2 × tCLK) + tSKEW1 or tCLK + tSKEW1. The latency timing applies only at the empty

boundary (EF is low).

B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.

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Figure 8. Single Register-Buffered Empty Flag Timing (Standard Mode)

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tCLKH tCLKL

tCLK

RCLK

REN

tENS tENH

tENS

Q0–Q15 PAE Offset PAF Offset PAE Offset

Unknown

tCLKH tCLKL

tCLK

WCLK

WEN

tENS tENH

tENS

tDS tDH

D0–D15

D0–D11

PAE Offset PAF Offset

PAE Offset

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Figure 9. Write Programmable Registers (Standard and FWFT Modes)

Figure 10. Read Programmable Registers (Standard Mode)

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NOTES: A. m = PAF offset

B. D = maximum FIFO depth

In FWFT mode: D = 4097

In standard mode: D = 4096

C. PAF is asserted to low on WCLK transition and reset to high on RCLK transition.

D. Select asynchronous modes by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during reset.

WCLK

WEN

tCLKH tCLKL

tENH

tENS

tPAFA

D – (m + 1) Words in FIFO

(see Notes A and B)

D – (m + 1) Words

in FIFO

tPAFA

PAF

RCLK

tENS

REN

D – m Words

in FIFO

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Figure 11. Asynchronous Programmable Almost-Empty-Flag Timing (Standard and FWFT Modes)

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WCLK

WEN

tCLKH tCLKL

tENH

tENS

tPAEA

n Words in FIFO

(see Note B)

n + 1 Words in FIFO

(see Note C) n + 1 Words in FIFO

(see Note B)

n + 2 Words in FIFO

(see Note C)

n Words in FIFO

(see Note B)

n + 1 Words in FIFO

(see Note C)

tPAEA

PAE

RCLK

tENS

REN

NOTES: A. n = PAE offset

B. For standard mode

C. For FWFT mode

D. PAE is asserted low on RCLK transition and reset to high on WCLK transition.

E. Select the asynchronous modes by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during reset.

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Figure 12. Asynchronous Programmable Almost-Full-Flag Timing (Standard and FWFT Modes)

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tCLKH

tXO

See

Note A

tENS

WCLK

WEN

WXO

NOTE A: Write to last physical location.

WCLK

WEN

tCLKH tCLKL

tENH

tENS

tHF

D/2 Words in FIFO,

(see Notes A and B)

tHF

RCLK

tENS

REN

D – 1

2+ 1 Words in FIFO

(see Notes A and C)

D – 1

2+ 2 D/2 Words in FIFO,

(see Notes A and B)

D – 1

2+ 1

NOTES: A. D = maximum FIFO depth

In FWFT mode: D = 4097

In standard mode: D = 4096

B. For standard mode

C. For FWFT mode

D. Select single-device mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset.

D/2+1 Words in FIFO,

(see Notes A and B)

Words in FIFO

(see Notes A

and C)

Words in FIFO

(see Notes A

and C)

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Figure 13. Half-Full-Flag Timing (Standard and FWFT Modes)

Figure 14. Write-Expansion-Out Timing

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tXIS

tXI

RCLK

RXI

tXIS

tXI

WCLK

WXI

tCLKH

tXO

See

Note A

tENS

RCLK

REN

RXO

NOTE A: Read from last physical location.

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Figure 15. Read-Expansion-Out Timing

Figure 16. Write-Expansion-In Timing

Figure 17. Read-Expansion-In Timing

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1 1

WCLK

D0–D17

tENS

WEN

tDH

tDS tDS

tDS tDS tENH

W1 W2 W3 W4 W[n+2] W[n+3] W[n+4] D – 1 + 1

D – 1 + 2

D – 1 + 3

W2W[D-m-2] W[D-m-1] W[D-m] W[D-m+1] W[D-m+2] W[D] W[D+1]

tSKEW1

RCLK

REN

Q0–Q17

1 2 3

Data in Output Register W1

tREF

tSKEW2 (see Note B)

tPAES

PAE

tHF

tPAFS

PAF

tWFF

NOTES: A. t SKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go low after two RCLK cycles plus tREF . If the time between the rising

edge of WLCK and the rising edge of RCLK is less than t SKEW1, the OR deassertion might be delayed one extra RCLK cycle.

B. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go high during the current clock cycle. If the time between the rising edge

of WCLK and the rising edge of RCLK is less than tSKEW2, the PAE deassertion might be delayed one extra RCLK cycle.

C. LD is high, OE is low.

D. n = PAE offset, m = PAF offset, D = maximum FIFO depth = 4097 words

E. Select synchronous FWFT mode by setting ( FL , RXI , WXI ) = (1,0,1) during reset.

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Figure 18. Write Timing With Synchronous Programmable Flags (FWFT Mode)

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WCLK

tENH

tENS

WEN

tSKEW1

(see Note A)

1 2

tSKEW2

(see Note B)

tDH

tDS

D0–D17

RCLK

tENS tENS

REN

tOE

tOHZ tA

tAtAtA

tAtA

tREF

Q0–Q17

tPAES

tHF

tPAFS

tWFF

PAE

PAF

W1 W1 W2 W3 W[m+3]Wm+2 W[m+4] D – 1+ 1

D – 1 + 2

W2W[D-n-1] W[D-n] W[D-n+1] W[D-n+2] W[D-1] WD

NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that IR goes low after one WCLK plus tWFF. If the time between the rising

edge of RLCK and the rising edge of WCLK is less than tSKEW1, the IR assertion might be delayed an extra WCLK cycle.

B. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go high during the current clock cycle. If the time between the rising edge

of RCLK and the rising edge of WCLK is less than tSKEW2, the PAF deassertion time may be delayed an extra WCLK cycle.

C. LD is high.

D. n = PAE offset, m = PAFoffset, D = maximum FIFO depth = 4097 words

E. Select synchronous FWFT mode by setting ( FL , RXI , WXI ) = (1,0,1) during reset.

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Figure 19. Read Timing With Synchronous Programmable Flags (FWFT Mode)

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WCLK

WEN

tCLKH tCLKL

tENH

tENS

PAE

n Words in FIFO,

(see Note B)

n + 1 Words in FIFO

(see Note C) n + 1 Words in FIFO,

(see Note B)

n + 2 Words in FIFO

(see Note C)

n Words in FIFO

(see Note B),

n + 1 Words in FIFO

(see Note C)

tPAES

(see Note C)

tSKEW2

(see Note D)

tPAES

RCLK

REN

tENH

tENS

NOTES: A. n = PAE offset

B. For standard mode

C. For FWFT mode

D. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go high during the current clock cycle.

If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, the PAE deassertion might be delayed

one extra RCLK cycle.

E. PAE is asserted and updated on the rising edge of RCLK only.

F. Select synchronous modes by setting (FL , RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during reset.

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Figure 20. Synchronous Programmable Almost-Empty-Flag Timing (Standard and FWFT Modes)

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WCLK

WEN

tCLKH tCLKL

tENH

tENS

PAF

tPAFS

RCLK

REN

tENH

tENS

tPAFS

D – (m + 1) Words in FIFO D – m Words in FIFO D – (m + 1) Words

in FIFO

tSKEW2

(see Note C)

NOTES: A. m = PAF offset

B. D = maximum FIFO depth

In FWFT mode: D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235, and 4097 for the SN74V245.

In standard mode: D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235, and 4096 for the SN74V245.

C. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go high during the current clock cycle.

If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, the PAF deassertion time might

be delayed an extra WCLK cycle.

D. PAF is asserted and updated on the rising edge of WCLK only.

E. Select synchronous modes by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during reset.

SN74V245-EP

SCAS932A –DECEMBER 2012–REVISED JANUARY 2013

www.ti.com

Figure 21. Synchronous Programmable Almost-Full-Flag Timing (Standard and FWFT Modes)

Product Folder Links: SN74V245-EP

WCLK

WEN

tSKEW1

(see Note A) tDS

tSKEW1

(see Note A) tDS

1 2 1 2

WdD0–D17

tWFF tWFF tWFF

Data Write

RCLK

tENS

tENH

tENS tENH

OE Low

tAtA

Data in Output Register Data Read Next Data Read

REN

Q0–Q17

NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high after one WCLK

cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, the FF deassertion

time might be delayed an extra WCLK cycle.

B. LD is high.

C. Select double register-buffered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.

Write

SN74V245-EP

www.ti.com

SCAS932A –DECEMBER 2012–REVISED JANUARY 2013

Figure 22. Double Register-Buffered Full-Flag Timing (Standard Mode)

Product Folder Links: SN74V245-EP

1 2

WCLK

WEN

D0–D17

tCLK

tCLKH

tCLKL

tDS

tDH

Data in

Valid

tENS tENH

tWFF

No Operation

tSKEW1

(see Note A)

RCLK

REN

NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high after one WCLK

cycle plus tRFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, the FF deassertion

might be delayed an extra WCLK cycle.

B. LD is high.

C. Select double register-buffered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.

SN74V245-EP

SCAS932A –DECEMBER 2012–REVISED JANUARY 2013

www.ti.com

Figure 23. Write-Cycle Timing With Double Register-Buffered FF (Standard Mode)

Product Folder Links: SN74V245-EP

1 2

RCLK

WEN

Q0–Q17

tCLK

tCLKH

tCLKL

tENS

tENH

REN No Operation

tREF tREF

tOLZ

tOE

tOHZ

tSKEW1

(see Note A)

tENS

tENH

WCLK

Last Word

tDH

tDS

First WordD0–D17

NOTES: A. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that EF goes high after one RCLK

cycle plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, the EF deassertion

might be delayed an extra RCLK cycle.

B. LD is high.

C. Select double register-buffered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.

SN74V245-EP

www.ti.com

SCAS932A –DECEMBER 2012–REVISED JANUARY 2013

Figure 24. Read-Cycle Timing With Double Register-Buffered EF (Standard Timing)

Product Folder Links: SN74V245-EP

WCLK

WEN

tENS

tENH

tDS

tDH

D0–D17

tDS

W1 W2 W3 W4

tSKEW1

(see Note A)

1 2 3

RCLK

REN

Q0–Q17

tREF tREF

W[n+2] W[n+3]

NOTES: A. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go high during the current cycle. If

the time between the rising edge of WLCK and the rising edge of RCLK is less than tSKEW1, the OR deassertion might be delayed

one extra RCLK cycle.

B. LD is high, OE is low.

C. Select FWFT mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during reset.

Data In Output Register W1

SN74V245-EP

SCAS932A –DECEMBER 2012–REVISED JANUARY 2013

www.ti.com

Figure 25. OR-Flag Timing and First Word Fall Through When FIFO is Empty (FWFT mode)

Product Folder Links: SN74V245-EP

Half-Full Flag (HF)

Programmable (PAE)

Full Flag/Input Ready (FF/IR)

Data In (D0–D17)

Load (LD)

Write Enable (WEN)

Write Clock (WCLK) Read Clock (RCLK)

Read Enable (REN)

Output Enable (OE)

Data Out (Q0–Q17)

Empty Flag/Output Ready (EF/OR)

Programmable (PAF)

Reset (RS)

FL RXI WXI

SN74V245

SN74V245-EP

www.ti.com

SCAS932A –DECEMBER 2012–REVISED JANUARY 2013

OPERATING CONFIGURATIONS

SINGLE-DEVICE CONFIGURATION

A single SN74V245 can be used when the application requirements are for 4096 words or fewer. These FIFOs

are in a single-device configuration when the first load (FL), write expansion in (WXI) and read expansion in

(RXI) control inputs are configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during

reset (see Figure 26).

Figure 26. Block Diagram of Single 4096 × 18 Synchronous FIFO

Product Folder Links: SN74V245-EP

WXI WXI

Half-Full Flag (HF)

Programmable (PAE)

Full Flag/

Input Ready

(FF/IR)

Data In (D)

Load (LD)

Write Enable (WEN)

Write Clock (WCLK) Read Clock (RCLK)

Read Enable (REN)

Output Enable (OE)

Data Out (Q)

Empty Flag/

Output Ready

(EF/OR)

Programmable (PAF)

Reset (RS)

SN74V245

Reset (RS)

FL RXI

FF/IR EF/OR

FL RXI

FF/IR EF/OR

SN74V245

36 18

NOTE A: Do not connect any output control signals directly together.

SN74V245-EP

SCAS932A –DECEMBER 2012–REVISED JANUARY 2013

www.ti.com

WIDTH-EXPANSION CONFIGURATION

Word width may be increased simply by connecting together the control signals of multiple devices. Status flags

can be detected from any one device. The exceptions are the empty flag/output ready and full flag/input ready.

Because of variations in skew between RCLK and WCLK, it is possible for flag assertion and deassertion to vary

by one cycle between FIFOs. To avoid problems, the user must create composite flags by gating the empty

flags/output ready of every FIFO, and separately gating all full flags/input ready. Figure 27 demonstrates a 36-

word width by using two SN74V245 memories. Any word width can be attained by adding additional SN74V245

memories. These FIFOs are in a single-device configuration when the first load (FL), write expansion in (WXI),

and read expansion in (RXI) control inputs are configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0),

(1,0,1) or (1,1,0) during reset (see Figure 27).

Figure 27. Block Diagram of 4096 × 36 Synchronous FIFO Memory Used in a Width-Expansion

Configuration

Product Folder Links: SN74V245-EP

RCLK

REN

EF/OR

PAE

RCLK

REN

EF/OR

PAE

RCLK

REN

EF/OR

PAE

WXO RXO

WXI RXI

WXO RXO

WXI RXI

WXO RXO

WXI RXI

WCLK

WEN

FF/IR

PAF

WCLK

WEN

FF/IR

PAF

WCLK

WEN

FF/IR

PAF

VCC

Data In

Write Clock Read Clock

Read Enable

Output Enable

Write Enable

Data Out

Reset

Load

FF/IR

PAF

First Load (FL)

PAE

EF/OR

SN74V245

NOTES: A. The first device must be designated by grounding the first load (FL) control input.

B. All other devices must have FL in the high state.

C. The write expansion out (WXO) pin of each device must be tied to the write expansion in (WXI) pin of the next device.

D. The read expansion out (RXO) pin of each device must be tied to the read expansion in (RXI) pin of the next device.

E. All load (LD) pins are tied together.

F. The half-full flag (HF) is not available in this depth-expansion configuration.

G. EF, FF, PAE, and PAF are created with composite flags by ORing together every respective flag for monitoring. The composite

PAE and PAF flags are not precise.

H. In daisy-chain mode, the flag outputs are single-register buffered and the partial flags are in asynchronous timing mode.

SN74V245-EP

www.ti.com

SCAS932A –DECEMBER 2012–REVISED JANUARY 2013

DEPTH-EXPANSION CONFIGURATION, DAISY-CHAIN TECHNIQUE (WITH PROGRAMMABLE

FLAGS)

These devices can be adapted easily to applications requiring more than 4096 words of buffering. Figure 28

shows depth expansion using three SN74V245 memories. Maximum depth is limited only by signal loading.

Figure 28. Block Diagram of 12288 × 18 Synchronous FIFO Memory With Programmable Flags Used in

Depth-Expansion Configuration

Product Folder Links: SN74V245-EP

REN

Data In

Write Enable

Write Clock

SN74V245 SN74V245

(0,1)

GND

VCC (0,1)

GND

VCC

WXI

RXIFL WXIRXIFL

PAF Transfer Clock

WCLK

WEN

RCLK

REN

WCLK

WEN

RCLK

PAE

Read Clock

Read Enable

Input Ready Output Ready

Output Enable

Data Out

GND

nn n

SN74V245-EP

SCAS932A –DECEMBER 2012–REVISED JANUARY 2013

www.ti.com

DEPTH-EXPANSION CONFIGURATION (FWFT MODE)

In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data

inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent

to the sum of the depths associated with each single FIFO. NO TAG shows a depth expansion using two

SN74V245 memories.

Care should be taken to select FWFT mode during master reset for all FIFOs in the depth expansion

configuration. The first word written to an empty configuration passes from one FIFO to the next (ripple down)

until it finally appears at the outputs of the last FIFO in the chain. No read operation is necessary, but the RCLK

of each FIFO must be free running. Each time the data word appears at the outputs of one FIFO, that device’s

OR line goes low, enabling a write to the next FIFO in line.

For an empty expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go low

(i.e., valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the sum of

the delays for each individual FIFO:

(N – 1) × (4 × transfer clock) + 3 × TRCLK (1)

Where: N is the number of FIFOs in the expansion and TRCLK is the RCLK period. Extra cycles should be added

for the possibility that the tSKEW1 specification is not met between WCLK and transfer clock, or RCLK and transfer

clock, for the OR flag.

The ripple-down delay is noticeable only for the first word written to an empty depth-expansion configuration.

There is no delay evident for subsequent words written to the configuration.

The first free location created by reading from a full depth-expansion configuration bubbles up from the last FIFO

to the previous one until finally it moves into the first FIFO of the chain. Each time a free location is created in

one FIFO of the chain, that FIFO’s IR line goes low, enabling the preceding FIFO to write a word to fill it.

For a full expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go low after a

word has been read from the last FIFO is the sum of the delays for each individual FIFO:

(N – 1) × (3 × transfer clock) + 2TWCLK (2)

Where: N is the number of FIFOs in the expansion and TWCLK is the WCLK period. Extra cycles should be added

for the possibility that the tSKEW1 specification is not met between RCLK and transfer clock, or WCLK and transfer

clock, for the IR flag.

The transfer clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result in

data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain.

Figure 29. Block Diagram of 8192 × 18 Synchronous FIFO Memory With Programmable Flags Used in

Depth-Expansion Configuration

Product Folder Links: SN74V245-EP

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Top-Side Markings

(4)

Samples

SN74V245-15PAGEP ACTIVE TQFP PAG 64 160 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -55 to 125 V245-15EP

V62/13606-01XE ACTIVE TQFP PAG 64 160 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -55 to 125 V245-15EP

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74V245-EP :

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 2

•Catalog: SN74V245

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

MECHANICAL DATA

MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK

0,13 NOM

0,25

0,45

0,75

Seating Plane

0,05 MIN

4040282/C 11/96

Gage Plane

0,17

0,27

7,50 TYP

9,80

1,05

0,95

11,80

12,20

1,20 MAX

10,20 SQ

0,08

0,50 M

0,08

0°–7°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

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