LTC3026-1 1.5A Low Input Voltage VLDO Linear Regulator FEATURES DESCRIPTION n The LTC(R)3026-1 is a very low dropout (VLDOTM) linear regulator that can operate at input voltages down to 1.14V. The device is capable of supplying 1.5A of output current with a typical dropout voltage of only 100mV. Output current comes directly from the input supply to maximize efficiency. n n n n n n n n n n n Input Voltage Range: 1.14V to 5.5V Low Dropout Voltage: 100mV at IOUT = 1.5A Adjustable Output Range: 0.4V to 2.6V Output Current: Up to 1.5A Excellent Supply Rejection Even Near Dropout Shutdown Disconnects Load from VIN and VBST Low Operating Current: IIN = 95A at VIN = 1.5V IBIAS = 175A at VBIAS = 5V Low Shutdown Current: IIN < 1A (Typ), IBST = 0.1A (Typ) Stable with 10F or Greater Ceramic Capacitors Short-Circuit, Reverse Current Protected Overtemperature Protected Available in 10-Lead MSOP and 10-Lead (3mm x 3mm) DFN Packages The LTC3026-1 is the same as the LTC3026 but has the boost converter internally disabled. With the boost converter disabled, the SW pin of the LTC3026 is replaced with a ground pin and the BST pin is replaced with a BIAS pin that requires an external 5V supply for operation. The LTC3026-1 regulator is stable with 10F or greater ceramic output capacitors. The device has a low 0.4V reference voltage which is used to program the output voltage via two external resistors. The device also has internal current limit, overtemperature shutdown, and reverse output current protection. The LTC3026-1 is available in a small 10-lead MSOP or low profile (0.75mm) 10-lead 3mm x 3mm DFN package. APPLICATIONS n n n High Efficiency Linear Regulator Post Regulator for Switching Supplies Microprocessor Supply L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks and ThinSOT, VLDO are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 1.2V Output Voltage from 1.5V Input Supply Dropout Voltage vs Output Current 150 LTC3026-1 BIAS IN 1F 0.4V VBIAS = 5V 1F + - VOUT = 1.2V, 1.5A OUT 8.06k OFF ON SHDN ADJ GNDS GND DROPOUT (mV) VIN = 1.5V 100 1.2V 1.5V 2.0V 2.6V 50 COUT 10F 100k 4.02k 0 PG 30261 TA01a 0 1.0 0.5 1.5 IOUT (A) 30261 TA01b 30261f 1 LTC3026-1 ABSOLUTE MAXIMUM RATINGS (Note 1) VBIAS to GND................................................ -0.3V to 6V VIN to GND ................................................... -0.3V to 6V PG to GND ................................................... -0.3V to 6V SHDN to GND............................................ -0.3V to 6.3V ADJ to GND.................................. -0.3V to (VIN + 0.3V) GND to GNDS............................................ -0.3V to 0.3V Output Short-Circuit Duration .......................... Indefinite Operating Junction Temperature Range (Note 7) ............................................. -40C to 125C Storage Temperature Range .................. -65C to 125C Lead Temperature (MSE, Soldering, 10 sec) ......... 300C PIN CONFIGURATION TOP VIEW IN 1 IN 2 TOP VIEW 10 OUT IN IN GND GNDS BIAS 9 OUT 11 GND GND 3 GNDS 4 7 PG BIAS 5 6 SHDN 8 ADJ 1 2 3 4 5 11 GND 10 9 8 7 6 OUT OUT ADJ PG SHDN MSE PACKAGE 10-LEAD PLASTIC MSOP DD PACKAGE 10-LEAD (3mm = 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB TJMAX = 125C, JA = 40C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3026EDD-1#PBF LTC3026EDD-1#TRPBF LGHG 10-Lead (3mm x 3mm) Plastic DFN -40C to 125C LTC3026IDD-1#PBF LTC3026IDD-1#TRPBF LGHG 10-Lead (3mm x 3mm) Plastic DFN -40C to 125C LTC3026EMSE-1#PBF LTC3026EMSE-1#TRPBF LTGHH 10-Lead Plastic MSOP -40C to 125C LTC3026IMSE-1#PBF LTC3026IMSE-1#TRPBF LTGHH 10-Lead Plastic MSOP -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 30261f 2 LTC3026-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25C. (Note 7) VIN = 1.5V, VOUT = 1.2V, VBIAS = 5V, CIN = CBIAS = 1F, COUT = 10F (all capacitors ceramic) unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Operating Voltage (Note 2) l 5.5 V IIN Operating Current IOUT = 100A, VSHDN = VIN, 1.2V VIN 5V l 95 200 A Shutdown Current VSHDN = 0V, VIN = 3.5V l 0.6 20 A VBIAS BIAS Operating Voltage (Note 6) VSHDN = VIN VBIASUVLO BIAS Undervoltage Lockout l 4.5 5 5.5 V l 4.0 4.25 4.4 V 175 275 A 1 5 A 0.4 0.4 0.403 0.405 V V 2.6 V 250 mV 100 nA l BIAS Operating Current IOUT = 100A, VSHDN = VIN BIAS Shutdown Current VSHDN = 0V VADJ Regulation Voltage (Note 4) 1mA IOUT 1.5A, 1.14V VIN 3.5V, VBST = 5V, VOUT = 0.8V 1mA IOUT 1.5A, 1.14V VIN 3.5V, VBST = 5V, VOUT = 0.8V l OUT Programming Range IBIAS 1.14 l 0.397 0.395 0.4 Dropout Voltage (Note 5) VIN = 1.5V, VADJ = 0.38, IOUT = 1.5A l IADJ ADJ Input Current VADJ = 0.4V l -100 VSHDN = VIN l 1.5 IOUT Continuous Output Current ILIM Output Current Current Limit en Output Voltage Noise f = 10Hz to 100kHz, IL = 800mA VIHSHDN SHDN Input High Voltage 1.14V VIN 3.5V 3.5V VIN 5.5V l l VILSHDN SHDN Input Low Voltage 1.14V VIN 5.5V l IIHSHDN SHDN Input High Current SHDN = VIN IILSHDN SHDN Input Low Current SHDN = 0V 100 A 3 VOLPG PG Output Low Voltage IPG = 2mA IOHPG PG Output High Leakage Current VPG = 5.5V PG Output Threshold (Note 3) PG High to Low PG Low to High Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. This IC has overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperatures will exceed 125C when overtemperature is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 2: Minimum Operating Voltage required for regulation is: VIN VOUT(MIN) + VDROPOUT Note 3: PG threshold expressed as a percentage difference from the "VADJ Regulation Voltage" as given in the table. Note 4: Operating conditions are limited by maximum junction temperature. The regulated output voltage specification will not apply for all possible combinations of input voltage and output current. When operating at maximum input voltage, the output current range must be limited. When operating at maximum output current, the input voltage range must be limited. A 110 VRMS 1.0 1.2 V V 0.4 V -1 1 A -1 1 A l -12 -10 0.1 0.4 V 0.01 1 A -9 -7 -6 -4 % % Note 5: Dropout voltage is minimum input to output voltage differential needed to maintain regulation at a specified output current. In dropout, the output voltage will be equal to VIN - VDROPOUT. Note 6: To maintain correct regulation VOUT VBIAS - 2.4V Note 7: The LTC3026-1 is tested under pulsed load conditions such that TJ TA. The LTC3026E-1 is guaranteed to meet specifications from 0C to 125C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3026I-1 is guaranteed over the -40C to 125C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. The junction temperature (TJ, in C) is calculated from the ambient temperature (TA, in C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD * JA), where JA (in C/W) is the package thermal impedance. 30261f 3 LTC3026-1 TYPICAL PERFORMANCE CHARACTERISTICS BIAS Supply Current ADJ Voltage vs Temperature IN Supply Current 200 404 200 403 100 VBIAS = 5V 125C 85C 25C -40C 50 100 3.5 140 DROPOUT (mV) 2.0 3.5V 100 80 2.5V 125C 85C 25C -40C 20 1.2V 0 1.2 125 1.4 1.6 1.8 2.0 2.4 2.2 VIN (V) 30261 G04 VIN Ripple Rejection VBIAS = 5V VIN = 1.5V VOUT =1.2V IOUT = 800mA COUT = 10F 10 0 100 1000 10000 100000 1000000 1E+07 FREQUENCY (Hz) 30261 G07 30 20 VBIAS = 5V VOUT =1.2V IOUT = 800mA COUT = 10F 0 1.2 2.6 1.4 1.6 1.8 2.0 VIN (V) 2.2 2.4 2.6 30261 G06 Output Current Limit 5.0 RISE RISE FALL FALL RISE 900 FALL VOUT = 0V TA = 25C 4.5 4.0 3.5 IOUT (A) VSHDN THRESHOLD (mV) RIPPLE REJECTION (dB) 30 20 100kHz 30261 G05 60 40 125 1MHz Shutdown Threshold 50 100 40 10 1200 70 25 50 75 TEMPERATURE (C) 10kHz 60 100 0 50 40 0 25 50 75 TEMPERATURE (C) -25 VIN Ripple Rejection 120 1.0 -25 VBIAS = 5V VIN = 1.5V VOUT =1.2V 30261 G03 RIPPLE REJECTION (dB) 4.0 0 -50 398 60 VFB = 0.38V 180 I OUT =1.5A 160 4.5 2.5 1.5A 399 396 -50 200 3.0 1mA 400 Dropout Voltage vs Input Voltage IN Shutdown Current 0.5 401 30261 G02 5.0 1.5 402 397 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) 30261 G01 INPUT CURRENT (A) 5V VBST BIAS==5V 125C 85C 25C -40C 50 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) ADJUST VOLTAGE (mV) 150 IIN (A) IBIAS (A) 150 3.0 2.5 600 CURRENT LIMIT 2.0 125C 25C -40C 300 1 2 3 4 VIN (V) 5 THERMAL LIMIT 1.5 6 30261 G08 1.0 1.0 1.5 2.0 2.5 VIN (V) 3.0 3.5 30261 G09 30261f 4 LTC3026-1 TYPICAL PERFORMANCE CHARACTERISTICS Delay from Enable to PG BIAS to OUT Headroom Voltage 2.22 400 2.20 375 2.16 350 2.14 DELAY (s) VBIAS - VOUT (V) 2.18 2.12 2.10 325 300 2.08 2.06 VOUT = 0.8V ROUT = 8 85C 25C -40C 275 2.04 2.02 -50 -25 50 25 0 75 TEMPERATURE (C) 100 250 125 30261 G10 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) 30261 G11 Output Load Transient Response IN Supply Transient Response 1.5A IOUT 2mA 2V VIN 1.5V OUT AC 20mV/DIV VOUT AC 10mV/DIV VOUT = 1.5V COUT = 10F VIN = 1.7V VBIAS = 5V 50s/DIV 30261 G12 VOUT = 1.2V IOUT = 800mA COUT = 10F VBIAS = 5V TA = 25C 10s/DIV 30261 G13 30261f 5 LTC3026-1 PIN FUNCTIONS IN (Pins 1, 2): Input Supply Voltage. Output load current is supplied directly from IN. The IN pin should be locally bypassed to ground if the LTC3026-1 is more than a few inches away from another source of bulk capacitance. In general, the output impedance of a battery rises with frequency, so it is usually advisable to include an input bypass capacitor when supplying IN from a battery. A capacitor in the range of 0.1F to 4.7F is usually sufficient. GND (Pin 3, Exposed Pad Pin 11): Ground and Heat Sink. Connect the exposed pad to the PCB ground plane or large pad for optimum thermal performance. GNDS (Pin 4): Ground Sense Pin. Tie directly to Pin 3 GND external to the part. BIAS (Pin 5): BIAS Voltage Pin. Must be connected to an external 5V supply. A 1F low ESR ceramic capacitor is recommended for bypassing the BIAS pin. SHDN (Pin 6): Shutdown Input Pin, Active Low. This pin is used to put the LTC3026-1 into shutdown. The SHDN pin current is typically less than 10nA. The SHDN pin cannot be left floating and must be tied to a valid logic level (such as IN) if not used. PG (Pin 7): Power Good Pin. When PG is high impedance OUT is in regulation, and low impedance when OUT is in shutdown or out of regulation. ADJ (Pin 8): Output Adjust Pin. This is the input to the error amplifier. It has a typical bias current of 0.1nA flowing into the pin. The ADJ pin reference voltage is 0.4V referenced to ground. The output voltage range is 0.4V to 2.6V and is typically set by connecting ADJ to a resistor divider from OUT to GND. See Figure 3. OUT (Pins 9, 10): Regulated Output Voltage. The OUT pins supply power to the load. A minimum output capacitance of 5F is required to ensure stability. Larger output capacitors may be required for applications with large transient loads to limit peak voltage transients. See the Applications Information section for more information on output capacitance. 30261f 6 LTC3026-1 BLOCK DIAGRAM SHDN 6 5 BIAS SHDN + 0.4V REFERENCE - UVLO VOFF 7 - - PG IN 1,2 0.372V OUT 9,10 + - + + 8 ADJ OVERSHOOT DETECT GNDS 4 GND 3, 11 30261 BD 30261f 7 LTC3026-1 OPERATION The LTC3026-1 is a VLDO (very low dropout) linear regulator which operates from input voltages as low as 1.14V. The LDO uses an internal NMOS transistor as the pass device in a source-follower configuration. The BIAS pin provides the higher supply necessary for the LDO circuitry while the output current comes directly from the IN input for high efficiency regulation. 1.5A IOUT 0mA OUT AC 20mV/DIV The LTC3026-1 is the same as the LTC3026 but has the boost converter disabled. The SW pin of the LTC3026 has been replaced with a GNDS pin. Because the boost converter is disabled, an external 5V supply must be present to drive the BIAS pin (formally BST on the LTC3026). LDO Operation An undervoltage lockout comparator (UVLO) senses the BIAS pin voltage to ensure that the bias supply for the LDO is greater than 4.2V before enabling the LDO. If BIAS is below 4.2V, the UVLO shuts down the LDO, and OUT is pulled to GND through the external divider. The LDO provides a high accuracy output capable of supplying 1.5A of output current with a typical dropout voltage of only 100mV. A single ceramic capacitor as small as 10F is all that is required for output bypassing. A low reference voltage allows the LTC3026-1 output to be programmed to much lower voltages than available in common LDOs (range of 0.4V to 2.6V). The devices also include current limit and thermal overload protection, and will survive an output short-circuit indefinitely. The fast transient response of the follower output stage overcomes the traditional trade-off between dropout voltage, quiescent current and load transient response inherent in most LDO regulator architectures, see Figure 1. The LTC3026-1 also includes a soft-start feature to prevent excessive current flow at VIN during start-up. When the LDO is enabled, the soft-start circuitry gradually increases the LDO reference voltage from 0V to 0.4V over a period of approximately 200s, see Figure 2. VOUT = 1.5V COUT = 10F VIN = 1.7V VBIAS = 5V 100s/DIV 30261 F01 Figure 1. Output Load Step Response SHDN HI LO 1.5V OUT 0V 1.5V PG 0V TA = 25C ROUT = 1 VIN = 1.7V VBIAS = 5V 100s/DIV 30261 F02 Figure 2. Soft-Start with Boost Disable Adjustable Output Voltage The output voltage is set by the ratio of two external resistors as shown in Figure 3. The device servos the output to maintain the ADJ pin voltage at 0.4V (referenced to ground). Thus, the current in R1 is equal to 0.4V/R1. For good transient response, stability and accuracy the current in R1 should be at least 80A, thus, the value of R1 should be no greater than 5k. The current in R2 is the current in R1 plus the ADJ pin bias current. Since the ADJ pin bias current is typically <10nA it can be ignored in the output voltage calculation. The output voltage can be calculated using the formula in Figure 3. Note that in shutdown the output is turned off and the divider current will be zero once COUT is discharged. 30261f 8 LTC3026-1 OPERATION R2 R2 VOUT = 0.4V 1+ R1 COUT ADJ R1 GND 30261 F03 Figure 3. Programming the LTC3026-1 The LTC3026-1 operates at a relatively high gain of 270V/A referred to the ADJ input. Thus, a load current change of 1mA to 1.5A produces a 400V drop at the ADJ input. To calculate the change in the output, simply multiply by the gain of the feedback network (i.e. 1 + R2/R1). For example, to program the output for 1.2V choose R2/R1 = 2. In this example an output current change of 1mA to 1.5A produces -400V * (1 + 2) = 1.2mV drop at the output. Power Good Operation The LTC3026-1 includes an open-drain power good (PG) output pin with hysteresis. If the chip is in shutdown or under UVLO conditions (VBIAS < 4.25V typ.), PG is low impedance to ground. PG becomes high impedance when VOUT rises to 93% of its regulation voltage. PG stays high impedance until VOUT falls back down to 91% of its regulation value. A pull-up resistor can be inserted between PG and a positive logic supply (such as IN, OUT, BIAS, etc.) to signal a valid power good condition. VIN should be the minimum operating voltage (1.14V) or greater for PG to function correctly. LTC3026-1 will increase the effective output capacitor value. High ESR tantalum and electrolytic capacitors may be used, but a low ESR ceramic capacitor must be in parallel at the output. There is no minimum ESR or maximum capacitor size requirements. Extra consideration must be given to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but exhibit strong voltage and temperature coefficients as shown in Figures 4 and 5. When used with a 2V regulator, a 10F Y5V capacitor can exhibit an effective value as low as 1F to 2F over the operating temperature range. The X5R and X7R dielectrics result in 20 X5R -20 -40 -60 Y5V -80 -100 0 1 2 3 4 DC BIAS VOLTAGE (V) 5 6 30261 F04 Figure 4. Ceramic Capacitor DC Bias Characteristics 20 X5R Output Capacitance and Transient Response 0 CHANGE IN VALUE (%) The LTC3026-1 is designed to be stable with a wide range of ceramic output capacitors. The ESR of the output capacitor affects stability, most notably with small capacitors. An output capacitor of 10F or greater with an ESR of 0.05 or less is recommended to ensure stability. The LTC3026-1 is a micropower device and output transient response will be a function of output capacitance. Larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. Note that bypass capacitors used to decouple individual components powered by the BOTH CAPACITORS ARE 10F, 6.3V, 0805 CASE SIZE 0 CHANGE IN VALUE (%) VOUT LTC3026-1 -20 Y5V -40 -60 -80 BOTH CAPACITORS ARE 10F, 6.3V, 0805 CASE SIZE -100 -50 -25 50 25 0 TEMPERATURE (C) 75 30261 F05 Figure 5. Ceramic Capacitor Temperature Characteristics 30261f 9 LTC3026-1 OPERATION more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. A minimum capacitance of 5F must be maintained at all times on the LTC3026-1 LDO output. Thermal Considerations The power handling capability of the device will be limited by the maximum rated junction temperature (125C). The majority of the power dissipated in the device will be the output current multiplied by the input/output voltage differential: (IOUT)(VIN - VOUT). Note that the BIAS current is less than 200A even under heavy loads, so its power consumption can be ignored for thermal calculations. The LTC3026-1 has internal thermal limiting designed to protect the device during momentary overload conditions. For continuous normal conditions, the maximum junction temperature rating of 125C must not be exceeded. It is important to give careful consideration to all sources of thermal resistance from junction to ambient. Additional heat sources mounted nearby must also be considered. For surface mount devices, heat sinking is accomplished by using the heat-spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through holes can also be used to spread the heat generated by power devices. A junction-to-ambient thermal coefficient of 40C/W is achieved by connecting the exposed pad of the MSOP or DFN package directly to a ground plane of about 2500mm2. Calculating Junction Temperature Example: Given an output voltage of 1.2V, an input voltage of 1.8V 4%, an output current range of 0mA to 1A and a maximum ambient temperature of 50C, what will the maximum junction temperature be? The power dissipated by the device will be approximately: IOUT(MAX)(VIN(MAX) - VOUT) where: IOUT(MAX) = 1A VIN(MAX) = 1.87V so: P = 1A(1.87V - 1.2V) = 0.67W Even under worst-case conditions LTC3026-1's BIAS pin power dissipation is only about 1mW, thus can be ignored. The junction to ambient thermal resistance will be on the order of 40C/W. The junction temperature rise above ambient will be approximately equal to: 0.67W(40C/W) = 26.8C The maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: TA = 26.8C + 50C = 76.8C 30261f 10 LTC3026-1 OPERATION Short-Circuit/Thermal Protection The LTC3026-1 has built-in output short-circuit current limiting as well as overtemperature protection. During short-circuit conditions, internal circuitry automatically limits the output current to approximately 3A. At higher temperatures, or in cases where internal power dissipation cause excessive self heating on-chip, the thermal shutdown circuitry will shut down the boost converter and LDO when the junction temperature exceeds approximately 150C. It will reenable the converter and LDO once the junction temperature drops back to approximately 140C. The LTC3026-1 will cycle in and out of thermal shutdown without latchup or damage until the overstress condition is removed. Long term overstress (TJ > 125C) should be avoided as it can degrade the performance or shorten the life of the part. Reverse Input Current Protection The LTC3026-1 features reverse input current protection to limit current draw from any supplementary power source at the output. Figure 6 shows the reverse output current limit for constant input and output voltages cases. Note: Positive input current represents current flowing into the VIN pin of LTC3026-1. 30 IN CURRENT LIMIT ABOVE 1.45V IIN CURRENT (A) 20 With VOUT held at or below the output regulation voltage and VIN varied, IN current flow will follow Figure 6's curves. IIN reverse current ramps up to about 16A as the VIN approaches VOUT. Reverse input current will spike up as VIN approaches within about 30mV of VOUT as the reverse current protection circuitry is disabled and normal operation resumes. As VIN transitions above VOUT the reverse current transitions into short-circuit current as long as VOUT is held below the regulation voltage. Layout Considerations Connection from BIAS and OUT pins to their respective ceramic bypass capacitor should be kept as short as possible. The ground side of the bypass capacitors should be connected directly to the ground plane for best results or through short traces back to the GND pin of the part. Long traces will increase the effective series ESR and inductance of the capacitor which can degrade performance. Because the ADJ pin is relatively high impedance (depending on the resistor divider used), stray capacitance at this pin should be minimized (<10pF) to prevent phase shift in the error amplifier loop. Additionally special attention should be given to any stray capacitances that can couple external signals onto the ADJ pin producing undesirable output ripple. For optimum performance connect the ADJ pin to R1 and R2 with a short PCB trace and minimize all other stray capacitance to the ADJ pin. 10 CIN 0 -10 -20 -30 1 IN OUT 10 2 IN OUT 9 3 GND ADJ 8 4 GNDS PG 7 5 BIAS 0 0.3 0.9 0.6 1.2 INPUT VOLTAGE (V) 1.5 COUT R2 R1 SHDN 6 1.8 30261 F06 Figure 6. Input Current vs Input Voltage CBIAS 30261 F07 VIA CONNECTION TO GND PLANE Figure 7. Suggested Layout 30261f 11 LTC3026-1 TYPICAL APPLICATIONS Using 1 Boost with Multiple Regulators VIN = 2.5V TO ADDITIONAL REGULATORS 10H BST SW BIAS 4.7F LTC3026 IN VOUT1 1.8V, 1.5A OUT 1F LTC3026-1 IN VOUT2 1.5V, 1.5A OUT 11k 14k SHDN COUT1 10F ADJ 100k 4.7F GND 4.02k PG LTC3026 WITH BOOST ENABLED FANOUT: 3-LTC3026-1 FOR VIN <1.4V 5-LTC3026-1 FOR VIN >1.4V SHDN 1F PG1 100k GNDS GND COUT2 10F ADJ PG 4.02k PG2 30261 TA02 30261f 12 LTC3026-1 TYPICAL APPLICATIONS 2.5V Output from 3.3V Supply with External 5V Bias VBIAS = 5V BIAS 1F LTC3026-1 VIN = 3.3V IN VOUT 2.5V, 1.5A OUT 21k SHDN 1F 100k GNDS GND COUT 10F ADJ PG 4.02k PG 3026 TA03 30261f 13 LTC3026-1 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm x 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 0.05 3.55 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 0.10 (4 SIDES) R = 0.125 TYP 6 0.40 0.10 10 1.65 0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER PIN 1 TOP MARK (SEE NOTE 6) (DD) DFN REV C 0310 5 0.200 REF 1 0.75 0.05 0.00 - 0.05 0.25 0.05 0.50 BSC 2.38 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 30261f 14 LTC3026-1 PACKAGE DESCRIPTION MSE Package 10-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1664 Rev H) BOTTOM VIEW OF EXPOSED PAD OPTION 1.88 t0.102 (.074 t.004) 5.23 (.206) MIN 0.889 t0.127 (.035 t.005) 1.68 t0.102 (.066 t.004) 1 0.05 REF 10 0.305 t 0.038 (.0120 t.0015) TYP RECOMMENDED SOLDER PAD LAYOUT 3.00 t0.102 (.118 t.004) (NOTE 3) DETAIL "B" CORNER TAIL IS PART OF DETAIL "B" THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 10 9 8 7 6 DETAIL "A" 0s - 6s TYP 1 2 3 4 5 GAUGE PLANE 0.53 t0.152 (.021 t.006) DETAIL "A" 0.18 (.007) 0.497 t0.076 (.0196 t.003) REF 3.00 t0.102 (.118 t.004) (NOTE 4) 4.90 t0.152 (.193 t.006) 0.254 (.010) 0.29 REF 1.68 (.066) 3.20 - 3.45 (.126 - .136) 0.50 (.0197) BSC 1.88 (.074) SEATING PLANE 1.10 (.043) MAX 0.17 - 0.27 (.007 - .011) TYP 0.50 (.0197) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.86 (.034) REF 0.1016 t0.0508 (.004 t.002) MSOP (MSE) 0911 REV H 30261f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC3026-1 TYPICAL APPLICATION Efficient, Low Noise 1.5V Output from 1.8V DC/DC Buck Converter 4.5V ) VIN ) 5.5V 33pF 200pF 30k 1 ITH 0.1F SW 10 RSENSE 0.04 LTC1773 2 3 4 CIN 47F 10V 5 RUN/SS SENSE- SYNC/FCB VIN VFB TG GND BG 9 8 L1 2.5H 7 BIAS LTC3026-1 IN OUT SHDN ADJ VOUT 1.5V 1.5A 11k 6 1F Si9942DY 80.6k 1% 1F VBUCK 1.8V 2A CBUCK 47F 10V 100k 1% 100k GNDS GND COUT 10F 4.02k PG PG 30261 TA04 CIN, CBUCK: TAIYO YUDEN LMK550BJ476MM L1: CDRH5D28 RSENSE: IRC LR1206-01-R040-F RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1761 100mA, Low Noise LDO in ThinSOTTM 300mV Dropout Voltage, Low Noise: 20VRMS, VIN = 1.8V to 20V, ThinSOT Package LT1762 150mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20VRMS, VIN = 1.8V to 20V, MS8 Package LT1763 500mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20VRMS, VIN = 1.8V to 20V, SO-8 Package LT1764A 3A, Fast Transient Response, Low Noise LDO 340mV Dropout Voltage, Low Noise: 40VRMS, VIN = 2.7V to 20V, TO-220 and DD Packages LT1844 150mA, Very Low Dropout LDO 80mV Dropout Voltage, Low Noise <30VRMS, VIN = 1.6V to 6.5V, Stable with 1F Output Capacitors, ThinSOT Package LT1962 300mA, Low Noise LDO 270mV Dropout Voltage, Low Noise 20VRMS, VIN = 1.8V to 20V, MS8 Package LT1963A 1.5A Low Noise, Fast Transient Response LDO 340mV Dropout Voltage, Low Noise: 40VRMS, VIN = 2.5V to 20V, TO-220, DD, SOT-223 and SO-8 Packages LT1964 200mA, Low Noise, Negative LDO 340mV Dropout Voltage, Low Noise 30VRMS, VIN = -1.8V to -20V, ThinSOT Package LT1965 1.1A, Low Noise, Low Dropout Linear Regulator 290mV Dropout Voltage, Low Noise 40VRMS, VIN = 1.8V to 20V, TO-220, DDPak, MSOP and 3mm x 3mm DFN Packages LTC3025 300mA Micropower VLDO Linear Regulator 45mV Dropout Voltage, Low Noise 80VRMS, VIN = 0.9V to 5.5V, Low IQ: 54A, 2mm x 2mm 6-Lead DFN Package LT3080/LT3080-1 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2 Supply), Low Noise 40VRMS, VIN = 1.2V to 36V, VOUT = 0V to 35.7V, Directly Parallelable, TO-220, SOT-223, MSOP-8 and 3mm x 3mm DFN Packages LT3150 Fast Transient Response, VLDO Regulator Controller 0.035mV Dropout Voltage via External FET, VIN = 1.3V to 10V LTC3026 1.5A Low Input Voltage VLDO Linear Regulator 100mV Dropout Voltage at 1.5A, Low Noise 110VRMS, VIN = 1.14 to 5.5V, VOUT = 0.4V to 2.6V, Low IQ: 95A MSOP-10, 3mm x 3mm DFN Packages 30261f 16 Linear Technology Corporation LT 0812 * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2012