Super Sequencer with Margining Control
Data Sheet ADM1069
Rev. E Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Complete supervisory and sequencing solution for up to
8 supplies
8 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
4 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP3 (VPx)
4 dual-function inputs, VX1 to VX4 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
8 programmable driver outputs, PDO1 to PDO8 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open-collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Complete voltage margining solution for 4 voltage rails
4 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages
Reference input (REFIN) has 2 input options
Driven directly from 2.048 V (±0.25%) REFOUT pin
More accurate external reference for improved ADC
performance
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 32-lead, 7 mm × 7 mm LQFP and 40-lead,
6 mm × 6 mm LFCSP packages
FUNCTIONAL BLOCK DIAGRAM
04735-001
PDO7
PDO8
PDOGND
VDDCAP
VDD
ARBITRATOR
DAC1
V
OUT
DAC
DAC2
V
OUT
DAC
DAC3
V
OUT
DAC
DAC4
V
OUT
DAC
GND
VCCP
VX1
VX2
VP1
VP2
VP3
VH
A
GND
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LO GIC SIGNALS )
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
VX3
VX4
SDA SCL A1 A0
SMBus
INTERFACE
REFIN REFOUT REFGND
VREF
12-BIT
SAR ADC
MUX
EEPROM
CLOSED-LOOP
MARG INING SYSTEM
ADM1069
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(HV CA PABLE OF
DRIVING GATES
OF N-FET)
Figure 1.
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1069 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems. In addition
to these functions, the ADM1069 integrates a 12-bit analog-to-
digital converter (ADC) and four 8-bit voltage output digital-to-
analog converters (DACs). These circuits can implement a closed-
loop margining system that enables supply adjustment by altering
either the feedback node or reference of a dc-to-dc converter
using the DAC outputs.
For more information about the ADM1069 register map, refer
to the AN-721 Application Note.
ADM1069 Data Sheet
Rev. E | Page 2 of 34
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Detailed Block Diagram .................................................................. 4
Specifications ..................................................................................... 5
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Powering the ADM1069 ................................................................ 14
Slew Rate Consideration ............................................................ 14
Inputs ................................................................................................ 15
Supply Supervision ..................................................................... 15
Programming the Supply Fault Detectors ............................... 15
Input Comparator Hysteresis .................................................... 15
Input Glitch Filtering ................................................................. 16
Supply Supervision with VXx Inputs ....................................... 16
VXx Pins as Digital Inputs ........................................................ 17
Outputs ............................................................................................ 18
Supply Sequencing Through Configurable Output Drivers . 18
Default Output Configuration .................................................. 18
Sequencing Engine ......................................................................... 20
Overview ...................................................................................... 20
Warnings ...................................................................................... 20
SMBus Jump (Unconditional Jump) ........................................ 20
Sequencing Engine Application Example ............................... 21
Fault and Status Reporting ........................................................ 22
Voltage Readback............................................................................ 23
Supply Supervision with the ADC ........................................... 23
Supply Margining ........................................................................... 24
Overview ..................................................................................... 24
Open-Loop Supply Margining ................................................. 24
Closed-Loop Supply Margining ............................................... 24
Writing to the DACs .................................................................. 25
Choosing the Size of the Attenuation Resistor ....................... 25
DAC Limiting and Other Safety Features ............................... 25
Applications Diagram .................................................................... 26
Communicating with the ADM1069 ........................................... 27
Configuration Download at Power-Up ................................... 27
Updating the Configuration ..................................................... 27
Updating the Sequencing Engine ............................................. 28
Internal Registers ........................................................................ 28
EEPROM ..................................................................................... 28
Serial Bus Interface..................................................................... 28
SMBus Protocols for RAM and EEPROM .............................. 31
Write Operations ........................................................................ 31
Read Operations ......................................................................... 33
Outline Dimensions ....................................................................... 34
Ordering Guide .......................................................................... 34
Data Sheet ADM1069
Rev. E | Page 3 of 34
REVISION HISTORY
6/2016—Rev. D to Rev. E
Changes to Figure 4........................................................................... 9
Updated Outline Dimensions ........................................................ 33
Changes to Ordering Guide ........................................................... 33
1/2015—Rev. C to Rev. D
Changed Round-Robin Circuit to
ADC Round-Robin ....................................................... Throughout
Moved Revision History ................................................................... 3
Changes to Figure 4 and Table 4 ..................................................... 9
Added Slew Rate Consideration Section ...................................... 14
Added VP1 Glitch Filtering Section ............................................. 16
Added SCL Held Low Section and False Start Detection Section .. 28
Updated Outline Dimensions ........................................................ 33
6/2011—Rev. B to Rev. C
Change to Serial Bus Timing Parameter in Table 1 ...................... 4
Changes to Ordering Guide ........................................................... 31
8/2008—Rev. A to Rev. B
Added 40-Lead LFCSP ...................................................... Universal
Changes to Table 1 ............................................................................ 4
Moved Absolute Maximum Ratings Section ................................. 7
Changes to Table 3 ............................................................................ 7
Added Figure 4, Renumbered Sequentially ................................... 8
Changes to Table 4 ............................................................................ 8
Changes to Powering the ADM1069 Section .............................. 13
Changes to Default Output Configuration Section .................... 16
Changes to Sequence Detector Section ........................................ 18
Changes to Figure 32 ...................................................................... 21
Changes to Configuration Download at Power-Up Section ..... 24
Changes to Table 11 ........................................................................ 25
Changes to Figure 45 and Error Correction Section .................. 30
Updated Outline Dimensions........................................................ 31
Changes to Ordering Guide ........................................................... 31
10/2006—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Changes to Figure 2 .......................................................................... 3
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 7
Changes to Table 3 ............................................................................ 8
Inserted Table 4; Renumbered Sequentially .................................. 8
Changes to Programming the Supply Fault Detectors Section ...... 13
Changes to Outputs Section .......................................................... 16
Changes to Fault Reporting Section ............................................. 21
Changes to Table 9 .......................................................................... 22
Inserted Table 11 ............................................................................. 28
Changes to Ordering Guide ........................................................... 33
3/2005—Revision 0: Initial Version
ADM1069 Data Sheet
Rev. E | Page 4 of 34
Supply margining can be performed with a minimum of external
components. The margining loop can be used for in-circuit
testing of a board during production (for example, to verify
board functionality at −5% of nominal supplies), or it can be
used dynamically to accurately control the output voltage of
a dc-to-dc converter.
The device also provides up to eight programmable inputs for
monitoring undervoltage faults, overvoltage faults, or out-of-
window faults on up to eight supplies. In addition, there are eight
programmable outputs that can be used as logic enables. Six of
these programmable outputs can also provide up to a 12 V output
for driving the gate of an N-FET that can be placed in the path
of a supply.
The logical core of the device is a sequencing engine (SE). This
state machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs, based
on the condition of the inputs.
The ADM1069 is controlled via configuration data that can be
programmed into an EEPROM. The entire configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
DETAILED BLOCK DIAGRAM
04735-002
GPI SIGNAL
CONDITIONING
SFD
GPI SIGNAL
CONDITIONING
SFD
SFD
SFD
SELECTABLE
ATTENUATOR
SELECTABLE
ATTENUATOR
DEVICE
CONTROLLER
OSC
EEPROM
SDA SCL A1 A0
SMBus
INTERFACE
REFOUTREFIN REFGND
VREF
12-BIT
SAR ADC
ADM1069
CONFIGURABLE
OUT P UT DRI V E R
(HV) PDO1
PDO2
PDOGND
PDO3
VCCPGND
PDO4
PDO5
CONFIGURABLE
OUT P UT DRI V E R
(HV) PDO6
CONFIGURABLE
OUT P UT DRI V E R
(LV) PDO7
CONFIGURABLE
OUT P UT DRI V E R
(LV) PDO8
SEQUENCING
ENGINE
VX2
VX3
VP2
VP3
VH
VP1
VX1
AGND
VX4
VDD
ARBITRATOR
REG 5.25V
CHARGE P UM P
DAC1
VOUT
DAC
DAC4
VOUT
DAC
DAC2 DAC3
VDDCAP
Figure 2.
Data Sheet ADM1069
Rev. E | Page 5 of 34
SPECIFICATIONS
VH = 3.0 V to 14.4 V,1 VPx = 3.0 V to 6.0 V,1 TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY ARBITRATION
VH, VPx 3.0 V Minimum supply required on one of VH, VPx
VPx 6.0 V Maximum VDDCAP = 5.1 V, typical
VH 14.4 V VDDCAP = 4.75 V
VDDCAP 2.7 4.75 5.4 V Regulated LDO output
CVDDCAP 10 µF Minimum recommended decoupling
capacitance
POWER SUPPLY
Supply Current, IVH, IVPx 4.2 6 mA VDDCAP = 4.75 V, PDO1 to PDO8 off, DACs off,
ADC off
Additional Currents
All PDO FET Drivers On 1 mA VDDCAP = 4.75 V, PDO1 to PDO6 loaded with
1 µA each, PDO7 to PDO8 off
Current Available from VDDCAP 2 mA Maximum additional load that can be drawn
from all PDO pull-ups to VDDCAP
DAC Supply Currents 2.2 mA Four DACs on with 100 µA maximum load on each
ADC Supply Current 1 mA Running ADC round-robin loop
EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V
SUPPLY FAULT DETECTORS
VH Pin
Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Midrange and high range
Detection Ranges
High Range
6
14.4
V
Midrange 2.5 6 V
VPx Pins
Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Low range and midrange
Detection Ranges
Midrange 2.5 6 V
Low Range 1.25 3 V
Ultralow Range 0.573 1.375 V No input attenuation error
VXx Pins
Input Impedance 1 MΩ
Detection Ranges
Ultralow Range 0.573 1.375 V No input attenuation error
Absolute Accuracy ±1 % VREF error + DAC nonlinearity + comparator
offset error
Threshold Resolution 8 Bits
Digital Glitch Filter 0 µs Minimum programmable filter length
100 µs Maximum programmable filter length
ADM1069 Data Sheet
Rev. E | Page 6 of 34
Parameter Min Typ Max Unit Test Conditions/Comments
ANALOG-TO-DIGITAL CONVERTER
Signal Range 0 VREFIN V The ADC can convert signals presented to the
VH, VPx, and VXx pins; VPx and VH input signals
are attenuated depending on the selected
range; a signal at the pin corresponding to the
selected range is from 0.573 V to 1.375 V at the
ADC input
Input Reference Voltage on REFIN Pin, VREFIN 2.048 V
Resolution 12 Bits
INL ±2.5 LSB Endpoint corrected, VREFIN = 2.048 V
Gain Error ±0.05 % VREFIN = 2.048 V
Conversion Time 0.44 ms One conversion on one channel
84 ms All eight channels selected, averaging enabled
Offset Error ±2 LSB VREFIN = 2.048 V
Input Noise 0.25 LSBrms Direct input (no attenuator)
BUFFERED VOLTAGE OUTPUT DACs
Resolution 8 Bits
Code 0x80 Output Voltage Four DACs are individually selectable for
centering on one of four output voltage ranges
Range 1 0.592 0.6 0.603 V
Range 2 0.796 0.8 0.803 V
Range 3 0.996 1 1.003 V
Range 4 1.246 1.25 1.253 V
Output Voltage Range 601.25 mV Same range, independent of center point
LSB Step Size 2.36 mV
INL ±0.75 LSB Endpoint corrected
DNL ±0.4 LSB
Gain Error 1 %
Maximum Load Current (Source) 100 µA
Maximum Load Current (Sink) 100 µA
Maximum Load Capacitance 50 pF
Settling Time into 50 pF Load 2 µs
Load Regulation 2.5 mV Per mA
PSRR 60 dB DC
40
dB
100 mV step in 20 ns with 50 pF load
REFERENCE OUTPUT
Reference Output Voltage 2.043 2.048 2.053 V No load
Load Regulation −0.25 mV Sourcing current, IDACxMAX = −100 µA
+0.25 mV Sinking current, IDACxMAX = +100 µA
Minimum Load Capacitance 1 µF Capacitor required for decoupling, stability
PSRR 60 dB DC
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode
(PDO1 to PDO6)
Output Impedance 500 kΩ
VOH 11 12.5 14 V IOH = 0 µA
10.5 12 13.5 V IOH = 1 µA
IOU TAVG 20 µA 2 V < VOH < 7 V
Data Sheet ADM1069
Rev. E | Page 7 of 34
Parameter Min Typ Max Unit Test Conditions/Comments
Standard (Digital Output) Mode (PDO1 to PDO8)
VOH 2.4 V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
4.5 V VPU to VPx = 6.0 V, IOH = 0 mA
VPU − 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA
V
OL
0
0.50
V
I
OL
= 20 mA
IOL2 20 mA Maximum sink current per PDOx pin
ISINK2 60 mA Maximum total sink for all PDOx pins
RPULL-UP 16 20 29 kΩ Internal pull-up
ISOURCE (VPx)2 2 mA Current load on any VPx pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
VPx pin
Three-State Output Leakage Current 10 µA VPDO = 14.4 V
Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V
Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V
Input High Current, IIH −1 µA VIN = 5.5 V
Input Low Current, I
IL
1
µA
V
IN
= 0 V
Input Capacitance 5 pF
Programmable Pull-Down Current, IPULL-DOWN 20 µA VDDCAP = 4.75 V, TA = 25°C, if known logic state
is required
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Output Low Voltage, VOL2 0.4 V IOUT = −3.0 mA
SERIAL BUS TIMING3
Clock Frequency, fSCLK 400 kHz
Bus Free Time, tBUF 1.3 µs
Start Setup Time, tSU;STA 0.6 µs
Stop Setup Time, tSU;STO 0.6 µs
Start Hold Time, tHD;STA 0.6 µs
SCL Low Time, tLOW 1.3 µs
SCL High Time, tHIGH 0.6 µs
SCL, SDA Rise Time, tR 300 ns
SCL, SDA Fall Time, t
F
300
ns
Data Setup Time, tS U;DAT 100 ns
Data Hold Time, tHD ;DAT 5 ns
Input Low Current, IIL 1 µA VIN = 0 V
SEQUENCING ENGINE TIMING
State Change Time 10 µs
1 At least one of the VH, VPx pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Timing specifications are guaranteed by design and supported by characterization data.
ADM1069 Data Sheet
Rev. E | Page 8 of 34
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Voltage on VH Pin 16 V
Voltage on VPx Pins 7 V
Voltage on VXx Pins −0.3 V to +6.5 V
Voltage on A0, A1 Pins −0.3 V to +7 V
Voltage on REFIN, REFOUT Pins 5 V
Voltage on VDDCAP, VCCP Pins 6.5 V
Voltage on DACx Pins 6.5 V
Voltage on PDOx Pins
16 V
Voltage on SDA, SCL Pins 7 V
Voltage on GND, AGND, PDOGND,
REFGND Pins
−0.3 V to +0.3 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
Soldering Vapor Phase, 60 sec 215°C
ESD Rating, All Pins 2000 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
32-Lead LQFP 54 °C/W
40-Lead LFCSP
25
°C/W
ESD CAUTION
Data Sheet ADM1069
Rev. E | Page 9 of 34
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04735-003
124
25
32
8
9
17
16
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
GND
VDDCAP
SDA
SCL
A1
A0
VCCP
PDOGND
AGND
REFGND
REFIN
REFOUT
DAC1
DAC2
DAC3
DAC4
PIN 1
INDICATOR
ADM1069
TOP VIEW
(Not to Scale)
Figure 3. 32-Lead LQFP Pin Configuration
04735-004
AGND
REFGND
REFIN
REFOUT
NC
NC
DAC1
DAC2
DAC3
DAC4
NC
VX1
VX2
VX3
VX4
NC
VP1
VP2
VP3
VH
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
NC
NC
PIN 1
INDICATOR
NOTES
1. NC = NO CO NNE C T. DO NOT CONNECT TO THIS PIN.
2. THE LF CS P HAS AN E X P OSED P AD ON T HE BOTTO M .
THIS PAD IS A NO CONNECT (NC). IF POSSIBLE, THIS
PAD SHO ULD BE S OLDE RE D TO THE BO ARD FO R
IM PROVE D M E CHANICAL S TABI LI TY.
A0
A1
SCL
SDA
NC
NC
VDDCAP
GND
VCCP
PDOGND
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
ADM1069
TOP VIEW
(No t t o Scal e)
Figure 4. 40-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
32-Lead
LQFP
40-Lead
LFCSP
1, 6, 15, 16,
21, 22, 37,
38
NC No Connect. Do not connect to this pin.
1 to 4 2 to 5 VX1 to VX4
(VXx)
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V
to 1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
5 to 7 7 to 9 VP1 to VP3
(VPx)
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a supply
fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from 1.25 V to 3.00 V, and from 0.573 V
to 1.375 V.
8
10
VH
High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply
fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.
9 11 AGND1 Ground Return for Input Attenuators.
10 12 REFGND1 Ground Return for On-Chip Reference Circuits.
11 13 REFIN Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage. The
on-board reference can be used by connecting the REFOUT pin to the REFIN pin. This is the normal
configuration.
12 14 REFOUT 2.048 V Reference Output. A reservoir capacitor must be connected between this pin and GND.
A 10 µF capacitor is recommended for this purpose.
13 to 16 17 to 20 DAC1 to
DAC4
Voltage Output DACs. These pins default to high impedance at power-up.
17 to 24 23 to 30 PDO8 to
PDO1
Programmable Output Drivers.
25 31 PDOGND1 Ground Return for Output Drivers.
26 32 VCCP Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this
pin and GND. A 10 µF capacitor is recommended for this purpose.
27
33
A0
Logic Input. This pin sets the seventh bit of the SMBus interface address.
28 34 A1 Logic Input. This pin sets the sixth bit of the SMBus interface address.
29 35 SCL SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up.
30 36 SDA SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.
ADM1069 Data Sheet
Rev. E | Page 10 of 34
Pin No.
Mnemonic Description
32-Lead
LQFP
40-Lead
LFCSP
31 39 VDDCAP Device Supply Voltage. Linearly regulated from the highest of the VPx, VH pins to a typical of 4.75 V.
Note that a capacitor must be connected between this pin and GND. A 10 µF capacitor is recom-
mended for this purpose.
32 40 GND1 Supply Ground.
N/A2 EPAD The LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this pad
must be soldered to the board for improved mechanical stability.
1 In a typical application, all ground pins are connected together.
2 N/A means not applicable.
Data Sheet ADM1069
Rev. E | Page 11 of 34
TYPICAL PERFORMANCE CHARACTERISTICS
6
0
1
2
3
4
5
0 654321
04735-050
VVP1 (V)
VVDDCAP (V)
Figure 5. VVDDCAP vs. VVP1
6
0
1
2
3
4
5
0 161412108642
04735-051
VVH (V)
VVDDCAP (V)
Figure 6. VVDDCAP vs. VVH
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
00 1 23456
04735-052
VVP1 (V)
IVP1 (mA)
Figure 7. IVP1 vs. VVP1 (VP1 as Supply)
180
160
140
120
100
80
60
40
20
00123456
04735-053
VVP1 (V)
IVP1 (µA)
Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
00 161412108642
04735-054
VVH (V)
IVH (mA)
Figure 9. IVH vs. VVH (VH as Supply)
350
300
250
200
150
100
50
00 654321
04735-055
VVH (V)
IVH ( µ A)
Figure 10. IVH vs. VVH (VH Not as Supply)
ADM1069 Data Sheet
Rev. E | Page 12 of 34
14
12
10
8
6
4
2
0015.0
12.5
10.0
7.5
5.0
2.5
04735-056
ILOAD (µA)
CHARGE- P UM P E D VPDO1 (V)
Figure 11. Charge-Pumped VPDO1 (FET Drive Mode) vs. ILOAD
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
00 6
54321
04735-057
ILOAD (mA)
VPDO1 (V)
VP1 = 5V
VP1 = 3V
Figure 12. VPDO1 (Strong Pull-Up to VPx) vs. ILOAD
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
006050
40302010
04735-058
ILOAD (µA)
VPDO1 (V)
VP1 = 5V
VP1 = 3V
Figure 13. VPDO1 (Weak Pull-Up to VPx) vs. ILOAD
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
4000
1000 2000 3000
0
04735-066
CODE
DNL (LSB)
Figure 14. DNL for ADC
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 4000300020001000
04735-063
CODE
INL (LSB)
Figure 15. INL for ADC
12000
10000
8000
6000
4000
2000
0204920482047
04735-064
CODE
HITS PER CODE
81
9894
25
Figure 16. ADC Noise, Midcode Input, 10,000 Reads
Data Sheet ADM1069
Rev. E | Page 13 of 34
04735-059
CH1 200mV M1.00µs CH1 756mV
1
DAC
BUFFER
OUTPUT PROBE
POINT
47pF
20kΩ
Figure 17. Transient Response of DAC Code Change into Typical Load
04735-060
CH1 200mV M1.00µs CH1 944mV
1
DAC
BUFFER
OUTPUT
1V
PROBE
POINT
100kΩ
Figure 18. Transient Response of DAC to Turn-On from High-Z State
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
–40 –20 0 20 40 60 10080
04735-065
TEMPERATURE (C)
DAC OUTPUT
VP1 = 3.0V
VP1 = 4.75V
Figure 19. DAC Output vs. Temperature
2.058
2.038
2.043
2.048
2.053
–40 –20 0 20 40 60 10080
04735-061
TEMPERATURE (C)
REFOUT (V)
VP1 = 3.0V
VP1 = 4.75V
Figure 20. REFOUT vs. Temperature
ADM1069 Data Sheet
Rev. E | Page 14 of 34
POWERING THE ADM1069
The ADM1069 is powered from the highest voltage input on
either the positive-only supply inputs (VPx) or the high voltage
supply input (VH). This technique offers improved redundancy
because the device is not dependent on any particular voltage rail
to keep it operational. The same pins are used for supply fault
detection (see the Supply Supervision section). A VDD arbitrator
on the device chooses which supply to use. The arbitrator can
be considered an OR’ing of four low dropout regulators (LDOs)
together. A supply comparator chooses the highest input to
provide the on-chip supply. There is minimal switching loss
with this architecture (~0.2 V), resulting in the ability to power
the ADM1069 from a supply as low as 3.0 V. Note that the
supply on the VXx pins cannot power the device.
An external capacitor to GND is required to decouple the on-
chip supply from noise. This capacitor must be connected to the
VDDCAP pin, as shown in Figure 21. The capacitor has another
use during brownouts (momentary loss of power). Under these
conditions, when the input supply (VPx or VH) dips transiently
below VDD, the synchronous rectifier switch immediately turns
off so that it does not pull VDD down. The VDD capacitor can then
act as a reservoir to keep the device active until the next highest
supply takes over the powering of the device. A 10 µF capacitor
is recommended for this reservoir/decoupling function.
The VH input pin can accommodate supplies up to 14.4 V, which
allows the ADM1069 to be powered using a 12 V backplane supply.
In cases where this 12 V supply is hot swapped, it is recommended
that the ADM1069 not be connected directly to the supply. Suitable
precautions, such as the use of a hot swap controller, must be
taken to protect the device from transients that can cause damage
during hot swap events.
When two or more supplies are within 100 mV of each other,
the supply that first takes control of VDD keeps control. For
example, if VP1 is connected to a 3.3 V supply, VDD powers up
to approximately 3.1 V through VP1. If VP2 is then connected
to another 3.3 V supply, VP1 still powers the device unless VP2
goes 100 mV higher than VP1.
SUPPLY
COMPARATOR
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
VH
VP3
VP2
VP1 VDDCAP
INTERNAL
DEVICE
SUPPLY
04735-022
Figure 21. VDD Arbitrator Operation
SLEW RATE CONSIDERATION
When the ambient temperature of operation is less than
approximately −20°C, and in the event of a power loss where all
supply inputs fail for less than a few hundreds of milliseconds
(for example, due to a system supply brownout), it is recommended
that the supply voltage recovers with a ramp rate of at least
1.5 V/ms or less than 0.5 V/ms.
Data Sheet ADM1069
Rev. E | Page 15 of 34
INPUTS
SUPPLY SUPERVISION
The ADM1069 has eight programmable inputs. Four of these
are dedicated supply fault detectors (SFDs). These dedicated
inputs are called VH and VPx (VP1 to VP3) by default. The
other four inputs are labeled VXx (VX1 to VX4) and have dual
functionality. They can be used either as SFDs, with functionality
similar to the VH and VPx, or as CMOS-/TTL-compatible logic
inputs to the device. Therefore, the ADM1069 can have up to
eight analog inputs, a minimum of four analog inputs and four
digital inputs, or a combination thereof. If an input is used as
an analog input, it cannot be used as a digital input. Therefore,
a configuration requiring eight analog inputs has no available
digital inputs. Table 6 shows the details of each input.
PROGRAMMING THE SUPPLY FAULT DETECTORS
The ADM1069 can have up to eight SFDs on the eight input
channels. These highly programmable reset generators enable
the supervision of up to eight supply voltages. The supplies can
be as low as 0.573 V and as high as 14.4 V. The inputs can be
configured to detect an undervoltage fault (the input voltage
drops below a preprogrammed value), an overvoltage fault (the
input voltage rises above a preprogrammed value), or an out-of-
window fault (the input voltage is outside a preprogrammed
range). The thresholds can be programmed to an 8-bit resolution
in registers provided in the ADM1069. This translates to a voltage
resolution that is dependent on the range selected. The resolution
is given by
Step Size = Threshold Range/255
Therefore, if the high range is selected on VH, the step size can
be calculated as follows:
(14.4 V − 6.0 V)/255 = 32.9 mV
Table 5 lists the upper and lower limits of each available range,
the bottom of each range (VB), and the range itself (VR).
Table 5. Voltage Range Limits
Voltage Range (V) VB (V) VR (V)
0.573 to 1.375 0.573 0.802
1.25 to 3.00 1.25 1.75
2.5 to 6.0 2.5 3.5
6.0 to 14.4 6.0 8.4
The threshold value required is given by
VT = (VR × N)/255 + VB
where:
VT is the desired threshold voltage (undervoltage or overvoltage).
VR is the voltage range.
N is the decimal value of the 8-bit code.
VB is the bottom of the range.
Reversing the equation, the code for a desired threshold is
given by
N = 255 × (VT − VB)/VR
For example, if the user wants to set a 5 V overvoltage threshold
on VP1, the code to be programmed in the PS1OVTH register
(as discussed in the AN-721 Application Note) is given by
N = 255 × (5 − 2.5)/3.5
Therefore, N = 182 (1011 0110 or 0xB6).
INPUT COMPARATOR HYSTERESIS
The undervoltage (UV) and overvoltage (OV) comparators shown
in Figure 22 are always monitoring VPx. To avoid chatter (multiple
transitions when the input is very close to the set threshold level),
these comparators have digitally programmable hysteresis. The
hysteresis can be programmed up to the values shown in Table 6.
04735-023
+
–
+
–
UV
COMPARATOR
VREF
FAULT TYPE
SELECT
OV
COMPARATOR
FAULT
OUTPUT
GLITCH
FILTER
VPx
MID
LOW
RANGE
SELECT
ULTRA
LOW
Figure 22. Supply Fault Detector Block
The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program the amount above
the undervoltage threshold to which the input must rise before
an undervoltage fault is deasserted. Similarly, the user can program
the amount below the overvoltage threshold to which an input
must fall before an overvoltage fault is deasserted.
Table 6. Input Functions, Thresholds, and Ranges
Input Function Voltage Range (V) Maximum Hysteresis Voltage Resolution (mV) Glitch Filter (µs)
VH High voltage analog input 2.5 to 6.0 425 mV 13.7 0 to 100
6.0 to 14.4 1.02 V 32.9 0 to 100
VPx Positive analog input 0.573 to 1.375 97.5 mV 3.14 0 to 100
1.25 to 3.00 212 mV 6.8 0 to 100
2.5 to 6.0 425 mV 13.7 0 to 100
VXx High-Z analog input 0.573 to 1.375 97.5 mV 3.14 0 to 100
Digital input
0 to 5.0
Not applicable
Not applicable
0 to 100
ADM1069 Data Sheet
Rev. E | Page 16 of 34
The hysteresis value is given by
VHYST = VR × NTHRESH/255
where:
VHYST is the desired hysteresis voltage.
NTHRESH is the decimal value of the 5-bit hysteresis code.
Note that NTHRESH has a maximum value of 31. The maximum
hysteresis for the ranges is listed in Table 6.
INPUT GLITCH FILTERING
The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators,
which allows the user to remove any spurious transitions such
as supply bounce at turn-on. The glitch filter function is in addition
to the digitally programmable hysteresis of the SFD comparators.
The glitch filter timeout is programmable up to 100 µs.
For example, when the glitch filter timeout is 100 µs, any pulse
appearing on the input of the glitch filter block that is less than
100 µs in duration is prevented from appearing on the output of
the glitch filter block. Any input pulse that is longer than 100 µs
appears on the output of the glitch filter block. The output is
delayed with respect to the input by 100 µs. The filtering
process is shown in Figure 23.
04735-024
t
0
t
GF
t
0
t
GF
t
0
t
GF
t
0
t
GF
INPUT
INPUT PULSE SHORTER
THAN GLITCH FILTER TIMEOUT INPUT PULSE LONGER
THAN GLITCH FILTER TIMEOUT
OUTPUT
PROGRAMMED
TIMEOUT PROGRAMMED
TIMEOUT
INPUT
OUTPUT
Figure 23. Input Glitch Filter Function
VP1 Glitch Filtering
If the ADC round-robin is used, it is recommended to enable
glitch filtering on VP1 because the ADC input mux is connected
to VP1 when the ADC round-robin stops. When the ADC
round-robin stops, a small internal glitch on the VP1 monitor
rail occurs, and if the rail is close to the UV threshold, it can be
enough to trip the VP1 UV comparator. Use any value of glitch
filter greater than 0 µs to avoid false UV triggers. For more
information about the ADC round-robin, see the Voltage
Readback section.
SUPPLY SUPERVISION WITH VXx INPUTS
The VXx inputs have two functions. They can be used as either
supply fault detectors or digital logic inputs. When selected as
analog (SFD) inputs, the VXx pins have functionality that is
very similar to the VH and VPx pins. The primary difference is
that the VXx pins have only one input range: 0.573 V to 1.375 V.
Therefore, these inputs can directly supervise only the very low
supplies. However, the input impedance of the VXx pins is high,
allowing an external resistor divide network to be connected to
the pin. Thus, potentially any supply can be divided down into
the input range of the VXx pin and supervised. This enables the
ADM1069 to monitor other supplies, such as +24 V, +48 V,
a n d −5 V.
An additional supply supervision function is available when the
VXx pins are selected as digital inputs. In this case, the analog
function is available as a second detector on each of the dedi-
cated analog inputs, VPx and VH. The analog function of VX1
is mapped to VP1, VX2 is mapped to VP2, and so on. VX4 is
mapped to VH. In this case, these SFDs can be viewed as secondary
or warning SFDs.
The secondary SFDs are fixed to the same input range as the
primary SFDs. They o indicate warning levels rather than failure
levels. This allows faults and warnings to be generated on a single
supply using only one pin. For example, if VP1 is set to output a
fault when a 3.3 V supply drops to 3.0 V, VX1 can be set to output a
warning at 3.1 V. Warning outputs are available for readback from
the status registers. They are also OR’ed together and fed into
the SE, allowing warnings to generate interrupts on the PDOs.
Therefore, in this example, if the supply drops to 3.1 V, a warning
is generated, and remedial action can be taken before the supply
drops out of tolerance.
Data Sheet ADM1069
Rev. E | Page 17 of 34
VXx PINS AS DIGITAL INPUTS
As discussed in the Supply Supervision with VXx Inputs section,
the VXx input pins on the ADM1069 have dual functionality. The
second function is as a digital logic input to the device. Therefore,
the ADM1069 can be configured for up to four digital inputs.
These inputs are TTL-/CMOS-compatible. Standard logic signals
can be applied to the pins: RESET from reset generators, PWRGD
signals, fault flags, manual resets, and so on. These signals are
available as inputs to the SE and, therefore, can control the status of
the PDOs. The inputs can be configured to detect either a change
in level or an edge.
When configured for level detection, the output of the digital
block is a buffered version of the input. When configured for
edge detection, a pulse of programmable width is output from
the digital block once the logic transition is detected. The width
is programmable from 0 µs to 100 µs.
The digital blocks feature the same glitch filter function that is
available on the SFDs. This enables the user to ignore spurious
transitions on the inputs. For example, the filter can debounce a
manual reset switch.
When configured as digital inputs, each VXx pin has a weak
(10 µA) pull-down current source available for placing the input
into a known condition, even if left floating. The current source,
if selected, weakly pulls the input to GND.
04735-027
DETECTOR
VXx
(DIGITAL INP UT) GLITCH
FILTER
VREF = 1.4V
TO
SEQUENCING
ENGINE
+
–
Figure 24. VXx Digital Input Function
ADM1069 Data Sheet
Rev. E | Page 18 of 34
OUTPUTS
SUPPLY SEQUENCING THROUGH
CONFIGURABLE OUTPUT DRIVERS
Supply sequencing is achieved with the ADM1069 using the
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.
The sequence in which the PDOs are asserted (and, therefore,
the supplies are turned on) is controlled by the sequencing engine
(SE). The SE determines what action is taken with the PDOs
based on the condition of the ADM1069 inputs. Therefore, the
PDOs can be set up to assert when the SFDs are in tolerance,
the correct input signals are received on the VXx digital pins, no
warnings are received from any of the inputs of the device, and at
other times. The PDOs can be used for a variety of functions. The
primary function is to provide enable signals for LDOs or dc-
to-dc converters that generate supplies locally on a board. The
PDOs can also provide a PWRGD signal, when all the SFDs are
in tolerance, or a RESET output if one of the SFDs goes out of
specification (this can be used as a status signal for a DSP,
FPGA, or other microcontroller).
The PDOs can be programmed to pull up to a number of
different options. The outputs can be programmed as follows:
• Open-drain (allowing the user to connect an external pull-
up resistor).
• Open-drain with weak pull-up to VDD.
• Open-drain with strong pull-up to VDD.
• Open-drain with weak pull-up to VPx.
• Open-drain with strong pull-up to VPx.
• Strong pull-down to GND.
• Internally charge-pumped high drive
(12 V, PDO1 to PDO6 only).
The last option (available only on PDO1 to PDO6) allows the
user to directly drive a voltage high enough to fully enhance an
external N-FET, which isolates, for example, a card-side voltage
from a backplane supply (a PDO can sustain greater than 10.5 V
into a 1 µA load). The pull-down switches can also drive status
LEDs directly.
The data driving each of the PDOs can come from one of three
sources. The source can be enabled in the PDOxCFG configuration
register (see the AN-721 Application Note for details).
The data sources are as follows:
• Output from the SE.
• Directly from the SMBus. A PDO can be configured so that
the SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be
initiate a software power-up/power-down sequence.
• On-chip clock. A 100 kHz clock is generated on the device.
This clock can be made available on any of the PDOs. It
can be used, for example, to clock an external device such
as an LED.
DEFAULT OUTPUT CONFIGURATION
All of the internal registers in an unprogrammed ADM1069 device
from the factory are set to 0. Because of this, the PDOx pins are
pulled to GND by a weak (20 kΩ) on-chip pull-down resistor.
As the input supply to the ADM1069 ramps up on VPx or VH,
all PDOx pins behave as follows:
• Input supply = 0 V to 1.2 V. The PDOs are high impedance.
• Input supply = 1.2 V t o 2 . 7 V. The PDOs are pulled to GND
by a weak (20 kΩ) on-chip pull-down resistor.
• Supply > 2.7 V. Factory programmed devices continue to
pull all PDOs to GND by a weak (20 kΩ) on-chip pull-
down resistor. Programmed devices download current
EEPROM configuration data, and the programmed setup is
latched. The PDO then goes to the state demanded by the
configuration. This provides a known condition for the
PDOs during power-up.
The internal pull-down can be overdriven with an external pull-
up of suitable value tied from the PDOx pin to the required
pull-up voltage. The 20 kΩ resistor must be accounted for in
calculating a suitable value. For example, if PDOx must be pulled
up to 3.3 V, and 5 V is available as an external supply, the pull-
up resistor value is given by
3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)
Therefore,
RUP = (100 kΩ − 66 kΩ)/3.3 V = 10 kΩ
Data Sheet ADM1069
Rev. E | Page 19 of 34
04735-028
PDO
SE DAT A
CFG4 CFG5 CFG6
SMBus DATA
CLK DATA
10Ω
20kΩ
10Ω
20kΩ
VP1
SEL VP4
10Ω
20kΩ
VDD
VFET (PDO1 TO PDO6 ONLY)
20kΩ
Figure 25. Programmable Driver Output
ADM1069 Data Sheet
Rev. E | Page 20 of 34
SEQUENCING ENGINE
OVERVIEW
The ADM1069 sequencing engine (SE) provides the user with
powerful and flexible control of sequencing. The SE implements
a state machine control of the PDO outputs, with state changes
conditional on input events. SE programs can enable complex
control of boards such as power-up and power-down sequence
control, fault event handling, interrupt generation on warnings,
and so on. A watchdog function that verifies the continued
operation of a processor clock can be integrated into the SE
program. The SE can also be controlled via the SMBus, giving
software or firmware control of the board sequencing.
The SE state machine comprises 63 state cells. Each state has the
following attributes:
• Monitors signals indicating the status of the eight input
pins, VP1 to VP3, VH, and VX1 to VX4.
• Can be entered from any other state.
• Three exit routes move the state machine onto a next state:
sequence detection, fault monitoring, and timeout.
• Delay timers for the sequence and timeout blocks can be
programmed independently, and changed with each state
change. The range of timeouts is from 0 ms to 400 ms.
• Output condition of the eight PDO pins is defined and
fixed within a state.
• Transition from one state to the next is made in less than
20 µs, which is the time needed to download a state
definition from EEPROM to the SE.
04735-029
SEQUENCE
TIMEOUT
MONITOR
FAULT STATE
Figure 26. State Cell
The ADM1069 offers up to 63 state definitions. The signals
monitored to indicate the status of the input pins are the
outputs of the SFDs.
WARNINGS
The SE also monitors warnings. These warnings can be generated
when the ADC readings violate their limit register value or when
the secondary voltage monitors on VPx and VH are triggered.
The warnings are OR’ed together and are available as a single
warning input to each of the three blocks that enable exiting
a state.
SMBus JUMP (UNCONDITIONAL JUMP)
The SE can be forced to advance to the next state uncondition-
ally. This enables the user to force the SE to advance. Examples
of the use of this feature include moving to a margining state or
debugging a sequence. The SMBus jump or go-to command can
be seen as another input to sequence and timeout blocks to
provide an exit from each state.
Table 7. Sample Sequence State Entries
State Sequence Timeout Monitor
IDLE1 If VX1 is low, go to State IDLE2.
IDLE2 If VP1 is okay, go to State EN3V3.
EN3V3 If VP2 is okay, go to State EN2V5. If VP2 is not okay after 10 ms,
go to State DIS3V3.
If VP1 is not okay, go to State IDLE1.
DIS3V3 If VX1 is high, go to State IDLE1.
EN2V5 If VP3 is okay, go to State PWRGD. If VP3 is not okay after 20 ms,
go to State DIS2V5.
If VP1 or VP2 is not okay, go to State FSEL2.
DIS2V5
If VX1 is high, go to State IDLE1.
FSEL1 If VP3 is not okay, go to State DIS2V5. If VP1 or VP2 is not okay, go to State FSEL2.
FSEL2 If VP2 is not okay, go to State DIS3V3. If VP1 is not okay, go to State IDLE1.
PWRGD If VX1 is high, go to State DIS2V5. If VP1, VP2, or VP3 is not okay, go to State FSEL1.
Data Sheet ADM1069
Rev. E | Page 21 of 34
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the SE. Figure 28 shows how the simple building block of a
single SE state can build a power-up sequence for a three-supply
system. Table 8 lists the PDO outputs for each state in the same
SE implementation. In this system, a good 5 V supply on VP1 and
the VX1 pin held low are the triggers required to start a power-up
sequence. The sequence next turns on the 3.3 V supply, then the
2.5 V supply (assuming successful turn-on of the 3.3 V supply).
When all three supplies have turned on correctly, the PWRGD
state is entered, where the SE remains until a fault occurs on one
of the three supplies, or until it is instructed to go through a
power-down sequence by VX1 going high.
Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following three sections (the Sequence
Detector section, the Monitoring Fault Detector section, and
the Timeout Detector section) describe the individual blocks
and use the sample application shown in Figure 28 to demonstrate
the actions of the state machine.
Sequence Detector
The sequence detector block detects when a step in a sequence
has been completed. It looks for one of the SE inputs to change
state, and is most often used as the gate for successful progress
through a power-up or power-down sequence. A timer block
that is included in this detector can insert delays into a power-
up or power-down sequence, if required. Timer delays can be
set from 10 µs to 400 ms. Figure 27 is a block diagram of the
sequence detector.
04735-032
SUPPLY FAULT
DETECTION
LOGIC INPUT CHANGE
OR FAULT DETECTION
WARNINGS
FORCE FLOW
(UNCONDITIONAL JUMP)
VP1
VX4
INVERT
SEQUENCE
DETECTOR
SELECT
TIMER
Figure 27. Sequence Detector Block Diagram
If a timer delay is specified, the input to the sequence detector
must remain in the defined state for the duration of the timer
delay. If the input changes state during the delay, the timer is reset.
The sequence detector can also help to identify monitoring faults.
In the sample application shown in Figure 28, the FSEL1 and
FSEL2 states first identify which of the VP1, VP2, or VP3 pins
has faulted, and then they take appropriate action.
04735-030
IDLE1
IDLE2
EN3V3
DIS3V3
DIS2V5
PWRGD
FSEL1
FSEL2
SEQUENCE
STATES
MONITOR FAULT
STATES TIMEOUT
STATES
VX1 = 0
VP1 = 1
VP1 = 0
(VP1 + VP2) = 0
(VP1 + VP2 + VP3) = 0
(VP1 +
VP2) = 0
VP2 = 1
VP3 = 1
VP2 = 0
VX1 = 1
VP3 = 0
VP2 = 0
VP1 = 0
VX1 = 1
VX1 = 1
10ms
20ms
EN2V5
Figure 28. Sample Application Flow Diagram
Table 8. PDO Outputs for Each State
PDO Outputs IDLE1 IDLE2 EN3V3 EN2V5 DIS3V3 DIS2V5 PWRGD FSEL1 FSEL2
PDO1 = 3V3ON 0 0 1 1 0 1 1 1 1
PDO2 = 2V5ON 0 0 0 1 1 0 1 1 1
PDO3 = FAULT 0 0 0 0 1 1 0 1 1
ADM1069 Data Sheet
Rev. E | Page 22 of 34
Monitoring Fault Detector
The monitoring fault detector block detects a failure on an input.
The logical function implementing this is a wide OR gate that
can detect when an input deviates from the expected condition.
The clearest demonstration of the use of this block is in the
PWRGD state, where the monitor block indicates that a failure
on one or more of the VP1, VP2, or VP3 inputs has occurred.
No programmable delay is available in this block because the
triggering of a fault condition is likely to be caused by a supply
falling out of tolerance. In this situation, the device must react as
quickly as possible. Some latency occurs when moving out of this
state because it takes a finite amount of time (~20 µs) for the state
configuration to download from EEPROM into the SE. Figure 29
is a block diagram of the monitoring fault detector.
04735-033
SUPPLY FAULT
DETECTION
LOGIC INPUT CHANGE
OR FAULT DETECTION
VP1
VX4
MONITORING FAULT
DETECTOR
MASK
SENSE
1-BIT FAULT
DETECTOR
FAULT
WARNINGS
MASK
1-BIT FAULT
DETECTOR
FAULT
MASK
SENSE
1-BIT FAULT
DETECTOR
FAULT
Figure 29. Monitoring Fault Detect or Block Diagram
Timeout Detector
The timeout detector allows the user to trap a failure to ensure
proper progress through a power-up or power-down sequence.
In the sample application shown in Figure 28, the timeout next-
state transition is from the EN3V3 and EN2V5 states. For the
EN3V3 state, the signal 3V3ON is asserted on the PDO1 output
pin upon entry to this state to turn on a 3.3 V supply.
This supply rail is connected to the VP2 pin, and the sequence
detector looks for the VP2 pin to go above the undervoltage
threshold, which is set in the supply fault detector (SFD)
attached to that pin.
The power-up sequence progresses when this change is detected.
If, however, the supply fails (perhaps due to a short circuit over-
loading this supply), the timeout block traps the problem. In this
example, if the 3.3 V supply fails within 10 ms, the SE moves to
the DIS3V3 state and turns off this supply by bringing PDO1
low. It also indicates that a fault has occurred by taking PDO3
high. Timeout delays of 100 µs to 400 ms can be programmed.
FAULT AND STATUS REPORTING
The ADM1069 has a fault latch for recording faults. Two registers,
FSTAT1 and FSTAT2, are set aside for this purpose. A single bit
is assigned to each input of the device, and a fault on that input
sets the relevant bit. The contents of the fault register can be
read out over the SMBus to determine which input(s) faulted.
The fault register can be enabled/disabled in each state. To latch
data from one state, ensure that the fault latch is disabled in the
following state. This ensures that only real faults are captured
and not, for example, undervoltage conditions that can be present
during a power-up or power-down sequence.
The ADM1069 also has a number of status registers. These
include more detailed information, such as whether an under-
voltage or overvoltage fault is present on a particular input. The
status registers also include information on ADC limit faults.
Note that the data in the status registers is not latched in any
way and, therefore, is subject to change at any time.
See the AN-721 Application Note for full details about the
ADM1069 registers.
Data Sheet ADM1069
Rev. E | Page 23 of 34
VOLTAGE READBACK
The ADM1069 has an on-board, 12-bit, accurate ADC for voltage
readback over the SMBus. The ADC has an 8-channel analog
mux on the front end. The eight channels consist of the eight
SFD inputs (VH, VPx, and VXx). Any or all of these inputs can be
selected to be read, in turn, by the ADC. The circuit controlling
this operation is called the ADC round-robin. This circuit can be
selected to run through the loop of conversions once or conti-
nuously. Averaging is also provided for each channel. In this case,
the ADC round-robin runs through the loop of conversions
16 times before returning a result for each channel. At the end
of this cycle, the results are written to the output registers.
The ADC samples single-sided inputs with respect to the AGND
pin. A 0 V input gives out Code 0, and an input equal to the
voltage on REFIN gives out full code (4095 decimal).
The inputs to the ADC come directly from the VXx pins and from
the back of the input attenuators on the VPx and VH pins,
as shown in Figure 30 and Figure 31.
04735-025
VXx
2.048V V RE F
NO ATTENUATION
12-BIT
ADC
DIGITIZED
VOLTAGE
READING
Figure 30. ADC Reading on VXx Pins
04735-026
2.048V V RE F
ATTENUATION NETWORK
(DEPENDS ON RANGE SELECTED)
12-BIT
ADC
DIGITIZED
VOLTAGE
READING
VPx/VH
Figure 31. ADC Reading on VPx/VH Pins
The voltage at the input pin can be derived from the following
equation:
V =
4095
CodeADC
× Attenuation Factor × VREFIN
where VREFIN = 2.048 V when the internal reference is used (that is,
the REFIN pin is connected to the REFOUT pin).
The ADC input voltage ranges for the SFD input ranges are
listed in Table 9.
Table 9. ADC Input Voltage Ranges
SFD Input
Range (V)
Attenuation
Factor
ADC Input Voltage
Range (V)
0.573 to 1.375 1 0 to 2.048
1.25 to 3.00 2.181 0 to 4.46
2.5 to 6.0 4.363 0 to 6.01
6.0 to 14.4 10.472 0 to 14.41
1 The upper limit is the absolute maximum allowed voltage on the VPx and
VH pins.
The typical way to supply the reference to the ADC on the
REFIN pin is to connect the REFOUT pin to the REFIN pin.
REFOUT provides a 2.048 V reference. As such, the supervising
range covers less than half the normal ADC range. It is possible,
however, to provide the ADC with a more accurate external
reference for improved readback accuracy.
Supplies can also be connected to the input pins purely for ADC
readback, even though these pins can go above the expected
supervisory range limits (but not above the absolute maximum
ratings on these pins). For example, a 1.5 V supply connected to
the VX1 pin can be correctly read out as an ADC code of approxi-
mately 3/4 full scale, but it always sits above any supervisory limits
that can be set on that pin. The maximum setting for the REFIN
pin is 2.048 V.
SUPPLY SUPERVISION WITH THE ADC
In addition to the readback capability, another level of supervision
is provided by the on-chip 12-bit ADC. The ADM1069 has limit
registers with which the user can program a maximum or mini-
mum allowable threshold. Exceeding the threshold generates a
warning that can either be read back from the status registers
or input into the SE to determine what sequencing action the
ADM1069 must take. Only one register is provided for each
input channel. Therefore, either an undervoltage threshold or
overvoltage threshold (but not both) can be set for a given channel.
The ADC round-robin can be enabled via an SMBus write, or it
can be programmed to turn on in any state in the SE program.
For example, it can be set to start after a power-up sequence is
complete, and all supplies are known to be within expected
tolerance limits.
Note that a latency is built into this supervision, dictated by the
conversion time of the ADC. With all 12 channels selected, the
total time for the ADC round-robin operation (averaging off) is
approximately 6 ms (500 µs per channel selected). Supervision
using the ADC, therefore, does not provide the same real-time
response as the SFDs.
ADM1069 Data Sheet
Rev. E | Page 24 of 34
SUPPLY MARGINING
OVERVIEW
It is often necessary for the system designer to adjust supplies,
either to optimize their level or force them away from nominal
values to characterize the system performance under these
conditions. This is a function typically performed during an
in-circuit test (ICT), such as when a manufacturer wants to
guarantee that a product under test functions correctly at
nominal supplies minus 10%.
OPEN-LOOP SUPPLY MARGINING
The simplest method of margining a supply is to implement
an open-loop technique (see Figure 32). A popular way to do
this is to switch extra resistors into the feedback node of a power
module, such as a dc-to-dc converter or low dropout regulator
(LDO). The extra resistor alters the voltage at the feedback or
trim node and forces the output voltage to margin up or down
by a certain amount.
The ADM1069 can perform open-loop margining for up to four
supplies. The four on-board voltage DACs (DAC1 to DAC4) can
drive into the feedback pins of the power modules to be margined.
The simplest circuit to implement this function is an attenuation
resistor that connects the DACx pin to the feedback node of a
dc-to-dc converter. When the DACx output voltage is set equal
to the feedback voltage, no current flows into the attenuation
resistor, and the dc-to-dc converter output voltage does not change.
Taking DACx above the feedback voltage forces current into the
feedback node, and the output of the dc-to-dc converter is forced
to fall to compensate for this. The dc-to-dc converter output can be
forced high by setting the DACx output voltage lower than the
feedback node voltage. The series resistor can be split in two, and
the node between them can be decoupled with a capacitor to
ground. This can help to decouple any noise picked up from the
board. Decoupling to a ground local to the dc-to-dc converter
is recommended.
The ADM1069 can be commanded to margin a supply up or
down over the SMBus by updating the values on the relevant
DAC output.
CLOSED-LOOP SUPPLY MARGINING
A more accurate and comprehensive method of margining is to
implement a closed-loop system (see Figure 33). The voltage on
the rail to be margined can be read back to accurately margin the
rail to the target voltage. The ADM1069 incorporates all the circuits
required to do this, with the 12-bit successive approximation ADC
reading back the level of the supervised voltages, and the six voltage
output DACs, implemented as described in the Open-Loop Supply
Margining section, adjusting supply levels. These circuits can be
used along with other intelligence, such as a microcontroller, to
implement a closed-loop margining system that allows any dc-to-
dc converter or LDO supply to be set to any voltage, accurate to
within ±0.5% of the target.
To implement closed-loop margining,
1. 1. Disable the four DACx outputs.
2. 2. Set the DAC output voltage equal to the voltage on the
feedback node.
3. 3. Enable the DAC.
4. 4. Read the voltage at the dc-to-dc converter output that
is connected to one of the VPx, VH, or VXx pins.
5. 5. If necessary, modify the DACx output code up or
down
to adjust the dc-to-dc converter output voltage. Otherwise,
stop because the target voltage has been reached.
6. 6. Set the DAC output voltage to a value that alters the
supply output by the required amount (for example, ±5%).
7. 7. Repeat Step 4 through Step 6 until the measured
supply reaches the target voltage.
Step 1 to Step 3 ensure that when the DACx output buffer is turned
on, it has little effect on the dc-to-dc converter output. The DAC
output buffer is designed to power up without glitching by first
powering up the buffer to follow the pin voltage. It does not drive
out onto the pin at this time. Once the output buffer is properly
enabled, the buffer input is switched over to the DAC, and the
output stage of the buffer is turned on. Output glitching is
negligible.
04735-067
OUTPUT
DC-TO-DC
CONVERTER
FEEDBACK
GND
ATTENUATION
RESI ST O R, R3
PCB
TRACE NO ISE
DECOUPLING
CAPACITOR
ADM1069
DACx
V
OUT
DAC
MICROCONTROLLER
VIN
DEVICE
CONTROLLER
(SMBus)
R1
R2
Figure 32. Open-Loop Margining System Using the ADM1069
Data Sheet ADM1069
Rev. E | Page 25 of 34
04735-034
OUTPUT
DC-TO-DC
CONVERTER
FEEDBACK
GND
ATTENUATION
RESISTOR
PCB
TRACE NOI SE
DECOUPLING
CAPACITOR
VH/VPx/VXx
ADM1069
DACx
MUX ADC
DAC
DEVICE
CONTROLLER
(SMBus)
MICROCONTROLLER
VIN
Figure 33. Closed-Loop Margining System Using the ADM1069
WRITING TO THE DACS
Four DAC ranges are offered. They can be placed with midcode
(Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V. These voltages are
placed to correspond to the most common feedback voltages.
Centering the DAC outputs in this way provides the best use of
the DAC resolution. For most supplies, it is possible to place the
DAC midcode at the point where the dc-to-dc converter output
is not modified, thereby giving half of the DAC range to margin
up and the other half to margin down.
The DAC output voltage is set by the code written to the DACx
register. The voltage is linear with the unsigned binary number
in this register. Code 0x7F is placed at the midcode voltage, as
described previously. The output voltage is given by
DAC Output = (DACx − 0x7F)/255 × 0.6015 + VOFF
where VOFF is one of the four offset voltages.
There are 256 DAC settings available. The midcode value is
located at DAC Code 0x7F, as close as possible to the middle
of the 256 code range. The full output swing of the DACs is
+302 mV (+128 codes) and −300 mV (−127 codes) around the
selected midcode voltage. The voltage range for each midcode
voltage is shown in Table 10.
Table 10. Ranges for Midcode Voltages
Midcode
Voltage (V)
Minimum Voltage
Output (V)
Maximum Voltage
Output (V)
0.6 0.300 0.902
0.8 0.500 1.102
1.0 0.700 1.302
1.25 0.950 1.552
CHOOSING THE SIZE OF THE ATTENUATION
RESISTOR
The size of the attenuation resistor, R3, determines how much
the DAC voltage swing affects the output voltage of the dc-to-dc
converter that is being margined (see Figure 33).
Because the voltage at the feedback pin remains constant, the
current flowing from the feedback node to GND through R2 is
a constant. In addition, the feedback node itself is high impedance.
This means that the current flowing through R1 is the same as
the current flowing through R3. Therefore, a direct relationship
exists between the extra voltage drop across R1 during margining
and the voltage drop across R3.
This relationship is given by the following equation:
ΔVOUT = R3
R1 (VFB − VDACOUT)
where:
ΔVOUT is the change in VOUT.
VFB is the voltage at the feedback node of the dc-to-dc converter.
VDACOUT is the voltage output of the margining DAC.
This equation demonstrates that if the user wants the output
voltage to change by ±300 mV, then R1 = R3. If the user wants
the output voltage to change by ±600 mV, R1 = 2 × R3, and so on.
It is best to use the full DAC output range to margin a supply.
Choosing the attenuation resistor in this way provides the most
resolution from the DAC, meaning that with one DAC code
change, the smallest effect on the dc-to-dc converter output
voltage is induced. If the resistor is sized up to use a code such
as 27 decimal to 227 decimal to move the dc-to-dc converter
output by ±5%, it takes 100 codes to move 5% (each code moves
the output by 0.05%). This is beyond the readback accuracy of
the ADC, but it must not prevent the user from building a
circuit to use the most resolution.
DAC LIMITING AND OTHER SAFETY FEATURES
Limit registers (called DPLIMx and DNLIMx) on the device
offer the user some protection from firmware bugs that can
cause catastrophic board problems by forcing supplies beyond
their allowable output ranges. Essentially, the DAC code written
into the DACx register is clipped such that the code thar sets
the DAC voltage is given by
DAC Code
= DACx, DACx ≥ DNLIMx and DACx ≤ DPLIMx
= DNLIMx, DACx < DNLIMx
= DPLIMx, DACx > DPLIMx
In addition, the DAC output buffer is three-stated if DNLIMx >
DPLIMx. By programming the limit registers this way, the user
can make it very difficult for the DAC output buffers to be turned
on during normal system operation. The limit registers are among
the registers downloaded from EEPROM at startup.
ADM1069 Data Sheet
Rev. E | Page 26 of 34
APPLICATIONS DIAGRAM
04735-068
3.3V OUT
VH
PDO8
PDO7 SYSTEM RESET
PDO6 PWRGD
PDO2
DAC1
PDO1
PDO5
PDO4
PDO3
EN OUT
DC-TO-DC1
IN
3.3V OUT
3V OUT
5V OUT
12V OUT
EN OUT
DC-TO-DC2
IN
1.25V OUT
EN OUT
DC-TO-DC3
IN
1.2V OUT
0.9V OUT
5V OUT
12V IN
5V IN
3V IN
VP1
3V OUT VP2
3.3V OUT VP 3
1.25V OUT VX1
1.2V OUT VX 2
0.9V OUT VX 3
REFOUT
POWRON VX4
10µF 10µF 10µF
REFIN VCCP VDDCAP GND
EN TRIM
OUT
DC-TO-DC4
IN
ADM1069
*ONL Y ONE MARG INING CI RCUIT
SHOWN F OR CLARI TY. DAC1 TO DAC4
ALL OW MARGINING FOR UP TO
FOUR VOLTAGE RAILS .
Figure 34. Applications Diagram
Data Sheet ADM1069
Rev. E | Page 27 of 34
COMMUNICATING WITH THE ADM1069
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1069 (undervoltage/overvoltage
thresholds, glitch filter timeouts, PDO configurations, and so on)
is dictated by the contents of the RAM. The RAM comprises
digital latches that are local to each of the functions on the device.
The latches are double-buffered and have two identical latches,
Latch A and Latch B. Therefore, when an update to a function
occurs, the contents of Latch A are updated first, and then the
contents of Latch B are updated with identical data. The advantages
of this architecture are explained in detail in the Updating the
Configuration section.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the EEPROM
(nonvolatile memory) to the local latches. This download occurs
in steps, as follows:
1. With no power applied to the device, the PDOs are all high
impedance.
2. When 1.2 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPx), the PDOs are all weakly pulled
to GND with a 20 kΩ resistor.
3. When the supply rises above the undervoltage lockout of
the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.
4. The EEPROM downloads the contents to all Latch As.
5. When the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals
all Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
6. At 0.5 ms after the configuration download completes, the first
state definition is downloaded from the EEPROM into
the SE.
Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1069 to issue
a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
the EEPROM into the RAM registers, the user may need to alter
the configuration of functions on the ADM1069, such as changing
the undervoltage or overvoltage limit of an SFD, changing the
fault output of an SFD, or adjusting the rise time delay of one of
the PDOs.
The ADM1069 provides several options that allow the user to
update the configuration over the SMBus interface. The
following three options are controlled in the UPDCFG register.
Option 1
Update the configuration in real time. The user writes to the RAM
across the SMBus, and the configuration is updated immediately.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1069 remains unchanged
and continues to operate in the original setup until the instruction
is given to update the Latch Bs.
Option 3
Change the EEPROM register contents without changing the RAM
contents, and then download the revised EEPROM contents to the
RAM registers. With this method, the configuration of the
ADM1069 remains unchanged and continues to operate in the
original setup until the instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents if
revisions to the configuration are unsatisfactory. For example,
if the user must alter an overvoltage threshold, the RAM register
can be updated, as described in Option 1. However, if the user is
not satisfied with the change and wants to revert to the original
programmed value, the device controller can issue a command
to download the EEPROM contents to the RAM again, as
described in Option 3, restoring the ADM1069 to the original
configuration.
The topology of the ADM1069 makes this type of operation
possible. The local, volatile registers (RAM) are all double-buffered
latches. Setting Bit 0 of the UPDCFG register to 1 leaves the
double-buffered latches open at all times. If Bit 0 is set to 0 when a
RAM write occurs across the SMBus, only the first side of the
double-buffered latch is written to. The user must then write a 1
to Bit 1 of the UPDCFG register. This generates a pulse to update
all the second latches at once. EEPROM writes occur in a
similar way.
The final bit in this register can enable or disable EEPROM page
erasure. If this bit is set high, the contents of an EEPROM page
can all be set to 1. If low, the contents of a page cannot be erased,
even if the command code for page erasure is programmed across
the SMBus. The bit map for the UPDCFG register is shown in
the AN-721 Application Note. A flow diagram for download at
power-up and subsequent configuration updates is shown in
Figure 35.
ADM1069 Data Sheet
Rev. E | Page 28 of 34
04735-035
POWER-UP
(V
CC
> 2.5V)
EEPROM
E
E
P
R
O
M
L
D
D
A
T
A
R
A
M
L
D
U
P
D
SMBus
DEVICE
CONTROLLER
LATCH A LATCH B FUNCTION
(OV THRESHOLD
ON VP1)
Figure 35. Configuration Update Flow Diagram
UPDATING THE SEQUENCING ENGINE
Sequencing engine (SE) functions are not updated in the same
way as regular configuration latches. The SE has a dedicated 512-
byte EEPROM for storing state definitions, providing 63 individual
states, each with a 64-bit word (one state is reserved). At power-
up, the first state is loaded from the SE EEPROM into the engine
itself. When the conditions of this state are met, the next state is
loaded from the EEPROM into the engine, and so on. The loading
of each new state takes approximately 10 µs.
To alter a state, the required changes must be made directly to
the EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to the EEPROM.
INTERNAL REGISTERS
The ADM1069 contains a large number of data registers.
The principal registers are the address pointer register and
the configuration registers.
Address Pointer Register
The address pointer register contains the address that selects one
of the other internal registers. When writing to the ADM1069,
the first byte of data is always a register address that is written to
the address pointer register.
Configuration Registers
The configuration registers provide control and configuration
for various operating parameters of the ADM1069.
EEPROM
The ADM1069 has two 512-byte cells of nonvolatile, electrically
erasable, programmable read-only memory (EEPROM), from
Register Address 0xF800 to Register Address 0xFBFF. The
EEPROM is used for permanent storage of data that is not lost
when the ADM1069 is powered down. One EEPROM cell contains
the configuration data of the device; the other contains the state
definitions for the SE. Although referred to as read-only memory,
the EEPROM can be written to, as well as read from, using the
serial bus in exactly the same way as the other registers.
The major differences between the EEPROM and other
registers are as follows:
• An EEPROM location must be blank before it can be
written to. If it contains data, the data must first be erased.
• Writing to the EEPROM is slower than writing to the RAM.
• Writing to the EEPROM must be restricted because it has a
limited write/cycle life of typically 10,000 write operations,
due to the usual EEPROM wear-out mechanisms.
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes
each. Page 0 to Page 6, starting at Address 0xF800, hold the
configuration data for the applications on the ADM1069 (such
as the SFDs and PDOs). These EEPROM addresses are the same
as the RAM register addresses, prefixed by F8. Page 7 is
reserved. Page 8 to Page 15 are for customer use.
Data can be downloaded from the EEPROM to the RAM in one
of the following ways:
• At power-up, when Page 0 to Page 6 are downloaded.
• By setting Bit 0 of the UDOWNLD register (0xD8), which
performs a user download of Page 0 to Page 6.
SERIAL BUS INTERFACE
The ADM1069 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device,
under the control of a master device. It takes approximately
1 ms after power-up for the ADM1069 to download from the
EEPROM. Therefore, access to the ADM1069 is restricted until
the download is complete.
Identifying the ADM1069 on the SMBus
The ADM1069 has a 7-bit serial bus slave address (see Table 11).
The device is powered up with a default serial bus address. The
five MSBs of the address are set to 10011; the two LSBs are
determined by the logical states of Pin A1 and Pin A0. This
allows the connection of four ADM1069 devices to one SMBus.
Table 11. Serial Bus Slave Address
A1 Pin A0 Pin Hex Address 7-Bit Address1
Low Low 0x98 1001100x
Low High 0x9A 1001101x
High Low 0x9C 1001110x
High High 0x9E 1001111x
1 x means read/write bit. The address is shown only as the first 7 MSBs.
Data Sheet ADM1069
Rev. E | Page 29 of 34
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 12 lists these registers
with their values and functions.
Table 12. Identification Register Values and Functions
Name Address Value Function
MANID 0xF4 0x41 Manufacturer ID for Analog Devices
REVID 0xF5 0x02 Silicon revision
MARK1 0xF6 0x00 Software brand
MARK2 0xF7 0x00 Software brand
General SMBus Timing
Figure 36, Figure 37, and Figure 38 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and Read Operations sections.
The general SMBus protocol operates as follows:
Step 1
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data (SDA) line,
while the serial clock line (SCL) remains high. This indicates that
a data stream follows. All slave peripherals connected to the serial
bus respond to the start condition and shift in the next eight bits,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 = write,
1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low period
before the ninth clock pulse, known as the acknowledge bit, and
by holding it low during the high period of this clock pulse.
All other devices on the bus remain idle while the selected device
waits for data to be read from or written to it. If the R/W bit is a 0,
the master writes to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
Step 2
Data is sent over the serial bus in sequences of nine clock pulses:
eight bits of data followed by an acknowledge bit from the slave
device. Data transitions on the data line must occur during the
low period of the clock signal and remain stable during the high
period because a low-to-high transition when the clock is high
can be interpreted as a stop signal. If the operation is a write
operation, the first data byte after the slave address is a command
byte. This command byte tells the slave device what to expect next.
It can be an instruction telling the slave device to expect a block
write, or it can be a register address that tells the slave where
subsequent data is to be written. Because data can flow in only
one direction, as defined by the R/W bit, sending a command
to a slave device during a read operation is not possible. Before
a read operation, it can be necessary to perform a write operation
to tell the slave what sort of read operation to expect and/or the
address from which data is to be read.
Step 3
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line high
during the 10th clock pulse to assert a stop condition. In read
mode, the master device releases the SDA line during the low
period before the ninth clock pulse, but the slave device does not
pull it low. This is known as a no acknowledge. The master then
takes the data line low during the low period before the 10th clock
pulse and then high during the 10th clock pulse to assert a stop
condition.
SCL Held Low Timeout
If the bus master holds the SCL low for a time that is a multiple
of approximately 30 ms, the ADM1069 bus interface can timeout.
If this timeout happens, the in progress transaction is NACKed,
and the transaction must be repeated. This behavior is only seen
if the I2C bus master is interrupted midtransaction by a higher
priority task that delays completion of the transaction.
False Start Detection
The data hold time specification defines the time that data must
be valid on the SDA line, following an SCL falling edge. If there
are multiple ADM1069 devices on the same bus, one of the
ADM1069 devices can see the SCL/SDA transition due to an
acknowledge (ACK) from a different device as a start condition
because of internal timing skew, which for most transactions,
this is not an issue. In a case where the data appearing on the
bus after the false start is detected happens to match the address
of another ADM1069 on the bus, that device can incorrectly ACK.
A bus master can see this ACK as another bus master talking on
the bus, halt the bus transaction, and not produce any more
clocks on the SCL. As a result, the ADM1069 device that
incorrectly ACKed continues to hold down the SDA line low.
To retry the halted bus transaction, the bus master performs a
clock flush on the SCL by sending a series of up to 16 clock pulses.
The clock flush forces the ADM1069 to release the SDA line.
ADM1069 Data Sheet
Rev. E | Page 30 of 34
04735-036
19 91
19 91
START BY
MASTER ACK. BY
SLAVE ACK. BY
SLAVE
ACK. BY
SLAVE ACK. BY
SLAVE
FRAME 2
COMMAND CODE
FRAME 1
SLAVE ADDRESS
FRAME N
DATA BYTE
FRAME 3
DATA BYTE
SCL
SDA R/W
STOP
BY
MASTER
SCL
(CONTINUED)
SDA
(CONTINUED)
D7A0A11001 1 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 36. General SMBus Write Timing Diagram
04735-037
19 91
19 91
START BY
MASTER ACK. BY
SLAVE ACK. BY
MASTER
ACK. BY
MASTER NO ACK.
FRAME 2
DATA BYTE
FRAME 1
SLAVE ADDRESS
FRAME N
DATA BYTE
FRAME 3
DATA BYTE
SCL
SDA R/W
STOP
BY
MASTER
SCL
(CONTINUED)
SDA
(CONTINUED)
D7A0A11001 1 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 37. General SMBus Read Timing Diagram
04735-038
SCL
SDA
PS S P
tSU;STO
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
tHD;STA tHIGH
tBUF
tLOW
tRtF
Figure 38. Serial Bus Timing Diagram
Data Sheet ADM1069
Rev. E | Page 31 of 34
SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1069 contains volatile registers (RAM) and nonvola-
tile registers (EEPROM). User RAM occupies Address 0x00 to
Address 0xDF; the EEPROM occupies Address 0xF800 to
Address 0xFBFF.
Data can be written to and read from both the RAM and the
EEPROM as single data bytes. Data can be written only to
unprogrammed EEPROM locations. To write new data to a
programmed location, the location contents must first be erased.
EEPROM erasure cannot be done at the byte level. The EEPROM
is arranged as 32 pages of 32 bytes each, and an entire page must
be erased.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in Figure 39 to Figure 47:
S = Start
P = Stop
R = Read
W = Write
A = Acknowledge
A = No acknowledge
The ADM1069 uses the following SMBus write protocols.
Send Byte
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
In the ADM1069, the send byte protocol is used for the following
two purposes:
To write a register address to the RAM for a subsequent
single byte read from the same address, or for a block read
or a block write starting at that address, as shown in Figure 39.
04735-039
2413 56
SLAVE
ADDRESS RAM
ADDRESS
(0x00 TO 0xDF)
SWA AP
Figure 39. Setting a RAM Address for Subsequent Read
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before writing
to one or more EEPROM memory locations that are already
programmed, the page(s) containing those locations must
first be erased. EEPROM memory is erased by writing a
command byte.
The master sends a command code telling the slave device to
erase the page. The ADM1069 command code for a page
erasure is 0xFE (1111 1110). Note that, for a page erasure
to take place, the page address must be given in the previous
write word transaction (see the Write Byte/Word section).
In addition, Bit 2 in the UPDCFG register (Address 0x90)
must be set to 1.
04735-040
2413 56
SLAVE
ADDRESS COMMAND
BYTE
(0xFE)
SWA AP
Figure 40. EEPROM Page Erasure
As soon as the ADM1069 receives the command byte,
page erasure begins. The master device can send a stop
command as soon as it sends the command byte. Page
erasure takes approximately 20 ms. If the ADM1069 is
accessed before erasure is complete, it responds with a NACK.
ADM1069 Data Sheet
Rev. E | Page 32 of 34
Write Byte/Word
In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device,
as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code.
5. The slave asserts an ACK on SDA.
6. The master sends a data byte.
7. The slave asserts an ACK on SDA.
8. The master sends a data byte (or asserts a stop condition).
9. The slave asserts an ACK on SDA.
10. The master asserts a stop condition on SDA to end the
transaction.
In the ADM1069, the write byte/word protocol is used for the
following three purposes:
To write a single byte of data to the RAM. In this case, the
command byte is RAM Address 0x00 to RAM Address
0xDF, and the only data byte is the actual data, as shown in
Figure 41.
04735-041
SLAVE
ADDRESS RAM
ADDRESS
(0x00 TO 0xDF)
S W A DATAAPA
2413 5876
Figure 41. Single Byte Write to the RAM
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erasure. In this case,
the command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The only data byte is the low byte
of the EEPROM address, as shown in Figure 42.
04735-042
SLAVE
ADDRESS
EEPROM
ADDRESS
HIGH BYTE
(0xF8 TO 0xFB)
SWA EEPROM
ADDRESS
LOW BYTE
(0x00 TO 0xFF)
APA
2413 5 876
Figure 42. Setting an EEPROM Address
Because a page consists of 32 bytes, only the three MSBs of
the address low byte are important for page erasure. The
lower five bits of the EEPROM address low byte specify the
addresses within a page and are ignored during an erase
operation.
To write a single byte of data to the EEPROM. In this case, the
command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The first data byte is the low
byte of the EEPROM address, and the second data byte is
the actual data, as shown in Figure 43.
04735-043
SLAVE
ADDRESS
EEPROM
ADDRESS
HIGH BYTE
(0xF8 TO 0xFB)
SWA EEPROM
ADDRESS
LOW BYTE
(0x00 TO 0xFF)
APA
2413 5 107
A
9
DATA
86
Figure 43. Single Byte Write to the EEPROM
Block Write
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1069, a send byte opera-
tion sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code that tells the slave
device to expect a block write. The ADM1069 command
code for a block write is 0xFC (1111 1100).
5. The slave asserts an ACK on SDA.
6. The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
7. The slave asserts an ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts an ACK on SDA after each data byte.
10 The master asserts a stop condition on SDA to end the
transaction.
04735-044
SLAVE
ADDRESS
SWA
2
COMMAND 0xFC
(BLOCK WRITE)
413
A
5
BYTE
COUNT
6
A
7
A
910
A PA
DATA
1
8
DATA
N
DATA
2
Figure 44. Block Write to the EEPROM or RAM
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except when
There are fewer than N locations from the start address to
the highest EEPROM address (0xFBFF), which results in
writing to invalid addresses.
An address crosses a page boundary. In this case, both
pages must be erased before programming.
Note that the ADM1069 features a clock extend function for
writes to EEPROM. Programming an EEPROM byte takes
approximately 250 μs, which limits the SMBus clock for
repeated or block write operations. The ADM1069 pulls SCL
low and extends the clock pulse when it cannot accept any
more data.
Data Sheet ADM1069
Rev. E | Page 33 of 34
READ OPERATIONS
The ADM1069 uses the following SMBus read protocols.
Receive Byte
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts an ACK on SDA.
4. The master receives a data byte.
5. The master asserts a NACK on SDA.
6. The master asserts a stop condition on SDA, and the
transaction ends.
In the ADM1069, the receive byte protocol reads a single byte of
data from a RAM or EEPROM location whose address has
previously been set by a send byte or write byte/word operation,
as shown in Figure 45.
04735-045
231465
SLAVE
ADDRESS
S R DATA PA A
Figure 45. Single Byte Read from the EEPROM or RAM
Block Read
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1069, this is done by a
send byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as
follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code that tells the slave
device to expect a block read. The ADM1069 command
code for a block read is 0xFD (1111 1101).
5. The slave asserts an ACK on SDA.
6. The master asserts a repeat start condition on SDA.
7. The master sends the 7-bit slave address followed by the
read bit (high).
8. The slave asserts an ACK on SDA.
9. The ADM1069 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1069
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus Version 1.1 specification.
10. The master asserts an ACK on SDA.
11. The master receives 32 data bytes.
12. The master asserts an ACK on SDA after each data byte.
13. The master asserts a stop condition on SDA to end the
transaction.
04735-046
SLAVE
ADDRESS
SWA
2
COMMAND 0xFD
(BLO CK READ)
413
A
5
S
6
SLAVE
ADDRESS
7
BYTE
COUNT
910 1211
ARA
8
DATA
1
DATA
32 A
13
P
A
Figure 46. Block Read from the EEPROM or RAM
Error Correction
The ADM1069 provides the option of issuing a packet error
correction (PEC) byte after a write to the RAM, a write to the
EEPROM, a block write to the RAM/EEPROM, or a block read
from the RAM/ EEPROM. This option enables the user to verify
that the data received by or sent from the ADM1069 is correct.
The PEC byte is an optional byte sent after the last data byte has
been written to or read from the ADM1069. The protocol is the
same as a block read for Step 1 to Step 12 and then proceeds as
follows:
13. The ADM1069 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read, if the
PEC byte is incorrect.
14. A NACK is generated after the PEC byte to signal the end
of the read.
15. The master asserts a stop condition on SDA to end the
transaction.
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
C(x) = x8 + x2 + x1 + 1
See the SMBus Version 1.1 specification for details.
An example of a block read with the optional PEC byte is shown
in Figure 47.
04735-047
SLAVE
ADDRESS
SWA
2
COMMAND 0xFD
(BLOCK READ)
413
A
5
S
6
SLAVE
ADDRESS
7
BYTE
COUNT
910 1211
ARA
8
DATA
1
DATA
32 A
13
PEC
14
A
15
P
A
Figure 47. Block Read from the EEPROM or RAM with PEC
ADM1069 Data Sheet
Rev. E | Page 34 of 34
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-BBA
VIEW A
TOP VIEW
(PINS DOWN)
8
1
32 25
24
17
16
9
0.80
BSC
LEAD PITCH
9.00
BSC SQ
7.00
BSC SQ
1.60
MAX
0.75
0.60
0.45
0.45
0.37
0.30
PIN 1
0.20
0.09
1.45
1.40
1.35
0.10 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
0.15
0.05
Figure 48. 32-Lead Low Profile Quad Flat Package [LQFP]
(ST-32-2)
Dimensions shown in millimeters
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR
EXPOSED
PAD
PIN 1
INDICATOR
SEATING
PLANE
0.05 M AX
0.02 NO M
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
6.10
6.00 SQ
5.90
0.80
0.75
0.70
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
0.45
0.40
0.35
0.25 M IN
4.25
4.10 SQ
3.95
COM P LIANT T O JEDEC S TANDARDS M O-220-WJJD.
40
1
11
20
21
30
31
10
05-06-2011-A
Figure 49. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.75 mm Package Height
(CP-40-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADM1069ASTZ −40°C to +85°C 32-Lead Low Profile Quad Flat Package [LQFP] ST-32-2
ADM1069ASTZ-REEL7 −40°C to +85°C 32-Lead Low Profile Quad Flat Package [LQFP] ST-32-2
ADM1069ACPZ −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-9
ADM1069ACPZ-REEL −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-9
ADM1069ACPZ-REEL7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-9
EVAL-ADM1069LQEBZ Evaluation Board (LQFP Version)
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04735-0-6/16(E)
