NCD57000DWR2G - ON SEMICONDUCTOR

February, 2019 − Rev. 2

1Publication Order Number:

NCD57000/D

NCD57000

Isolated High Current IGBT

Gate Driver

NCD57000 is a high−current single channel IGBT driver with

internal galvanic isolation, designed for high system efficiency and

reliability in high power applications. Its features include

complementary inputs, open drain FAULT and Ready outputs, active

Miller clamp, accurate UVLOs, DESAT protection, soft turn−off at

DESAT, and separate high and low (OUTH and OUTL) driver outputs

for system design convenience. NCD57000 accommodates both 5 V

and 3.3 V signals on the input side and wide bias voltage range on the

driver side including negative voltage capability. NCD57000 provides

> 5 kVrms (UL1577 rating) galvanic isolation and > 1200 Viorm

(working voltage) capabilities. NCD57000 is available in the

wide−body SOIC−16 package with guaranteed 8 mm creepage

distance between input and output to fulfill reinforced safety

insulation requirements.

Features

•High Current Output (+4/−6 A) at IGBT Miller Plateau Voltages

•Low Output Impedance for Enhanced IGBT Driving

•Short Propagation Delays with Accurate Matching

•Active Miller Clamp to Prevent Spurious Gate Turn−on

•DESAT Protection with Programmable Delay

•Negative Voltage (Down to −9 V) Capability for DESAT

•Soft Turn Off During IGBT Short Circuit

•IGBT Gate Clamping During Short Circuit

•IGBT Gate Active Pull Down

•Tight UVLO Thresholds for Bias Flexibility

•Wide Bias Voltage Range including Negative VEE2

•3.3 V to 5 V Input Supply Voltage

•Designed for AEC−Q100 Certification

•5000 V Galvanic Isolation (to meet UL1577 Requirements)

•1200 V Working Voltage (per VDE0884−11 Requirements)

•High Transient Immunity

•High Electromagnetic Immunity

•These Devices are Pb−Free, Halogen Free and are RoHS Compliant

Typical Applications

•Solar Inverters

•Motor Control

•Uninterruptible Power Supplies (UPS)

•Industrial Power Supplies

•Welding

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SOIC−16 WB

CASE 751G−03

MARKING DIAGRAM

PIN ASSIGNMENT

See detailed ordering and shipping information on page 7 of

this data sheet.

ORDERING INFORMATION

1

XXXXX = Specific Device Code

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

16

1

XXXXXXXXXXX

AWLYYWWG

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

IN+

VDD1

IN−

RDY

GND1A

RST

FLT

GND1

DESAT

CLAMP

VEE2A

VDD2

GND2

VEE2

OUTH

OUTL

NCD57000

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2

+V2

GND2

DESAT

IN+

GND1

OUTH

RDY

VDD1

OUTL

IN−

VEE2

CLAMPFLT

RST

GND2

VDD2

GND1

V1

−V3

Figure 1. Simplified Block Diagram

Figure 2. Simplified Application Schematics

IN−

FLT

GND1

CLAMP

VDD1

RST

RDY

GND1A

IN+

VEE2A

VEE2

GND2

OUTL

OUTH

VDD2

DESAT

IDESAT−CHG

UVLO2

VDESAT−THR

VDD2

VEE2

+

−

VCLAMP−THR

UVLO1

2

1

VDD1

LogicLogic

VDD1

STO

+

−

NCD57000

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3

PIN DESCRIPTION

Pin Name No. I/O Description

ÁÁÁÁÁ

VEE2A

ÁÁÁ

1

ÁÁÁÁ

Power

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output side negative power supply. A good quality bypassing capacitor is required from these pins

to GND2 and should be placed close to the pins for best results. Connect it to GND2 for unipolar

supply application.

ÁÁÁÁÁ

VEE2

ÁÁÁ

8

ÁÁÁÁÁ

DESAT

ÁÁÁ

2

ÁÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input for detecting the desaturation of IGBT due to a short circuit condition. An internal constant

current source IDESAT−CHG charging an external capacitor connected to this pin allows a

programmable blanking delay every ON cycle before DESAT fault is processed, thus preventing

false triggering. When the DESAT voltage goes up and reaches VDESAT−THR, the output is driven

low. Further, the /FLT output is activated, please refer to Figure 5 on page 9.

A 5 ms mute time apply to IN+ and IN− once DESAT occurs.

ÁÁÁÁÁ

GND2

ÁÁÁ

3

ÁÁÁÁ

Power

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output side gate drive reference connecting to IGBT emitter or FET source.

ÁÁÁÁÁ

OUTH

ÁÁÁ

4

ÁÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Driver high output that provides the appropriate drive voltage and source current to the IGBT/FET

gate.

ÁÁÁÁÁ

VDD2

ÁÁÁ

5

ÁÁÁÁ

Power

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output side positive power supply. The operating range for this pin is from UVLO2 to its maximum

allowed value. A good quality bypassing capacitor is required from this pin to GND2 and should be

placed close to the pins for best results.

ÁÁÁÁÁ

OUTL

ÁÁÁ

6

ÁÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Driver low output that provides the appropriate drive voltage and sink current to the IGBT/FET

gate. OUTL is actively pulled low during start−up and under Fault conditions.

ÁÁÁÁÁ

CLAMP

ÁÁÁ

7

ÁÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Provides clamping for the IGBT/FET gate during the off period to protect it from parasitic turn−on.

Its internal N FET is turned on when the voltage of this pin falls below VEE2 + VCLAMP−THR. It is to

be tied directly to IGBT/FET gate with minimum trace length for best results.

ÁÁÁÁÁ

GND1A

ÁÁÁ

9

ÁÁÁÁ

Power

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input side ground reference.

ÁÁÁÁÁ

GND1

ÁÁÁ

16

ÁÁÁÁÁ

IN+

ÁÁÁ

10

ÁÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Non inverted gate driver input. It is internally clamped to VDD1 and has a pull−down resistor of

50 kW to ensure that output is low in the absence of an input signal. A minimum positive going

pulse−width is required at IN+ before OUTH/OUTL respond.

ÁÁÁÁÁ

IN−

ÁÁÁ

11

ÁÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Inverted gate driver input. It is internally clamped to VDD1 and has a pull−up resistor of 50 kW to

ensure that output is low in the absence of an input signal. A minimum negative going pulse−width

is required at IN− before OUTH/OUTL respond.

ÁÁÁÁÁ

RDY

ÁÁÁ

12

ÁÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power good indication output, active high when VDD1 and VDD2 are both good. There is an internal

50 kW pull−up resistor connected to this pin. Multiple of them from different drivers can be ”OR”ed

together.

OUTH/OUTL remain low when RDY is low. Short time delays may apply. See Figure 4 on page 8

for details.

ÁÁÁÁÁ

/FLT

ÁÁÁ

13

ÁÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Fault output (active low) that allows communication to the main controller that the driver has

encountered a desaturation condition and has deactivated the output. There is an internal 50 kW

pull−up resistor connected to this pin. Multiple of them from different drivers can be ”OR”ed

together.

ÁÁÁÁÁ

/RST

ÁÁÁ

14

ÁÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset input with an internal 50 kW pull−up resistor, active low to reset fault latch.

ÁÁÁÁÁ

VDD1

ÁÁÁ

15

ÁÁÁÁ

Power

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input side power supply (3.3 V to 5 V).

NCD57000

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4

ABSOLUTE MAXIMUM RATINGS (Over operating free−air temperature range unless otherwise noted) (Note 1)

Symbol Parameter Minimum Maximum Unit

VDD1−GND1 Supply voltage, input side −0.3 6 V

VDD2−GND2 Positive Power Supply, output side −0.3 25 V

VEE2−GND2 Negative Power Supply, output side −10 0.3 V

VDD2−VEE2 (VMAX2)Differential Power Supply, output side 0 25 V

VOUTH Positive gate−driver output voltage VEE2 − 0.3 VDD2 + 0.3 V

VOUTL Negative gate−driver output voltage VEE2 − 0.3 VDD2 + 0.3 V

IPK−SRC Gate−driver output sourcing current

(maximum pulse width = 10 ms, maximum duty cycle = 0.2%, VMAX2 = 23 V)

−7.8 A

IPK−SNK Gate−driver output sinking current

(maximum pulse width = 10 ms, maximum duty cycle = 0.2%, VMAX2 = 23 V)

−7.1 A

IPK−CLAMP Clamp sinking current

(maximum pulse width = 10 ms, maximum duty cycle = 0.2%, VCLAMP = 2.5 V)

−2.5 A

tCLP Maximum Short Circuit Clamping Time (IOUTH_CLAMP = 500 mA) −10 ms

VLIM−GND1 Voltage at IN+, IN−, /RST, /FLT, RDY −0.3 VDD1 + 0.3 V

ILIM−GND1 Output current of /FLT, RDY −10 mA

VDESAT−GND2 Desat Voltage (Note 2) −9 VDD2 + 0.3 V

VCLAMP−GND2 Clamp Voltage VEE2 − 0.3 VDD2 + 0.3 V

PDPower Dissipation (Note 3) −1400 mW

VISO Input to Output Isolation Voltage −1200 1200 V

TJ(max) Maximum Junction Temperature −40 150 °C

TSTG Storage Temperature Range −65 150 °C

ESDHBM ESD Capability, Human Body Model (Note 4) −±2 kV

ESDCDM ESD Capability, Charged Device Model (Note 4) −±2 kV

MSL Moisture Sensitivity Level −2−

TSLD Lead Temperature Soldering Reflow, Pb−Free Versions (Note 5) −260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

2. The minimum value is verified by characterization with a single pulse of 100 mA for 100 ms.

3. The value is estimated for ambient temperature 25°C and junction temperature 150°C, 650 mm2, 1 oz copper, 2 surface layers and 2 internal

power plane layers. Power dissipation is affected by the PCB design and ambient temperature.

4. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101)

Latchup Current Maximum Rating: ≤100 mA per JEDEC standard: JESD78, 25°C

5. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

THERMAL CHARACTERISTICS

Symbol Parameter Conditions Value Unit

RqJA Thermal Resistance, Junction−to−Air 100 mm2, 1 oz Copper, 1 Surface Layer 150 °C/W

650 mm2, 1 oz Copper, 2 Surface Layers and

2 Internal Power Plane Layers

84

NCD57000

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5

OPERATING RANGES (Note 6)

Symbol Parameter Min Max Unit

VDD1−GND1 Supply voltage, input side UVLO1 5.5 V

VDD2−GND2 Positive Power Supply, output side UVLO2 24 V

VEE2−GND2 Negative Power Supply, output side −10 0 V

VDD2−VEE2 (VMAX2)Differential Power Supply, output side 0 24 V

VIL Low level input voltage at IN+, IN−, /RST 00.3 X VDD1 V

VIH High level input voltage at IN+, IN−, /RST 0.7 X VDD1 VDD1 V

|dVISO/dt| Common Mode Transient Immunity 100 −kV/ms

TAAmbient Temperature −40 125 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

ELECTRICAL CHARACTERISTICS (VDD1 = 5 V, VDD2 = 15 V, VEE2 = −8 V. For typical values TA = 25°C, for min/max values,

TA is the operating ambient temperature range that applies, unless otherwise noted)

Symbol Parameter Test Condition Min Typ Max Unit

VOLTAGE SUPPLY

VUVLO1−OUT−ON UVLO1 Output Enabled − −3.05 V

VUVLO1−OUT−OFF UVLO1 Output Disabled 2.4 − −V

VUVLO1−HYST UVLO1 Hysteresis 0.125 − −V

VUVLO2−OUT−ON UVLO2 Output Enabled 13.2 13.5 13.8 V

VUVLO2−OUT−OFF UVLO2 Output Disabled 12.2 12.5 12.8 V

VUVLO2−HYST UVLO2 Hysteresis −1 V

IDD1−0Input Supply Quiescent Current

Output Low

IN+ = Low, IN− = Low −1 2 mA

RDY = High, /FLT = High

IDD1−100 Input Supply Quiescent Current

Output High

IN+ = High, IN− = Low −4.8 6 mA

RDY = High, /FLT = High

IDD2−0Output Positive Supply Quiescent

Current, Output Low

IN+ = Low, IN− = Low −3.3 4 mA

RDY = High, /FLT = High, no load

IDD2−100 Output Positive Supply Quiescent

Current, Output High

IN+ = High, IN− = Low −3.6 4 mA

RDY = High, /FLT = High, no load

IEE2−0Output Negative Supply

Quiescent Current, Output Low

IN+ = High, IN− = Low, no load −0.4 2 mA

IEE2−100 Output Negative Supply

Quiescent Current, Output High

IN+ = High, IN− = Low, no load −0.2 2 mA

LOGIC INPUT AND OUTPUT

VIL IN+, IN−, /RST Low Input Voltage − − 0.3 x

VDD1

V

VIH IN+, IN−, /RST High Input Voltage 0.7 x

VDD1

− − V

VIN−HYST Input Hysteresis Voltage −0.15 x

VDD1

−V

IIN−L, IRST−LIN−, /RST Input Current

(50 kW pull−up resistor)

VIN−/VRST = 0 V − −100 −mA

IIN+H IN+ Input Current

(50 kW pull−down resistor)

VIN+ = 5 V −100 −mA

NCD57000

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6

ELECTRICAL CHARACTERISTICS (VDD1 = 5 V, VDD2 = 15 V, VEE2 = −8 V. For typical values TA = 25°C, for min/max values,

TA is the operating ambient temperature range that applies, unless otherwise noted) (continued)

Symbol UnitMaxTypMinTest ConditionParameter

LOGIC INPUT AND OUTPUT

IRDY−L, IFLT−LRDY, /FLT Pull−up Current

(50 kW pull−up resistor)

VRDY/VFLT = Low −100 −mA

VRDY−L, VFLT−LRDY, /FLT Low Level Output Voltage IRDY/IFLT = 5 mA − − 0.3 V

tMIN1 Input Pulse Width of IN+, IN− for

No Response at Output

− − 10 ns

tMIN2 Input Pulse Width of IN+, IN− for

Guaranteed Response at Output

40 − − ns

tRST−MIN Pulse Width of /RST for Resetting

/FLT

800 − − ns

DRIVER OUTPUT

VOUTL1 Output Low State

(VOUTL – VEE2)

ISINK = 200 mA − 0.1 0.2 V

VOUTL3 ISINK = 1.0 A, TA = 25°C −0.5 0.8

VOUTH1 Output High State

(VDD2 – VOUTH)

ISRC = 200 mA −0.3 0.5 V

VOUTH3 ISRC = 1.0 A, TA = 25°C−0.8 1

IPK−SNK1 Peak Driver Current, Sink (Note 7) VOUTH = 7.9 V −7.1 −A

IPK−SRC1 Peak Driver Current, Source (Note 7) VOUTL = −5 V −7.8 −A

MILLER CLAMP

VCLAMP Clamp Voltage

(VCLAMP – VEE2)

ICLAMP = 2.5 A, TA = 25°C− 1.3 1.7 V

ICLAMP = 2.5 A, TA = −40°C to 125°C − −2.7

VCLAMP−THR Clamp Activation Threshold

(VCLAMP – VEE2)

1.5 2 2.5 V

IGBT SHORT CIRCUIT CLAMPING

VCLAMP−OUTH Clamping Voltage, Sourcing

(VOUTH − VDD2)

IN+ = Low, IN− = High,

ICLAMP−OUTH = 500 mA

(pulse test, tCLPmax = 10 ms)

−0.9 1 V

VCLAMP−OUTL Clamping Voltage, Sinking

(VOUTL − VDD2)

IN+ = High, IN− = Low,

ICLAMP−OUTL = 500 mA

(pulse test, tCLPmax = 10 ms)

−1.2 1.5 V

VCLAMP−CLAMP Clamping Voltage, Clamp

(VCLAMP − VDD2)

IN+ = High, IN− = Low,

ICLAMP−CLAMP = 500 mA

(pulse test, tCLPmax = 10 ms)

−1.4 1.6 V

DESAT PROTECTION

VDESAT−THR DESAT Threshold Voltage 8.5 9 9.5 V

VDESAT−NEG DESAT Negative Voltage IDESAT = 1.5 mA − −8−V

IDESAT−CHG Blanking Charge Current VDESAT = 7 V 0.45 0.5 0.6 mA

IDESAT−DIS Blanking Discharge Current −50 −mA

DYNAMIC CHARACTERISTICS

tPD−ON IN+, IN− to Output High Propagation

Delay

CLOAD = 10 nF

VIH to 10% of output change for

PW > 150 ns. OUTH, OUTL and

CLAMP pins are connected together

40 60 90 ns

tPD−OFF IN+, IN− to Output Low Propagation

Delay

CLOAD = 10 nF

VIL to 90% of output change for

PW > 150 ns. OUTH, OUTL and

CLAMP pins are connected together

40 66 90 ns

tDISTORT Propagation Delay Distortion

(= tPD−ON − tPD−OFF)

TA = 25°C, PW > 150 ns −15 −6 15 ns

TA = −40°C to 125°C, PW > 150 ns −25 −25

NCD57000

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7

ELECTRICAL CHARACTERISTICS (VDD1 = 5 V, VDD2 = 15 V, VEE2 = −8 V. For typical values TA = 25°C, for min/max values,

TA is the operating ambient temperature range that applies, unless otherwise noted) (continued)

Symbol UnitMaxTypMinTest ConditionParameter

DYNAMIC CHARACTERISTICS

tDISTORT_TOT Prop Delay Distortion between Parts PW > 150 ns −30 0 30 ns

tRISE Rise Time (see Fig. 3) (Note 7) CLOAD = 1 nF, 10% to 90% of

Output Change

−10 −ns

tFALL Fall Time (see Fig. 3) (Note 7) CLOAD = 1 nF, 90% to 10% of

Output Change

−15 −ns

tLEB DESAT Leading Edge Blanking Time

(See Fig. 5)

−450 −ns

tFILTER DESAT Threshold Filtering Time

(see Fig. 5)

−320 −ns

tSTO Soft Turn Off Time (see Fig. 5) CLOAD =10nF,R

G=10W.V

EE2 = 0 V −1.8 −ms

CLOAD = 10 nF, RG = 10 W−2.6 −

tFLT Delay after tFILTER to /FLT −450 −ns

tRST /RST Rise to /FLT Rise Delay −23 −ns

tRDY1O RDY High to Output High Delays

(see Fig. 4)

−55 −ns

tRDY2O

tRDY1F VUVLO2−OUT−OFF to RDY Low

Delays (see Fig. 4)

−8−ms

tRDY2F

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

7. Values based on design and/or characterization.

ORDERING INFORMATION

Device Package Type Shipping†

NCD57000DWR2G SOIC−16 Wide Body

(Pb−Free)

1,000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

NCD57000

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8

VIL

VIH

tPD−ON

tRISE

tPD−OFF

90%

10%

tFALL

tMIN1

IN+

OUTH

/OUTL

OUTH

/OUTL

IN+

RDY

VDD1

VUVLO2−OUT−ON

VUVLO2−OUT−OFF

tRDY2F

RDY

IN+

VUVLO2−OUT−ON

VUVLO2−OUT−OFF

Figure 3. Propagation Delay, Rise and Fall Time

Figure 4. UVLO Waveform

tRDY1F

VDD2

OUTH

/OUTL

VUVLO1−OUT−ON

VUVLO1−OUT−OFF

tRDY2O tRDY1O

tMIN2 tMIN2

tMIN1

NCD57000

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9

VDESAT−THR

tSTO

tFILTER

tLEB

tFLT

IN+

VOUTH/L

DESAT

FLT

RST

tMUTE

tRST

tPD−ON

tRST−MIN

VEE2 + 2 V

Figure 5. DESAT Response Waveform

NCD57000

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10

TYPICAL CHARACTERISTICS

(Conditions for the following figures are the same as stated for ELECTRICAL CHARACTERISTICS Table unless otherwise noted.

Typical and/or average values are used.)

0.0

1.0

2.0

3.0

4.0

5.0

6.0

−40 −20 0 20 40 60 80 100 120

Temperature (5C)

VDD1 = 5 V, IN+ = Low, IN− = LOW

VDD1 = 5 V, IN+ = High, IN− = LOW

VDD1 = 3.3 V, IN+ = Low, IN− = LOW

VDD1 = 3.3 V, IN+ = High, IN− = LOW

0.0

1.0

2.0

3.0

4.0

5.0

6.0

−40 −20 0 20 40 60 80 100 120

IDD2 (mA)

Temperature (5C)

0.0

0.1

0.2

0.3

0.4

0.5

−40 −20 0 20406080100120

I

EE2

(

m

A)

Temperature (5C)

−1.0

0.0

1.0

2.0

3.0

4.0

5.0

0 100 200 300 400 500

Supply Current (mA)

Input Frequency (kHz)

2.5

2.6

2.7

2.8

2.9

3.0

−40 −200 20406080100120

UVLO1 (V)

Temperature (5C)

VUVLO1−OUT−ON

VUVLO1−OUT−OFF

12.0

12.5

13.0

13.5

14.0

−40 −20 0 20 40 60 80 100 120

UVLO2 (V)

Temperature (5C)

Figure 6. VDD1 Supply Current Figure 7. VDD2 Supply Current

Figure 8. VEE2 Supply Current Figure 9. Supply Current vs Frequency

Figure 10. UVLO1 Threshold Voltage Figure 11. UVLO2 Threshold Voltage

IDD1 (mA)

VDD2 = 15 V, IN+ = Low, IN− = LOW

VDD2 = 15 V, IN+ = 1 MHz, IN− = LOW

VDD2 = 15 V, IN+ = High, IN− = LOW

VEE2 = −8 V, IN+ = Low, IN− = LOW

VEE2 = −8 V, IN+ = High, IN− = LOW IDD1, VDD1 = 5 V

IDD2, VDD2 = 15 V

IEE2, VEE2 = −8 V

VUVLO2−OUT−ON

VUVLO2−OUT−OFF

NCD57000

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11

TYPICAL CHARACTERISTICS

(Conditions for the following figures are the same as stated for ELECTRICAL CHARACTERISTICS Table unless otherwise noted.

Typical and/or average values are used.) (continued)

Figure 12. Output Voltage Drop, Sourcing Figure 13. Output Voltage Drop, Sinking

Figure 14. CLAMP Voltage Drop Figure 15. IGBT Short Circuit Clamp Voltage Drop

Figure 16. Propagation Delay Figure 17. Rise and Fall Time

0.0

0.5

1.0

1.5

2.0

−40 −20 0 20406080100120

VOUTH (V)

Temperature (5C)

0.0

0.5

1.0

1.5

2.0

−40 −20 0 20406080100120

Temperature (5C)

0.0

0.5

1.0

1.5

2.0

2.5

−40 −20 0 20406080100120

CLAMP Voltage (V)

Temperature (5C)

0.0

0.5

1.0

1.5

2.0

−40 −200 20406080100120

Temperature (5C)

40

50

60

70

80

90

−40 −20 0 20 40 60 80 100 120

Propagation Delay (ns)

Temperature (5C)

0

5

10

15

20

25

30

35

40

−40 −20 0 20 40 60 80 100 120

Rise and Fall Time (ns)

Temperature (5C)

VOUTH (0.2 A) VEE2 = −8 V

VOUTH (1 A) VEE2 = −8 V

VOUTL (V)

VOUTL (0.2 A) VEE2 = −8 V

VOUTL (1 A) VEE2 = −8 V

VCLAMP (2.5 A) VEE2 = −8 V

VCLAMP− (V)

VCLAMP−OUTL (0.5 A) VEE2 = −8 V

VCLAMP−CLAMP (0.5 A) VEE2 = −8 V

VCLAMP−OUTH (0.5 A) VEE2 = −8 V

tPD−ON

tPD−OFF

tRISE,VEE2 = −8 V

tFALL,VEE2 = −8 V

tRISE,VEE2 = 0 V

tFALL,VEE2 = 0 V

NCD57000

www.onsemi.com

12

Figure 18. Soft Turn Off Time

0.0

1.0

2.0

3.0

4.0

−40 −20 0 20 40 60 80 100 120

Temperature (5C)

Soft Turn Off Time (ms)

tSTO,VEE2 = −8 V

tSTO,VEE2 = 0 V

SOIC−16 WB

CASE 751G−03

ISSUE D

DATE 12 FEB 2013

SCALE 1:1

D

14X

B16X

SEATING

PLANE

S

A

M

0.25 B S

T

16 9

81

hX 45_

M

B

M

0.25

H8X

E

B

A

eT

A1

A

L

C

qNOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN

EXCESS OF THE B DIMENSION AT MAXIMUM

MATERIAL CONDITION.

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D10.15 10.45

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

__

XXXXX = Specific Device Code

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

GENERIC

MARKING DIAGRAM*

16

1

XXXXXXXXXXX

AWLYYWWG

1

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

11.00

16X 0.58

16X

1.62 1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

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SOIC−16 WB

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